1+ # --------------------------------------------------------------------------------------------------
2+ # Constraint File for the Zybo-Z7 20 Board
3+ # --------------------------------------------------------------------------------------------------
4+
5+ # --------------------------------------------------------------------------------------------------
6+ # Clock Source
7+ # --------------------------------------------------------------------------------------------------
8+ set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sys_clk_p }]; # IO_L12P_T1_MRCC_35 Sch=sysclk
9+ create_clock -add -name sys_clk -period 8.00 -waveform {0 4} [get_ports { sys_clk_p }];
10+
11+
12+ # SoC clock is generated by clock wizard and its constraints
13+ set SOC_TCK 50.0
14+ set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_20]]
15+
16+ # --------------------------------------------------------------------------------------------------
17+ # Switches
18+ # --------------------------------------------------------------------------------------------------
19+ set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { fetch_en_i }]; # IO_L19N_T3_VREF_35 Sch=sw[0]
20+ set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { gpio_i[0] }]; # IO_L24P_T3_34 Sch=sw[1]
21+ set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { gpio_i[1] }]; # IO_L4N_T0_34 Sch=sw[2]
22+ set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { gpio_i[2] }]; # IO_L9P_T1_DQS_34 Sch=sw[3]
23+
24+ # set_false_path -from [get_ports {fetch_en_i}] -to *
25+ # set_input_delay -clock sys_clk 0.0 [get_ports {fetch_en_i}]
26+
27+ set_false_path -from [get_ports {gpio_i*}] -to *
28+ set_input_delay -clock sys_clk 0.0 [get_ports {gpio_i*}]
29+
30+ # --------------------------------------------------------------------------------------------------
31+ # Buttons
32+ # --------------------------------------------------------------------------------------------------
33+ set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { sys_reset }]; # IO_L12N_T1_MRCC_35 Sch=btn[0]
34+ set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { gpio_i[3] }]; # IO_L24N_T3_34 Sch=btn[1]
35+
36+
37+ # --------------------------------------------------------------------------------------------------
38+ # LEDs
39+ # --------------------------------------------------------------------------------------------------
40+ set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { status_o }]; # IO_L23P_T3_35 Sch=led[0]
41+ set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[0] }]; # IO_L23N_T3_35 Sch=led[1]
42+ set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[1] }]; # IO_0_35 Sch=led[2]
43+ set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[2] }]; # IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
44+ set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[3] }]; # IO_L6N_T0_VREF_35 Sch=led6_g
45+
46+ set_false_path -from * -to [get_ports {status_o}]
47+ set_output_delay -clock sys_clk 0.0 [get_ports {status_o}]
48+
49+ set_false_path -from * -to [get_ports {gpio_o*}]
50+ set_output_delay -clock sys_clk 0.0 [get_ports {gpio_o*}]
51+
52+
53+
54+ # --------------------------------------------------------------------------------------------------
55+ # Pmod Header JB (Zybo Z7-20 only)
56+ # --------------------------------------------------------------------------------------------------
57+ set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jtag_tms_i }]; # IO_L15P_T2_DQS_13 Sch=jb_p[1]
58+ set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { jtag_tdi_i }]; # IO_L15N_T2_DQS_13 Sch=jb_n[1]
59+ set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { jtag_tdo_o }]; # IO_L11P_T1_SRCC_13 Sch=jb_p[2]
60+ set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jtag_tck_i }]; # IO_L11N_T1_SRCC_13 Sch=jb_n[2]
61+
62+ # --------------------------------------------------------------------------------------------------
63+ # Pmod Header JC
64+ # --------------------------------------------------------------------------------------------------
65+ set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_i }]; # IO_L10P_T1_34 Sch=jc_p[1]
66+ set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_o }]; # IO_L10N_T1_34 Sch=jc_n[1]
67+
68+
69+
70+ # ###########
71+ # Switches #
72+ # ###########
73+
74+ set_input_delay -min -clock $soc_clk [expr { $SOC_TCK * 0.10 }] [ \
75+ get_ports {fetch_en_i}]
76+ set_input_delay -max -clock $soc_clk [expr { $SOC_TCK * 0.35 }] [ \
77+ get_ports {fetch_en_i}]
78+
79+ set_max_delay [expr { 2 * $SOC_TCK }] -from [get_ports {fetch_en_i}]
80+ set_false_path -hold -from [get_ports {fetch_en_i}]
81+
82+ # ################
83+ # Clock routing #
84+ # ################
85+
86+ # JTAG is on non-clock-capable GPIOs (if not using BSCANE)
87+ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]]
88+ set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]]
89+
90+ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports sys_reset*]]
91+ set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports sys_reset*]]
92+
93+ # Remove avoid tc_clk_mux2 to use global clock routing
94+ set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of \
95+ [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]]
96+ set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux
97+ set_property CLOCK_BUFFER_TYPE NONE $all_in_mux
98+
99+ # #######
100+ # JTAG #
101+ # #######
102+
103+ # 10 MHz (max) JTAG clock
104+ set JTAG_TCK 100.0
105+
106+ # JTAG Clock
107+ create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i]
108+ set_input_jitter clk_jtag 1.000
109+
110+ # JTAG Clock is asynchronous to all other clocks
111+ set_clock_groups -name jtag_async -asynchronous -group {clk_jtag}
112+
113+ set_input_delay -min -clock clk_jtag [expr { 0.10 * $JTAG_TCK }] [get_ports {jtag_tdi_i jtag_tms_i}]
114+ set_input_delay -max -clock clk_jtag [expr { 0.20 * $JTAG_TCK }] [get_ports {jtag_tdi_i jtag_tms_i}]
115+
116+ set_output_delay -min -clock clk_jtag [expr { 0.10 * $JTAG_TCK }] [get_ports jtag_tdo_o]
117+ set_output_delay -max -clock clk_jtag [expr { 0.20 * $JTAG_TCK }] [get_ports jtag_tdo_o]
118+
119+ # set_max_delay -from [get_ports jtag_trst_ni] $JTAG_TCK
120+ # set_false_path -hold -from [get_ports jtag_trst_ni]
121+
122+ # #######
123+ # UART #
124+ # #######
125+
126+ # UART speed is at most 5 Mb/s
127+ set UART_IO_SPEED 200.0
128+
129+ set_max_delay [expr { $UART_IO_SPEED * 0.35 }] -from [get_ports uart_rx_i]
130+ set_false_path -hold -from [get_ports uart_rx_i]
131+
132+ set_max_delay [expr { $UART_IO_SPEED * 0.35 }] -to [get_ports uart_tx_o]
133+ set_false_path -hold -to [get_ports uart_tx_o]
134+
135+ # #######
136+ # CDCs #
137+ # #######
138+
139+ # Disable hold checks on CDCs
140+ set_property KEEP_HIERARCHY SOFT [get_cells -hier \
141+ -filter {ORIG_REF_NAME==" sync" " sync"
142+ set_false_path -hold -through [get_pins -of_objects [get_cells -hier \
143+ -filter {ORIG_REF_NAME==" sync" " sync"
144+
145+ set_false_path -hold -through [get_pins -of_objects [get_cells -hier \
146+ -filter {ORIG_REF_NAME =~ cdc_*src* || REF_NAME =~ cdc_*src*}] -filter {NAME =~ *async*}]
147+ set_false_path -hold -through [get_pins -of_objects [get_cells -hier \
148+ -filter {ORIG_REF_NAME =~ cdc_*dst* || REF_NAME =~ cdc_*dst*}] -filter {NAME =~ *async*}]
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