openroad: improve timing constraints

Author: phsauter

openroad/src/constraints.sdc

@@ -29,11 +29,11 @@ set_driving_cell [all_inputs] -lib_cell sg13g2_IOPadOut16mA -pin pad
 ##################
 puts "Clocks..."
 
-# We target 80 MHz
-set TCK_SYS 12.5
+# We target 100 MHz
+set TCK_SYS 10.0
 create_clock -name clk_sys -period $TCK_SYS [get_ports clk_i]
 
-set TCK_JTG 20.0
+set TCK_JTG 25.0
 create_clock -name clk_jtg -period $TCK_JTG [get_ports jtag_tck_i]
 
 set TCK_RTC 50.0
@@ -45,7 +45,9 @@ create_clock -name clk_rtc -period $TCK_RTC [get_ports ref_clk_i]
 ##################################
 
 # Define which clocks are asynchronous to each other
-# -allow_paths re-activates timing checks between asyncs -> we must constrain CDCs!
+# If you have added a clock it is a good idea to temporarily add -allow_paths.
+# This means the paths between clocks (CDC) are timed and will show up as violations,
+# making them very easy to find and write constraints for.
 set_clock_groups -asynchronous -name clk_groups_async \
      -group {clk_rtc} \
      -group {clk_jtg} \
@@ -62,17 +64,17 @@ set_clock_transition  0.2 [all_clocks]
 ####################
 puts "CDC/Sync..."
 
-# Clock Domain Crossings: paths going from a FF with one clock to an FF with another another)
-# to increase the metastability-recovery window we do not wants any additional delays in these paths
-# so we deactivate the hold checking (as it may add buffers)
+# Clock Domain Crossings: paths going from an FF with one clock to an FF with another.
+# The setup/hold checks on these paths are deactivated by set_clock_groups -asynchronous.
+# An additional requirement is that the max delay is below min($TCK_SYS, $TCK_JTG) 
+# to make sure any change propages within one cycle of either clock.
+# An (optional) lower delay is better for metastability recovery -> 3ns as a reasonable goal
 
-# Constrain `cdc_2phase` for DMI request
-set_false_path -hold                  -through $JTAG_ASYNC_REQ
-set_max_delay  [expr $TCK_SYS * 0.35] -through $JTAG_ASYNC_REQ -ignore_clock_latency
+## Constrain `cdc_2phase` for DMI request
+set_max_delay 3.0 -from $JTAG_ASYNC_REQ_START -to $JTAG_ASYNC_REQ_END -ignore_clock_latency
 
 # Constrain `cdc_2phase` for DMI response
-set_false_path -hold                  -through $JTAG_ASYNC_RSP
-set_max_delay  [expr $TCK_SYS * 0.35] -through $JTAG_ASYNC_RSP -ignore_clock_latency
+set_max_delay 3.0 -from $JTAG_ASYNC_RSP_START -to $JTAG_ASYNC_RSP_END -ignore_clock_latency
 
 
 #############
@@ -91,10 +93,10 @@ set_max_delay $TCK_SYS -from [get_ports rst_ni]
 ##########
 puts "JTAG..."
 
-set_input_delay  -min -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.10 ]     [get_ports {jtag_tdi_i jtag_tms_i}]
-set_input_delay  -max -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.50 ]     [get_ports {jtag_tdi_i jtag_tms_i}]
-set_output_delay -min -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.10 / 2 ] [get_ports jtag_tdo_o]
-set_output_delay -max -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.50 / 2 ] [get_ports jtag_tdo_o]
+set_input_delay  -min -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.10 ] [get_ports {jtag_tdi_i jtag_tms_i}]
+set_input_delay  -max -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.30 ] [get_ports {jtag_tdi_i jtag_tms_i}]
+set_output_delay -min -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.10 ] [get_ports jtag_tdo_o]
+set_output_delay -max -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.30 ] [get_ports jtag_tdo_o]
 
 # Reset should propagate to system domain within a clock cycle.
 set_input_delay -max [ expr $TCK_JTG * 0.10 ] [get_ports jtag_trst_ni]  
@@ -110,8 +112,12 @@ puts "GPIO..."
 set_input_delay  -min -add_delay -clock clk_sys [ expr $TCK_SYS * 0.10 ] [get_ports {gpio* fetch_en_i}]
 set_input_delay  -max -add_delay -clock clk_sys [ expr $TCK_SYS * 0.30 ] [get_ports {gpio* fetch_en_i}]
 
-set_output_delay -min -add_delay -clock clk_sys [ expr $TCK_SYS * 0.10 ] [get_ports {status_o gpio*}]
-set_output_delay -max -add_delay -clock clk_sys [ expr $TCK_SYS * 0.30 ] [get_ports {status_o gpio*}]
+set_output_delay -min -add_delay -clock clk_sys [ expr $TCK_SYS * 0.10 ] [get_ports {gpio*}]
+set_output_delay -max -add_delay -clock clk_sys [ expr $TCK_SYS * 0.30 ] [get_ports {gpio*}]
+
+# The timing of these signals are not important but we want to keep them in-cycle
+set_output_delay -min -add_delay -clock clk_sys [ expr $TCK_SYS * 0.10 ] [get_ports {status_o unused*}]
+set_output_delay -max -add_delay -clock clk_sys [ expr $TCK_SYS * 0.10 ] [get_ports {status_o unused*}]
 
 
 ##########

openroad/src/instances.tcl

@@ -31,5 +31,36 @@ set bank0_sram0 $SRAM$sram$SRAM_512x32
 set sram {\[1\].i_sram/}
 set bank1_sram0 $SRAM$sram$SRAM_512x32
 
-set JTAG_ASYNC_REQ [get_nets $JTAG/i_dmi_cdc.i_cdc_req/*async_*]
-set JTAG_ASYNC_RSP [get_nets $JTAG/i_dmi_cdc.i_cdc_resp/*async_*]
+# JTAG request and response CDCs
+# Goal: Find the async nets and their source and destination cells
+# We only want to constrain paths internal to the CDC and going through the async nets.
+# It is more complex than usual due to how OpenROAD currently dissolves hierarchy when reading in designs.
+set JTAG_CDC_REQ $JTAG/i_dmi_cdc.i_cdc_req
+# find all startpoints (flops) that drive through async_data nets and flops that directly drive async nets
+set JTAG_ASYNC_REQ_START [get_fanin -to [get_nets $JTAG_CDC_REQ/*async_data*] -flat -startpoints_only -only_cells]
+set JTAG_ASYNC_REQ_START [concat $JTAG_ASYNC_REQ_START [get_cells $JTAG_CDC_REQ/*async*_o*_reg]]
+# find all endpoints (flops) that are driven through async nets and are in the CDC
+set JTAG_ASYNC_REQ_END [list]
+set JTAG_ASYNC_REQ_CANDIDATES [get_fanout -from [get_nets $JTAG_CDC_REQ/*async*_data*] -flat -endpoints_only -only_cells]
+foreach cell $JTAG_ASYNC_REQ_CANDIDATES {
+	if {[string match "${JTAG_CDC_REQ}/*" [get_name $cell]]} {
+		lappend JTAG_ASYNC_REQ_END $cell
+	}
+}
+# These paths (clear and isolate) go out of the CDC but we know they cannot cause timing violations
+# because they have a seperate 4-phase handshake making sure they stay stable for multiple cycles in each clock domain.
+lappend JTAG_ASYNC_REQ_END {*}[get_fanout -from [get_pins $JTAG_CDC_REQ/*i_cdc_reset_ctrlr_half_a*async_data*_reg/Q] -flat -endpoints_only -only_cells]
+
+# The same for the response CDC
+set JTAG_CDC_RSP $JTAG/i_dmi_cdc.i_cdc_resp
+set JTAG_ASYNC_RSP_START [get_fanin -to [get_nets $JTAG_CDC_RSP/*async_data*] -flat -startpoints_only -only_cells]
+set JTAG_ASYNC_RSP_START [concat $JTAG_ASYNC_RSP_START [get_cells $JTAG_CDC_RSP/*async*_o*_reg]]
+set JTAG_ASYNC_RSP_END [list]
+set JTAG_ASYNC_RSP_CANDIDATES [get_fanout -from [get_nets $JTAG_CDC_RSP/*async*_data*] -flat -endpoints_only -only_cells]
+foreach cell $JTAG_ASYNC_RSP_CANDIDATES {
+	if {[string match "${JTAG_CDC_RSP}/*" [get_name $cell]]} {
+		lappend JTAG_ASYNC_RSP_END $cell
+	}
+}
+lappend JTAG_ASYNC_RSP_END {*}[get_fanout -from [get_pins $JTAG_CDC_RSP/*i_cdc_reset_ctrlr_half_a*async_data*_reg/Q] -flat -endpoints_only -only_cells]
+

yosys/scripts/yosys_synthesis.tcl

@@ -46,7 +46,10 @@ yosys setattr -set keep_hierarchy 1 "t:reg_uart_wrap$*"
 yosys setattr -set keep_hierarchy 1 "t:soc_ctrl_regs$*"
 yosys setattr -set keep_hierarchy 1 "t:tc_clk*$*"
 yosys setattr -set keep_hierarchy 1 "t:tc_sram_impl$*"
-yosys setattr -set keep_hierarchy 1 "t:cdc_*$*"
+yosys setattr -set keep_hierarchy 1 "t:cdc_reset*$*"
+yosys setattr -set keep_hierarchy 1 "t:cdc*phase_*$*"
+yosys setattr -set keep_hierarchy 1 "t:cdc*_src*$*"
+yosys setattr -set keep_hierarchy 1 "t:cdc*_dst*$*"
 yosys setattr -set keep_hierarchy 1 "t:sync$*"
 
 
@@ -55,6 +58,7 @@ yosys blackbox "t:tc_sram_blackbox$*"
 
 # map dont_touch attribute commonly applied to output-nets of async regs to keep
 yosys attrmap -rename dont_touch keep
+yosys attrmap -tocase keep -imap keep="true" keep=1
 # copy the keep attribute to their driving cells (retain on net for debugging)
 yosys attrmvcp -copy -attr keep
 
@@ -77,7 +81,9 @@ yosys tee -q -o "${rep_dir}/${top_design}_initial_opt.rpt" stat
 yosys wreduce 
 yosys peepopt
 yosys opt_clean
+yosys write_verilog -norename -noexpr ${tmp_dir}/${top_design}_yosys_abstract4.v
 yosys opt -full
+yosys write_verilog -norename -noexpr ${tmp_dir}/${top_design}_yosys_abstract5.v
 yosys booth
 yosys share
 yosys opt
@@ -92,10 +98,12 @@ yosys share
 yosys opt -full
 yosys clean -purge
 
-yosys write_verilog -norename ${tmp_dir}/${top_design}_yosys_abstract.v
+yosys clean -purge
+yosys write_verilog -norename -noexpr ${tmp_dir}/${top_design}_yosys_abstract.v
 yosys tee -q -o "${rep_dir}/${top_design}_abstract.rpt" stat -tech cmos
 
 yosys techmap
+yosys write_verilog -norename -noexpr ${tmp_dir}/${top_design}_yosys_abstract3.v
 yosys opt -fast
 yosys clean -purge
 
@@ -105,7 +113,10 @@ yosys tee -q -o "${rep_dir}/${top_design}_generic.rpt" stat -tech cmos
 yosys tee -q -o "${rep_dir}/${top_design}_generic.json" stat -json -tech cmos
 
 # flatten all hierarchy except marked modules
+yosys write_verilog -norename ${tmp_dir}/${top_design}_yosys_abstract2.v
 yosys flatten
+yosys write_verilog -norename ${tmp_dir}/${top_design}_flatten.v
+# yosys opt_hier
 
 yosys clean -purge
 
@@ -116,6 +127,7 @@ yosys clean -purge
 yosys splitnets -format __v
 # rename DFFs from the driven signal
 yosys rename -wire -suffix _reg t:*DFF*
+yosys write_verilog -norename ${tmp_dir}/${top_design}_yosys_rename.v
 yosys select -write ${rep_dir}/${top_design}_registers.rpt t:*DFF*
 # rename all other cells
 yosys autoname t:*DFF* %n