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Merge pull request #7 from micprog/bender
Update dependencies and build order in Bender.yml, use non-deprecated clk_gating
2 parents 46d6ec8 + c01b6b2 commit 0336a85

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+15
-10
lines changed

2 files changed

+15
-10
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Bender.yml

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,18 +4,25 @@ package:
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- "Francesco Conti <[email protected]>"
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dependencies:
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tech_cells_generic: { git: "git@github.com:pulp-platform/tech_cells_generic.git", version: 0.1.6 }
7+
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.2 }
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sources:
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- include_dirs:
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- rtl
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files:
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- rtl/hwpe_ctrl_package.sv
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# Source files grouped in levels. Files in level 0 have no dependencies on files in this
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# package. Files in level 1 only depend on files in level 0, files in level 2 on files in
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# levels 1 and 0, etc. Files within a level are ordered alphabetically.
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# Level 0
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- rtl/hwpe_ctrl_interfaces.sv
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- rtl/hwpe_ctrl_regfile.sv
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- rtl/hwpe_ctrl_package.sv
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# Level 1
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- rtl/hwpe_ctrl_regfile_latch.sv
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- rtl/hwpe_ctrl_regfile_latch_test_wrap.sv
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- rtl/hwpe_ctrl_slave.sv
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- rtl/hwpe_ctrl_seq_mult.sv
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- rtl/hwpe_ctrl_uloop.sv
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# Level 2
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- rtl/hwpe_ctrl_regfile_latch_test_wrap.sv
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# Level 3
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- rtl/hwpe_ctrl_regfile.sv
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# Level 4
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- rtl/hwpe_ctrl_slave.sv

rtl/hwpe_ctrl_regfile_latch.sv

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -62,8 +62,7 @@ module hwpe_ctrl_regfile_latch
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genvar x;
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genvar y;
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cluster_clock_gating CG_WE_GLOBAL
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(
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tc_clk_gating CG_WE_GLOBAL (
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.clk_o ( clk_int ),
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.en_i ( WriteEnable | clear ),
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.test_en_i ( 1'b0 ),
@@ -119,8 +118,7 @@ module hwpe_ctrl_regfile_latch
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begin : CG_CELL_WORD_ITER
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for(y=0; y<NUM_BYTE; y++)
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begin : CG_CELL_BYTE_ITER
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cluster_clock_gating CG_Inst
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(
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tc_clk_gating CG_Inst (
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.clk_o(ClocksxC[x][y]),
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.en_i(WAddrOneHotxD[x][y]),
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.test_en_i(1'b0),

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