BUG? signal trx_rx_clk_reset to disable incoming RWDS clock may not work when continuous read transactions happen #23
Description
When a read transaction happens, the hyperbus receiver will create an rx_rwds_clk, which is gated by rx_rwds_clk_ena signal in src/hyperbus_trx.sv. rx_rwds_clk_ena is disabled by b_pending_clear signal generated in src/hyperbus_phy.sv.
However, b_pending_clear will only generate one pulse when a write tanscation is complete according to the source code src/hyperbus_phy.sv line 186: assign b_pending_clear = b_valid_o & b_ready_i;, that is to say, rx_rwds_clk will keep running after one read transcation until a new write transaction is complete.
This may introduce read error when two or more continuous read transactions happen. As rx_rwds_clk will be free-running after the first read transcation, rx_rwds_fifo_valid signal in src/hyperbus_trx.sv driven by rx_rwds_clk will be set to high earlier than real valid hyper_dq_i data, leading to wrong data sampling.
Possible solution: changing the assignment logic of rx_rwds_clk_ena as the following:
assign trx_rx_clk_reset = (state_q == WaitRWR);
This will disable incoming RWDS clock enable once all words received.