[treewide] Enable different RedMulE instances to share streams

Author: Andrea Belano

Bender.yml

@@ -52,7 +52,7 @@ sources:
     - rtl/redmule_reduction_unit.sv
     - rtl/redmule_mux.sv
 
-    - target: redmule_hwpe
+    - target: redmule_test_hwpe
       files:
         - rtl/redmule_wrap.sv
 

rtl/redmule_memory_scheduler.sv

@@ -286,4 +286,7 @@ module redmule_memory_scheduler
   assign cntrl_streamer_o.output_cast_dst_fmt = fpnew_pkg::fp_format_e'(reg_file_i.hwpe_params[OP_SELECTION][15:13]);
 
   assign cntrl_streamer_o.z_priority = z_priority_i;
+
+  assign cntrl_streamer_o.receive_w_stream = reg_file_i.hwpe_params[STREAM_CONF][0];
+  assign cntrl_streamer_o.receive_x_stream = reg_file_i.hwpe_params[STREAM_CONF][2];
 endmodule : redmule_memory_scheduler

rtl/redmule_pkg.sv

@@ -46,6 +46,10 @@ package redmule_pkg;
   parameter int unsigned MCFIG0 = 3; // 0x0C --> [31:16] -> K size, [15: 0] -> M size
   parameter int unsigned MCFIG1 = 4; // 0x10 --> [31: 0] -> N Size
   // Matrix arithmetic config register
+  // [20:20] -> Send X stream
+  // [19:19] -> Receive X stream
+  // [18:18] -> Send W stream
+  // [17:17] -> Receive W stream
   // [16:16] -> Reduction initialization
   // [15:14] -> Reduction operation
   // [13:13] -> PACE mode selection
@@ -103,10 +107,17 @@ package redmule_pkg;
   // [0:0]   -> init enable
   parameter int unsigned R_CONF      = 22; // 0x58
 
+  // X/W Streams configuration
+  // [3:3]   -> Send X
+  // [2:2]   -> Receive X
+  // [1:1]   -> Send W
+  // [0:0]   -> Receive W
+  parameter int unsigned STREAM_CONF = 23; // 0x5C
+
   `ifdef PACE_ENABLED
-    parameter int unsigned PACE_IN_ADDR   = 23; // 0x5C
-    parameter int unsigned PACE_OUT_ADDR  = 24; // 0x60
-    parameter int unsigned PACE_D0_LENGTH = 25; // 0x68
+    parameter int unsigned PACE_IN_ADDR   = 24; // 0x60
+    parameter int unsigned PACE_OUT_ADDR  = 25; // 0x68
+    parameter int unsigned PACE_D0_LENGTH = 26; // 0x6C
   `endif
 
   parameter bit[6:0] MCNFIG = 7'b0001011; // 0x0B
@@ -161,6 +172,8 @@ package redmule_pkg;
     fpnew_pkg::fp_format_e                  output_cast_dst_fmt;
     logic                                   z_priority;
     logic                                   pace_mode;
+    logic                                   receive_w_stream;
+    logic                                   receive_x_stream;
 `ifdef PACE_ENABLED
     hci_package::hci_streamer_ctrl_t        pace_stream_source_ctrl;
     hci_package::hci_streamer_ctrl_t        pace_stream_sink_ctrl;
@@ -367,6 +380,10 @@ package redmule_pkg;
     logic [31:0] r_addr;
     logic        red_init;
     red_op_t     red_op;
+    logic        send_w;
+    logic        receive_w;
+    logic        send_x;
+    logic        receive_x;
   } redmule_config_t;
 
   typedef enum {

rtl/redmule_streamer.sv

@@ -399,7 +399,9 @@ assign source_ctrl[RsourceStreamId]      = ctrl_i.r_stream_source_ctrl;
 
 for (genvar i = 0; i < NumStreamSources; i++) begin: gen_tcdm2stream
 
-    hci_core_assign i_load_assign ( .tcdm_target (load_fifo_d[i]), .tcdm_initiator (virt_tcdm[i]) );
+  logic source_enable;
+
+  hci_core_assign i_load_assign ( .tcdm_target (load_fifo_d[i]), .tcdm_initiator (virt_tcdm[i]) );
 
   hci_core_fifo #(
     .FIFO_DEPTH  ( 4  ), // to avoid protocol violations, as the consumer has a throughput
@@ -453,6 +455,13 @@ for (genvar i = 0; i < NumStreamSources; i++) begin: gen_tcdm2stream
   assign load_fifo_q[i].ecc      = tcdm_cast[i].ecc;
   assign tcdm_cast[i].r_ecc      = load_fifo_q[i].r_ecc;
 
+  if (i == WsourceStreamId) begin
+    assign source_enable = enable_i & ~ctrl_i.receive_w_stream;
+  end else if (i == XsourceStreamId) begin
+    assign source_enable = enable_i & ~ctrl_i.receive_x_stream;
+  end else begin
+    assign source_enable = enable_i;
+  end
 
   hci_core_source       #(
     .MISALIGNED_ACCESSES   ( REALIGN                    ),
@@ -462,7 +471,7 @@ for (genvar i = 0; i < NumStreamSources; i++) begin: gen_tcdm2stream
     .rst_ni              ( rst_ni          ),
     .test_mode_i         ( test_mode_i     ),
     .clear_i             ( clear_i         ),
-    .enable_i            ( enable_i        ),
+    .enable_i            ( source_enable   ),
     .tcdm                ( tcdm_cast[i]    ),
     .stream              ( out_stream[i]   ),
     .ctrl_i              ( source_ctrl[i]  ),

rtl/redmule_tiler.sv

@@ -63,6 +63,10 @@ assign config_d.gemm_output_fmt = gemm_fmt_e'(reg_file_i.hwpe_params[MACFG][ 9:
 assign config_d.r_addr          = reg_file_i.hwpe_params[R_ADDR_R];
 assign config_d.red_init        = reg_file_i.hwpe_params[MACFG][16];
 assign config_d.red_op          = red_op_t'(reg_file_i.hwpe_params[MACFG][15:14]);
+assign config_d.receive_w       = reg_file_i.hwpe_params[MACFG][17];
+assign config_d.send_w          = reg_file_i.hwpe_params[MACFG][18];
+assign config_d.receive_x       = reg_file_i.hwpe_params[MACFG][19];
+assign config_d.send_x          = reg_file_i.hwpe_params[MACFG][20];
 
 // Calculating the number of iterations alng the two dimensions of the X matrix
 logic [15:0] x_rows_iter_nolftovr;
@@ -281,6 +285,10 @@ assign reg_file_o.hwpe_params[K_SIZE]              = config_d.k_size;
 assign reg_file_o.hwpe_params[R_ADDR]              = config_d.r_addr;
 assign reg_file_o.hwpe_params[R_CONF][0]           = config_d.red_init;
 assign reg_file_o.hwpe_params[R_CONF][2:1]         = config_d.red_op;
+assign reg_file_o.hwpe_params[STREAM_CONF][0]      = config_d.receive_w;
+assign reg_file_o.hwpe_params[STREAM_CONF][1]      = config_d.send_w;
+assign reg_file_o.hwpe_params[STREAM_CONF][2]      = config_d.receive_x;
+assign reg_file_o.hwpe_params[STREAM_CONF][3]      = config_d.send_x;
 `ifdef PACE_ENABLED
   assign reg_file_o.hwpe_params[OP_SELECTION][ 9: 2] = '0;
   assign reg_file_o.hwpe_params[OP_SELECTION][0]     = config_q.gemm_selection;

rtl/redmule_top.sv

@@ -35,6 +35,14 @@ module redmule_top
   input  logic                    test_mode_i,
   output logic                    busy_o     ,
   output logic [N_CORES-1:0][1:0] evt_o      ,
+  // External W stream
+  hwpe_stream_intf_stream.sink    w_stream_i ,
+  // External X stream
+  hwpe_stream_intf_stream.sink    x_stream_i ,
+  // Broadcasted W stream
+  hwpe_stream_intf_stream.source  w_stream_o ,
+  // Broadcasted X stream
+  hwpe_stream_intf_stream.source  x_stream_o ,
   // Periph slave port for the controller side
   hwpe_ctrl_intf_periph.slave periph,
   // TCDM master ports for the memory side
@@ -103,10 +111,12 @@ flgs_red_t red_flags;
 // Implementation of the incoming and outgoing streaming interfaces (one for each kind of data)
 
 // X streaming interface + X FIFO interface
+hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) x_stream_str       ( .clk( clk_i ) );
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) x_buffer_d         ( .clk( clk_i ) );
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) x_buffer_fifo      ( .clk( clk_i ) );
 
 // W streaming interface + W FIFO interface
+hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) w_stream_str       ( .clk( clk_i ) );
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) w_buffer_d         ( .clk( clk_i ) );
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) w_buffer_fifo      ( .clk( clk_i ) );
 
@@ -147,8 +157,8 @@ redmule_streamer #(
   .enable_i        ( 1'b1            ),
   .clear_i         ( clear           ),
   // Source interfaces for the incoming streams
-  .x_stream_o      ( x_buffer_d      ),
-  .w_stream_o      ( w_buffer_d      ),
+  .x_stream_o      ( x_stream_str    ),
+  .w_stream_o      ( w_stream_str    ),
   .y_stream_o      ( y_buffer_d      ),
   .r_stream_o      ( red_init_d      ),
   // Sink interface for the outgoing stream
@@ -165,6 +175,38 @@ redmule_streamer #(
   .flags_o         ( flgs_streamer   )
 );
 
+logic w_sel;
+logic w_send;
+
+assign w_sel  = reg_file.hwpe_params[STREAM_CONF][0];
+assign w_send = reg_file.hwpe_params[STREAM_CONF][1];
+
+assign w_buffer_d.valid   = ((w_sel) ? w_stream_i.valid : w_stream_str.valid) && ((w_send) ? w_stream_o.ready && w_buffer_d.ready : 1'b1);
+assign w_buffer_d.data    = (w_sel) ? w_stream_i.data  : w_stream_str.data;
+assign w_buffer_d.strb    = (w_sel) ? w_stream_i.strb  : w_stream_str.strb;
+assign w_stream_str.ready = (w_sel) ? 1'b0             : w_buffer_d.ready && ((w_send) ? w_stream_o.ready : 1'b1);
+assign w_stream_i.ready   = (w_sel) ? w_buffer_d.ready : 1'b0;
+
+assign w_stream_o.valid = (w_send) ? w_buffer_d.valid : 1'b0;
+assign w_stream_o.data  = (w_send) ? w_buffer_d.data : '0;
+assign w_stream_o.strb  = (w_send) ? w_buffer_d.strb : '0;
+
+logic x_sel;
+logic x_send;
+
+assign x_sel  = reg_file.hwpe_params[STREAM_CONF][2];
+assign x_send =  reg_file.hwpe_params[STREAM_CONF][3];
+
+assign x_buffer_d.valid   = ((x_sel) ? x_stream_i.valid : x_stream_str.valid) && ((x_send) ? x_stream_o.ready && x_buffer_d.ready : 1'b1);
+assign x_buffer_d.data    = (x_sel) ? x_stream_i.data  : x_stream_str.data;
+assign x_buffer_d.strb    = (x_sel) ? x_stream_i.strb  : x_stream_str.strb;
+assign x_stream_str.ready = (x_sel) ? 1'b0             : x_buffer_d.ready && ((x_send) ? x_stream_o.ready : 1'b1);
+assign x_stream_i.ready   = (x_sel) ? x_buffer_d.ready : 1'b0;
+
+assign x_stream_o.valid = (x_send) ? x_buffer_d.valid : 1'b0;
+assign x_stream_o.data  = (x_send) ? x_buffer_d.data : '0;
+assign x_stream_o.strb  = (x_send) ? x_buffer_d.strb : '0;
+
 hwpe_stream_fifo #(
   .DATA_WIDTH     ( DATAW_ALIGN   ),
   .FIFO_DEPTH     ( 4             )
@@ -331,7 +373,7 @@ redmule_z_buffer #(
 cntrl_red_t red_ctrl;
 
 assign red_ctrl.row_len = reg_file.hwpe_params[K_SIZE];
-assign red_ctrl.op      = reg_file.hwpe_params[R_CONF][2:1];
+assign red_ctrl.op      = red_op_t'(reg_file.hwpe_params[R_CONF][2:1]);
 assign red_ctrl.load    = reg_file.hwpe_params[R_CONF][0];
 assign red_ctrl.enable  = busy_o;
 assign red_ctrl.ready   = red_out_q.ready;

rtl/redmule_wrap.sv

@@ -184,6 +184,65 @@ logic [N_CORES-1:0][1:0] evt;
   assign periph_r_id_o    = periph.r_id;
 `endif
 
+hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW ) ) w_stream_i ( .clk( clk_i ) );
+hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW ) ) w_stream_o ( .clk( clk_i ) );
+hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW ) ) x_stream_i ( .clk( clk_i ) );
+hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW ) ) x_stream_o ( .clk( clk_i ) );
+
+logic w_stream_ready, x_stream_ready;
+logic w_stream_valid, x_stream_valid;
+
+assign w_stream_i.valid = w_stream_valid;
+assign w_stream_i.data  = '1;
+assign w_stream_i.strb  = '1;
+
+assign x_stream_i.valid = x_stream_valid;
+assign x_stream_i.data  = '1;
+assign x_stream_i.strb  = '1;
+
+assign w_stream_o.ready = w_stream_ready;
+assign x_stream_o.ready = x_stream_ready;
+
+always_ff @(posedge clk_i, negedge rst_ni) begin
+  if (~rst_ni) begin
+    w_stream_valid <= '0;
+  end else begin
+    if (w_stream_i.ready && w_stream_i.valid || ~w_stream_i.valid) begin
+      w_stream_valid <= $urandom_range(1, 0);
+    end
+  end
+end
+
+always_ff @(posedge clk_i, negedge rst_ni) begin
+  if (~rst_ni) begin
+    x_stream_valid <= '0;
+  end else begin
+    if (x_stream_i.ready && x_stream_i.valid || ~x_stream_o.valid) begin
+      x_stream_valid <= $urandom_range(1, 0);
+    end
+  end
+end
+
+always_ff @(posedge clk_i, negedge rst_ni) begin
+  if (~rst_ni) begin
+    w_stream_ready <= '0;
+  end else begin
+    if (w_stream_o.ready && w_stream_o.valid || ~w_stream_o.ready) begin
+      w_stream_ready <= $urandom_range(1, 0);
+    end
+  end
+end
+
+always_ff @(posedge clk_i, negedge rst_ni) begin
+  if (~rst_ni) begin
+    x_stream_ready <= '0;
+  end else begin
+    if (x_stream_o.ready && x_stream_o.valid || ~x_stream_o.ready) begin
+      x_stream_ready <= $urandom_range(1, 0);
+    end
+  end
+end
+
 redmule_top #(
   .ID_WIDTH              ( ID_WIDTH              ),
   .N_CORES               ( N_CORES               ),
@@ -198,6 +257,10 @@ redmule_top #(
   .test_mode_i        ( test_mode_i        ),
   .evt_o              ( evt_o              ),
   .busy_o             ( busy_o             ),
+  .w_stream_i         ( w_stream_i         ),
+  .w_stream_o         ( w_stream_o         ),
+  .x_stream_i         ( x_stream_i         ),
+  .x_stream_o         ( x_stream_o         ),
   .tcdm               ( tcdm               ),
   .periph             ( periph             )
 );