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Andrea Belano
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[instruction decoder] Make the system more flexible and return operation ID
1 parent 616b833 commit 08c2ac2

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2 files changed

+122
-62
lines changed

2 files changed

+122
-62
lines changed

‎rtl/redmule_inst_decoder.sv‎

Lines changed: 58 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ module redmule_inst_decoder
99
import redmule_pkg::*;
1010
#(
1111
parameter int unsigned InstFifoDepth = 4,
12+
parameter int unsigned OpIdWidth = 4,
1213
parameter int unsigned XifIdWidth = 4,
1314
parameter int unsigned XifNumHarts = 1,
1415
parameter int unsigned XifIssueRegisterSplit = 0,
@@ -21,8 +22,9 @@ module redmule_inst_decoder
2122
input logic clk_i,
2223
input logic rst_ni,
2324
input logic clear_i,
24-
input logic busy_i,
25+
input logic config_ready_i,
2526
input logic tiler_done_i,
27+
input logic op_done_i,
2628
output logic config_valid_o,
2729
output redmule_config_t config_o,
2830
input x_issue_req_t x_issue_req_i,
@@ -48,6 +50,10 @@ module redmule_inst_decoder
4850
x_issue_req_t [XifNumHarts-1:0] cur_issue;
4951
x_register_t [XifNumHarts-1:0] cur_register;
5052

53+
x_result_t x_result_d, x_result_q;
54+
55+
logic [XifNumHarts-1:0] [OpIdWidth-1:0] op_id_counter_in_q, op_id_counter_out_q;
56+
5157
logic [HartIdWidth-1:0] rr_counter_d, rr_counter_q;
5258
logic [XifNumHarts-1:0][HartIdWidth-1:0] rr_priority;
5359
logic [HartIdWidth-1:0] winner;
@@ -57,7 +63,6 @@ module redmule_inst_decoder
5763
redmule_config_t [XifNumHarts-1:0] config_d, config_q;
5864

5965
logic pop_enable;
60-
logic busy_q;
6166

6267
always_comb begin : legal_inst_assignment
6368
legal_inst = 1'b0;
@@ -69,18 +74,18 @@ module redmule_inst_decoder
6974
end
7075

7176
assign x_issue_resp_o.accept = legal_inst;
72-
assign x_issue_resp_o.writeback = '0; // We never perform writebacks
77+
assign x_issue_resp_o.writeback = x_issue_req_i.instr[6:0] == MARITH;
7378
assign x_issue_resp_o.register_read = 7; // We always read 3 registers
7479

75-
assign x_result_valid_o = ~issue_fifo_empty[winner] && ~register_fifo_empty[winner] && x_result_ready_i;
80+
assign x_result_valid_o = ~issue_fifo_empty[winner] && ~register_fifo_empty[winner];
7681
assign x_result_o.hartid = cur_issue[winner].hartid;
7782
assign x_result_o.id = cur_issue[winner].id;
78-
assign x_result_o.data = '0;
79-
assign x_result_o.rd = '0;
80-
assign x_result_o.we = '0;
83+
assign x_result_o.data = op_id_counter_in_q[winner];
84+
assign x_result_o.rd = cur_issue[winner].instr[11:7];
85+
assign x_result_o.we = cur_issue[winner].instr[6:0] == MARITH;
8186

8287
assign config_o = config_d[winner];
83-
assign config_valid_o = ~busy_i && ~issue_fifo_empty[winner] && ~register_fifo_empty[winner] && x_result_ready_i && cur_issue[winner].instr[6:0] == MARITH;
88+
assign config_valid_o = ~issue_fifo_empty[winner] && ~register_fifo_empty[winner] && x_result_ready_i && cur_issue[winner].instr[6:0] == MARITH;
8489

8590
always_comb begin : x_issue_ready_assignment
8691
x_issue_ready_o = 1'b0;
@@ -108,7 +113,7 @@ module redmule_inst_decoder
108113
end else begin
109114
if (clear_i) begin
110115
rr_counter_q <= '0;
111-
end else if (tiler_done_i/*~busy_i && ~config_valid_o && |(~issue_fifo_empty & ~register_fifo_empty)*/) begin
116+
end else if (config_ready_i && config_valid_o) begin
112117
rr_counter_q <= rr_counter_d;
113118
end
114119
end
@@ -132,20 +137,52 @@ module redmule_inst_decoder
132137
end
133138
end
134139

135-
always_ff @(posedge clk_i, negedge rst_ni) begin : busy_delay
136-
if(~rst_ni) begin
137-
busy_q <= '0;
138-
end else begin
139-
if (clear_i) begin
140-
busy_q <= '0;
140+
fifo_v3 #(
141+
.FALL_THROUGH ( 0 ),
142+
.DEPTH ( InstFifoDepth * XifNumHarts ),
143+
.DATA_WIDTH ( HartIdWidth )
144+
) i_current_hartid_fifo (
145+
.clk_i ( clk_i ),
146+
.rst_ni ( rst_ni ),
147+
.flush_i ( clear_i ),
148+
.testmode_i ( '0 ),
149+
.full_o ( ),
150+
.empty_o ( ),
151+
.usage_o ( ),
152+
.data_i ( winner ),
153+
.push_i ( config_ready_i && config_valid_o ),
154+
.data_o ( current_hartid_q ),
155+
.pop_i ( op_done_i )
156+
);
157+
158+
for (genvar i = 0; i < XifNumHarts; i++) begin : gen_op_id_counters
159+
always_ff @(posedge clk_i or negedge rst_ni) begin : op_id_counter_in
160+
if (~rst_ni) begin
161+
op_id_counter_in_q[i] <= 0;
141162
end else begin
142-
busy_q <= busy_i;
163+
if (clear_i) begin
164+
op_id_counter_in_q[i] <= 0;
165+
end else if (winner == i && x_result_ready_i && x_result_valid_o && cur_issue[i].instr[6:0] == MARITH) begin
166+
op_id_counter_in_q[i] <= op_id_counter_in_q[i] + 1;
167+
end
168+
end
169+
end
170+
171+
always_ff @(posedge clk_i or negedge rst_ni) begin : op_id_counter_out
172+
if (~rst_ni) begin
173+
op_id_counter_out_q[i] <= '1;
174+
end else begin
175+
if (clear_i) begin
176+
op_id_counter_out_q[i] <= '1;
177+
end else if (current_hartid_q == i && op_done_i) begin
178+
op_id_counter_out_q[i] <= op_id_counter_out_q[i] + 1;
179+
end
143180
end
144181
end
145182
end
146183

147184
// Pop the fifos the first cycle the tiler is no longer busy if we detect a MARITH instruction
148-
assign pop_enable = (cur_issue[winner].instr[6:0] == MARITH ? tiler_done_i : 1'b1);
185+
assign pop_enable = (cur_issue[winner].instr[6:0] == MARITH ? config_ready_i && config_valid_o : 1'b1);
149186

150187
for (genvar i = 0; i < XifNumHarts; i++) begin : gen_instruction_fifos
151188

@@ -224,7 +261,7 @@ module redmule_inst_decoder
224261

225262
assign fifo_flush = cur_issue[i].id == kill_id_d && kill_id_valid_d && ~issue_fifo_empty[i];
226263

227-
assign issue_push = x_issue_valid_i & legal_inst & x_commit_i.hartid == i;
264+
assign issue_push = x_issue_valid_i && legal_inst && ~issue_fifo_full[i] && x_commit_i.hartid == i;
228265
assign issue_pop = winner == i && pop_enable && x_result_ready_i && ~issue_fifo_empty[i] && ~register_fifo_empty[i];
229266
assign register_pop = issue_pop;
230267

@@ -304,9 +341,10 @@ module redmule_inst_decoder
304341
config_d[i].x_addr = cur_register[i].rs[0][31:0];
305342
config_d[i].w_addr = cur_register[i].rs[1][31:0];
306343
config_d[i].z_addr = cur_register[i].rs[2][31:0];
344+
// TODO: These are fixed for now
307345
config_d[i].gemm_ops = GEMM;
308-
config_d[i].gemm_input_fmt = cur_issue[i].instr[9:7];
309-
config_d[i].gemm_output_fmt = cur_issue[i].instr[9:7];
346+
config_d[i].gemm_input_fmt = redmule_pkg::Float16;
347+
config_d[i].gemm_output_fmt = redmule_pkg::Float16;
310348
end
311349
endcase
312350
end

‎rtl/redmule_top.sv‎

Lines changed: 64 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -125,11 +125,13 @@ flgs_red_t red_flags;
125125
redmule_config_t dec_config;
126126
logic dec_config_valid;
127127

128+
logic config_fifo_empty, config_fifo_full;
129+
128130
tc_clk_gating i_acc_clock_gating (
129-
.clk_i ( clk_i ),
130-
.en_i ( dec_config_valid | busy_o ),
131-
.test_en_i ( '0 ),
132-
.clk_o ( clk_acc )
131+
.clk_i ( clk_i ),
132+
.en_i ( dec_config_valid | config_fifo_empty | busy_o ),
133+
.test_en_i ( '0 ),
134+
.clk_o ( clk_acc )
133135
);
134136

135137
/*--------------------------------------------------------------*/
@@ -566,6 +568,7 @@ redmule_memory_scheduler #(
566568
/*---------------------------------------------------------------*/
567569

568570
logic tiler_busy;
571+
redmule_config_t dec_config_q;
569572

570573
redmule_inst_decoder #(
571574
.InstFifoDepth ( 4 ),
@@ -578,25 +581,44 @@ redmule_inst_decoder #(
578581
.x_commit_t ( x_commit_t ),
579582
.x_result_t ( x_result_t )
580583
) i_inst_decoder (
581-
.clk_i ( clk_i ),
582-
.rst_ni ( rst_ni ),
583-
.clear_i ( '0 ),
584-
.busy_i ( tiler_busy ),
585-
.tiler_done_i ( cfg_complete ),
586-
.config_valid_o ( dec_config_valid ),
587-
.config_o ( dec_config ),
588-
.x_issue_req_i ( x_issue_req_i ),
589-
.x_issue_resp_o ( x_issue_resp_o ),
590-
.x_issue_valid_i ( x_issue_valid_i ),
591-
.x_issue_ready_o ( x_issue_ready_o ),
592-
.x_register_i ( x_register_i ),
593-
.x_register_valid_i ( x_register_valid_i ),
594-
.x_register_ready_o ( x_register_ready_o ),
595-
.x_commit_i ( x_commit_i ),
596-
.x_commit_valid_i ( x_commit_valid_i ),
597-
.x_result_o ( x_result_o ),
598-
.x_result_valid_o ( x_result_valid_o ),
599-
.x_result_ready_i ( x_result_ready_i )
584+
.clk_i ( clk_i ),
585+
.rst_ni ( rst_ni ),
586+
.clear_i ( '0 ),
587+
.config_ready_i ( ~config_fifo_full ),
588+
.tiler_done_i ( /*cfg_complete*/ ),
589+
.op_done_i ( flgs_streamer.z_stream_sink_flags.done ),
590+
.config_valid_o ( dec_config_valid ),
591+
.config_o ( dec_config ),
592+
.x_issue_req_i ( x_issue_req_i ),
593+
.x_issue_resp_o ( x_issue_resp_o ),
594+
.x_issue_valid_i ( x_issue_valid_i ),
595+
.x_issue_ready_o ( x_issue_ready_o ),
596+
.x_register_i ( x_register_i ),
597+
.x_register_valid_i ( x_register_valid_i ),
598+
.x_register_ready_o ( x_register_ready_o ),
599+
.x_commit_i ( x_commit_i ),
600+
.x_commit_valid_i ( x_commit_valid_i ),
601+
.x_result_o ( x_result_o ),
602+
.x_result_valid_o ( x_result_valid_o ),
603+
.x_result_ready_i ( x_result_ready_i )
604+
);
605+
606+
fifo_v3 #(
607+
.FALL_THROUGH ( 0 ),
608+
.DEPTH ( 2 ),
609+
.dtype ( redmule_config_t )
610+
) i_config_fifo (
611+
.clk_i ( clk_acc ),
612+
.rst_ni ( rst_ni ),
613+
.flush_i ( clear ),
614+
.testmode_i ( '0 ),
615+
.full_o ( config_fifo_full ),
616+
.empty_o ( config_fifo_empty ),
617+
.usage_o ( ),
618+
.data_i ( dec_config ),
619+
.push_i ( dec_config_valid ),
620+
.data_o ( dec_config_q ),
621+
.pop_i ( cfg_complete )
600622
);
601623

602624
/*---------------------------------------------------------------*/
@@ -613,25 +635,25 @@ redmule_ctrl #(
613635
.Width ( Width ),
614636
.NumPipeRegs ( NumPipeRegs )
615637
) i_control (
616-
.clk_i ( clk_acc ),
617-
.rst_ni ( rst_ni ),
618-
.test_mode_i ( test_mode_i ),
619-
.flgs_streamer_i ( flgs_streamer ),
620-
.busy_o ( busy_o ),
621-
.tiler_busy_o ( tiler_busy ),
622-
.clear_o ( clear ),
623-
.evt_o ( evt_o ),
624-
.config_i ( dec_config ),
625-
.config_o ( redmule_config ),
626-
.reg_enable_i ( reg_enable ),
627-
.fifo_empty_i ( z_fifo_empty ),
628-
.fifo_ready_i ( ~z_fifo_full ),
629-
.start_cfg_i ( dec_config_valid ),
630-
.cfg_complete_o ( cfg_complete ),
631-
.w_loaded_i ( flgs_scheduler.w_loaded ),
632-
.flush_o ( engine_flush ),
633-
.cntrl_scheduler_o ( cntrl_scheduler ),
634-
.cntrl_flags_o ( cntrl_flags )
638+
.clk_i ( clk_acc ),
639+
.rst_ni ( rst_ni ),
640+
.test_mode_i ( test_mode_i ),
641+
.flgs_streamer_i ( flgs_streamer ),
642+
.busy_o ( busy_o ),
643+
.tiler_busy_o ( tiler_busy ),
644+
.clear_o ( clear ),
645+
.evt_o ( evt_o ),
646+
.config_i ( dec_config_q ),
647+
.config_o ( redmule_config ),
648+
.reg_enable_i ( reg_enable ),
649+
.fifo_empty_i ( z_fifo_empty ),
650+
.fifo_ready_i ( ~z_fifo_full ),
651+
.start_cfg_i ( ~config_fifo_empty ),
652+
.cfg_complete_o ( cfg_complete ),
653+
.w_loaded_i ( flgs_scheduler.w_loaded ),
654+
.flush_o ( engine_flush ),
655+
.cntrl_scheduler_o ( cntrl_scheduler ),
656+
.cntrl_flags_o ( cntrl_flags )
635657
);
636658

637659

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