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Andrea Belano
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[redmule_top] implement clock-gate with XIF
1 parent 5749e6a commit 3cf63f3

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+54
-47
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1 file changed

+54
-47
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‎rtl/redmule_top.sv‎

Lines changed: 54 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,8 @@ module redmule_top
7171

7272
localparam int unsigned DATAW_ALIGN = DATAW;
7373

74+
logic clk_acc;
75+
7476
logic fsm_z_clk_en, ctrl_z_clk_en;
7577
logic enable, clear;
7678
logic y_buffer_depth_count,
@@ -81,7 +83,7 @@ logic w_shift;
8183
logic w_load;
8284
logic reg_enable,
8385
gate_en;
84-
logic start_cfg, cfg_complete;
86+
logic cfg_complete;
8587
logic [31:0] x_cols_offs,
8688
x_rows_offs;
8789
logic [$clog2(Width):0] x_rows_lftover;
@@ -90,8 +92,6 @@ logic [$clog2(TOT_DEPTH):0] w_cols_lftovr,
9092
logic [$clog2(Height):0] w_rows_lftovr;
9193
logic [$clog2(Width):0] y_rows_lftovr;
9294

93-
assign start_cfg = '0; // TODO make this signal XIF-related
94-
9595
// Streamer control signals and flags
9696
cntrl_streamer_t cntrl_streamer_int, cntrl_streamer;
9797
flgs_streamer_t flgs_streamer;
@@ -122,44 +122,54 @@ cntrl_flags_t cntrl_flags;
122122

123123
flgs_red_t red_flags;
124124

125+
redmule_config_t dec_config;
126+
logic dec_config_valid;
127+
128+
tc_clk_gating i_acc_clock_gating (
129+
.clk_i ( clk_i ),
130+
.en_i ( dec_config_valid | busy_o ),
131+
.test_en_i ( '0 ),
132+
.clk_o ( clk_acc )
133+
);
134+
125135
/*--------------------------------------------------------------*/
126136
/* | Streamer | */
127137
/*--------------------------------------------------------------*/
128138

129139
// Implementation of the incoming and outgoing streaming interfaces (one for each kind of data)
130140

131141
// X streaming interface + X FIFO interface
132-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) x_stream_str ( .clk( clk_i ) );
133-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) x_buffer_d ( .clk( clk_i ) );
134-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) x_buffer_fifo ( .clk( clk_i ) );
142+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) x_stream_str ( .clk( clk_acc ) );
143+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) x_buffer_d ( .clk( clk_acc ) );
144+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) x_buffer_fifo ( .clk( clk_acc ) );
135145

136146
// W streaming interface + W FIFO interface
137-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) w_stream_str ( .clk( clk_i ) );
138-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) w_buffer_d ( .clk( clk_i ) );
139-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) w_buffer_fifo ( .clk( clk_i ) );
147+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) w_stream_str ( .clk( clk_acc ) );
148+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) w_buffer_d ( .clk( clk_acc ) );
149+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) w_buffer_fifo ( .clk( clk_acc ) );
140150

141151
// Y streaming interface + Y FIFO interface
142-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) y_buffer_d ( .clk( clk_i ) );
143-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) y_buffer_fifo ( .clk( clk_i ) );
152+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) y_buffer_d ( .clk( clk_acc ) );
153+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) y_buffer_fifo ( .clk( clk_acc ) );
144154

145155
// R streaming interface + R FIFO interface
146-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) red_init_d ( .clk( clk_i ) );
147-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) red_init_fifo ( .clk( clk_i ) );
156+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) red_init_d ( .clk( clk_acc ) );
157+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) red_init_fifo ( .clk( clk_acc ) );
148158

149159
// Z streaming interface + Z FIFO interface
150-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) z_buffer_q ( .clk( clk_i ) );
151-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) z_buffer_fifo ( .clk( clk_i ) );
160+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) z_buffer_q ( .clk( clk_acc ) );
161+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) z_buffer_fifo ( .clk( clk_acc ) );
152162

153163
// R streaming interface + R FIFO interface
154-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) red_out_q ( .clk( clk_i ) );
155-
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) red_out_fifo ( .clk( clk_i ) );
164+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) red_out_q ( .clk( clk_acc ) );
165+
hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) red_out_fifo ( .clk( clk_acc ) );
156166

157167
// The streamer will present a single master TCDM port used to stream data to and from the memeory.
158168
redmule_streamer #(
159169
.DW ( DW ),
160170
.`HCI_SIZE_PARAM(tcdm) ( `HCI_SIZE_PARAM(tcdm) )
161171
) i_streamer (
162-
.clk_i ( clk_i ),
172+
.clk_i ( clk_acc ),
163173
.rst_ni ( rst_ni ),
164174
.test_mode_i ( test_mode_i ),
165175
// Controller generated signals
@@ -215,7 +225,7 @@ hwpe_stream_fifo #(
215225
.DATA_WIDTH ( DATAW_ALIGN ),
216226
.FIFO_DEPTH ( 4 )
217227
) i_x_buffer_fifo (
218-
.clk_i ( clk_i ),
228+
.clk_i ( clk_acc ),
219229
.rst_ni ( rst_ni ),
220230
.clear_i ( clear ),
221231
.flags_o ( ),
@@ -227,7 +237,7 @@ hwpe_stream_fifo #(
227237
.DATA_WIDTH ( DATAW_ALIGN ),
228238
.FIFO_DEPTH ( 4 )
229239
) i_w_buffer_fifo (
230-
.clk_i ( clk_i ),
240+
.clk_i ( clk_acc ),
231241
.rst_ni ( rst_ni ),
232242
.clear_i ( clear ),
233243
.flags_o ( w_fifo_flgs ),
@@ -239,7 +249,7 @@ hwpe_stream_fifo #(
239249
.DATA_WIDTH ( DATAW_ALIGN ),
240250
.FIFO_DEPTH ( 2 )
241251
) i_red_init_fifo (
242-
.clk_i ( clk_i ),
252+
.clk_i ( clk_acc ),
243253
.rst_ni ( rst_ni ),
244254
.clear_i ( clear ),
245255
.flags_o ( ),
@@ -251,7 +261,7 @@ hwpe_stream_fifo #(
251261
.DATA_WIDTH ( DATAW_ALIGN ),
252262
.FIFO_DEPTH ( 4 )
253263
) i_y_buffer_fifo (
254-
.clk_i ( clk_i ),
264+
.clk_i ( clk_acc ),
255265
.rst_ni ( rst_ni ),
256266
.clear_i ( clear ),
257267
.flags_o ( ),
@@ -263,7 +273,7 @@ hwpe_stream_fifo #(
263273
.DATA_WIDTH ( DATAW_ALIGN ),
264274
.FIFO_DEPTH ( 2 )
265275
) i_z_buffer_fifo (
266-
.clk_i ( clk_i ),
276+
.clk_i ( clk_acc ),
267277
.rst_ni ( rst_ni ),
268278
.clear_i ( clear ),
269279
.flags_o ( z_fifo_flgs ),
@@ -275,7 +285,7 @@ hwpe_stream_fifo #(
275285
.DATA_WIDTH ( DATAW_ALIGN ),
276286
.FIFO_DEPTH ( 2 )
277287
) i_red_out_fifo (
278-
.clk_i ( clk_i ),
288+
.clk_i ( clk_acc ),
279289
.rst_ni ( rst_ni ),
280290
.clear_i ( clear ),
281291
.flags_o ( ),
@@ -302,13 +312,13 @@ redmule_x_buffer #(
302312
.Height ( Height ),
303313
.Width ( Width )
304314
) i_x_buffer (
305-
.clk_i ( clk_i ),
306-
.rst_ni ( rst_ni ),
307-
.clear_i ( clear ),
308-
.ctrl_i ( x_buffer_ctrl ),
309-
.flags_o ( x_buffer_flgs ),
310-
.x_buffer_o ( x_buffer_q ),
311-
.x_buffer_i ( x_buffer_fifo.data )
315+
.clk_i ( clk_acc ),
316+
.rst_ni ( rst_ni ),
317+
.clear_i ( clear ),
318+
.ctrl_i ( x_buffer_ctrl ),
319+
.flags_o ( x_buffer_flgs ),
320+
.x_buffer_o ( x_buffer_q ),
321+
.x_buffer_i ( x_buffer_fifo.data )
312322
);
313323

314324
logic [Height-1:0][BITW-1:0] w_buffer_q;
@@ -318,13 +328,13 @@ redmule_w_buffer #(
318328
.FpFormat ( FpFormat ),
319329
.Height ( Height )
320330
) i_w_buffer (
321-
.clk_i ( clk_i ),
322-
.rst_ni ( rst_ni ),
323-
.clear_i ( clear ),
324-
.ctrl_i ( w_buffer_ctrl ),
325-
.flags_o ( w_buffer_flgs ),
326-
.w_buffer_o ( w_buffer_q ),
327-
.w_buffer_i ( w_buffer_fifo.data )
331+
.clk_i ( clk_acc ),
332+
.rst_ni ( rst_ni ),
333+
.clear_i ( clear ),
334+
.ctrl_i ( w_buffer_ctrl ),
335+
.flags_o ( w_buffer_flgs ),
336+
.w_buffer_o ( w_buffer_q ),
337+
.w_buffer_i ( w_buffer_fifo.data )
328338
);
329339

330340
logic [Width-1:0][BITW-1:0] z_buffer_d, y_bias_q;
@@ -333,7 +343,7 @@ redmule_z_buffer #(
333343
.FpFormat ( FpFormat ),
334344
.Width ( Width )
335345
) i_z_buffer (
336-
.clk_i ( clk_i ),
346+
.clk_i ( clk_acc ),
337347
.rst_ni ( rst_ni ),
338348
.clear_i ( clear ),
339349
.reg_enable_i ( reg_enable ),
@@ -451,7 +461,7 @@ redmule_engine #(
451461
.NumPipeRegs ( NumPipeRegs ),
452462
.PipeConfig ( PipeConfig )
453463
) i_redmule_engine (
454-
.clk_i ( clk_i ),
464+
.clk_i ( clk_acc ),
455465
.rst_ni ( rst_ni ),
456466
.x_input_i ( x_buffer_q ),
457467
.w_input_i ( w_buffer_q ),
@@ -493,7 +503,7 @@ redmule_memory_scheduler #(
493503
.W ( Width ),
494504
.H ( Height )
495505
) i_memory_scheduler (
496-
.clk_i ( clk_i ),
506+
.clk_i ( clk_acc ),
497507
.rst_ni ( rst_ni ),
498508
.clear_i ( clear ),
499509
.z_priority_i ( z_priority ),
@@ -508,9 +518,6 @@ redmule_memory_scheduler #(
508518
/* | Instruction Decoder | */
509519
/*---------------------------------------------------------------*/
510520

511-
redmule_config_t dec_config;
512-
logic dec_config_valid;
513-
514521
redmule_inst_decoder #(
515522
.InstFifoDepth ( 4 ),
516523
.XifIdWidth ( XifIdWidth ),
@@ -522,7 +529,7 @@ redmule_inst_decoder #(
522529
.x_commit_t ( x_commit_t ),
523530
.x_result_t ( x_result_t )
524531
) i_inst_decoder (
525-
.clk_i ( clk_i ),
532+
.clk_i ( clk_acc ),
526533
.rst_ni ( rst_ni ),
527534
.clear_i ( '0 ),
528535
.busy_i ( busy_o ),
@@ -556,7 +563,7 @@ redmule_ctrl #(
556563
.Width ( Width ),
557564
.NumPipeRegs ( NumPipeRegs )
558565
) i_control (
559-
.clk_i ( clk_i ),
566+
.clk_i ( clk_acc ),
560567
.rst_ni ( rst_ni ),
561568
.test_mode_i ( test_mode_i ),
562569
.flgs_streamer_i ( flgs_streamer ),
@@ -583,7 +590,7 @@ redmule_scheduler #(
583590
.Width ( Width ),
584591
.NumPipeRegs ( NumPipeRegs )
585592
) i_scheduler (
586-
.clk_i ( clk_i ),
593+
.clk_i ( clk_acc ),
587594
.rst_ni ( rst_ni ),
588595
.test_mode_i ( test_mode_i ),
589596
.clear_i ( clear ),

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