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Commit 50b3447

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author
Andrea Belano
committed
[treewide] Initial support for XIF v1.0.0
1 parent 8e6e3eb commit 50b3447

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5 files changed

+385
-266
lines changed

5 files changed

+385
-266
lines changed

Bender.yml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ sources:
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- rtl/redmule_memory_scheduler.sv
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- rtl/redmule_reduction_unit.sv
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- rtl/redmule_mux.sv
54+
- rtl/redmule_inst_decoder.sv
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- target: redmule_test_hwpe
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files:

rtl/redmule_ctrl.sv

Lines changed: 8 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,8 @@ module redmule_ctrl
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output logic busy_o ,
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output logic clear_o ,
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output logic [N_CORES-1:0][1:0] evt_o ,
30-
output redmule_config_t config_o ,
30+
input redmule_config_t config_i ,
31+
output redmule_config_t config_o ,
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input logic reg_enable_i ,
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input logic start_cfg_i ,
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input flgs_streamer_t flgs_streamer_i ,
@@ -38,9 +39,7 @@ module redmule_ctrl
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output logic flush_o ,
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// Control signals for the state machine
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output cntrl_scheduler_t cntrl_scheduler_o ,
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output cntrl_flags_t cntrl_flags_o,
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// Peripheral slave port
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hwpe_ctrl_intf_periph.slave periph
42+
output cntrl_flags_t cntrl_flags_o
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);
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logic clear, latch_clear;
@@ -58,36 +57,14 @@ module redmule_ctrl
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redmule_config_t redmule_config;
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61-
hwpe_ctrl_package::ctrl_regfile_t reg_file;
62-
hwpe_ctrl_package::ctrl_slave_t cntrl_slave;
63-
hwpe_ctrl_package::flags_slave_t flgs_slave;
64-
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// Control slave interface
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hwpe_ctrl_slave #(
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.REGFILE_SCM ( 0 ),
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.N_CORES ( N_CORES ),
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.N_CONTEXT ( N_CONTEXT ),
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.N_IO_REGS ( REDMULE_REGS ),
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.N_GENERIC_REGS ( 6 ),
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.ID_WIDTH ( ID_WIDTH )
73-
) i_slave (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.clear_o ( clear ),
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.cfg ( periph ),
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.ctrl_i ( cntrl_slave ),
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.flags_o ( flgs_slave ),
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.reg_file ( reg_file )
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);
82-
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redmule_tiler i_cfg_tiler (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.clear_i ( clear ),
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.setback_i ( tiler_setback ),
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.start_cfg_i ( start_cfg_i ),
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.reg_file_i ( reg_file ),
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.valid_o ( tiler_valid ),
67+
.config_i ( config_i ),
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.config_o ( redmule_config )
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);
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@@ -115,7 +92,7 @@ module redmule_ctrl
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end else begin
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if (clear || tiler_setback)
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slave_start <= 1'b0;
118-
else if (flgs_slave.start)
95+
else if (start_cfg_i)
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slave_start <= 1'b1;
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end
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end
@@ -131,9 +108,7 @@ module redmule_ctrl
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assign cntrl_scheduler_o.first_load = current == REDMULE_STARTING;
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assign tiler_setback = current == REDMULE_IDLE && next == REDMULE_STARTING;
134-
assign cntrl_slave.done = current == REDMULE_FINISHED;
135-
assign cntrl_slave.evt = '0;
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assign busy_o = current != REDMULE_LATCH_RST && current != REDMULE_IDLE && current != REDMULE_FINISHED;
111+
assign busy_o = slave_start | (current != REDMULE_LATCH_RST && current != REDMULE_IDLE && current != REDMULE_FINISHED);
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assign flush_o = current == REDMULE_FINISHED;
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assign cntrl_scheduler_o.rst = current == REDMULE_FINISHED;
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assign cntrl_scheduler_o.finished = current == REDMULE_FINISHED;
@@ -176,7 +151,7 @@ module redmule_ctrl
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/*---------------------------------------------------------------------------------------------*/
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/* Other combinational assigmnets */
178153
/*---------------------------------------------------------------------------------------------*/
179-
assign evt_o = flgs_slave.evt[7:0];
180-
assign clear_o = clear || latch_clear || cntrl_slave.done;
154+
assign evt_o = current == REDMULE_COMPUTING && next == REDMULE_FINISHED;
155+
assign clear_o = clear || latch_clear || current == REDMULE_FINISHED;
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182157
endmodule : redmule_ctrl

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