@@ -27,7 +27,8 @@ module redmule_ctrl
2727 output logic busy_o ,
2828 output logic clear_o ,
2929 output logic [N_CORES - 1 : 0 ][1 : 0 ] evt_o ,
30- output redmule_config_t config_o ,
30+ input redmule_config_t config_i ,
31+ output redmule_config_t config_o ,
3132 input logic reg_enable_i ,
3233 input logic start_cfg_i ,
3334 input flgs_streamer_t flgs_streamer_i ,
@@ -38,9 +39,7 @@ module redmule_ctrl
3839 output logic flush_o ,
3940 // Control signals for the state machine
4041 output cntrl_scheduler_t cntrl_scheduler_o ,
41- output cntrl_flags_t cntrl_flags_o,
42- // Peripheral slave port
43- hwpe_ctrl_intf_periph.slave periph
42+ output cntrl_flags_t cntrl_flags_o
4443);
4544
4645 logic clear, latch_clear;
@@ -58,36 +57,14 @@ module redmule_ctrl
5857
5958 redmule_config_t redmule_config;
6059
61- hwpe_ctrl_package :: ctrl_regfile_t reg_file;
62- hwpe_ctrl_package :: ctrl_slave_t cntrl_slave;
63- hwpe_ctrl_package :: flags_slave_t flgs_slave;
64-
65- // Control slave interface
66- hwpe_ctrl_slave # (
67- .REGFILE_SCM ( 0 ),
68- .N_CORES ( N_CORES ),
69- .N_CONTEXT ( N_CONTEXT ),
70- .N_IO_REGS ( REDMULE_REGS ),
71- .N_GENERIC_REGS ( 6 ),
72- .ID_WIDTH ( ID_WIDTH )
73- ) i_slave (
74- .clk_i ( clk_i ),
75- .rst_ni ( rst_ni ),
76- .clear_o ( clear ),
77- .cfg ( periph ),
78- .ctrl_i ( cntrl_slave ),
79- .flags_o ( flgs_slave ),
80- .reg_file ( reg_file )
81- );
82-
8360 redmule_tiler i_cfg_tiler (
8461 .clk_i ( clk_i ),
8562 .rst_ni ( rst_ni ),
8663 .clear_i ( clear ),
8764 .setback_i ( tiler_setback ),
8865 .start_cfg_i ( start_cfg_i ),
89- .reg_file_i ( reg_file ),
9066 .valid_o ( tiler_valid ),
67+ .config_i ( config_i ),
9168 .config_o ( redmule_config )
9269 );
9370
@@ -115,7 +92,7 @@ module redmule_ctrl
11592 end else begin
11693 if (clear || tiler_setback)
11794 slave_start <= 1'b0 ;
118- else if (flgs_slave.start )
95+ else if (start_cfg_i )
11996 slave_start <= 1'b1 ;
12097 end
12198 end
@@ -131,9 +108,7 @@ module redmule_ctrl
131108
132109 assign cntrl_scheduler_o.first_load = current == REDMULE_STARTING ;
133110 assign tiler_setback = current == REDMULE_IDLE && next == REDMULE_STARTING ;
134- assign cntrl_slave.done = current == REDMULE_FINISHED ;
135- assign cntrl_slave.evt = '0 ;
136- assign busy_o = current != REDMULE_LATCH_RST && current != REDMULE_IDLE && current != REDMULE_FINISHED ;
111+ assign busy_o = slave_start | (current != REDMULE_LATCH_RST && current != REDMULE_IDLE && current != REDMULE_FINISHED );
137112 assign flush_o = current == REDMULE_FINISHED ;
138113 assign cntrl_scheduler_o.rst = current == REDMULE_FINISHED ;
139114 assign cntrl_scheduler_o.finished = current == REDMULE_FINISHED ;
@@ -176,7 +151,7 @@ module redmule_ctrl
176151 /* ---------------------------------------------------------------------------------------------*/
177152 /* Other combinational assigmnets */
178153 /* ---------------------------------------------------------------------------------------------*/
179- assign evt_o = flgs_slave.evt[ 7 : 0 ] ;
180- assign clear_o = clear || latch_clear || cntrl_slave.done ;
154+ assign evt_o = current == REDMULE_COMPUTING && next == REDMULE_FINISHED ;
155+ assign clear_o = clear || latch_clear || current == REDMULE_FINISHED ;
181156
182157endmodule : redmule_ctrl
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