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FrancescoContiFrancescoConti
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Draft (uncompiled, untested) integration of redmule_target_decoder into redmule_top
Also, propagate target_clear to the controller when using HWPE_TARGET interface (XIF currently does not provide a software-based soft clear mechanism, which is a significant liability...)
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4 files changed

+93
-57
lines changed

4 files changed

+93
-57
lines changed

‎rtl/ctrl/redmule_target_decoder.sv‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -13,18 +13,18 @@ module redmule_target_decoder
1313
import redmule_pkg::*;
1414
import redmule_regif_pkg::*;
1515
#(
16-
parameter int unsigned InstFifoDepth = 4,
1716
parameter int unsigned OpIdWidth = 4
1817
)(
1918
input logic clk_i,
2019
input logic rst_ni,
21-
input logic clear_i,
20+
input logic clear_i | target_clear_o,
21+
output logic regif_clear_o,
2222
input logic config_ready_i,
2323
input logic op_done_i,
2424
output logic config_valid_o,
2525
output redmule_config_t config_o,
26-
// periph slave port
27-
hwpe_ctrl_intf_periph.slave periph
26+
// target port
27+
hwpe_ctrl_intf_target.slave target
2828
);
2929

3030
// target signals
@@ -64,8 +64,8 @@ module redmule_target_decoder
6464
) i_target (
6565
.clk_i ( clk_i ),
6666
.rst_ni ( rst_ni ),
67-
.clear_o ( clear_o ),
68-
.target ( periph ),
67+
.clear_o ( regif_clear_o ),
68+
.target ( target ),
6969
.job_trigger_o ( job_trigger ),
7070
.job_done_i ( job_done ),
7171
.job_status_i ( job_status ),
@@ -117,7 +117,7 @@ module redmule_target_decoder
117117
if(~rst_ni) begin
118118
config_valid_q <= '0;
119119
end else begin
120-
if(clear_i) begin // TODO: connect target-generated clear as well!
120+
if(clear_i | target_clear_o) begin // TODO: connect target-generated clear as well!
121121
config_valid_q <= '0;
122122
end
123123
else if(job_trigger) begin
@@ -134,7 +134,7 @@ module redmule_target_decoder
134134
if(~rst_ni) begin
135135
job_status <= '0;
136136
end else begin
137-
if(clear_i) begin // TODO: connect target-generated clear as well!
137+
if(clear_i | target_clear_o) begin // TODO: connect target-generated clear as well!
138138
job_status <= '0;
139139
end
140140
else if((config_valid_q | job_trigger) & config_ready_i) begin
@@ -173,7 +173,7 @@ module redmule_target_decoder
173173
if (~rst_ni) begin
174174
op_id_counter_in_q <= 0;
175175
end else begin
176-
if (clear_i) begin
176+
if (clear_i | target_clear_o) begin
177177
op_id_counter_in_q <= 0;
178178
end else if (job_trigger) begin
179179
op_id_counter_in_q <= op_id_counter_in_q + 1;
@@ -188,7 +188,7 @@ module redmule_target_decoder
188188
if (~rst_ni) begin
189189
op_id_counter_out_q <= '1;
190190
end else begin
191-
if (clear_i) begin
191+
if (clear_i | target_clear_o) begin
192192
op_id_counter_out_q <= '1;
193193
end else if (op_done_i) begin
194194
op_id_counter_out_q <= op_id_counter_out_q + 1;

‎rtl/redmule_ctrl.sv‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ module redmule_ctrl
2121
input logic rst_ni ,
2222
input logic test_mode_i ,
2323
output logic busy_o ,
24+
input logic target_clear_i ,
2425
output logic clear_o ,
2526
output logic evt_o ,
2627
input redmule_config_t config_i ,
@@ -156,6 +157,6 @@ module redmule_ctrl
156157
/* Other combinational assigmnets */
157158
/*---------------------------------------------------------------------------------------------*/
158159
assign evt_o = flgs_streamer_i.z_stream_sink_flags.done;
159-
assign clear_o = latch_clear || current == REDMULE_FINISHED;
160+
assign clear_o = target_clear_i || latch_clear || current == REDMULE_FINISHED;
160161

161162
endmodule : redmule_ctrl

‎rtl/redmule_pkg.sv‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,8 @@ package redmule_pkg;
2222
parameter int unsigned WsourceStreamId = 1;
2323
parameter int unsigned YsourceStreamId = 2;
2424

25+
typedef enum logic { HWPE_TARGET, XIF } ctrl_intf_e;
26+
2527
typedef enum logic { LD_IN_FMP, LD_WEIGHT } source_sel_e;
2628
typedef enum logic { LOAD, STORE } ld_st_sel_e;
2729

‎rtl/redmule_top.sv‎

Lines changed: 79 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,9 @@ module redmule_top
2424
parameter bit LatchBuffers = 0,
2525
parameter fpnew_pkg::fmt_logic_t FpFmtConfig = 6'b001101,
2626
parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = 4'b1000,
27-
// Custom instrunctions
27+
// Choose interface
28+
parameter ctrl_intf_e CtrlIntfConfig = XIF;
29+
// Custom instructions
2830
parameter logic [6:0] McnfigOpCode = 7'b0001011,
2931
parameter logic [6:0] MarithOpCode = 7'b0001011,
3032
parameter logic [6:0] MopcntOpCode = 7'b0001011,
@@ -59,7 +61,7 @@ module redmule_top
5961
hwpe_stream_intf_stream.source w_stream_o ,
6062
// Broadcasted X stream
6163
hwpe_stream_intf_stream.source x_stream_o ,
62-
// XIF ports
64+
// XIF ports (unused if CtrlIntfConfig = HWPE_TARGET)
6365
input x_issue_req_t x_issue_req_i,
6466
output x_issue_resp_t x_issue_resp_o,
6567
input logic x_issue_valid_i,
@@ -73,7 +75,9 @@ module redmule_top
7375
output logic x_result_valid_o,
7476
input logic x_result_ready_i,
7577
// TCDM master ports for the memory side
76-
hci_core_intf.initiator tcdm
78+
hci_core_intf.initiator tcdm,
79+
// HWPE-ctrl target port (unused if CtrlIntfConfig = XIF)
80+
hwpe_ctrl_intf_target.slave target
7781
);
7882

7983
localparam int unsigned FpWidth = fp_width(FpFormat);
@@ -83,6 +87,7 @@ logic clk_acc;
8387

8488
logic fsm_z_clk_en, ctrl_z_clk_en;
8589
logic enable, clear;
90+
logic target_clear;
8691
logic y_buffer_depth_count,
8792
y_buffer_load,
8893
z_buffer_fill,
@@ -495,7 +500,7 @@ redmule_memory_scheduler #(
495500
) i_memory_scheduler (
496501
.clk_i ( clk_acc ),
497502
.rst_ni ( rst_ni ),
498-
.clear_i ( '0 ),
503+
.clear_i ( target_clear ),
499504
.z_priority_i ( z_priority ),
500505
.config_i ( redmule_config ),
501506
.config_valid_i ( cfg_complete ),
@@ -509,52 +514,79 @@ redmule_memory_scheduler #(
509514
);
510515

511516
/*---------------------------------------------------------------*/
512-
/* | Instruction Decoder | */
517+
/* | Instruction Decoder (XIF) or Target Decoder (HWPE_TARGET) | */
513518
/*---------------------------------------------------------------*/
514519

515520
logic tiler_busy;
516521
redmule_config_t dec_config_q;
517522

518-
redmule_inst_decoder #(
519-
.InstFifoDepth ( 4 ),
520-
.McnfigOpCode ( McnfigOpCode ),
521-
.MarithOpCode ( MarithOpCode ),
522-
.MopcntOpCode ( MopcntOpCode ),
523-
.McnfigFunct3 ( McnfigFunct3 ),
524-
.MarithFunct3 ( MarithFunct3 ),
525-
.MopcntFunct3 ( MopcntFunct3 ),
526-
.McnfigFunct2 ( McnfigFunct2 ),
527-
.MarithFunct2 ( MarithFunct2 ),
528-
.MopcntFunct2 ( MopcntFunct2 ),
529-
.XifIdWidth ( XifIdWidth ),
530-
.XifNumHarts ( XifNumHarts ),
531-
.XifIssueRegisterSplit ( XifIssueRegisterSplit ),
532-
.x_issue_req_t ( x_issue_req_t ),
533-
.x_issue_resp_t ( x_issue_resp_t ),
534-
.x_register_t ( x_register_t ),
535-
.x_commit_t ( x_commit_t ),
536-
.x_result_t ( x_result_t )
537-
) i_inst_decoder (
538-
.clk_i ( clk_i ),
539-
.rst_ni ( rst_ni ),
540-
.clear_i ( '0 ),
541-
.config_ready_i ( ~config_fifo_full ),
542-
.op_done_i ( flgs_streamer.z_stream_sink_flags.done ),
543-
.config_valid_o ( dec_config_valid ),
544-
.config_o ( dec_config ),
545-
.x_issue_req_i ( x_issue_req_i ),
546-
.x_issue_resp_o ( x_issue_resp_o ),
547-
.x_issue_valid_i ( x_issue_valid_i ),
548-
.x_issue_ready_o ( x_issue_ready_o ),
549-
.x_register_i ( x_register_i ),
550-
.x_register_valid_i ( x_register_valid_i ),
551-
.x_register_ready_o ( x_register_ready_o ),
552-
.x_commit_i ( x_commit_i ),
553-
.x_commit_valid_i ( x_commit_valid_i ),
554-
.x_result_o ( x_result_o ),
555-
.x_result_valid_o ( x_result_valid_o ),
556-
.x_result_ready_i ( x_result_ready_i )
557-
);
523+
if(CtrlIntfConfig == XIF) begin : xif_ctrl_intf_gen
524+
redmule_inst_decoder #(
525+
.InstFifoDepth ( 4 ),
526+
.McnfigOpCode ( McnfigOpCode ),
527+
.MarithOpCode ( MarithOpCode ),
528+
.MopcntOpCode ( MopcntOpCode ),
529+
.McnfigFunct3 ( McnfigFunct3 ),
530+
.MarithFunct3 ( MarithFunct3 ),
531+
.MopcntFunct3 ( MopcntFunct3 ),
532+
.McnfigFunct2 ( McnfigFunct2 ),
533+
.MarithFunct2 ( MarithFunct2 ),
534+
.MopcntFunct2 ( MopcntFunct2 ),
535+
.XifIdWidth ( XifIdWidth ),
536+
.XifNumHarts ( XifNumHarts ),
537+
.XifIssueRegisterSplit ( XifIssueRegisterSplit ),
538+
.x_issue_req_t ( x_issue_req_t ),
539+
.x_issue_resp_t ( x_issue_resp_t ),
540+
.x_register_t ( x_register_t ),
541+
.x_commit_t ( x_commit_t ),
542+
.x_result_t ( x_result_t )
543+
) i_inst_decoder (
544+
.clk_i ( clk_i ),
545+
.rst_ni ( rst_ni ),
546+
.clear_i ( '0 ), // TODO: fixme, not having a software-based clear mechanism is a bad idea.
547+
.config_ready_i ( ~config_fifo_full ),
548+
.op_done_i ( flgs_streamer.z_stream_sink_flags.done ),
549+
.config_valid_o ( dec_config_valid ),
550+
.config_o ( dec_config ),
551+
.x_issue_req_i ( x_issue_req_i ),
552+
.x_issue_resp_o ( x_issue_resp_o ),
553+
.x_issue_valid_i ( x_issue_valid_i ),
554+
.x_issue_ready_o ( x_issue_ready_o ),
555+
.x_register_i ( x_register_i ),
556+
.x_register_valid_i ( x_register_valid_i ),
557+
.x_register_ready_o ( x_register_ready_o ),
558+
.x_commit_i ( x_commit_i ),
559+
.x_commit_valid_i ( x_commit_valid_i ),
560+
.x_result_o ( x_result_o ),
561+
.x_result_valid_o ( x_result_valid_o ),
562+
.x_result_ready_i ( x_result_ready_i )
563+
);
564+
// bind unused HWPE_TARGET signals
565+
assign target_clear = '0; // TODO: a software-accessible clear should be added also to the XIF interface
566+
assign target.gnt = '1;
567+
assign target.r_data = '0;
568+
assign target.r_valid = '0;
569+
assign target.r_id = '0;
570+
end
571+
else begin
572+
redmule_target_decoder i_target_decoder (
573+
.clk_i ( clk_i ),
574+
.rst_ni ( rst_ni ),
575+
.clear_i ( '0 ), // ORed internally with target_clear
576+
.target_clear_o ( target_clear ),
577+
.config_ready_i ( ~config_fifo_full ),
578+
.op_done_i ( flgs_streamer.z_stream_sink_flags.done ),
579+
.config_valid_o ( dec_config_valid ),
580+
.config_o ( dec_config ),
581+
.target ( target )
582+
);
583+
// bind unused XIF signals
584+
assign x_issue_resp_o = '0;
585+
assign x_issue_ready_o = '0;
586+
assign x_register_ready_o = '0;
587+
assign x_result_o = '0;
588+
assign x_result_valid_o = '0;
589+
end
558590

559591
fifo_v3 #(
560592
.FALL_THROUGH ( 0 ),
@@ -591,6 +623,7 @@ redmule_ctrl #(
591623
.flgs_streamer_i ( flgs_streamer ),
592624
.busy_o ( busy_o ),
593625
.tiler_busy_o ( tiler_busy ),
626+
.target_clear_i ( target_clear ),
594627
.clear_o ( clear ),
595628
.evt_o ( evt_o ),
596629
.config_i ( dec_config_q ),
@@ -620,7 +653,7 @@ redmule_scheduler #(
620653
.clk_i ( clk_acc ),
621654
.rst_ni ( rst_ni ),
622655
.test_mode_i ( test_mode_i ),
623-
.clear_i ( '0 ),
656+
.clear_i ( target_clear ),
624657
.x_valid_i ( x_buffer_fifo.valid ),
625658
.w_valid_i ( w_buffer_fifo.valid ),
626659
.y_valid_i ( y_buffer_fifo.valid ),

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