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Commit ef6f08a

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author
Andrea Belano
committed
[tiler] Fix trivial mistake in always_ff blocks
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rtl/redmule_tiler.sv

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@ assign x_rows_by_w_cols_iter_d = start_cfg_i ? config_d.x_rows_iter * config_d.w
9999
always_ff @(posedge clk_i or negedge rst_ni) begin
100100
if (~rst_ni) begin
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x_rows_by_w_cols_iter_q <= '0;
102-
end begin
102+
end else begin
103103
if (clear_i | setback_i) begin
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x_rows_by_w_cols_iter_q <= '0;
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end else begin
@@ -113,7 +113,7 @@ assign x_rows_by_w_cols_iter_valid_d = start_cfg_i;
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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x_rows_by_w_cols_iter_valid_q <= '0;
116-
end begin
116+
end else begin
117117
if (clear_i | setback_i) begin
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x_rows_by_w_cols_iter_valid_q <= '0;
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end else begin
@@ -131,7 +131,7 @@ assign x_rows_by_w_cols_by_x_cols_iter_d = x_rows_by_w_cols_iter_valid_q ? confi
131131
always_ff @(posedge clk_i or negedge rst_ni) begin
132132
if (~rst_ni) begin
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x_rows_by_w_cols_by_x_cols_iter_q <= '0;
134-
end begin
134+
end else begin
135135
if (clear_i | setback_i) begin
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x_rows_by_w_cols_by_x_cols_iter_q <= '0;
137137
end else begin
@@ -145,7 +145,7 @@ assign x_rows_by_w_cols_by_x_cols_iter_valid_d = x_rows_by_w_cols_iter_valid_q;
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always_ff @(posedge clk_i or negedge rst_ni) begin
146146
if (~rst_ni) begin
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x_rows_by_w_cols_by_x_cols_iter_valid_q <= '0;
148-
end begin
148+
end else begin
149149
if (clear_i | setback_i) begin
150150
x_rows_by_w_cols_by_x_cols_iter_valid_q <= '0;
151151
end else begin
@@ -163,7 +163,7 @@ assign x_rows_by_w_cols_by_w_rows_iter_d = x_rows_by_w_cols_iter_valid_q ? confi
163163
always_ff @(posedge clk_i or negedge rst_ni) begin
164164
if (~rst_ni) begin
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x_rows_by_w_cols_by_w_rows_iter_q <= '0;
166-
end begin
166+
end else begin
167167
if (clear_i | setback_i) begin
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x_rows_by_w_cols_by_w_rows_iter_q <= '0;
169169
end else begin
@@ -177,7 +177,7 @@ assign x_rows_by_w_cols_by_w_rows_iter_valid_d = x_rows_by_w_cols_iter_valid_q;
177177
always_ff @(posedge clk_i or negedge rst_ni) begin
178178
if (~rst_ni) begin
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x_rows_by_w_cols_by_w_rows_iter_valid_q <= '0;
180-
end begin
180+
end else begin
181181
if (clear_i | setback_i) begin
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x_rows_by_w_cols_by_w_rows_iter_valid_q <= '0;
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end else begin

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