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Add MemPool's Xqueue atomic extension
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config.mk

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@@ -12,5 +12,5 @@ RV32XPULPIMG += opcodes-xpulpbitop_CUSTOM
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SNITCH_OPCODES := opcodes-dma_CUSTOM opcodes-frep_CUSTOM opcodes-ssr_CUSTOM
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# default configurations
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MEMPOOL_ISA := opcodes-frep_CUSTOM $(RV32XPULPIMG) opcodes-xpulppostmod_CUSTOM opcodes-rv32d-zfh_DRAFT opcodes-rv32q-zfh_DRAFT opcodes-rv32zfh_DRAFT opcodes-rv64zfh_DRAFT opcodes-sflt_CUSTOM
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MEMPOOL_ISA := opcodes-frep_CUSTOM $(RV32XPULPIMG) opcodes-xpulppostmod_CUSTOM opcodes-rv32d-zfh_DRAFT opcodes-rv32q-zfh_DRAFT opcodes-rv32zfh_DRAFT opcodes-rv64zfh_DRAFT opcodes-sflt_CUSTOM opcodes-xqueues_CUSTOM
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SNITCH_ISA := $(RV32XPULPIMG) $(SNITCH_OPCODES) opcodes-sflt_CUSTOM

opcodes-xqueue_CUSTOM

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# format of a line in this file:
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# <instruction name> <args> <opcode>
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#
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# <opcode> is given by specifying one or more range/value pairs:
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# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0)
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#
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# <args> is one of rd, rs1, rs2, rs3, imm20, imm12, imm12lo, imm12hi,
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# shamtw, shamt, rm
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# Xqueue extension (atomic queue operations)
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# IMPORTANT: THIS IS AN ILLEGAL EXTENSION OF THE STANDARD ATOMIC INSTRUCTIONS
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# queue push and pop (32-bit)
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q.push rd rs1 rs2 aqrl 31..29=1 28..27=3 14..12=2 6..2=0x0B 1..0=3
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q.pop rd rs1 24..20=0 aqrl 31..29=1 28..27=2 14..12=2 6..2=0x0B 1..0=3

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