treewide: Support reduction and DCA (#260)

Co-authored-by: Raphael Roth <[email protected]>
Co-authored-by: Lorenzo Leone <[email protected]>
Co-authored-by: Tim Fischer <[email protected]>

Author: 4 people

Bender.lock

@@ -7,10 +7,10 @@ packages:
     dependencies:
     - common_cells
   axi:
-    revision: bd1abffc0812f8170902e5fb93142c7785c0b8c1
+    revision: 06410c36819924e32db2afa428d244dbdbcd5d4e
     version: null
     source:
-      Git: https://github.com/colluca/axi.git
+      Git: https://github.com/colluca/axi
     dependencies:
     - common_cells
     - common_verification
@@ -42,7 +42,7 @@ packages:
     - scm
     - tech_cells_generic
   common_cells:
-    revision: bef3d3c5ed0e2cc211e69a6dbd81c4fe3a97025c
+    revision: ca9d577f2fbc45ec557ab4e0905bbfc154441540
     version: null
     source:
       Git: https://github.com/pulp-platform/common_cells.git
@@ -71,8 +71,8 @@ packages:
     dependencies:
     - common_cells
   idma:
-    revision: 7829f71691a62c1e2e5e3230f370f222c7a83087
-    version: null
+    revision: 28a36e5e07705549e59fc33db96ab681bc1ca88e
+    version: 0.6.5
     source:
       Git: https://github.com/pulp-platform/iDMA.git
     dependencies:

Bender.yml

@@ -19,28 +19,32 @@ package:
     - Matheus Cavalcante <[email protected]>
 
 dependencies:
-  axi:                { git: https://github.com/colluca/axi,                      rev:  multicast       }
+  axi:                { git: https://github.com/colluca/axi,                      rev: multicast }
   axi_riscv_atomics:  { git: https://github.com/pulp-platform/axi_riscv_atomics,  version:  0.6.0       }
   common_cells:       { git: https://github.com/pulp-platform/common_cells,       rev:      snitch      }
   apb:                { git: https://github.com/pulp-platform/apb.git,            version:  0.2.2       }
   FPnew:              { git: https://github.com/pulp-platform/cvfpu.git,          rev:      pulp-v0.1.3 }
   tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version:  0.2.13      }
   riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg,          version:  0.8.0       }
   cluster_icache:     { git: https://github.com/pulp-platform/cluster_icache.git, rev: 64e21ae455bbdde850c4df13bef86ea55ac42537 }
-  idma:               { git: https://github.com/pulp-platform/iDMA.git,           rev: __deploy__bebefa3__master }
+  idma:               { git: https://github.com/pulp-platform/iDMA.git,           version:  0.6.5       }
 
 export_include_dirs:
   - hw/reqrsp_interface/include
   - hw/mem_interface/include
   - hw/tcdm_interface/include
+  - hw/dca_interface/include
   - hw/snitch/include
+  - hw/snitch_fp_ss/include
   - hw/snitch_ssr/include
   - hw/generated
 
 sources:
   # reqrsp_interface
   - files:
       # Level 0
+      - hw/reqrsp_interface/src/generic_reqrsp_cut.sv
+      - hw/reqrsp_interface/src/generic_reqrsp_mux.sv
       - hw/reqrsp_interface/src/reqrsp_pkg.sv
       # Level 1
       - hw/reqrsp_interface/src/reqrsp_intf.sv
@@ -89,6 +93,10 @@ sources:
       - hw/tcdm_interface/test/reqrsp_to_tcdm_tb.sv
       - hw/tcdm_interface/test/tcdm_mux_tb.sv
 
+  # dca_interface
+  - files:
+      - hw/dca_interface/src/dca_fork.sv
+
   # snitch
   - files:
       # Level 0
@@ -149,20 +157,25 @@ sources:
       # Level 1
       - hw/snitch_ipu/src/snitch_ipu.sv
 
+  # snitch_fp_ss
+  - files:
+      # Level 0
+      - hw/snitch_fp_ss/src/snitch_fpu.sv
+      - hw/snitch_fp_ss/src/snitch_sequencer.sv
+      # Level 1
+      - hw/snitch_fp_ss/src/snitch_fp_ss.sv
+
   # snitch_cluster
   - files:
       # Level 0
       - hw/snitch_cluster/src/snitch_amo_shim.sv
       - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv
       - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv
       - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv
-      - hw/snitch_cluster/src/snitch_fpu.sv
-      - hw/snitch_cluster/src/snitch_sequencer.sv
       - hw/snitch_cluster/src/snitch_tcdm_fc_interconnect.sv
       - hw/bootrom/snitch_bootrom.sv
       # Level 1
       - hw/snitch_cluster/src/snitch_barrier.sv
-      - hw/snitch_cluster/src/snitch_fp_ss.sv
       - hw/snitch_cluster/src/snitch_tcdm_interconnect.sv
       # Level 2
       - hw/snitch_cluster/src/snitch_cc.sv

cfg/default.json

@@ -9,8 +9,7 @@
         cluster_base_hartid: 0,
         addr_width: 48,
         data_width: 64,
-        atomic_id_width: 5, // clog2(total number of clusters)
-        user_width: 53, // addr_width + atomic_id_width
+        atomic_id_width: 5,
         tcdm: {
             size: 128,
             banks: 32,
@@ -23,8 +22,6 @@
         dma_req_fifo_depth: 8,
         narrow_trans: 4,
         wide_trans: 32,
-        dma_user_width: 48,
-        enable_multicast: true,
         // We don't need Snitch debugging in Occamy
         enable_debug: false,
         // We don't need Snitch (core-internal) virtual memory support

cfg/dma_mchan.json

@@ -9,8 +9,7 @@
         cluster_base_hartid: 0,
         addr_width: 48,
         data_width: 64,
-        atomic_id_width: 5, // clog2(total number of clusters)
-        user_width: 53, // addr_width + atomic_id_width
+        atomic_id_width: 5,
         tcdm: {
             size: 128,
             banks: 32,
@@ -24,8 +23,6 @@
         dma_req_fifo_depth: 8,
         narrow_trans: 4,
         wide_trans: 32,
-        dma_user_width: 48,
-        enable_multicast: true,
         // We don't need Snitch debugging in Occamy
         enable_debug: false,
         // We don't need Snitch (core-internal) virtual memory support

cfg/frep_xl.json

@@ -9,8 +9,7 @@
         cluster_base_hartid: 0,
         addr_width: 48,
         data_width: 64,
-        atomic_id_width: 5, // clog2(total number of clusters)
-        user_width: 53, // addr_width + atomic_id_width
+        atomic_id_width: 5,
         tcdm: {
             size: 128,
             banks: 32,
@@ -23,8 +22,6 @@
         dma_req_fifo_depth: 8,
         narrow_trans: 4,
         wide_trans: 32,
-        dma_user_width: 48,
-        enable_multicast: true,
         // We don't need Snitch debugging in Occamy
         enable_debug: false,
         // We don't need Snitch (core-internal) virtual memory support

cfg/frep_xs.json

@@ -9,7 +9,7 @@
         cluster_base_hartid: 0,
         addr_width: 48,
         data_width: 64,
-        user_width: 5, // clog2(total number of clusters)
+        atomic_id_width: 5,
         tcdm: {
             size: 128,
             banks: 32,
@@ -22,7 +22,6 @@
         dma_req_fifo_depth: 8,
         narrow_trans: 4,
         wide_trans: 32,
-        dma_user_width: 1,
         // We don't need Snitch debugging in Occamy
         enable_debug: false,
         // We don't need Snitch (core-internal) virtual memory support

cfg/github-ci.json

@@ -9,8 +9,7 @@
         cluster_base_hartid: 0,
         addr_width: 48,
         data_width: 64,
-        atomic_id_width: 5, // clog2(total number of clusters)
-        user_width: 53, // addr_width + atomic_id_width
+        atomic_id_width: 5,
         tcdm: {
             size: 128,
             banks: 32,
@@ -23,8 +22,6 @@
         dma_req_fifo_depth: 8,
         narrow_trans: 4,
         wide_trans: 32,
-        dma_user_width: 48,
-        enable_multicast: true,
         // We don't need Snitch debugging in Occamy
         enable_debug: false,
         // We don't need Snitch (core-internal) virtual memory support

cfg/omega.json

@@ -9,8 +9,7 @@
         cluster_base_hartid: 0,
         addr_width: 48,
         data_width: 64,
-        atomic_id_width: 5, // clog2(total number of clusters)
-        user_width: 53, // addr_width + atomic_id_width
+        atomic_id_width: 5,
         tcdm: {
             size: 128,
             banks: 32,
@@ -24,8 +23,6 @@
         dma_req_fifo_depth: 8,
         narrow_trans: 4,
         wide_trans: 32,
-        dma_user_width: 48,
-        enable_multicast: true,
         // We don't need Snitch debugging in Occamy
         enable_debug: false,
         // We don't need Snitch (core-internal) virtual memory support

experiments/frep/experiments.py

@@ -7,10 +7,9 @@
 
 from copy import deepcopy
 from snitch.target.SimResults import SimRegion
-from snitch.target.experiment_utils import ExperimentManager
+import snitch.target.experiment_utils as eu
 import random
 
-from mako.template import Template
 from pathlib import Path
 
 NUM_GEMM_SIZES = 50
@@ -57,11 +56,10 @@
     'zonl64dobu': str(Path.cwd() / 'hw/zonl64dobu/bin/snitch_cluster.vsim'),
     'zonl48dobu': str(Path.cwd() / 'hw/zonl48dobu/bin/snitch_cluster.vsim'),
 }
-DATA_DIR = Path('data').absolute()
 VERIFY_PY = Path('../../../../sw/blas/gemm/scripts/verify.py').absolute()
 
 
-class FrepExperimentManager(ExperimentManager):
+class FrepExperimentManager(eu.ExperimentManager):
 
     def derive_axes(self, experiment):
         return {
@@ -72,16 +70,7 @@ def derive_axes(self, experiment):
         }
 
     def derive_data_cfg(self, experiment):
-        # Create parent directory for configuration file
-        cfg_path = DATA_DIR / experiment['name'] / 'cfg.json'
-        cfg_path.parent.mkdir(parents=True, exist_ok=True)
-
-        # Fill in configuration template and write configuration file
-        with open('cfg.json.tpl') as f:
-            cfg = Template(f.read()).render(experiment=experiment)
-        with open(cfg_path, 'w') as f:
-            f.write(cfg)
-        return cfg_path
+        return eu.derive_data_cfg_from_template(experiment)
 
     def derive_hw_cfg(self, experiment):
         return Path.cwd() / 'cfg' / f'{experiment["hw"]}.json'

hw/bootrom/bootrom.S

@@ -31,15 +31,15 @@ _snitch_park:
     wfi
 
 _snitch_resume:
-    auipc   t0, 0
+    la      t0, _snitch_park
     # We need to know the address of the scratch1 register in
     # the peripherals, which is a constant offset of our current PC,
     # independent of the cluster configuration.
     # This offset can be calculated as follows:
-    # - 0x20 (start of this bootrom)
+    #   _snitch_park (start of this bootrom)
     # + 0x1000 (bootrom size 4kB)
     # + 0x188 (offset of the scratch1 register)
-    li      t1, 0x1168
+    li      t1, 0x1188
     add     t0, t0, t1
     lw      t0, 0(t0)
     jalr    ra, 0(t0)