bender: add generated files needed for bender

Author: Navaneeth-KunhiPurayil

.gitlab/.gitlab-ci.yml

@@ -106,7 +106,7 @@ snRuntime-test-vsim:
     - ${PYTHON3} -m pip install --user mako
     # Compile the binaries
     - cd hw/system/spatz_cluster
-    - make sw.vsim SPATZ_CLUSTER_CFG=${cfg}.hjson
+    - make sw.vsim SPATZ_CLUSTER_CFG=${cfg}.hjson -B
     # Run the test
     - cd sw/build/snRuntime
     - ${CTEST} --output-on-failure
@@ -135,7 +135,7 @@ snRuntime-test-vcs:
     - ${PYTHON3} -m pip install --user mako
     # Compile the binaries
     - cd hw/system/spatz_cluster
-    - ${VCS} make sw.vcs SPATZ_CLUSTER_CFG=${cfg}.hjson
+    - ${VCS} make sw.vcs SPATZ_CLUSTER_CFG=${cfg}.hjson -B
     # Run the test
     - cd sw/build/snRuntime
     - ${CTEST} --output-on-failure
@@ -165,7 +165,7 @@ snRuntime-test-vlt:
     - ${PYTHON3} -m pip install --user mako
     # Compile the binaries
     - cd hw/system/spatz_cluster
-    - make sw.vlt SPATZ_CLUSTER_CFG=${cfg}.hjson
+    - make sw.vlt SPATZ_CLUSTER_CFG=${cfg}.hjson -B
     # Run the test
     - cd sw/build/snRuntime
     - ${CTEST} --output-on-failure
@@ -196,7 +196,7 @@ riscvTests-test-vlt:
     - ${PYTHON3} -m pip install --user mako
     # Compile the binaries
     - cd hw/system/spatz_cluster
-    - ${VCS} make sw.vlt SPATZ_CLUSTER_CFG=${cfg}.hjson
+    - ${VCS} make sw.vlt SPATZ_CLUSTER_CFG=${cfg}.hjson -B
     # Run the test
     - cd sw/build/riscvTests
     - ${CTEST} --output-on-failure -j4
@@ -227,7 +227,7 @@ spatzBenchmarks-test-vlt:
     - ${PYTHON3} -m pip install --user mako
     # Compile the binaries
     - cd hw/system/spatz_cluster
-    - ${VCS} make sw.vlt SPATZ_CLUSTER_CFG=${cfg}.hjson
+    - ${VCS} make sw.vlt SPATZ_CLUSTER_CFG=${cfg}.hjson -B
     # Run the test
     - cd sw/build/spatzBenchmarks
     - ${CTEST} --verbose

hw/ip/spatz/src/generated/spatz_pkg.sv

@@ -68,6 +68,9 @@ package spatz_pkg;
   // Largest element width that Spatz supports
   localparam vew_e MAXEW = RVD ? EW_64 : EW_32;
 
+  // Encodes both the scalar RD and the VD address in the VRF
+  localparam int VFURespAddrWidth  = GPRWidth > $clog2(NrVRFWords) ? GPRWidth : $clog2(NrVRFWords);
+
   //////////////////////
   // Type Definitions //
   //////////////////////
@@ -83,6 +86,7 @@ package spatz_pkg;
 
   // VREG address, byte enable, and data type
   typedef logic [$clog2(NrVRFWords)-1:0] vrf_addr_t;
+  typedef logic [VFURespAddrWidth-1:0] vfu_rsp_addr_t;
   typedef logic [N_FU*ELENB-1:0] vrf_be_t;
   typedef logic [N_FU*ELEN-1:0] vrf_data_t;
 

hw/system/spatz_cluster/src/generated/bootrom.sv

@@ -0,0 +1,40 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Description: Automatically generated bootrom
+//
+// Generated by hardware/scripts/generate_bootrom.py
+
+module bootrom #(
+  /* Automatically generated. DO NOT CHANGE! */
+  parameter int unsigned DataWidth = 512,
+  parameter int unsigned AddrWidth = 32
+) (
+  input  logic                 clk_i,
+  input  logic                 req_i,
+  input  logic [AddrWidth-1:0] addr_i,
+  output logic [DataWidth-1:0] rdata_o
+);
+  localparam int RomSize = 4;
+  localparam int AddrBits = RomSize > 1 ? $clog2(RomSize) : 1;
+
+  const logic [RomSize-1:0][DataWidth-1:0] mem = {
+    512'h000000000000000000000000000200000000000000100000000000000000000000000000000000020000000000001000ffdff06f10500073000380670003a383,
+    512'h000383930583839301c383b30205ae030185a3831050007330461073008666133040267330431073800303130000133704858593000005973053107304c30313,
+    512'h0000031700000f9300000f1300000e9300000e1300000d9300000d1300000c9300000c1300000b9300000b1300000a9300000a13000009930000091300000893,
+    512'h00000813000007930000071300000693000006130000059300000513000004930000041300000393000003130000029300000213000001930000011300000093
+  };
+
+  logic [AddrBits-1:0] addr_q;
+
+  always_ff @(posedge clk_i) begin
+    if (req_i) begin
+      addr_q <= addr_i[AddrBits-1+6:6];
+    end
+  end
+
+  // this prevents spurious Xes from propagating into
+  // the speculative fetch stage of the core
+  assign rdata_o = (addr_q < RomSize) ? mem[addr_q] : '0;
+endmodule