pbio/drv/clock/clock_ev3: Switch to timer 12 instead of 34

The PRU1 code which will be added in the future expects the 34 part of Timer0
to count with a period which is a multiple of 256*256 in order to generate
accurate PWM widths. We switch the system tick in order to not conflict with it.

Author: ArcaneNibble

lib/pbio/drv/clock/clock_ev3.c

@@ -26,6 +26,8 @@
 // every millisecond, and we configure the timer to reset to 0 when it reaches a count value
 // corresponding to one millisecond of time. Finer timing resolution can be obtained by
 // combining the software-managed millisecond counter with the timer value.
+//
+// The system tick uses the "12" half of the timer, and the PRU1 (TODO) uses the "34" half.
 const uint32_t auxclk_freq_hz = 24000000;
 const uint32_t timer_ms_period = (auxclk_freq_hz / 1000) - 1;
 
@@ -39,8 +41,8 @@ volatile uint32_t systick_ms = 0;
  */
 void systick_isr_C(void) {
     /* Clear the interrupt status in AINTC and in timer */
-    IntSystemStatusClear(SYS_INT_TINT34_0);
-    TimerIntStatusClear(SOC_TMR_0_REGS, TMR_INTSTAT34_TIMER_NON_CAPT);
+    IntSystemStatusClear(SYS_INT_TINT12_0);
+    TimerIntStatusClear(SOC_TMR_0_REGS, TMR_INTSTAT12_TIMER_NON_CAPT);
 
     ++systick_ms;
 
@@ -54,15 +56,15 @@ void systick_isr_C(void) {
  */
 void systick_suspend(void) {
     /* Disable the timer interrupt */
-    TimerDisable(SOC_TMR_0_REGS, TMR_TIMER34);
+    TimerDisable(SOC_TMR_0_REGS, TMR_TIMER12);
 }
 
 /**
  * Enable the timer and therefore the systick
  */
 void systick_resume(void) {
     /* Enable the timer interrupt */
-    TimerEnable(SOC_TMR_0_REGS, TMR_TIMER34, TMR_ENABLE_CONT);
+    TimerEnable(SOC_TMR_0_REGS, TMR_TIMER12, TMR_ENABLE_CONT);
 }
 
 /**
@@ -77,23 +79,22 @@ void pbdrv_clock_init(void) {
 
     /* Set up the timer */
     TimerConfigure(SOC_TMR_0_REGS, TMR_CFG_32BIT_UNCH_CLK_BOTH_INT);
-    TimerPreScalarCount34Set(SOC_TMR_0_REGS, 0);
-    TimerPeriodSet(SOC_TMR_0_REGS, TMR_TIMER34, timer_ms_period);
+    TimerPeriodSet(SOC_TMR_0_REGS, TMR_TIMER12, timer_ms_period);
 
     /* Register the Timer ISR */
-    IntRegister(SYS_INT_TINT34_0, systick_isr_C);
+    IntRegister(SYS_INT_TINT12_0, systick_isr_C);
 
     /* Set the channel number for Timer interrupt, it will map to IRQ */
-    IntChannelSet(SYS_INT_TINT34_0, 3);
+    IntChannelSet(SYS_INT_TINT12_0, 3);
 
     /* Enable timer interrupts in AINTC */
-    IntSystemEnable(SYS_INT_TINT34_0);
+    IntSystemEnable(SYS_INT_TINT12_0);
 
     /* Enable the timer interrupt */
-    TimerIntEnable(SOC_TMR_0_REGS, TMR_INT_TMR34_NON_CAPT_MODE);
+    TimerIntEnable(SOC_TMR_0_REGS, TMR_INT_TMR12_NON_CAPT_MODE);
 
     /* Start the timer */
-    TimerEnable(SOC_TMR_0_REGS, TMR_TIMER34, TMR_ENABLE_CONT);
+    TimerEnable(SOC_TMR_0_REGS, TMR_TIMER12, TMR_ENABLE_CONT);
 }
 
 uint32_t pbdrv_clock_get_us(void) {