pbio/drv/display_ev3: Use EDMA3 for data transfer.

With 178*128/3 bytes to send per display frame, this should reduce overhead considerably.

Fixes pybricks/support#2152

This also sets things up for other peripherals that can use DMA, such as UART.

Author: laurensvalk

lib/pbio/drv/display/display_ev3.c

@@ -21,11 +21,14 @@
 #include <pbio/error.h>
 #include <pbio/util.h>
 
+#include <tiam1808/edma.h>
 #include <tiam1808/spi.h>
 #include <tiam1808/psc.h>
 #include <tiam1808/hw/soc_AM1808.h>
 #include <tiam1808/hw/hw_types.h>
+#include <tiam1808/hw/hw_edma3cc.h>
 #include <tiam1808/hw/hw_syscfg0_AM1808.h>
+#include <tiam1808/armv5/am1808/edma_event.h>
 #include <tiam1808/armv5/am1808/interrupt.h>
 
 #include "../drv/gpio/gpio_ev3.h"
@@ -338,50 +341,75 @@ static pbdrv_display_st7586s_action_t init_script[] = {
     { ST7586S_ACTION_WRITE_COMMAND, ST7586_RAMWR},
 };
 
-static uint32_t tx_size;
-static uint32_t tx_progress;
-static uint8_t *tx_data;
-
 /**
- * SPI interrupt service routine for transmitting data.
+ * Called on SPI1 DMA transfer completion.
+ *
+ * @param [in] status Status of the transfer.
  */
-void SPIIsr(void) {
-    uint32_t intCode = 0;
-    IntSystemStatusClear(SYS_INT_SPINT1);
-
-    while ((intCode = SPIInterruptVectorGet(SOC_SPI_1_REGS))) {
-        if (intCode != SPI_TX_BUF_EMPTY) {
-            continue;
-        }
-
-        SPITransmitData1(SOC_SPI_1_REGS, *tx_data++);
-
-        if (++tx_progress == tx_size) {
-            SPIIntDisable(SOC_SPI_1_REGS, SPI_TRANSMIT_INT);
-            spi_status = SPI_STATUS_COMPLETE;
-            process_poll(&pbdrv_display_ev3_init_process);
-        }
-    }
+void pbdrv_display_ev3_spi1_tx_complete(uint32_t status) {
+    SPIIntDisable(SOC_SPI_1_REGS, SPI_DMA_REQUEST_ENA_INT);
+    spi_status = SPI_STATUS_COMPLETE;
+    process_poll(&pbdrv_display_ev3_init_process);
 }
 
 /**
- * Begin writing data to the display.
+ * Begin writing data to the display via DMA.
  *
- * @param data Data to write.
- * @param size Size of the data.
+ * @param [in] data Data to write.
+ * @param [in] size Size of the data.
  */
 void pbdrv_display_st7586s_write_data_begin(uint8_t *data, uint32_t size) {
-    tx_data = data;
-    tx_size = size;
-    tx_progress = 0;
     spi_status = SPI_STATUS_WAIT;
     pbdrv_gpio_out_low(&pin_lcd_cs);
-    SPIEnable(SOC_SPI_1_REGS);
-    SPIIntEnable(SOC_SPI_1_REGS, SPI_TRANSMIT_INT);
+
+    // Parameter object must be volatile since it is copied byte-by-byte in the
+    // TI API, causing it to be optimized out.
+    volatile EDMA3CCPaRAMEntry paramSet = {
+        // Address of the data to be sent.
+        .srcAddr = (uint32_t)data,
+        // Address of the destination register.
+        .destAddr = SOC_SPI_1_REGS + SPI_SPIDAT1,
+        // Number of bytes in an array.
+        .aCnt = 1,
+        // Number of such arrays to be transferred.
+        .bCnt = size,
+        // Number of frames of aCnt*bBcnt bytes to be transferred.
+        .cCnt = 1,
+        // The srcBidx should be incremented by aCnt number of bytes since the
+        // source used here is memory.
+        .srcBIdx = 1,
+        // A sync Transfer Mode is set in OPT. srCIdx and destCIdx set to
+        // zero since ASYNC Mode is used.
+        .srcCIdx = 0,
+        // Linking transfers in EDMA3 are not used.
+        .linkAddr = 0xFFFF,
+        // bCntReload is not used.
+        .bCntReload = 0,
+        // Options for the transfer. SAM field in OPT is set to zero since
+        // source is memory and memory pointer needs to be incremented. DAM
+        // field in OPT is set to zero since destination is not a FIFO.
+        .opt = (
+            // Transfer completion code.
+            ((EDMA3_CHA_SPI1_TX << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC) |
+            // EDMA3 Interrupt is enabled and Intermediate Interrupt Disabled.
+            (1 << EDMA3CC_OPT_TCINTEN_SHIFT)
+            ),
+    };
+
+    // Now write the PaRam Set to EDMA3.
+    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, EDMA3_CHA_SPI1_TX, (EDMA3CCPaRAMEntry *)&paramSet);
+
+    // EDMA3 Transfer is Enabled.
+    EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_SPI1_TX, EDMA3_TRIG_MODE_EVENT);
+
+    // Enable SPI controller to generate DMA events.
+    SPIIntEnable(SOC_SPI_1_REGS, SPI_DMA_REQUEST_ENA_INT);
 }
 
 /**
- * Initialize the display SPI driver. Pinmux is already set up in platform.c.
+ * Initialize the display SPI driver.
+ *
+ * Pinmux and common EDMA handlers are already set up in platform.c.
  */
 void pbdrv_display_init(void) {
 
@@ -395,11 +423,6 @@ void pbdrv_display_init(void) {
     // Waking up the SPI1 instance.
     PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_SPI1, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
 
-    // Register the ISR in the Interrupt Vector Table.
-    IntRegister(SYS_INT_SPINT1, SPIIsr);
-    IntChannelSet(SYS_INT_SPINT1, 2);
-    IntSystemEnable(SYS_INT_SPINT1);
-
     // Reset.
     SPIReset(SOC_SPI_1_REGS);
     SPIOutOfReset(SOC_SPI_1_REGS);
@@ -416,6 +439,13 @@ void pbdrv_display_init(void) {
     SPIDelayConfigure(SOC_SPI_1_REGS, 0, 0, 10, 10);
     SPIIntLevelSet(SOC_SPI_1_REGS, SPI_RECV_INTLVL | SPI_TRANSMIT_INTLVL);
 
+    // Request DMA Channel and TCC for SPI Transmit with queue number 0.
+    EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, EDMA3_CHA_SPI1_TX, EDMA3_CHA_SPI1_TX, 0);
+
+    // Enable the SPI controller.
+    SPIEnable(SOC_SPI_1_REGS);
+
+    // Start SPI process and ask pbdrv to wait until it is initialized.
     pbdrv_init_busy_up();
     process_start(&pbdrv_display_ev3_init_process);
 }

lib/pbio/drv/display/display_ev3.h

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: MIT
+// Copyright (c) 2025 The Pybricks Authors
+
+#ifndef _INTERNAL_PBDRV_DISPLAY_EV3_H_
+#define _INTERNAL_PBDRV_DISPLAY_EV3_H_
+
+#include <stdint.h>
+
+#include "pbdrvconfig.h"
+
+void pbdrv_display_ev3_spi1_tx_complete(uint32_t status);
+
+#endif // _INTERNAL_PBDRV_DISPLAY_EV3_H_

lib/pbio/platform/ev3/platform.c

@@ -3,19 +3,55 @@
 //
 // SPDX-License-Identifier: MPL-1.0
 // Copyright (c) 2016 Tobias Schießl (System Init / partial pinmux / boot order / exceptionhandler)
-
-#include <tiam1808/psc.h>
+//
+/*
+* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <tiam1808/armv5/am1808/edma_event.h>
+#include <tiam1808/armv5/am1808/evmAM1808.h>
 #include <tiam1808/armv5/am1808/interrupt.h>
-#include <tiam1808/hw/soc_AM1808.h>
-#include <tiam1808/hw/hw_types.h>
+#include <tiam1808/edma.h>
+#include <tiam1808/hw/hw_edma3cc.h>
 #include <tiam1808/hw/hw_syscfg0_AM1808.h>
 #include <tiam1808/hw/hw_syscfg1_AM1808.h>
-#include <tiam1808/armv5/am1808/evmAM1808.h>
+#include <tiam1808/hw/hw_types.h>
+#include <tiam1808/hw/soc_AM1808.h>
+#include <tiam1808/psc.h>
 
 #include <pbdrv/ioport.h>
 #include <pbio/port_interface.h>
 
 #include "../../drv/button/button_gpio.h"
+#include "../../drv/display/display_ev3.h"
 #include "../../drv/gpio/gpio_ev3.h"
 #include "../../drv/led/led_array_pwm.h"
 #include "../../drv/led/led_dual.h"
@@ -361,6 +397,127 @@ void copy_vector_table(void) {
     }
 }
 
+unsigned int EDMAVersionGet(void) {
+    return 1;
+}
+
+/**
+ * Callback for completion of all EDMA3 transfers on this platform.
+ *
+ * @param tccNum [in]   Transfer completion code number.
+ * @param status [in]   Status of the transfer. Currently only EDMA3_XFER_COMPLETE.
+ */
+static void Edma3CompleteCallback(unsigned int tccNum, unsigned int status) {
+    if (tccNum == EDMA3_CHA_SPI1_TX) {
+        pbdrv_display_ev3_spi1_tx_complete(status);
+    }
+    // Add other callbacks here as needed.
+}
+
+/**
+ * ISR for completion of all EDMA3 transfers on this platform.
+ *
+ * This is unchanged from the TI StarterWare example.
+ */
+static void Edma3ComplHandlerIsr(void) {
+    volatile unsigned int pendingIrqs;
+    volatile unsigned int isIPR = 0;
+
+    volatile unsigned int indexl;
+    volatile unsigned int Cnt = 0;
+    indexl = 1;
+    IntSystemStatusClear(SYS_INT_CCINT0);
+    isIPR = EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS);
+    if (isIPR) {
+        while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT) && (indexl != 0)) {
+            indexl = 0;
+            pendingIrqs = EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS);
+            while (pendingIrqs) {
+                if ((pendingIrqs & 1) == TRUE) {
+                    // Here write to ICR to clear the corresponding IPR bits.
+                    EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, indexl);
+                    Edma3CompleteCallback(indexl, EDMA3_XFER_COMPLETE);
+                }
+                ++indexl;
+                pendingIrqs >>= 1;
+            }
+            Cnt++;
+        }
+    }
+
+}
+
+/**
+ * ISR for error handling of all EDMA3 transfers on this platform.
+ *
+ * This is unchanged from the TI StarterWare example.
+ */
+static void Edma3CCErrHandlerIsr(void) {
+    volatile unsigned int pendingIrqs = 0;
+    unsigned int Cnt = 0;
+    unsigned int index = 1;
+    unsigned int regionNum = 0;
+    unsigned int evtqueNum = 0;
+
+    IntSystemStatusClear(SYS_INT_CCERRINT);
+
+    if ((HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_EMR) != 0)
+        || (HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_QEMR) != 0)
+        || (HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_CCERR) != 0)) {
+        // Loop for EDMA3CC_ERR_HANDLER_RETRY_COUNT number of time, breaks
+        // when no pending interrupt is found.
+        while ((Cnt < EDMA3CC_ERR_HANDLER_RETRY_COUNT) && (index != 0)) {
+            index = 0;
+            pendingIrqs = HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_EMR);
+            while (pendingIrqs) {
+                // Process all the pending interrupts.
+                if ((pendingIrqs & 1) == TRUE) {
+                    // Write to EMCR to clear the corresponding EMR bits.
+                    HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_EMCR) = (1 << index);
+                    // Clear any SER
+                    HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_S_SECR(regionNum)) = (1 << index);
+                }
+                ++index;
+                pendingIrqs >>= 1;
+            }
+            index = 0;
+            pendingIrqs = HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_QEMR);
+            while (pendingIrqs) {
+                // Process all the pending interrupts.
+                if ((pendingIrqs & 1) == TRUE) {
+                    // Here write to QEMCR to clear the corresponding QEMR bits.
+                    HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_QEMCR) = (1 << index);
+                    // Clear any QSER
+                    HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_S_QSECR(0)) = (1 << index);
+                }
+                ++index;
+                pendingIrqs >>= 1;
+            }
+            index = 0;
+            pendingIrqs = HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_CCERR);
+            if (pendingIrqs != 0) {
+                // Process all the pending CC error interrupts.
+                // Queue threshold error for different event queues.
+                for (evtqueNum = 0; evtqueNum < EDMA3_0_NUM_EVTQUE; evtqueNum++)
+                {
+                    if ((pendingIrqs & (1 << evtqueNum)) != 0) {
+                        // Clear the error interrupt.
+                        HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_CCERRCLR) = (1 << evtqueNum);
+                    }
+                }
+
+                // Transfer completion code error.
+                if ((pendingIrqs & (1 << EDMA3CC_CCERR_TCCERR_SHIFT)) != 0) {
+                    HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_CCERRCLR) = \
+                        (0x01 << EDMA3CC_CCERR_TCCERR_SHIFT);
+                }
+                ++index;
+            }
+            Cnt++;
+        }
+    }
+}
+
 // Called from assembly code in startup.s. After this, the "main" function in
 // lib/pbio/sys/main.c is called. That contains all calls to the driver
 // initialization (low level in pbdrv, high level in pbio), and system level
@@ -371,21 +528,26 @@ void SystemInit(void) {
 
     copy_vector_table();
 
-    /* Initialize AINTC */
+    // Initialize advanced interrupt controller (AINTC)
     IntAINTCInit();
-
-    /* Enable IRQ for ARM (in CPSR)*/
     IntMasterIRQEnable();
-
-    /* Enable AINTC interrupts in GER */
     IntGlobalEnable();
-
-    /* Enable IRQ in AINTC */
     IntIRQEnable();
-
     IntMasterFIQEnable();
     IntFIQEnable();
 
+    // Initialization of EDMA3
+    PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_CC0, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
+    PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_TC0, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
+    EDMA3Init(SOC_EDMA30CC_0_REGS, 0); // Que num 0
+    IntRegister(SYS_INT_CCINT0, Edma3ComplHandlerIsr);
+    IntChannelSet(SYS_INT_CCINT0, 2);
+    IntSystemEnable(SYS_INT_CCINT0);
+    IntRegister(SYS_INT_CCERRINT, Edma3CCErrHandlerIsr);
+    IntChannelSet(SYS_INT_CCERRINT, 2);
+    IntSystemEnable(SYS_INT_CCERRINT);
+
+
     PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_GPIO, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
 
     // Must set the power enable bin before disabling the pull up on the power