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dlechdlech
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platform: move interrupt configuration
Technically speaking, the SysTick interrupt is enabled when clocks are configured so configuration related to interrupts should happen before then.
1 parent 6719ac5 commit b094823

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5 files changed

+51
-56
lines changed

5 files changed

+51
-56
lines changed

‎lib/pbio/platform/city_hub/platform.c‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -200,15 +200,23 @@ extern uint32_t _fw_isr_vector_dst[48];
200200
// this function is a mash up of ports/stm32/system_stm32f0.c from MicroPython
201201
// and the official LEGO firmware
202202
void SystemInit(void) {
203+
// since the firmware starts at 0x08005000, we need to relocate the
204+
// interrupt vector table to a place where the CPU knows about it.
205+
// The space at the start of SRAM is reserved in via the linker script.
206+
memcpy(_fw_isr_vector_dst, _fw_isr_vector_src, sizeof(_fw_isr_vector_dst));
207+
208+
// this maps SRAM to 0x00000000
209+
SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE_Msk) | (3 << SYSCFG_CFGR1_MEM_MODE_Pos);
210+
211+
// enable 8-byte stack alignment for IRQ handlers, in accord with EABI
212+
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
213+
203214
// normally, the system clock would be setup here, but it is already
204215
// configured by the bootloader, so no need to do it again.
205216

206217
// SysTick set for 1ms ticks
207218
SysTick_Config(PBDRV_CONFIG_SYS_CLOCK_RATE / 1000);
208219

209-
// enable 8-byte stack alignment for IRQ handlers, in accord with EABI
210-
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
211-
212220
// Enable all of the hardware modules we are using
213221
RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN
214222
| RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | RCC_AHBENR_GPIOFEN;
@@ -224,7 +232,7 @@ void SystemInit(void) {
224232
GPIOB->MODER = (GPIOB->MODER & ~GPIO_MODER_MODER2_Msk) | (1 << GPIO_MODER_MODER2_Pos);
225233
GPIOB->BSRR = GPIO_BSRR_BS_2;
226234

227-
// not sure what the rest of these pins do
235+
// Unused pins
228236

229237
// PA5 output, low
230238
GPIOA->MODER = (GPIOA->MODER & ~GPIO_MODER_MODER5_Msk) | (1 << GPIO_MODER_MODER5_Pos);
@@ -265,12 +273,4 @@ void SystemInit(void) {
265273
// PF1 output, low
266274
GPIOF->MODER = (GPIOF->MODER & ~GPIO_MODER_MODER1_Msk) | (1 << GPIO_MODER_MODER1_Pos);
267275
GPIOF->BSRR = GPIO_BSRR_BR_1;
268-
269-
// since the firmware starts at 0x08005000, we need to relocate the
270-
// interrupt vector table to a place where the CPU knows about it.
271-
// The space at the start of SRAM is reserved in via the linker script.
272-
memcpy(_fw_isr_vector_dst, _fw_isr_vector_src, sizeof(_fw_isr_vector_dst));
273-
274-
// this maps SRAM to 0x00000000
275-
SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE_Msk) | (3 << SYSCFG_CFGR1_MEM_MODE_Pos);
276276
}

‎lib/pbio/platform/debug/platform.c‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -265,10 +265,16 @@ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8,
265265
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
266266

267267
void SystemInit(void) {
268-
RCC_OscInitTypeDef osc_init;
269-
RCC_ClkInitTypeDef clk_init;
268+
269+
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
270+
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
271+
#endif
272+
273+
// enable 8-byte stack alignment for IRQ handlers, in accord with EABI
274+
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
270275

271276
// Using internal 16Mhz oscillator
277+
RCC_OscInitTypeDef osc_init;
272278
osc_init.OscillatorType = RCC_OSCILLATORTYPE_HSE;
273279
osc_init.HSEState = RCC_HSE_ON;
274280
osc_init.HSIState = RCC_HSI_OFF;
@@ -281,6 +287,7 @@ void SystemInit(void) {
281287

282288
HAL_RCC_OscConfig(&osc_init);
283289

290+
RCC_ClkInitTypeDef clk_init;
284291
clk_init.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
285292
clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
286293
clk_init.AHBCLKDivider = RCC_SYSCLK_DIV1; // HCLK 48MHz (max 180MHz)
@@ -289,13 +296,6 @@ void SystemInit(void) {
289296

290297
HAL_RCC_ClockConfig(&clk_init, FLASH_LATENCY_5);
291298

292-
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
293-
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
294-
#endif
295-
296-
// enable 8-byte stack alignment for IRQ handlers, in accord with EABI
297-
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
298-
299299
// enable all of the hardware modules we are using
300300
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN |
301301
RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN |

‎lib/pbio/platform/move_hub/platform.c‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -252,15 +252,23 @@ extern uint32_t _fw_isr_vector_dst[48];
252252
// this function is a mash up of ports/stm32/system_stm32f0.c from MicroPython
253253
// and the official LEGO firmware
254254
void SystemInit(void) {
255+
// since the firmware starts at 0x08005000, we need to relocate the
256+
// interrupt vector table to a place where the CPU knows about it.
257+
// The space at the start of SRAM is reserved in via the linker script.
258+
memcpy(_fw_isr_vector_dst, _fw_isr_vector_src, sizeof(_fw_isr_vector_dst));
259+
260+
// this maps SRAM to 0x00000000
261+
SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE_Msk) | (3 << SYSCFG_CFGR1_MEM_MODE_Pos);
262+
263+
// enable 8-byte stack alignment for IRQ handlers, in accord with EABI
264+
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
265+
255266
// normally, the system clock would be setup here, but it is already
256267
// configured by the bootloader, so no need to do it again.
257268

258269
// SysTick set for 1ms ticks
259270
SysTick_Config(PBDRV_CONFIG_SYS_CLOCK_RATE / 1000);
260271

261-
// enable 8-byte stack alignment for IRQ handlers, in accord with EABI
262-
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
263-
264272
// Enable all of the hardware modules we are using
265273
RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN
266274
| RCC_AHBENR_GPIODEN | RCC_AHBENR_GPIOFEN;
@@ -276,7 +284,7 @@ void SystemInit(void) {
276284
GPIOB->BSRR = GPIO_BSRR_BS_2;
277285
GPIOB->MODER = (GPIOB->MODER & ~GPIO_MODER_MODER2_Msk) | (1 << GPIO_MODER_MODER2_Pos);
278286

279-
// not sure what the rest of these pins do
287+
// Unused pins
280288

281289
// PF0 output, high
282290
GPIOF->BSRR = GPIO_BSRR_BS_0;
@@ -301,12 +309,4 @@ void SystemInit(void) {
301309
// PF1 output, high
302310
GPIOF->BSRR = GPIO_BSRR_BS_1;
303311
GPIOF->MODER = (GPIOF->MODER & ~GPIO_MODER_MODER1_Msk) | (1 << GPIO_MODER_MODER1_Pos);
304-
305-
// since the firmware starts at 0x08005000, we need to relocate the
306-
// interrupt vector table to a place where the CPU knows about it.
307-
// The space at the start of SRAM is reserved in via the linker script.
308-
memcpy(_fw_isr_vector_dst, _fw_isr_vector_src, sizeof(_fw_isr_vector_dst));
309-
310-
// this maps SRAM to 0x00000000
311-
SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE_Msk) | (3 << SYSCFG_CFGR1_MEM_MODE_Pos);
312312
}

‎lib/pbio/platform/prime_hub/platform.c‎

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -696,14 +696,19 @@ extern uint32_t *_fw_isr_vector_src;
696696

697697
// Called from assembly code in startup.s
698698
void SystemInit(void) {
699+
// enable 8-byte stack alignment for IRQ handlers, in accord with EABI
700+
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
701+
702+
// since the firmware starts at 0x08008000, we need to set the vector table offset
703+
SCB->VTOR = (uint32_t)&_fw_isr_vector_src;
699704

700-
RCC_OscInitTypeDef osc_init;
701-
RCC_ClkInitTypeDef clk_init;
705+
// bootloader disables interrupts
706+
__enable_irq();
702707

703708
// Using external 16Mhz oscillator
709+
RCC_OscInitTypeDef osc_init = { 0 };
704710
osc_init.OscillatorType = RCC_OSCILLATORTYPE_HSE;
705711
osc_init.HSEState = RCC_HSE_ON;
706-
osc_init.HSIState = RCC_HSI_OFF;
707712
osc_init.PLL.PLLState = RCC_PLL_ON;
708713
osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE;
709714
osc_init.PLL.PLLM = 8; // VCO_IN 2MHz (16MHz / 8)
@@ -713,6 +718,7 @@ void SystemInit(void) {
713718

714719
HAL_RCC_OscConfig(&osc_init);
715720

721+
RCC_ClkInitTypeDef clk_init = { 0 };
716722
clk_init.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
717723
clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
718724
clk_init.AHBCLKDivider = RCC_SYSCLK_DIV1; // HCLK 96MHz
@@ -721,15 +727,6 @@ void SystemInit(void) {
721727

722728
HAL_RCC_ClockConfig(&clk_init, FLASH_LATENCY_5);
723729

724-
// enable 8-byte stack alignment for IRQ handlers, in accord with EABI
725-
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
726-
727-
// since the firmware starts at 0x08008000, we need to set the vector table offset
728-
SCB->VTOR = (uint32_t)&_fw_isr_vector_src;
729-
730-
// bootloader disables interrupts
731-
__enable_irq();
732-
733730
// If we are running dual boot, jump to other firmware if no buttons are pressed
734731
pbio_platform_dual_boot();
735732

‎lib/pbio/platform/technic_hub/platform.c‎

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -449,15 +449,18 @@ extern uint32_t *_fw_isr_vector_src;
449449

450450
// Called from assembly code in startup.s
451451
void SystemInit(void) {
452-
RCC_OscInitTypeDef osc_init = { 0 };
453-
RCC_ClkInitTypeDef clk_init = { 0 };
454-
GPIO_InitTypeDef gpio_init = { 0 };
455-
456452
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
457453
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
458454
#endif
459455

456+
// enable 8-byte stack alignment for IRQ handlers, in accord with EABI
457+
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
458+
459+
// since the firmware starts at 0x08008000, we need to set the vector table offset
460+
SCB->VTOR = (uint32_t)&_fw_isr_vector_src;
461+
460462
// Using external 16Mhz oscillator
463+
RCC_OscInitTypeDef osc_init = { 0 };
461464
osc_init.OscillatorType = RCC_OSCILLATORTYPE_MSI;
462465
osc_init.MSIState = RCC_MSI_ON;
463466
osc_init.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
@@ -472,6 +475,7 @@ void SystemInit(void) {
472475

473476
HAL_RCC_OscConfig(&osc_init);
474477

478+
RCC_ClkInitTypeDef clk_init = { 0 };
475479
clk_init.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
476480
clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
477481
clk_init.AHBCLKDivider = RCC_SYSCLK_DIV1; // HCLK 80MHz
@@ -481,9 +485,6 @@ void SystemInit(void) {
481485

482486
HAL_RCC_ClockConfig(&clk_init, FLASH_LATENCY_4);
483487

484-
// enable 8-byte stack alignment for IRQ handlers, in accord with EABI
485-
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
486-
487488
// enable clocks
488489
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN | RCC_AHB1ENR_DMA2EN | RCC_AHB1ENR_FLASHEN |
489490
RCC_AHB1ENR_CRCEN;
@@ -495,8 +496,8 @@ void SystemInit(void) {
495496
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_SPI1EN |
496497
RCC_APB2ENR_USART1EN | RCC_APB2ENR_TIM15EN | RCC_APB2ENR_TIM16EN;
497498

498-
499499
// Keep main power on (PC12)
500+
GPIO_InitTypeDef gpio_init = { 0 };
500501
gpio_init.Pin = GPIO_PIN_12;
501502
gpio_init.Mode = GPIO_MODE_OUTPUT_PP;
502503
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_12, GPIO_PIN_SET);
@@ -505,7 +506,4 @@ void SystemInit(void) {
505506
// Turn VCC_PORT on (PB12)
506507
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET);
507508
HAL_GPIO_Init(GPIOB, &gpio_init);
508-
509-
// since the firmware starts at 0x08008000, we need to set the vector table offset
510-
SCB->VTOR = (uint32_t)&_fw_isr_vector_src;
511509
}

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