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ArcaneNibbleArcaneNibble
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test two ports
1 parent fba5254 commit b9f6f02

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+43
-32
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2 files changed

+43
-32
lines changed

‎lib/pbio/drv/i2c/i2c_ev3.c‎

Lines changed: 42 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -70,8 +70,10 @@ pbio_error_t pbdrv_i2c_placeholder_operation(pbdrv_i2c_dev_t *i2c_dev, const cha
7070

7171
static pbio_os_process_t ev3_i2c_wip_process;
7272

73-
static pbdrv_gpio_t test_scl = PBDRV_GPIO_EV3_PIN(0, 15, 12, 0, 12);
74-
static pbdrv_gpio_t test_sda = PBDRV_GPIO_EV3_PIN(2, 7, 4, 1, 14);
73+
static pbdrv_gpio_t test_2_scl = PBDRV_GPIO_EV3_PIN(0, 15, 12, 0, 12);
74+
static pbdrv_gpio_t test_2_sda = PBDRV_GPIO_EV3_PIN(2, 7, 4, 1, 14);
75+
static pbdrv_gpio_t test_3_scl = PBDRV_GPIO_EV3_PIN(1, 27, 24, 0, 1);
76+
static pbdrv_gpio_t test_3_sda = PBDRV_GPIO_EV3_PIN(2, 3, 0, 1, 15);
7577

7678
static inline void delaydelay() {
7779
for (int i = 0; i < 100; i++) __asm__ volatile("");
@@ -80,7 +82,8 @@ static inline void delaydelay() {
8082
extern void panic_puts(const char *c);
8183
extern void panic_putu8(uint8_t x);
8284

83-
uint8_t i2c_wip_buf[16];
85+
uint8_t i2c_wip_buf_2[16];
86+
uint8_t i2c_wip_buf_3[16];
8487

8588
pbio_error_t ev3_i2c_wip_process_thread(pbio_os_state_t *state, void *context) {
8689
static pbio_os_timer_t timer;
@@ -90,46 +93,54 @@ pbio_error_t ev3_i2c_wip_process_thread(pbio_os_state_t *state, void *context) {
9093

9194
PBIO_OS_ASYNC_BEGIN(state);
9295

93-
pbdrv_gpio_out_low(&test_scl);
94-
pbdrv_gpio_input(&test_scl);
95-
pbdrv_gpio_out_low(&test_sda);
96-
pbdrv_gpio_input(&test_sda);
96+
pbdrv_gpio_out_low(&test_2_scl);
97+
pbdrv_gpio_input(&test_2_scl);
98+
pbdrv_gpio_out_low(&test_2_sda);
99+
pbdrv_gpio_input(&test_2_sda);
100+
pbdrv_gpio_out_low(&test_3_scl);
101+
pbdrv_gpio_input(&test_3_scl);
102+
pbdrv_gpio_out_low(&test_3_sda);
103+
pbdrv_gpio_input(&test_3_sda);
97104

98105
PBIO_OS_AWAIT_MS(state, &timer, 100);
99-
debug_pr("i2c test start C%d D%d\r\n", pbdrv_gpio_input(&test_scl), pbdrv_gpio_input(&test_sda));
100-
101-
i2c_wip_buf[0] = 0x10;
102-
i2c_wip_buf[1] = 0xaa;
103-
i2c_wip_buf[2] = 0x55;
104-
i2c_wip_buf[3] = 0x12;
105-
i2c_wip_buf[4] = 0x34;
106+
debug_pr("i2c test start C%d D%d\r\n", pbdrv_gpio_input(&test_2_scl), pbdrv_gpio_input(&test_2_sda));
107+
108+
i2c_wip_buf_2[0] = 0x10;
109+
i2c_wip_buf_3[0] = 0x10;
110+
i2c_wip_buf_3[1] = 0xaa;
111+
i2c_wip_buf_3[2] = 0x55;
112+
i2c_wip_buf_3[3] = 0x12;
113+
i2c_wip_buf_3[4] = 0x34;
106114
pbdrv_compiler_memory_barrier();
107-
*(volatile uint32_t *)(0x80010008) = (uint32_t)i2c_wip_buf;
108-
*(volatile uint32_t *)(0x80010004) = 0x17000501;
109-
// *(volatile uint32_t *)(0x80010004) = 0x01060103;
115+
*(volatile uint32_t *)(0x80010018) = (uint32_t)i2c_wip_buf_2;
116+
*(volatile uint32_t *)(0x80010020) = (uint32_t)i2c_wip_buf_3;
117+
118+
*(volatile uint32_t *)(0x80010014) = 0x01060103;
119+
*(volatile uint32_t *)(0x8001001c) = 0x17000501;
110120

111121
pbio_os_timer_set(&timer, 1000);
112-
PBIO_OS_AWAIT_UNTIL(state, *(volatile uint8_t *)(0x80010004) & 0x80 || pbio_os_timer_is_expired(&timer));
122+
PBIO_OS_AWAIT_UNTIL(state, ((*(volatile uint8_t *)(0x80010014) & 0x80) && (*(volatile uint8_t *)(0x8001001c) & 0x80)) || pbio_os_timer_is_expired(&timer));
113123
debug_pr("i2c test done\r\n");
114-
debug_pr("i2c flags %08x\r\n", *(volatile uint32_t *)(0x80010004));
115-
debug_pr("i2c max time %d\r\n", *(volatile uint32_t *)(0x8001000c));
124+
debug_pr("i2c flags %08x\r\n", *(volatile uint32_t *)(0x80010014));
125+
debug_pr("i2c flags %08x\r\n", *(volatile uint32_t *)(0x8001001c));
126+
debug_pr("i2c max time %d\r\n", *(volatile uint32_t *)(0x80010024));
116127

117-
debug_pr("i2c test end C%d D%d\r\n", pbdrv_gpio_input(&test_scl), pbdrv_gpio_input(&test_sda));
128+
debug_pr("i2c test end C%d D%d\r\n", pbdrv_gpio_input(&test_2_scl), pbdrv_gpio_input(&test_2_sda));
118129

119130
PBIO_OS_AWAIT_MS(state, &timer, 100);
120131

121-
debug_pr("i2c test end 2 C%d D%d\r\n", pbdrv_gpio_input(&test_scl), pbdrv_gpio_input(&test_sda));
132+
debug_pr("i2c test end 2 C%d D%d\r\n", pbdrv_gpio_input(&test_2_scl), pbdrv_gpio_input(&test_2_sda));
122133

123134
// NEW
124-
i2c_wip_buf[0] = 0x0e;
135+
i2c_wip_buf_3[0] = 0x0e;
125136
pbdrv_compiler_memory_barrier();
126-
*(volatile uint32_t *)(0x80010004) = 0x17060101;
137+
*(volatile uint32_t *)(0x8001001c) = 0x17060101;
127138

128139
pbio_os_timer_set(&timer, 1000);
129-
PBIO_OS_AWAIT_UNTIL(state, *(volatile uint8_t *)(0x80010004) & 0x80 || pbio_os_timer_is_expired(&timer));
140+
PBIO_OS_AWAIT_UNTIL(state, *(volatile uint8_t *)(0x8001001c) & 0x80 || pbio_os_timer_is_expired(&timer));
130141
debug_pr("i2c #2 test done\r\n");
131-
debug_pr("i2c #2 flags %08x\r\n", *(volatile uint32_t *)(0x80010004));
132-
debug_pr("i2c #2 max time %d\r\n", *(volatile uint32_t *)(0x8001000c));
142+
debug_pr("i2c #2 flags %08x\r\n", *(volatile uint32_t *)(0x8001001c));
143+
debug_pr("i2c #2 max time %d\r\n", *(volatile uint32_t *)(0x80010024));
133144

134145
PBIO_OS_AWAIT_MS(state, &timer, 100);
135146

@@ -141,7 +152,10 @@ pbio_error_t ev3_i2c_wip_process_thread(pbio_os_state_t *state, void *context) {
141152
}
142153

143154
for (i = 0; i < 6; i++) {
144-
debug_pr("i2c get %02x\r\n", i2c_wip_buf[1 + i]);
155+
debug_pr("i2c #1 get %02x\r\n", i2c_wip_buf_2[1 + i]);
156+
}
157+
for (i = 0; i < 6; i++) {
158+
debug_pr("i2c #2 get %02x\r\n", i2c_wip_buf_3[1 + i]);
145159
}
146160

147161
PBIO_OS_ASYNC_END(PBIO_SUCCESS);

‎lib/pbio/drv/pwm/pwm_ev3.c‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -27,10 +27,7 @@
2727
// This needs to match the interface expected by the PRU firmware
2828
typedef struct shared_ram {
2929
uint8_t pwms[PBDRV_PWM_EV3_NUM_CHANNELS];
30-
uint32_t dummy0;
31-
uint32_t dummy1;
32-
uint32_t dummy2;
33-
uint32_t dummy3;
30+
uint32_t dummy[9];
3431
} shared_ram;
3532
static volatile shared_ram pru1_shared_ram __attribute__((section(".shared1")));
3633

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