pbio/drv/adc_ev3: Give control to block device.

The block device initiates the ADC polling process when it is fully loaded, and awaits the ADC process to exit before it writes.

Fixes pybricks/support#2264

Author: laurensvalk

lib/pbio/drv/adc/adc_ev3.c

@@ -91,9 +91,6 @@ static const uint32_t channel_cmd[PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_
 static volatile uint16_t channel_data[PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_ADC_EV3_NUM_DELAY_SAMPLES];
 
 static int adc_soon;
-// Used to block ADC from interfering with flash upon shutdown
-static int shut_down_hack = 0;
-static int shut_down_hack_done = 0;
 
 static pbdrv_adc_callback_t pbdrv_adc_callbacks[1];
 static uint32_t pbdrv_adc_callback_count = 0;
@@ -124,24 +121,30 @@ pbio_error_t pbdrv_adc_get_ch(uint8_t ch, uint16_t *value) {
 
 static pbio_os_process_t pbdrv_adc_ev3_process;
 
+/**
+ * Request ADC process to exit and await until it does.
+ */
+pbio_error_t pbdrv_adc_ev3_exit(pbio_os_state_t *state) {
+    PBIO_OS_ASYNC_BEGIN(state);
+
+    pbio_os_process_make_request(&pbdrv_adc_ev3_process, PBIO_OS_PROCESS_REQUEST_TYPE_CANCEL);
+    PBIO_OS_AWAIT_UNTIL(state, pbdrv_adc_ev3_process.err == PBIO_SUCCESS);
+
+    PBIO_OS_ASYNC_END(PBIO_SUCCESS);
+}
+
 pbio_error_t pbdrv_adc_ev3_process_thread(pbio_os_state_t *state, void *context) {
     static pbio_os_timer_t timer;
 
     PBIO_OS_ASYNC_BEGIN(state);
 
-    // HACK: This waits until storage is completely done with SPI flash before we start
-    PBIO_OS_AWAIT_UNTIL(state, pbsys_storage_settings_get_settings());
-
-    // Once SPI flash init is finished, there is nothing further for us to do.
-    // We are ready to start sampling.
-
     pbio_os_timer_set(&timer, ADC_SAMPLE_PERIOD);
 
     for (;;) {
-        PBIO_OS_AWAIT_UNTIL(state, shut_down_hack || adc_soon || pbio_os_timer_is_expired(&timer));
+        PBIO_OS_AWAIT_UNTIL(state, pbdrv_adc_ev3_process.request || adc_soon || pbio_os_timer_is_expired(&timer));
 
-        if (shut_down_hack) {
-            shut_down_hack_done = 1;
+        // Here we can exit gracefully since no SPI operation is in progress.
+        if (pbdrv_adc_ev3_process.request & PBIO_OS_PROCESS_REQUEST_TYPE_CANCEL) {
             break;
         }
 
@@ -165,22 +168,26 @@ pbio_error_t pbdrv_adc_ev3_process_thread(pbio_os_state_t *state, void *context)
         }
     }
 
-    PBIO_OS_ASYNC_END(PBIO_SUCCESS);
-}
-
-void pbdrv_adc_init(void) {
-    // Immediately go into async mode so that we can wait for the SPI flash driver.
-    // We *don't* want to block the initial init phase, or else things will deadlock.
+    // Processes may be waiting on us to complete, so kick when done.
+    pbio_os_request_poll();
 
-    pbio_os_process_start(&pbdrv_adc_ev3_process, pbdrv_adc_ev3_process_thread, NULL);
+    PBIO_OS_ASYNC_END(PBIO_SUCCESS);
 }
 
 void pbdrv_adc_update_soon(void) {
     adc_soon = 1;
     pbio_os_request_poll();
 }
 
-void pbdrv_adc_ev3_configure_data_format() {
+// Public init is not used.
+void pbdrv_adc_init(void) {
+}
+
+// Init starts here instead. Called by SPI flash driver when it is done initializing.
+void pbdrv_adc_ev3_init(void) {
+
+    // Most of the SPI initialization is already done by the SPI flash driver.
+
     SPIClkConfigure(SOC_SPI_0_REGS, SOC_SYSCLK_2_FREQ, SPI_CLK_SPEED_ADC, SPI_DATA_FORMAT1);
     // NOTE: Cannot be CPOL=1 CPHA=1 like SPI flash
     // The ADC seems to use the last falling edge to trigger conversions (see Figure 1 in the datasheet).
@@ -193,14 +200,9 @@ void pbdrv_adc_ev3_configure_data_format() {
     // as well as the CS-assert-to-clock-start and clock-end-to-CS-deassert delays
     // (which are global and set in block_device_ev3.c).
     SPIWdelaySet(SOC_SPI_0_REGS, 0x3f << SPI_SPIFMT_WDELAY_SHIFT, SPI_DATA_FORMAT1);
-}
 
-void pbdrv_adc_ev3_shut_down_hack() {
-    shut_down_hack = 1;
-    pbio_os_request_poll();
-}
-int pbdrv_adc_ev3_is_shut_down_hack() {
-    return shut_down_hack_done;
+    // Begin polling.
+    pbio_os_process_start(&pbdrv_adc_ev3_process, pbdrv_adc_ev3_process_thread, NULL);
 }
 
 #endif // PBDRV_CONFIG_ADC_EV3

lib/pbio/drv/adc/adc_ev3.h

@@ -4,9 +4,7 @@
 #ifndef _INTERNAL_PBDRV_ADC_EV3_H_
 #define _INTERNAL_PBDRV_ADC_EV3_H_
 
-void pbdrv_adc_ev3_configure_data_format();
-
-void pbdrv_adc_ev3_shut_down_hack();
-int pbdrv_adc_ev3_is_shut_down_hack();
+void pbdrv_adc_ev3_init(void);
+pbio_error_t pbdrv_adc_ev3_exit(pbio_os_state_t *state);
 
 #endif // _INTERNAL_PBDRV_ADC_EV3_H_

lib/pbio/drv/block_device/block_device_ev3.c

@@ -616,6 +616,9 @@ pbio_error_t pbdrv_block_device_write_all(pbio_os_state_t *state, uint32_t used_
 
     PBIO_OS_ASYNC_BEGIN(state);
 
+    // Need to await the ADC process to exit before we can write to flash.
+    PBIO_OS_AWAIT(state, &sub, pbdrv_adc_ev3_exit(&sub));
+
     // Exit on invalid size.
     if (size == 0 || size > PBDRV_CONFIG_BLOCK_DEVICE_EV3_SIZE) {
         return PBIO_ERROR_INVALID_ARG;
@@ -624,13 +627,6 @@ pbio_error_t pbdrv_block_device_write_all(pbio_os_state_t *state, uint32_t used_
     // Store the new size so we know how much to load on next boot.
     ramdisk.saved_size = size;
 
-    #if PBDRV_CONFIG_ADC_EV3
-    // HACK
-    // We only store on shutdown. Block ADC.
-    pbdrv_adc_ev3_shut_down_hack();
-    PBIO_OS_AWAIT_UNTIL(state, pbdrv_adc_ev3_is_shut_down_hack());
-    #endif
-
     // Erase sector by sector.
     for (offset = 0; offset < size; offset += FLASH_SIZE_ERASE) {
         // Enable writing
@@ -719,6 +715,9 @@ pbio_error_t pbdrv_block_device_ev3_init_process_thread(pbio_os_state_t *state,
     // properly on shutdown.
     pbdrv_init_busy_down();
 
+    // ADC may start polling now.
+    pbdrv_adc_ev3_init();
+
     PBIO_OS_ASYNC_END(err);
 }
 
@@ -743,9 +742,8 @@ void pbdrv_block_device_init(void) {
     SPIConfigClkFormat(SOC_SPI_0_REGS, SPI_CLK_POL_LOW | SPI_CLK_OUTOFPHASE, SPI_DATA_FORMAT0);
     SPIShiftMsbFirst(SOC_SPI_0_REGS, SPI_DATA_FORMAT0);
     SPICharLengthSet(SOC_SPI_0_REGS, 8, SPI_DATA_FORMAT0);
-    #if PBDRV_CONFIG_ADC_EV3
-    pbdrv_adc_ev3_configure_data_format();
-    #endif
+
+    // Additional SPI configuration ADC is done when the ADC driver starts.
 
     // Configure the GPIO pins.
     pbdrv_gpio_alt(&pin_spi0_mosi, SYSCFG_PINMUX3_PINMUX3_15_12_SPI0_SIMO0);

lib/pbio/drv/block_device/block_device_ev3.h

@@ -10,15 +10,15 @@
 #define PBDRV_EV3_SPI0_FLASH_CS     (0)
 #define PBDRV_EV3_SPI0_ADC_CS       (3)
 
-void pbdrv_block_device_ev3_spi_tx_complete();
-void pbdrv_block_device_ev3_spi_rx_complete();
+void pbdrv_block_device_ev3_spi_tx_complete(void);
+void pbdrv_block_device_ev3_spi_rx_complete(void);
 
 // XXX The SPI flash and ADC both use the SPI0 peripheral.
 // Since we do not have a fully-fledged "bus" abstraction,
 // these two drivers have tight dependencies on each other.
 // These functions orchestrate the connection.
 
-int pbdrv_block_device_ev3_is_busy();
+int pbdrv_block_device_ev3_is_busy(void);
 pbio_error_t pbdrv_block_device_ev3_spi_begin_for_adc(const uint32_t *cmds, volatile uint16_t *data, unsigned int len);
 
 #endif // _INTERNAL_PBDRV_BLOCK_DEVICE_EV3_H_