bus width switch okay

Author: ArcaneNibble

lib/pbio/drv/mmcsd/mmcsd_ev3.c

@@ -154,6 +154,50 @@ pbio_error_t ev3_mmcsd_process_thread(pbio_os_state_t *state, void *context) {
     // pbdrv_uart_debug_printf("acmd51 %08x %08x\r\n", resp[0], resp[1]);
     pbdrv_uart_debug_printf("acmd51 %08x %08x\r\n", data[0], data[1]);
 
+    // acmd6
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCARGHL) = rca;
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCCMD) = (55 << MMCSD_MMCCMD_CMD_SHIFT) | (MMCSD_MMCCMD_RSPFMT_R1 << MMCSD_MMCCMD_RSPFMT_SHIFT) | MMCSD_MMCCMD_PPLEN;
+    PBIO_OS_AWAIT_UNTIL(state, HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCST0) & MMCSD_MMCST0_RSPDNE);
+    resp[0] = HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCRSP45);
+    resp[1] = HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCRSP67);
+    // pbdrv_uart_debug_printf("cmd55 %08x %08x\r\n", resp[0], resp[1]);
+
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCARGHL) = 2;
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCCMD) = (6 << MMCSD_MMCCMD_CMD_SHIFT) | (MMCSD_MMCCMD_RSPFMT_R1 << MMCSD_MMCCMD_RSPFMT_SHIFT) | MMCSD_MMCCMD_PPLEN;
+    PBIO_OS_AWAIT_UNTIL(state, HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCST0) & MMCSD_MMCST0_RSPDNE);
+    resp[0] = HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCRSP45);
+    resp[1] = HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCRSP67);
+    // pbdrv_uart_debug_printf("acmd6 %08x %08x\r\n", resp[0], resp[1]);
+
+    // switch host to 4-bit mode
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCCTL) |= MMCSD_MMCCTL_WIDTH1_WIDTH0_4BIT;
+
+    // acmd51 again for testing
+
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCFIFOCTL) = MMCSD_MMCFIFOCTL_FIFORST;
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCFIFOCTL) = MMCSD_MMCFIFOCTL_ACCWD_4BYTES | (0 << MMCSD_MMCFIFOCTL_FIFODIR_SHIFT);
+
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCARGHL) = rca;
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCCMD) = (55 << MMCSD_MMCCMD_CMD_SHIFT) | (MMCSD_MMCCMD_RSPFMT_R1 << MMCSD_MMCCMD_RSPFMT_SHIFT) | MMCSD_MMCCMD_PPLEN;
+    PBIO_OS_AWAIT_UNTIL(state, HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCST0) & MMCSD_MMCST0_RSPDNE);
+    resp[0] = HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCRSP45);
+    resp[1] = HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCRSP67);
+    // pbdrv_uart_debug_printf("cmd55 %08x %08x\r\n", resp[0], resp[1]);
+
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCBLEN) = 8;
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCNBLK) = 1;
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCARGHL) = 0;
+    HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCCMD) = (51 << MMCSD_MMCCMD_CMD_SHIFT) | (MMCSD_MMCCMD_RSPFMT_R1 << MMCSD_MMCCMD_RSPFMT_SHIFT) | MMCSD_MMCCMD_PPLEN | MMCSD_MMCCMD_WDATX;
+    PBIO_OS_AWAIT_WHILE(state, HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCST1) & MMCSD_MMCST1_FIFOEMP);
+    data[0] = HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCDRR);
+    PBIO_OS_AWAIT_WHILE(state, HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCST1) & MMCSD_MMCST1_FIFOEMP);
+    data[1] = HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCDRR);
+    PBIO_OS_AWAIT_UNTIL(state, HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCST0) & MMCSD_MMCST0_DATDNE);
+    resp[0] = HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCRSP45);
+    resp[1] = HWREG(SOC_MMCSD_0_REGS + MMCSD_MMCRSP67);
+    // pbdrv_uart_debug_printf("acmd51 %08x %08x\r\n", resp[0], resp[1]);
+    pbdrv_uart_debug_printf("acmd51 v2 %08x %08x\r\n", data[0], data[1]);
+
     pbdrv_uart_debug_printf("mmcsd init defer end\r\n");
 
     PBIO_OS_ASYNC_END(PBIO_SUCCESS);