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ArcaneNibbleArcaneNibble
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untested re-enable of adc stuff
1 parent be0d7ab commit c62fe10

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+38
-109
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+38
-109
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‎lib/pbio/drv/adc/adc_ev3.c‎

Lines changed: 38 additions & 109 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@
3737
#define PBDRV_CONFIG_ADC_EV3_NUM_DELAY_SAMPLES (2)
3838

3939
/**
40-
* Bus speeds.
40+
* Constants.
4141
*/
4242
enum {
4343
// The maximum ADC clock speed according to the datasheet is 20 MHz
@@ -49,6 +49,8 @@ enum {
4949
//
5050
// 150 MHz / 8 = 18.75 MHz
5151
SPI_CLK_SPEED_ADC = 18750000,
52+
53+
ADC_SAMPLE_PERIOD = 10,
5254
};
5355

5456
// Construct both SPI peripheral settings (data format, chip select)
@@ -85,8 +87,8 @@ static const uint32_t channel_cmd[PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_
8587
};
8688
// XXX What are the atomicity guarantees around this? What guarantees do we need?
8789
static volatile uint16_t channel_data[PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_CONFIG_ADC_EV3_NUM_DELAY_SAMPLES];
88-
static volatile uint8_t channel_data_index = 0;
89-
static volatile bool adc_busy = false;
90+
91+
static int adc_soon;
9092

9193
static pbdrv_adc_callback_t pbdrv_adc_callbacks[1];
9294
static uint32_t pbdrv_adc_callback_count = 0;
@@ -109,87 +111,42 @@ pbio_error_t pbdrv_adc_get_ch(uint8_t ch, uint16_t *value) {
109111
// return PBIO_SUCCESS;
110112
}
111113

112-
// static void spi0_isr(void) {
113-
// uint32_t intCode = 0;
114-
// IntSystemStatusClear(SYS_INT_SPINT0);
115-
116-
// while ((intCode = SPIInterruptVectorGet(SOC_SPI_0_REGS))) {
117-
// if (intCode != SPI_TX_BUF_EMPTY) {
118-
// continue;
119-
// }
120-
// // Payload encoding comes from the original EV3 sources, but we
121-
// // use the hardware SPI peripheral instead of bit-banging.
122-
// uint16_t payload = 0x1840 | (((channel_data_index % PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS) & 0x000F) << 7);
123-
// HWREG(SOC_SPI_0_REGS + SPI_SPIDAT0) = payload;
124-
// channel_data[channel_data_index] = SPIDataReceive(SOC_SPI_0_REGS);
125-
126-
// if (++channel_data_index == PBIO_ARRAY_SIZE(channel_data)) {
127-
// SPIIntDisable(SOC_SPI_0_REGS, SPI_TRANSMIT_INT);
128-
// adc_busy = false;
129-
// process_poll(&pbdrv_adc_process);
130-
// }
131-
// }
132-
// }
133-
134-
// static void pbdrv_adc_exit(void) {
135-
// SPIIntDisable(SOC_SPI_0_REGS, SPI_RECV_INT | SPI_TRANSMIT_INT);
136-
// }
137-
138-
// // ADC / Flash SPI0 data MOSI
139-
// static const pbdrv_gpio_t pin_spi0_mosi = PBDRV_GPIO_EV3_PIN(3, 15, 12, 8, 5);
140-
141-
// // ADC / Flash SPI0 data MISO
142-
// static const pbdrv_gpio_t pin_spi0_miso = PBDRV_GPIO_EV3_PIN(3, 11, 8, 8, 6);
114+
static pbio_os_process_t pbdrv_adc_ev3_process;
143115

144-
// // LCD SPI0 Clock
145-
// static const pbdrv_gpio_t pin_spi0_clk = PBDRV_GPIO_EV3_PIN(3, 3, 0, 1, 8);
116+
pbio_error_t pbdrv_adc_ev3_process_thread(pbio_os_state_t *state, void *context) {
117+
static pbio_os_timer_t timer;
146118

147-
// // ADC / Flash SPI0 chip select (active low).
148-
// static const pbdrv_gpio_t pin_spi0_cs = PBDRV_GPIO_EV3_PIN(3, 27, 24, 8, 2);
149-
150-
// // ADCACK PIN
151-
// static const pbdrv_gpio_t pin_adc_ack = PBDRV_GPIO_EV3_PIN(19, 19, 16, 6, 2);
152-
153-
// // ADCBATEN
154-
// static const pbdrv_gpio_t pin_adc_bat_en = PBDRV_GPIO_EV3_PIN(1, 7, 4, 0, 6);
155-
156-
static pbio_os_process_t pbdrv_adc_ev3_init_process;
157-
158-
pbio_error_t pbdrv_adc_ev3_init_process_thread(pbio_os_state_t *state, void *context) {
159119
PBIO_OS_ASYNC_BEGIN(state);
160120

161121
PBIO_OS_AWAIT_UNTIL(state, pbdrv_block_device_ev3_init_is_done());
162122

163-
pbdrv_uart_debug_printf("adc init init init\r\n");
164-
165-
pbdrv_block_device_ev3_spi_begin_for_adc(channel_cmd, channel_data, PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_CONFIG_ADC_EV3_NUM_DELAY_SAMPLES);
166-
PBIO_OS_AWAIT_WHILE(state, pbdrv_block_device_ev3_is_busy());
167-
for (int i = 0; i < 18; i++) {
168-
pbdrv_uart_debug_printf("%04x\r\n", channel_data[i] & 0xffff);
169-
}
170-
171-
172-
pbdrv_block_device_ev3_spi_begin_for_adc(channel_cmd, channel_data, PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_CONFIG_ADC_EV3_NUM_DELAY_SAMPLES);
173-
PBIO_OS_AWAIT_WHILE(state, pbdrv_block_device_ev3_is_busy());
174-
pbdrv_block_device_ev3_spi_begin_for_adc(channel_cmd, channel_data, PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_CONFIG_ADC_EV3_NUM_DELAY_SAMPLES);
175-
PBIO_OS_AWAIT_WHILE(state, pbdrv_block_device_ev3_is_busy());
176-
pbdrv_block_device_ev3_spi_begin_for_adc(channel_cmd, channel_data, PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_CONFIG_ADC_EV3_NUM_DELAY_SAMPLES);
177-
PBIO_OS_AWAIT_WHILE(state, pbdrv_block_device_ev3_is_busy());
178-
pbdrv_block_device_ev3_spi_begin_for_adc(channel_cmd, channel_data, PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_CONFIG_ADC_EV3_NUM_DELAY_SAMPLES);
179-
PBIO_OS_AWAIT_WHILE(state, pbdrv_block_device_ev3_is_busy());
180-
pbdrv_block_device_ev3_spi_begin_for_adc(channel_cmd, channel_data, PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_CONFIG_ADC_EV3_NUM_DELAY_SAMPLES);
181-
PBIO_OS_AWAIT_WHILE(state, pbdrv_block_device_ev3_is_busy());
182-
pbdrv_block_device_ev3_spi_begin_for_adc(channel_cmd, channel_data, PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_CONFIG_ADC_EV3_NUM_DELAY_SAMPLES);
183-
PBIO_OS_AWAIT_WHILE(state, pbdrv_block_device_ev3_is_busy());
184-
185-
186-
pbdrv_uart_debug_printf("adc 2222\r\n");
187-
188-
pbdrv_block_device_ev3_spi_begin_for_adc(channel_cmd, channel_data, PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_CONFIG_ADC_EV3_NUM_DELAY_SAMPLES);
189-
PBIO_OS_AWAIT_WHILE(state, pbdrv_block_device_ev3_is_busy());
190-
191-
for (int i = 0; i < 18; i++) {
192-
pbdrv_uart_debug_printf("%04x\r\n", channel_data[i] & 0xffff);
123+
// Once SPI flash init is finished, there is nothing further for us to do.
124+
// We are ready to start sampling.
125+
pbdrv_init_busy_down();
126+
127+
pbio_os_timer_set(&timer, ADC_SAMPLE_PERIOD);
128+
129+
for (;;) {
130+
PBIO_OS_AWAIT_UNTIL(state, adc_soon || pbio_os_timer_is_expired(&timer));
131+
132+
if (adc_soon) {
133+
adc_soon = 0;
134+
pbio_os_timer_set(&timer, ADC_SAMPLE_PERIOD);
135+
} else {
136+
// TODO: There should probably be a pbio OS function for this
137+
timer.start += timer.duration;
138+
}
139+
140+
// Do a sample of all channels
141+
pbdrv_block_device_ev3_spi_begin_for_adc(
142+
channel_cmd,
143+
channel_data,
144+
PBDRV_CONFIG_ADC_EV3_ADC_NUM_CHANNELS + PBDRV_CONFIG_ADC_EV3_NUM_DELAY_SAMPLES);
145+
PBIO_OS_AWAIT_WHILE(state, pbdrv_block_device_ev3_is_busy());
146+
147+
for (uint32_t i = 0; i < pbdrv_adc_callback_count; i++) {
148+
pbdrv_adc_callbacks[i]();
149+
}
193150
}
194151

195152
PBIO_OS_ASYNC_END(PBIO_SUCCESS);
@@ -198,42 +155,14 @@ pbio_error_t pbdrv_adc_ev3_init_process_thread(pbio_os_state_t *state, void *con
198155
void pbdrv_adc_init(void) {
199156
// Immediately go into async mode so that we can wait for the SPI flash driver
200157
pbdrv_init_busy_up();
201-
pbio_os_process_start(&pbdrv_adc_ev3_init_process, pbdrv_adc_ev3_init_process_thread, NULL);
202-
203-
// process_start(&pbdrv_adc_process);
158+
pbio_os_process_start(&pbdrv_adc_ev3_process, pbdrv_adc_ev3_process_thread, NULL);
204159
}
205160

206161
void pbdrv_adc_update_soon(void) {
207-
// process_poll(&pbdrv_adc_process);
162+
adc_soon = 1;
163+
pbio_os_request_poll();
208164
}
209165

210-
// PROCESS_THREAD(pbdrv_adc_process, ev, data) {
211-
// PROCESS_EXITHANDLER(pbdrv_adc_exit());
212-
213-
// static struct etimer etimer;
214-
215-
// PROCESS_BEGIN();
216-
217-
// etimer_set(&etimer, 10);
218-
// for (;;) {
219-
// PROCESS_WAIT_EVENT_UNTIL((ev == PROCESS_EVENT_TIMER && etimer_expired(&etimer)) || ev == PROCESS_EVENT_POLL);
220-
221-
// channel_data_index = 0;
222-
// adc_busy = true;
223-
// SPIEnable(SOC_SPI_0_REGS);
224-
// SPIIntEnable(SOC_SPI_0_REGS, SPI_TRANSMIT_INT);
225-
// PROCESS_WAIT_EVENT_UNTIL(ev == PROCESS_EVENT_POLL && !adc_busy);
226-
227-
// for (uint32_t i = 0; i < pbdrv_adc_callback_count; i++) {
228-
// pbdrv_adc_callbacks[i]();
229-
// }
230-
231-
// etimer_reset(&etimer);
232-
// }
233-
234-
// PROCESS_END();
235-
// }
236-
237166
void pbdrv_adc_ev3_configure_data_format() {
238167
SPIClkConfigure(SOC_SPI_0_REGS, SOC_SYSCLK_2_FREQ, SPI_CLK_SPEED_ADC, SPI_DATA_FORMAT1);
239168
// NOTE: Cannot be CPOL=1 CPHA=1 like SPI flash

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