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pbio/drv/block_device_ev3: Fix RX DMA channel.
Fix a typo where the RX channel for the wrong SPI peripheral was requested. Likely we didn't notice this because everything should already be set up correctly by the bootloader since it also uses this SPI for flash memory.
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lib/pbio/drv/block_device/block_device_ev3.c

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,6 @@
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#include <pbdrv/block_device.h>
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#include <pbdrv/clock.h>
27-
#include <pbdrv/compiler.h>
2827
#include <pbdrv/gpio.h>
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#include <tiam1808/edma.h>
@@ -243,7 +242,7 @@ static void spi_bus_init(void) {
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// Request DMA channels. This only needs to be done for the initial events (and not for linked parameter sets)
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EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, EDMA3_CHA_SPI0_TX, EDMA3_CHA_SPI0_TX, 0);
246-
EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, EDMA3_CHA_SPI1_RX, EDMA3_CHA_SPI1_RX, 0);
245+
EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, EDMA3_CHA_SPI0_RX, EDMA3_CHA_SPI0_RX, 0);
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// Enable!
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SPIEnable(SOC_SPI_0_REGS);
@@ -487,8 +486,8 @@ static pbio_error_t spi_begin_for_flash(
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spi_dev.status = SPI_STATUS_WAIT_TX | SPI_STATUS_WAIT_RX;
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490-
// TODO: eventually needs DMA cache management
491-
pbdrv_compiler_memory_barrier();
489+
// TODO: pbio probably needs a framework for memory barriers and DMA cache management
490+
__asm__ volatile ("" ::: "memory");
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EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_SPI0_TX, EDMA3_TRIG_MODE_EVENT);
494493
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_SPI0_RX, EDMA3_TRIG_MODE_EVENT);
@@ -806,8 +805,8 @@ static pbio_error_t pbdrv_block_device_ev3_spi_begin_for_adc(const uint32_t *cmd
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spi_dev.status = SPI_STATUS_WAIT_TX | SPI_STATUS_WAIT_RX;
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809-
// TODO: eventually needs DMA cache management
810-
pbdrv_compiler_memory_barrier();
808+
// TODO: pbio probably needs a framework for memory barriers and DMA cache management
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__asm__ volatile ("" ::: "memory");
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EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_SPI0_TX, EDMA3_TRIG_MODE_EVENT);
813812
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_SPI0_RX, EDMA3_TRIG_MODE_EVENT);

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