pbio/drv/usb/usb_ev3: Perform PHY reset and interrupt setup

These are the most basic steps needed for a USB peripheral to be detected.
After this commit, hosts will notice a USB device, but the device will
not function because none of the required USB requests are handled.

Author: ArcaneNibble

lib/pbio/drv/usb/usb_ev3.c

@@ -11,6 +11,7 @@
 #include <stdint.h>
 
 #include <pbdrv/usb.h>
+#include <pbio/os.h>
 #include <pbio/util.h>
 
 #include <tiam1808/armv5/am1808/interrupt.h>
@@ -22,11 +23,94 @@
 #include <tiam1808/hw/soc_AM1808.h>
 #include <tiam1808/hw/hw_psc_AM1808.h>
 #include <tiam1808/psc.h>
+#include <tiam1808/usb.h>
 
 #include <pbdrv/clock.h>
 
+static void usb_device_intr(void) {
+    IntSystemStatusClear(SYS_INT_USB0);
+}
+
+static pbio_os_process_t pbdrv_usb_ev3_process;
+
+static pbio_error_t pbdrv_usb_ev3_process_thread(pbio_os_state_t *state, void *context) {
+    PBIO_OS_ASYNC_BEGIN(state);
+
+    PBIO_OS_ASYNC_END(PBIO_SUCCESS);
+}
 
 void pbdrv_usb_init(void) {
+    // This reset sequence is from Example 34-1 in the AM1808 TRM (spruh82c.pdf)
+    // Because PHYs and clocking are... as they tend to be, use the precise sequence
+    // of operations specified.
+
+    // Power on and reset the controller
+    PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_USB0, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
+    USBReset(USB0_BASE);
+
+    // Reset the PHY
+    HWREG(CFGCHIP2_USBPHYCTRL) |= CFGCHIP2_RESET;
+    for (int i = 0; i < 50; i++) {
+        // Empty delay loop which should not be optimized out.
+        // This is the delay amount in the TI datasheet example.
+        __asm__ volatile ("");
+    }
+    HWREG(CFGCHIP2_USBPHYCTRL) &= ~CFGCHIP2_RESET;
+
+    // Set up the PHY and force it into device mode
+    HWREG(CFGCHIP2_USBPHYCTRL) =
+        (HWREG(CFGCHIP2_USBPHYCTRL) &
+            ~CFGCHIP2_OTGMODE &
+            ~CFGCHIP2_PHYPWRDN &            // Make sure PHY is on
+            ~CFGCHIP2_OTGPWRDN) |           // Make sure OTG subsystem is on
+        CFGCHIP2_FORCE_DEVICE |             // We only ever want device operation
+        CFGCHIP2_DATPOL |                   // Data lines are *not* inverted
+        CFGCHIP2_SESENDEN |                 // Enable various analog comparators
+        CFGCHIP2_VBDTCTEN;
+
+    HWREG(CFGCHIP2_USBPHYCTRL) =
+        (HWREG(CFGCHIP2_USBPHYCTRL) & ~CFGCHIP2_REFFREQ) |
+        CFGCHIP2_REFFREQ_24MHZ |            // Clock is 24 MHz
+        CFGCHIP2_USB2PHYCLKMUX;             // Clock comes from PLL
+
+    // Wait for PHY clocks to be ready
+    while (!(HWREG(CFGCHIP2_USBPHYCTRL) & CFGCHIP2_PHYCLKGD)) {
+    }
+
+    // Enable "PDR" mode for handling interrupts
+    //
+    // The datasheet doesn't clearly explain what this means,
+    // but what it appears TI has done is to wrap some custom interrupt and DMA
+    // logic around the Mentor Graphics core. The standard core registers
+    // thus now live at offset +0x400, and addresses below that pertain to the wrapper.
+    // This leaves some redundancy with how interrupts are set up, and this bit
+    // seems to enable accessing everything the TI way (more convenient) rather than
+    // the standard Mentor Graphics way (interrupt flags spread across more registers).
+    HWREG(USB_0_OTGBASE + USB_0_CTRL) &= ~USBOTG_CTRL_UINT;
+    HWREGH(USB0_BASE + USB_O_TXIE) = USB_TXIE_ALL_AM1808;
+    HWREGH(USB0_BASE + USB_O_RXIE) = USB_RXIE_ALL_AM1808;
+    HWREGB(USB0_BASE + USB_O_IE) = USB_IE_ALL;
+
+    // Enable the interrupts we actually care about
+    HWREG(USB_0_OTGBASE + USB_0_INTR_MASK_SET) =
+        USBOTG_INTR_RESET |
+        USBOTG_INTR_EP1_OUT |
+        USBOTG_INTR_EP1_IN |
+        USBOTG_INTR_EP0;
+
+    // Clear all the interrupts once
+    HWREG(USB_0_OTGBASE + USB_0_INTR_SRC_CLEAR) = HWREG(USB_0_OTGBASE + USB_0_INTR_SRC);
+
+    // Hook up interrupt handler
+    IntRegister(SYS_INT_USB0, usb_device_intr);
+    IntChannelSet(SYS_INT_USB0, 2);
+    IntSystemEnable(SYS_INT_USB0);
+
+    // Finally signal a connection
+    USBDevConnect(USB0_BASE);
+
+    // We are basically done. USB is event-driven, and so we don't have to block boot.
+    pbio_os_process_start(&pbdrv_usb_ev3_process, pbdrv_usb_ev3_process_thread, NULL);
 }
 
 pbdrv_usb_bcd_t pbdrv_usb_get_bcd(void) {

lib/tiam1808/tiam1808/hw/hw_usb.h

@@ -777,6 +777,8 @@
 #define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
                                             // Enable
 
+#define USB_TXIE_ALL_AM1808     0x0000001F  // EP0, EP1-4
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXIE register.
@@ -798,6 +800,8 @@
 #define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable
 #define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable
 
+#define USB_RXIE_ALL_AM1808     0x0000001E  // EP1-4
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_IS register.
@@ -828,6 +832,8 @@
 #define USB_IE_RESUME           0x00000002  // Enable RESUME Interrupt
 #define USB_IE_SUSPND           0x00000001  // Enable SUSPEND Interrupt
 
+#define USB_IE_ALL              0x000000FF
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_FRAME register.

lib/tiam1808/tiam1808/hw/hw_usbOtg_AM1808.h

@@ -79,6 +79,33 @@ extern "C"
 #define USB_0_GEN_RNDIS_SIZE_EP4	0x5C
 #define USB_0_GENR_INTR				0x22
 
+// Bits for CTRL
+#define USBOTG_CTRL_RESET           0x01
+#define USBOTG_CTRL_CLKFACK         0x02
+#define USBOTG_CTRL_UINT            0x08
+#define USBOTG_CTRL_RNDIS           0x10
+
+// The following are interrupt bits as found in the OTG wrapper
+#define USBOTG_INTR_EP0             0x00000001
+#define USBOTG_INTR_EP1_IN          0x00000002
+#define USBOTG_INTR_EP2_IN          0x00000004
+#define USBOTG_INTR_EP3_IN          0x00000008
+#define USBOTG_INTR_EP4_IN          0x00000010
+#define USBOTG_INTR_EP1_OUT         0x00000200
+#define USBOTG_INTR_EP2_OUT         0x00000400
+#define USBOTG_INTR_EP3_OUT         0x00000800
+#define USBOTG_INTR_EP4_OUT         0x00001000
+#define USBOTG_INTR_DRVVBUS         0x01000000  // DRVVBUS level change
+#define USBOTG_INTR_VBUSERR         0x00800000  // VBUS Error
+#define USBOTG_INTR_SESREQ          0x00400000  // SESSION REQUEST
+#define USBOTG_INTR_DISCON          0x00200000  // Session Disconnect
+#define USBOTG_INTR_CONN            0x00100000  // Session Connect
+#define USBOTG_INTR_SOF             0x00080000  // Start of Frame
+#define USBOTG_INTR_BABBLE          0x00040000  // Babble Detected
+#define USBOTG_INTR_RESET           0x00040000  // RESET Signaling Detected
+#define USBOTG_INTR_RESUME          0x00020000  // RESUME Signaling Detected
+#define USBOTG_INTR_SUSPEND         0x00010000  // SUSPEND Signaling Detected
+
 #ifdef __cplusplus
 }
 #endif