From 3d0d0671d400176b1ba2682f5962737311ed16c2 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Sun, 6 Jul 2025 15:09:26 -0500 Subject: [PATCH 1/2] pbio/drv/display/display_ev3: make readonly data const Data that never changes should be declared as const to allow the compiler to optimize it better and to prevent accidental modifications. --- lib/pbio/drv/display/display_ev3.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/pbio/drv/display/display_ev3.c b/lib/pbio/drv/display/display_ev3.c index c8a306646..32debe23a 100644 --- a/lib/pbio/drv/display/display_ev3.c +++ b/lib/pbio/drv/display/display_ev3.c @@ -140,7 +140,7 @@ static uint8_t pbdrv_display_user_frame[PBDRV_CONFIG_DISPLAY_NUM_ROWS][PBDRV_CON * Flag to indicate that the user frame has been updated and needs to be * encoded and sent to the display driver. */ -static bool pbdrv_display_user_frame_update_requested = false; +static bool pbdrv_display_user_frame_update_requested; /** * Display buffer in the format ready for sending to the st7586s display driver. @@ -194,7 +194,7 @@ static uint8_t encode_triplet(uint8_t p0, uint8_t p1, uint8_t p2) { * * Revisit: Use standard format, e.g. decompress PNG files from file storage or memory card. */ -static uint16_t pbdrv_display_pybricks_logo[] = { +static const uint16_t pbdrv_display_pybricks_logo[] = { 3227, 3359, 3403, 3539, 3580, 3718, 3757, 3897, 3934, 4076, 4111, 4255, 4289, 4433, 4466, 4612, 4644, 4790, 4822, 4968, 5000, 5146, 5178, 5324, 5356, 5502, 5534, 5548, 5666, 5680, 5712, 5725, 5845, 5858, 5890, 5903, 6023, 6036, 6068, 6081, 6201, 6214, 6246, 6259, 6379, 6392, 6424, 6437, @@ -235,7 +235,7 @@ static uint16_t pbdrv_display_pybricks_logo[] = { * * @param bitmap Pointer to the bitmap data. */ -static void pbdrv_display_load_indexed_bitmap(uint16_t *indexed_bitmap) { +static void pbdrv_display_load_indexed_bitmap(const uint16_t *indexed_bitmap) { bool set = 0; uint32_t switch_index = 0; for (size_t r = 0; r < PBDRV_CONFIG_DISPLAY_NUM_ROWS; r++) { @@ -275,7 +275,7 @@ void pbdrv_display_st7586s_encode_user_frame(void) { /** * Display initialization script adapted from ev3dev and EV3RT. */ -static pbdrv_display_st7586s_action_t init_script[] = { +static const pbdrv_display_st7586s_action_t init_script[] = { #if ST7586S_DO_RESET_AND_INIT { ST7586S_ACTION_WRITE_COMMAND, ST7586_ARDCTL}, { ST7586S_ACTION_WRITE_DATA, 0x9f}, @@ -475,7 +475,7 @@ PROCESS_THREAD(pbdrv_display_ev3_init_process, ev, data) { // For every action in the init script, either send a command or data, or // wait for a given delay. for (script_index = 0; script_index < PBIO_ARRAY_SIZE(init_script); script_index++) { - pbdrv_display_st7586s_action_t *action = &init_script[script_index]; + const pbdrv_display_st7586s_action_t *action = &init_script[script_index]; if (action->type == ST7586S_ACTION_DELAY) { // Simple delay. From ddf454c96f2af5ac7d9c13b1405665d6000f3c17 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Sun, 6 Jul 2025 16:55:49 -0500 Subject: [PATCH 2/2] pbio/platform/ev3/start: disable and flush caches Add a hack to disable and flush the I and D caches at in the startup code. Previously, when we were using the U-Boot Linux loader to load our firmware, U-Boot was doing this for us. But since we switched to a different loader in commit c24798f4b ("bricks/_common/arm_none_eabi.mk: ev3 uImage is not Linux"), it broke the display among other things. --- lib/pbio/platform/ev3/start.S | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/lib/pbio/platform/ev3/start.S b/lib/pbio/platform/ev3/start.S index aa962d0d9..1673fbf06 100755 --- a/lib/pbio/platform/ev3/start.S +++ b/lib/pbio/platform/ev3/start.S @@ -51,6 +51,18 @@ @ main() function. @ Entry: + @ HACK: The U-Boot Linux loader was doing this, but the ELF loader + @ does not. Adding this here until we sort out the proper way to handle + @ caching. But right now, it breaks the display driver and other things + @ if we don't do this. + mrc p15, #0, r0, c1, c0,#0 @ Read System Control Register + bic r0, r0, #0x1000 @ Clear bit 12 to disable ICache + bic r0, r0, #0x0004 @ Clear bit 2 to disable DCache + mcr p15, #0, r0, c1, c0, #0 @ Write back to System Control Register + mov r0, #0 @ Set r0 to 0 + mcr p15, #0, r0, c7, c7, #0 @ Invalidate all caches + @ END HACK + MRC p15, 0, r0, c1, c0, 0 @ Load Coprocessor Register C1 to ARM Register r0 ORR r0, r0, #0x00002000 @ Logical OR --> Set Bit 13 MCR p15, 0, r0, c1, c0, 0 @ Restore Coprocessor Register C1 from ARM Register r0