diff --git a/bricks/_common/arm_none_eabi.mk b/bricks/_common/arm_none_eabi.mk index 0d5c41216..95245a934 100644 --- a/bricks/_common/arm_none_eabi.mk +++ b/bricks/_common/arm_none_eabi.mk @@ -269,37 +269,27 @@ endif TI_AM1808_SRC_C = $(addprefix lib/tiam1808/,\ drivers/cppi41dma.c \ drivers/cpsw.c \ - drivers/dcan.c \ drivers/dmtimer.c \ drivers/ecap.c \ drivers/edma.c \ drivers/ehrpwm.c \ - drivers/elm.c \ - drivers/emac.c \ drivers/emifa.c \ drivers/gpio.c \ drivers/gpmc.c \ drivers/hs_mmcsd.c \ drivers/i2c.c \ - drivers/lan8710a.c \ - drivers/lidd.c \ - drivers/mailbox.c \ drivers/mcasp.c \ drivers/mcspi.c \ drivers/mdio.c \ - drivers/phy.c \ drivers/pruss.c \ drivers/psc.c \ - drivers/raster.c \ drivers/rtc.c \ drivers/spi.c \ drivers/syscfg.c \ drivers/timer.c \ - drivers/tsc_adc.c \ drivers/uart.c \ drivers/usb.c \ drivers/usbphyGS60.c \ - drivers/vpif.c \ drivers/watchdog.c \ system_config/armv5/gcc/cp15.c \ system_config/armv5/gcc/cpu.c \ diff --git a/lib/tiam1808/drivers/dcan.c b/lib/tiam1808/drivers/dcan.c deleted file mode 100644 index 5a300cd73..000000000 --- a/lib/tiam1808/drivers/dcan.c +++ /dev/null @@ -1,2021 +0,0 @@ -/** - * \file dcan.c - * - * \brief DCAN APIs. - * - * This file contains the device abstraction layer APIs for - * Dual Controller Area Network(DCAN). - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#include "hw_types.h" -#include "dcan.h" - -/******************************************************************************* -* INTERNAL MACRO DEFINITIONS -*******************************************************************************/ -#define CAN_CALC_MAX_ERROR (50u) -#define TX_REQUEST_X_MASK (0x0000FFFFu) -#define DCAN_STD_ID_SHIFT (18u) -#define MSG_VALID_X_MASK (0x0000FFFFu) -#define NEW_DATA_X_MASK (0x0000FFFFu) -#define INT_PEND_X_MASK (0x0000FFFFu) - -/******************************************************************************* -* API FUNCTION DEFINITIONS -*******************************************************************************/ -/** - * \brief This API will enable the DCAN peripheral in Initialization mode. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return None. - * - * \note By calling this API, communication on CAN bus is stopped and the - * CAN module enters initialization mode. - * - **/ -void DCANInitModeSet(unsigned int baseAdd) -{ - /* Set the Init field of DCAN_CTL register */ - HWREG(baseAdd + DCAN_CTL) |= DCAN_CTL_INIT; - - /* Wait for Init bit to set */ - while(!(HWREG(baseAdd + DCAN_CTL) & DCAN_CTL_INIT)); -} - -/** - * \brief This API will enable the DCAN peripheral in Normal mode of - * operation. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return None. - * - * \note By calling this API, the DCAN module exits Initialization mode - * and communication on CAN bus is started. - * - **/ -void DCANNormalModeSet(unsigned int baseAdd) -{ - /* Clear the CCE and Init bit */ - HWREG(baseAdd + DCAN_CTL) &= ~DCAN_CTL_INIT; - - /* Wait for Init bit to clear */ - while(HWREG(baseAdd + DCAN_CTL) & DCAN_CTL_INIT); -} - -/** - * \brief This API will write the CAN Bit-Timing values to the - * DCAN_BTR register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param btrValue Bit-Timing register value. - * - * \return None. - * - * \note To configure CAN bit timing the DCAN peripheral should be in - * initialization mode and CPU should have access to the DCAN - * configuration registers. - * 8 MHz is the minimum CAN clock frequency required to operate - * the DCAN at a bit rate of 1MBits/s. - * - **/ -void DCANBitTimingConfig(unsigned int baseAdd, unsigned int btrValue) -{ - /* Write the value to DCAN_BTR register */ - HWREG(baseAdd + DCAN_BTR) = btrValue; -} - -/** - * \brief This API will reset the DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return None. - * - * \note To perform software reset the DCAN peripheral should be enabled in - * initialization mode. - * - **/ -void DCANReset(unsigned int baseAdd) -{ - /* Set the SWR bit of DCAN_CTL register */ - HWREG(baseAdd + DCAN_CTL) |= DCAN_CTL_SWR; - - /* Poll in the loop until reset completes */ - while((HWREG(baseAdd + DCAN_CTL) & DCAN_CTL_SWR)); -} - -/** - * \brief This API will enable the Interrupts of DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param intFlags Enable Interrupts. - * - * 'intFlags' can take the following values \n - * DCAN_STATUS_CHANGE_INT - Enable Status change Interrupt \n - * DCAN_ERROR_INT - Enable error Interrupt \n - * - * \return None. - * - **/ -void DCANIntEnable(unsigned int baseAdd, unsigned int intFlags) -{ - /* Enable the DCAN interrupts */ - HWREG(baseAdd + DCAN_CTL) |= (intFlags & (DCAN_CTL_SIE | DCAN_CTL_EIE)); -} - -/** - * \brief This API will disable the Interrupts of DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param intFlags Disable Interrupts. - * - * 'intFlags' can take the following values \n - * DCAN_STATUS_CHANGE_INT - Disable Status change Interrupt \n - * DCAN_ERROR_INT - Disable error Interrupt \n - * - * \return None. - * - **/ -void DCANIntDisable(unsigned int baseAdd, unsigned int intFlags) -{ - /* Disable the DCAN interrupts */ - HWREG(baseAdd + DCAN_CTL) &= ~(intFlags & (DCAN_CTL_SIE | DCAN_CTL_EIE)); -} - -/** - * \brief This API will enable/disable the auto re-transmission of - * unsuccessful messages of DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param autoReTxn Enable/disable setting for Auto re-transmision. - * - * 'autoReTxn' can take the following values \n - * DCAN_AUTO_RETXN_ENABLE - Enable auto re-transmission \n - * DCAN_AUTO_RETXN_DISABLE - Disable auto re-transmission \n - * - * \return None. - * - **/ -void DCANAutoReTransmitControl(unsigned int baseAdd, unsigned int autoReTxn) -{ - /* Clear the DAR field of DCAN_CTL register */ - HWREG(baseAdd + DCAN_CTL) &= ~DCAN_CTL_DAR; - - /* Set the user sent value to DAR field */ - HWREG(baseAdd + DCAN_CTL) |= (autoReTxn & DCAN_CTL_DAR); -} - -/** - * \brief This API will enable/disable the CPU write access to the - * configuration registers of DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param regConfig Enable/disable write access to configuration - * registers. - * - * 'regConfig' can take the following values \n - * DCAN_CONF_REG_WR_ACCESS_ENABLE - Enable write access \n - * DCAN_CONF_REG_WR_ACCESS_DISABLE - Disable write access \n - * - * \return None. - * - * \note If the user wants to enable write access to configuration registers, - * then DCAN peripheral should be in initialization mode before doing - * so. - * - **/ -void DCANConfigRegWriteAccessControl(unsigned int baseAdd, - unsigned int regConfig) -{ - /* Clear the CCE field of DCAN_CTL register */ - HWREG(baseAdd + DCAN_CTL) &= ~DCAN_CTL_CCE; - - /* Set the CCE field with the user sent value */ - HWREG(baseAdd + DCAN_CTL) |= (regConfig & DCAN_CTL_CCE); -} - -/** - * \brief This API will enable/disable the test mode of DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param testMode Enable/disable test mode. - * - * 'testMode' can take the following values \n - * DCAN_TEST_MODE_ENABLE - Enable test mode of DCAN peripheral \n - * DCAN_TEST_MODE_DISABLE - Disable test mode and enable normal mode - * of DCAN peripheral \n - * - * \return None. - * - **/ -void DCANTestModeControl(unsigned int baseAdd, unsigned int testMode) -{ - /* Clear the Test field of DCAN_CTL register */ - HWREG(baseAdd + DCAN_CTL) &= ~DCAN_CTL_TEST; - - /* Set the Test field with the user sent value */ - HWREG(baseAdd + DCAN_CTL) |= (testMode & DCAN_CTL_TEST); -} - -/** - * \brief This API will configure the required setting for debug/suspend - * support feature of DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param modeConfig Debug support setting. - * - * 'modeConfig' can take the following values \n - * DCAN_DEBUG_SUSPEND_WAIT - When debug/suspend mode is requested, DCAN - * will wait for a started transmission or - * reception to be completed before entering - * debug/suspend mode. - * - * DCAN_DEBUG_SUSPEND_INTERRUPT - When debug/suspend mode is requested, DCAN - * will interrupt any transmission or reception - * and enter debug/suspend mode immediately. - * - * \return None. - * - **/ -void DCANDebugSuspendModeConfig(unsigned int baseAdd, unsigned int modeConfig) -{ - /* Clear the IDS field of DCAN_CTL register */ - HWREG(baseAdd + DCAN_CTL) &= ~DCAN_CTL_IDS; - - /* Set the IDS field with the user sent value */ - HWREG(baseAdd + DCAN_CTL) |= (modeConfig & DCAN_CTL_IDS); -} - -/** - * \brief This API will enable/disable the Auto-bus-on feature of DCAN - * peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param busControl Auto-bus-on mode setting. - * - * 'busControl' can take the following values \n - * DCAN_AUTO_BUS_ON_ENABLE - Enable Auto-bus-on feature of DCAN peripheral \n - * DCAN_AUTO_BUS_ON_DISABLE - Disable Auto-bus-on feature of DCAN - * peripheral \n - * - * \return None. - * - **/ -void DCANAutoBusOnControl(unsigned int baseAdd, unsigned int busControl) -{ - /* Clear the ABO field of DCAN_CTL register */ - HWREG(baseAdd + DCAN_CTL) &= ~DCAN_CTL_ABO; - - /* Set the ABO field with the user sent value */ - HWREG(baseAdd + DCAN_CTL) |= (busControl & DCAN_CTL_ABO); -} - -/** - * \brief This API will enable/disable the parity function of DCAN - * peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param paritySet Configure parity. - * - * 'paritySet' can take the following values \n - * DCAN_PARITY_FUNC_ENABLE - Enable parity function of DCAN peripheral \n - * DCAN_PARITY_FUNC_DISABLE - Disable parity function of DCAN peripheral \n - * - * \return None. - * - **/ -void DCANParityControl(unsigned int baseAdd, unsigned int paritySet) -{ - /* Clear the PMD field of DCAN_CTL register */ - HWREG(baseAdd + DCAN_CTL) &= ~DCAN_CTL_PMD; - - /* Set the PMD field with the user sent value */ - HWREG(baseAdd + DCAN_CTL) |= (paritySet & DCAN_CTL_PMD); -} - -/** - * \brief This API will check the status of debug state and return the status - * to the caller. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return This API returns the status of the DCAN debug state. - * - * The user can use these macros for checking the status \n - * DCAN_NOT_IN_DEBUG_MODE - DCAN is not in debug mode \n - * DCAN_IN_DEBUG_MODE - DCAN is in debug mode \n - * - **/ -unsigned int DCANInternalDebugStatusGet(unsigned int baseAdd) -{ - /* Return the debug state of DCAN peripheral */ - return(HWREG(baseAdd + DCAN_CTL) & DCAN_CTL_INITDBG); -} - -/** - * \brief This API will enable Interrupt lines of DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param enableLine Enable Interrupt lines. - * - * 'enableLine' can take the following values \n - * DCAN_INT_LINE0 - Enable Interrupt line 0 \n - * DCAN_INT_LINE1 - Enable Interrupt line 1 \n - * - * \return None. - * - * \note The Error and Status change interrupts can only be routed to - * DCANINT0 line and message object interrupts can be routed to - * both lines. Hence DCANINT0 line has to be enabled if error and - * status change interrupts have to be serviced. - * - **/ -void DCANIntLineEnable(unsigned int baseAdd, unsigned int enableLine) -{ - /* Enable the interrupt lines */ - HWREG(baseAdd + DCAN_CTL) |= (enableLine & (DCAN_CTL_IE1 | DCAN_CTL_IE0)); -} - -/** - * \brief This API will disable the Interrupt lines of DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param disableLine Disable Interrupt lines. - * - * 'disableLine' can take the following values \n - * DCAN_INT_LINE0 - Disable interrupt line 0 \n - * DCAN_INT_LINE1 - Disable interrupt line 1\n - * - * \return None. - * - **/ -void DCANIntLineDisable(unsigned int baseAdd, unsigned int disableLine) -{ - /* Disable the interrupt lines */ - HWREG(baseAdd + DCAN_CTL) &= ~(disableLine & (DCAN_CTL_IE1 | DCAN_CTL_IE0)); -} - -/** - * \brief This API will enable the DMA request line for Interface - * registers(IF[1:3]) of the DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param ifRegFlags Enable DMA request lines. - * - * 'ifRegFlags' can take the following values \n - * DCAN_DMA_REQUEST_LINE_IF1 - Enable DMA request line for IF1 \n - * DCAN_DMA_REQUEST_LINE_IF2 - Enable DMA request line for IF2 \n - * DCAN_DMA_REQUEST_LINE_IF3 - Enable DMA request line for IF3 \n - * - * \return None. - * - **/ -void DCANDmaRequestLineEnable(unsigned int baseAdd, unsigned int ifRegFlags) -{ - /* Enable the DMA request lines */ - HWREG(baseAdd + DCAN_CTL) |= (ifRegFlags & - (DCAN_CTL_DE1 | DCAN_CTL_DE2 | DCAN_CTL_DE3)); -} - -/** - * \brief This API will disable the DMA request line for Interface - * registers(IF[1:3]) of the DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param ifRegFlags Disable DMA request lines. - * - * 'ifRegFlags' can take the following values \n - * DCAN_DMA_REQUEST_LINE_IF1 - Disable DMA request line for IF1 \n - * DCAN_DMA_REQUEST_LINE_IF2 - Disable DMA request line for IF2 \n - * DCAN_DMA_REQUEST_LINE_IF3 - Disable DMA request line for IF3 \n - * - * \return None. - * - **/ -void DCANDmaRequestLineDisable(unsigned int baseAdd, unsigned int ifRegFlags) -{ - /* Disable the DMA request lines */ - HWREG(baseAdd + DCAN_CTL) &= ~(ifRegFlags & - (DCAN_CTL_DE1 | DCAN_CTL_DE2 | DCAN_CTL_DE3)); -} - -/** - * \brief This API will control the setting for local power down mode. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param pwrDwnCtl Power down mode setting. - * - * 'pwrDwnCtl' can take the following values \n - * DCAN_LOCAL_PWR_DWN_OFF - Local power down mode is off \n - * DCAN_LOCAL_PWR_DWN_ON - Local power down mode is on \n - * - * \return None. - * - * \note DCAN on entering Local power down mode will wait until a bus idle - * state is recognized and after this it enters the Initialization mode - * by setting the Init bit in DCAN_CTL register and it also sets PDA - * bit in the DCAN_ES register. - * When in local power down mode, the application should not clear the - * Init bit while PDR is set. If there are any messages in the message - * RAM which are configured as transmit messages and the application - * resets the Init bit then these messages may be sent. - * - **/ -void DCANPwrDwnControl(unsigned int baseAdd, unsigned int pwrDwnCtl) -{ - /* Clear the PDR field of DCAN_CTL register */ - HWREG(baseAdd + DCAN_CTL) &= ~DCAN_CTL_PDR; - - /* Set the PDR field with the user sent value */ - HWREG(baseAdd + DCAN_CTL) |= (pwrDwnCtl & DCAN_CTL_PDR); -} - -/** - * \brief This API will control the setting for wake up from local power - * down mode. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param wkUpCtl Wake up from power down setting. - * - * 'wkUpCtl' can take the following values \n - * DCAN_WKUP_DETECTION_DISABLED - Local power down mode is disabled \n - * DCAN_WKUP_DETECTION_ENABLED - Local power down mode is enabled \n - * - * \return None. - * - * \note To manually wakeup DCAN peripheral from power down mode the - * application should manually clear the PDR bit by calling the API - * 'DCANPwrDwnControl' by passing DCAN_LOCAL_PWR_DWN_OFF as the - * arguement for 'pwrDwnCtl'. Once this is done the Init bit should - * be cleared by calling the API 'DCANNormalModeSet'. - * But if wake up detection is enabled by passing the macro - * DCAN_WKUP_DETECTION_ENABLED to 'wkUpCtl' then user need not clear - * the PDR and Init bit manually since it will be done by the DCAN - * controller. - * The first CAN message, which initiates the bus activity, cannot be - * received. This means that the first message received in power-down - * and automatic wake-up mode is lost. - * - **/ -void DCANPwrDwnWkUpControl(unsigned int baseAdd, unsigned int wkUpCtl) -{ - /* Clear the WUBA field of DCAN_CTL register */ - HWREG(baseAdd + DCAN_CTL) &= ~DCAN_CTL_WUBA; - - /* Set the WUBA field with the user sent value */ - HWREG(baseAdd + DCAN_CTL) |= (wkUpCtl & DCAN_CTL_WUBA); -} - -/** - * \brief This API will return the status of Interrupt register DCAN_INT. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param intLnFlag Int line no whose status is to be returned. - * - * 'intLnFlag' can take the following values \n - * DCAN_INT_LINE0_STAT - Status of Interrupt line 0 \n - * DCAN_INT_LINE1_STAT - Status of Interrupt line 1 \n - * - * \return Returns the status of DCAN_INT register. - * - **/ -unsigned int DCANIntRegStatusGet(unsigned int baseAdd, unsigned int intLnFlag) -{ - /* Return the status of DCAN_INT register */ - return(HWREG(baseAdd + DCAN_INT) & intLnFlag); -} - -/** - * \brief This API will return the status of Error and status DCAN_ES register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return Returns the status of DCAN_ES register. - * - * The user can use these macros for handling the status of DCAN_ES - * register in the application code. - * - * DCAN_LST_ERRCODE_NO_ERR - No error in LEC field \n - * DCAN_LST_ERRCODE_STUFF_ERR - Stuff error is detected in LEC field \n - * DCAN_LST_ERRCODE_FORM_ERR - Form error detected in LEC field \n - * DCAN_LST_ERRCODE_ACK_ERR - Ack error detected in LEC field \n - * DCAN_LST_ERRCODE_BIT1_ERR - Bit1 error detected in LEC field \n - * DCAN_LST_ERRCODE_BIT0_ERR - Bit0 error detected in LEC field \n - * DCAN_LST_ERRCODE_CRC_ERR - CRC error detected in LEC field \n - * DCAN_NO_EVENT_ON_CAN_BUS - No event generated on CAN bus since - * last read of DCAN_ES register \n - * DCAN_TXD_MSG_SUCCESSFULLY - DCAN transmitted message successfully \n - * DCAN_RXD_MSG_SUCCESSFULLY - DCAN received message successfully \n - * DCAN_CORE_IN_ERR_PASSIVE - DCAN core in error passive state \n - * DCAN_ERR_WARN_STATE_RCHD - Atleast one of the counters have reached - * error warning limit \n - * DCAN_MOD_IN_BUS_OFF_STATE - DCAN in bus off state \n - * DCAN_PARITY_ERR_DETECTED - Parity error detected \n - * DCAN_INITIATED_SYSTEM_WKUP - DCAN initiated system wakeup \n - * DCAN_IN_LOCAL_PWR_DWN_MODE - DCAN in local power down mode \n - * - * \note Reading the error and status register will clear/set certain bits - * in the error and status register. For more information please refer - * the DCAN Technical Reference Manual(TRM). - * For debug support, the auto clear functionality of error and status - * register is disabled when in debug/suspend mode. - * - **/ -unsigned int DCANErrAndStatusRegInfoGet(unsigned int baseAdd) -{ - /* Return the status of DCAN_ES register to the caller */ - return(HWREG(baseAdd + DCAN_ES)); -} - -/** - * \brief This API will indicate end of interrupt(EOI) for parity error. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return None. - * - **/ -void DCANParityEndOfIntSet(unsigned int baseAdd) -{ - /* Set the PARITYERR_EOI field of DCAN_ES register */ - HWREG(baseAdd + DCAN_PARITYERR_EOI) |= DCAN_PARITYERR_EOI_PARITYERR_EOI; -} - -/** - * \brief This API will return the status of Error counter register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param cntrFlags Status to be returned from the API. - * - * 'cntrFlags' can take the following values \n - * DCAN_TX_ERR_CNTR - Return the TEC[7:0] field of DCAN_ERRC register \n - * DCAN_RX_ERR_CNTR - Return the REC[6:0] field of DCAN_ERRC register \n - * DCAN_RX_ERR_PASSIVE - Return the receiver error passive status \n - * - * \return This API returns the status of DCAN_ERRC register. - * - **/ -unsigned int DCANErrCntrRegStatusGet(unsigned int baseAdd, - unsigned int cntrFlags) -{ - /* Return the status of DCAN_ERRC register to the caller */ - return(HWREG(baseAdd + DCAN_ERRC) & cntrFlags); -} - -/** - * \brief This API will enable the test modes of DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param tstMode Enable test mode. - * - * 'tstMode' can take the following values \n - * DCAN_TST_SILENT_MD - Enable silent mode \n - * DCAN_TST_LPBCK_MD - Enable loopback mode \n - * DCAN_TST_EXTLPBCK_MD - Enable external loopback mode \n - * DCAN_TST_LPBCK_SILENT_MD - Enable loopback with silent mode \n - * DCAN_TST_RAM_DIRECT_ACCESS - Direct access to RAM enabled \n - * - * \return None. - * - * \note Before calling the API 'DCANTestModesEnable' ensure to enable DCAN - * in test mode by using the API 'DCANTestModeControl'. - * When internal loop-back mode is active, if external loopback is - * enabled then external loopback will be ignored. - * - **/ -void DCANTestModesEnable(unsigned int baseAdd, unsigned int tstMode) -{ - /* Set test mode fields of DCAN_TEST register with the user sent value */ - HWREG(baseAdd + DCAN_TEST) |= (tstMode & - (DCAN_TEST_RDA | DCAN_TEST_EXL | - DCAN_TEST_LBACK | DCAN_TEST_SILENT)); -} - -/** - * \brief This API will disable the test modes of DCAN peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param tstMode Disable test mode. - * - * 'tstMode' can take the following values \n - * DCAN_TST_SILENT_MD - Disable silent mode \n - * DCAN_TST_LPBCK_MD - Disable loopback mode \n - * DCAN_TST_EXTLPBCK_MD - Disable external loopback mode \n - * DCAN_TST_LPBCK_SILENT_MD - Disable loopback with silent mode \n - * DCAN_TST_RAM_DIRECT_ACCESS - Direct access to RAM disabled - * (normal operation enabled) \n - * - * \return None. - * - * \note Usage of this API is only valid if DCAN is enabled in test mode. - * DCAN can be enabled in test mode by using the API - * 'DCANTestModeControl'. - * - **/ -void DCANTestModesDisable(unsigned int baseAdd, unsigned int tstMode) -{ - /* Clear the mode fields of DCAN_TEST register with the user sent value */ - HWREG(baseAdd + DCAN_TEST) &= ~(tstMode & - (DCAN_TEST_RDA | DCAN_TEST_EXL | - DCAN_TEST_LBACK | DCAN_TEST_SILENT)); -} - -/** - * \brief This API will configure the control for CAN_TX pin. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param pinCtl Pin control used for CAN_TX. - * - * 'pinCtl' can take the following values \n - * DCAN_TST_TX_NRML_OP - Normal operation of CAN_TX pin \n - * DCAN_TST_TX_SAMPLE_PT_MNTR - Sample point can be monitored at CAN_TX pin \n - * DCAN_TST_TX_DRIV_DOM_VAL - CAN_TX pin drives a dominant value \n - * DCAN_TST_TX_DRIV_RSV_VAL - CAN_TX pin drives a recessive value \n - * - * \return None. - * - * \note Usage of this API is only valid if DCAN is enabled in test mode. - * DCAN can be enabled in test mode by using the API - * 'DCANTestModeControl'. - * Setting for CAN_TX pin other than DCAN_TST_TX_NRML_OP will disturb - * message transfer. - * - **/ -void DCANTxPinControl(unsigned int baseAdd, unsigned int pinCtl) -{ - /* Clear the TX[1:0] field of DCAN_TEST register */ - HWREG(baseAdd + DCAN_TEST) &= ~DCAN_TEST_TX; - - /* Set the TX[1:0] field with the user sent value */ - HWREG(baseAdd + DCAN_TEST) |= (pinCtl & DCAN_TEST_TX); -} - -/** - * \brief This API will return the status of CAN_RX pin. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return Returns the status of CAN_RX pin. - * - * User can use the below macros to check the status \n - * DCAN_TST_RX_IS_DOM - CAN bus is dominant \n - * DCAN_TST_RX_IS_RSV - CAN bus is recessive \n - * - * \note Usage of this API is only valid if DCAN is enabled in test mode. - * DCAN can be enabled in test mode by using the API - * 'DCANTestModeControl'. - * - **/ -unsigned int DCANRxPinStatusGet(unsigned int baseAdd) -{ - /* Return the status of CAN_RX pin to the caller */ - return(HWREG(baseAdd + DCAN_TEST) & DCAN_TEST_RX); -} - -/** - * \brief This API will return the status of parity error code register - * DCAN_PERR. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param statFlg Status of word/message number to be returned - * from API. - * - * \return Returns the status of DCAN_PERR register. - * - * User can use the below macros to check the status \n - * DCAN_PARITY_ERR_MSG_NUM - Message object number where parity - * error is detected \n - * DCAN_PARITY_ERR_WRD_NUM - Word number where parity error is - * detected \n - * - **/ -unsigned int DCANParityErrCdRegStatusGet(unsigned int baseAdd, - unsigned int statFlg) -{ - /* Return the status of Parity error code register */ - return(HWREG(baseAdd + DCAN_PERR) & statFlg); -} - -/** - * \brief This API will set the Auto-bus on timer value to the DCAN_ABOTR - * register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param timeVal Auto-bus on timer value. - * - * \return None. - * - * \note This API is valid only if the auto-bus-on feature is enabled using - * 'DCANAutoBusOnControl' API. - * On write access to the CAN control register while auto-bus-on timer - * is running, the auto-bus-on procedure will be aborted. - * During debug/suspend mode, running Auto-bus-on timer will be paused. - * - **/ -void DCANAutoBusOnTimeValSet(unsigned int baseAdd, unsigned int timeVal) -{ - /* Set the user sent value to DCAN_ABOTR register */ - HWREG(baseAdd + DCAN_ABOTR) = timeVal; -} - -/** - * \brief This API will return the auto-bus-on time register value. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return Returns the auto-bus-on timer value. - * - * \note This API is valid only if the auto-bus-on feature is enabled using - * 'DCANAutoBusOnControl' API. - * On write access to the CAN control register while auto-bus-on timer - * is running, the auto-bus-on procedure will be aborted. - * During debug/suspend mode, running Auto-bus-on timer will be paused. - * - **/ -unsigned int DCANAutoBusOnTimeValGet(unsigned int baseAdd) -{ - /* Return the Auto-bus-on timer value to the caller */ - return(HWREG(baseAdd + DCAN_ABOTR)); -} - -/** - * \brief This API will return the status from DCAN_TXRQ_X register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return Returns the status from the transmit request X register. - * User can use the below macro to check the status \n - * DCAN_TXRQST_X_REG(n) - Status of DCAN_TXRQ_X register - * corresponding to n \n - * where 1 <= n <= 8 \n - * - **/ -unsigned int DCANTxRqstXStatusGet(unsigned int baseAdd) -{ - /* Return the status from DCAN_TXRQ_X register */ - return(HWREG(baseAdd + DCAN_TXRQ_X) & TX_REQUEST_X_MASK); -} - -/** - * \brief This API will return the status from DCAN_TXRQ(n) register. - * Where n = 12,34,56,78. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param msgNum Message object number whose TxRqst status is to - * be returned. - * - * \return Returns the transmit request status from DCAN_TXRQ(n) register. - * Where n = 12,34,56,78. - * - * \note Values for 'msgNum' can range from \n - * 1 <= msgNum <= 128. - * - **/ -unsigned int DCANTxRqstStatusGet(unsigned int baseAdd, unsigned int msgNum) -{ - unsigned int regNum; - unsigned int offSet; - - regNum = (msgNum - 1) / 32; - offSet = (msgNum - 1) % 32; - - /* Return the status from DCAN_TXRQ register */ - return(HWREG(baseAdd + DCAN_TXRQ(regNum)) & (1 << offSet)); -} - -/** - * \brief This API will return the lowest message object number whose transmit - * request status is not set from DCAN_TXRQ(n) register. - * Where n = 12,34,56,78. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return Returns the transmit request status from DCAN_TXRQ(n) register. - * Where n = 12,34,56,78. - * - * \note This API is similar to 'DCANTxRqstStatusGet'. Only difference is - * that the user need not send the message number to read the TxRqst - * status of that message number. This API will return the lowest - * message object number whose TxRqst status is not set. - * - **/ -unsigned int DCANTxRqstStatGet(unsigned int baseAdd) -{ - unsigned int index = 1; - unsigned int regNum; - unsigned int offSet; - - while(index < 128) - { - regNum = (index - 1) / 32; - offSet = (index - 1) % 32; - - if(!(HWREG(baseAdd + DCAN_TXRQ(regNum)) & (1 << offSet))) - { - break; - } - index++; - } - - return(index); -} - -/** - * \brief This API will return the status from DCAN_NWDAT_X register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return Returns the status from DCAN_NWDAT_X register. - * User can use the below macro to check the status \n - * DCAN_NEWDAT_X_REG(n) - Status of DCAN_NWDAT_X register - * corresponding to n \n - * where 1 <= n <= 8 \n - * - **/ -unsigned int DCANNewDataXStatusGet(unsigned int baseAdd) -{ - /* Return the status from DCAN_NWDAT_X register */ - return(HWREG(baseAdd + DCAN_NWDAT_X) & NEW_DATA_X_MASK); -} - -/** - * \brief This API will return the status from DCAN_NWDAT(n) register. - * Where n = 12,34,56,78. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param msgNum Message object number whose NewDat status is - * to be returned. - * - * \return Returns the New data status from DCAN_NWDAT(n) register. - * Where n = 12,34,56,78. - * - * \note Values for 'msgNum' can range from \n - * 1 <= msgNum <= 128. - * - **/ -unsigned int DCANNewDataStatusGet(unsigned int baseAdd, unsigned int msgNum) -{ - unsigned int regNum; - unsigned int offSet; - - regNum = (msgNum - 1) / 32; - offSet = (msgNum - 1) % 32; - - /* Return the status from DCAN_NWDAT register */ - return(HWREG(baseAdd + DCAN_NWDAT(regNum)) & (1 << offSet)); -} - -/** - * \brief This API will return the lowest message object number whose new - * data status is set from DCAN_NWDAT(n) register. - * Where n = 12,34,56,78. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return Returns the new data status from DCAN_NWDAT(n) register. - * Where n = 12,34,56,78. - * - * \note This API is similar to 'DCANNewDataStatusGet'. Only difference is - * that the user need not send the message number to read the NewData - * status of that message number. This API will return the lowest - * message object number whose NewData status is set. - * - **/ -unsigned int DCANNewDataStatGet(unsigned int baseAdd) -{ - unsigned int index = 1; - unsigned int regNum; - unsigned int offSet; - - while(index < 128) - { - regNum = (index - 1) / 32; - offSet = (index - 1) % 32; - - if((HWREG(baseAdd + DCAN_NWDAT(regNum)) & (1 << offSet))) - { - break; - } - index++; - } - - return(index); -} - -/** - * \brief This API will return the status from DCAN_INTPND_X register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return Returns the status from DCAN_INTPND_X register. - * User can use the below macro to check the status \n - * DCAN_INTPND_X_REG(n) - Status of DCAN_INTPND_X register - * corresponding to n \n - * where 1 <= n <= 8 \n - * - **/ -unsigned int DCANIntPendingXStatusGet(unsigned int baseAdd) -{ - /* Return the status from DCAN_INTPND_X register */ - return(HWREG(baseAdd + DCAN_INTPND_X) & INT_PEND_X_MASK); -} - -/** - * \brief This API will return the status from DCAN_INTPND(n) register. - * Where n = 12,34,56,78. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param msgNum Message object number whose IntPnd status is to - * be returned. - * - * \return Returns the Interrupt pending status from DCAN_INTPND(n) register. - * Where n = 12,34,56,78. - * - * \note Values for 'msgNum' can range from \n - * 1 <= msgNum <= 128. - * - **/ -unsigned int DCANIntPendingStatusGet(unsigned int baseAdd, unsigned int msgNum) -{ - unsigned int regNum; - unsigned int offSet; - - regNum = (msgNum - 1) / 32; - offSet = (msgNum - 1) % 32; - - /* Return the status from DCAN_INTPND register */ - return(HWREG(baseAdd + DCAN_INTPND(regNum)) & (1 << offSet)); -} - -/** - * \brief This API will return the status from DCAN_MSGVAL_X register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return Returns the status from DCAN_MSGVAL_X register. - * User can use the below macro to check the status \n - * DCAN_MSGVAL_X_REG(n) - Status of DCAN_MSGVAL_X register - * corresponding to n \n - * where 1 <= n <= 8 \n - * - **/ -unsigned int DCANMsgValidXStatusGet(unsigned int baseAdd) -{ - /* Return the status from DCAN_MSGVAL_X register */ - return(HWREG(baseAdd + DCAN_MSGVAL_X) & MSG_VALID_X_MASK); -} - -/** - * \brief This API will return the status from DCAN_MSGVAL(n) register. - * Where n = 12,34,56,78. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param msgNum Message object number whose MsgVal status is to - * be returned. - * - * \return Returns the Message valid status from DCAN_MSGVAL(n) register. - * Where n = 12,34,56,78. - * - * \note Values for 'msgNum' can take the following values \n - * 1 <= msgNum <= 128. - * - **/ -unsigned int DCANMsgValidStatusGet(unsigned int baseAdd, unsigned int msgNum) -{ - unsigned int regNum; - unsigned int offSet; - - regNum = (msgNum - 1) / 32; - offSet = (msgNum - 1) % 32; - - /* Return the status from DCAN_MSGVAL register */ - return(HWREG(baseAdd + DCAN_MSGVAL(regNum)) & (1 << offSet)); -} - -/** - * \brief This API will configure which Interrupt line will be used to - * service interrupts from message objects. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param intLine Interrupt line to be configured. - * \param msgNum Message object number whose IntMux is to be - * configured. - * - * 'intLine' can take the following values \n - * DCAN_INT0_ACTIVE - DCANINT0 line is active if corresponding - * IntPnd flag is set \n - * DCAN_INT1_ACTIVE - DCANINT1 line is active if corresponding - * IntPnd flag is one \n - * - * \return None. - * - * \note Values for 'msgNum' can range from \n - * 1 <= msgNum <= 128. - * - **/ -void DCANIntMuxConfig(unsigned int baseAdd, unsigned int intLine, - unsigned int msgNum) -{ - unsigned int regNum; - unsigned int offSet; - - regNum = (msgNum - 1) / 32; - offSet = (msgNum - 1) % 32; - - /* Clear the IntMux field of DCAN_INTMUX register corresponding to msgNum */ - HWREG(baseAdd + DCAN_INTMUX(regNum)) &= ~(1 << offSet); - - /* Set the DCAN_INTMUX field corresponding to msgNum */ - HWREG(baseAdd + DCAN_INTMUX(regNum)) |= (msgNum << offSet); -} - -/** - * \brief This API will validate a message object. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param regNum Interface register number used. - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - IF register 1 is used \n - * DCAN_IF2_REG - IF register 2 is used \n - * - * \return None. - * - **/ -void DCANMsgObjValidate(unsigned int baseAdd, unsigned int regNum) -{ - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Validate the message object */ - HWREG(baseAdd + DCAN_IFARB(regNum)) |= DCAN_IFARB_MSGVAL; -} - -/** - * \brief This API will invalidate a message object. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param regNum Interface register number used. - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - IF register 1 is used \n - * DCAN_IF2_REG - IF register 2 is used \n - * - * \return None. - * - **/ -void DCANMsgObjInvalidate(unsigned int baseAdd, unsigned int regNum) -{ - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Invalidate the message object */ - HWREG(baseAdd + DCAN_IFARB(regNum)) &= ~DCAN_IFARB_MSGVAL; -} - -/** - * \brief This API will set the fields of DCAN_IFCMD register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param cmdFlags Fields of the DCAN_IFCMD register which are - * to be set. - * \param objNum Message object number to be configured. - * \param regNum Interface register number used. - * - * 'cmdFlags' can take the following values \n - * DCAN_DMA_ACTIVE - Enable DMA feature \n - * DCAN_DAT_A_ACCESS - Access data from IF DataA register \n - * DCAN_DAT_B_ACCESS - Access data from IF DataB register \n - * DCAN_TXRQST_ACCESS - Access the TxRqst bit \n - * DCAN_CLR_INTPND - Clear the IntPnd bit \n - * DCAN_ACCESS_CTL_BITS - Access control bits \n - * DCAN_ACCESS_ARB_BITS - Access Arbitration bits \n - * DCAN_ACCESS_MSK_BITS - Access the mask bits \n - * DCAN_MSG_WRITE - Transfer direction is from IF registers to - * message RAM \n - * DCAN_MSG_READ - Transfer direction is from message RAM to - * IF registers \n - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - IF register 1 is used \n - * DCAN_IF2_REG - IF register 2 is used \n - * - * \return None. - * - **/ -void DCANCommandRegSet(unsigned int baseAdd, unsigned int cmdFlags, - unsigned int objNum, unsigned int regNum) -{ - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Clear the DCAN_IFCMD register fields */ - HWREG(baseAdd + DCAN_IFCMD(regNum)) &= ~(DCAN_IFCMD_DMAACTIVE | - DCAN_IFCMD_DATAA | - DCAN_IFCMD_DATAB | - DCAN_IFCMD_TXRQST_NEWDAT | - DCAN_IFCMD_CLRINTPND | - DCAN_IFCMD_CONTROL | - DCAN_IFCMD_ARB | - DCAN_IFCMD_MASK | - DCAN_IFCMD_MESSAGENUMBER | - DCAN_IFCMD_WR_RD); - - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Set the DCAN_IFCMD register fields represented by cmdFlags */ - HWREG(baseAdd + DCAN_IFCMD(regNum)) |= ((cmdFlags & - (DCAN_IFCMD_DMAACTIVE | - DCAN_IFCMD_DATAA | - DCAN_IFCMD_DATAB | - DCAN_IFCMD_TXRQST_NEWDAT | - DCAN_IFCMD_CLRINTPND | - DCAN_IFCMD_CONTROL | - DCAN_IFCMD_ARB | - DCAN_IFCMD_MASK | - DCAN_IFCMD_WR_RD)) | - (objNum & DCAN_IFCMD_MESSAGENUMBER)); -} - -/** - * \brief This API will return the status of Busy field from DCAN_IFCMD - * register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param regNum Interface register number used. - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - Interface register 1 is used \n - * DCAN_IF2_REG - Interface register 2 is used \n - * - * \return Returns the Busy bit status from the DCAN_IFCMD register. - * User can use the below macros to check the status \n - * DCAN_IF_BUSY - Transfer between IF register and message RAM is - * in progress. - * DCAN_IF_NOT_BUSY - No Transfer between IF register and message RAM. - * - **/ -unsigned int DCANIFBusyStatusGet(unsigned int baseAdd, unsigned int regNum) -{ - /* Returns the status of BUSY field from DCAN_IF_CMD register */ - return(HWREG(baseAdd + DCAN_IFCMD(regNum)) & DCAN_IFCMD_BUSY); -} - -/** - * \brief This API will set the message identifier length and number. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param msgId Message identifier number. - * \param idLength Identifier length. - * \param regNum Interface register number used. - * - * 'idLength' can take the following values \n - * DCAN_11_BIT_ID - 11 bit identifier is used \n - * DCAN_29_BIT_ID - 29 bit identifier is used \n - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - Interface register 1 is used \n - * DCAN_IF2_REG - Interface register 2 is used \n - * - * \return None. - * - **/ -void DCANMsgIdSet(unsigned int baseAdd, unsigned int msgId, - unsigned int idLength, unsigned int regNum) -{ - - if(idLength == DCAN_11_BIT_ID) - { - msgId <<= DCAN_STD_ID_SHIFT; - } - - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Clear the Msk field of DCAN_IFARB register */ - HWREG(baseAdd + DCAN_IFARB(regNum)) &= ~(DCAN_IFARB_MSK | DCAN_IFARB_XTD); - - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Set the Msk field with the ID value */ - HWREG(baseAdd + DCAN_IFARB(regNum)) |= ((msgId & DCAN_IFARB_MSK) | - (idLength & DCAN_IFARB_XTD)); -} - -/** - * \brief This API will set the direction for the message object. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param msgDir Message direction for the message object. - * \param regNum Interface register number used. - * - * 'msgDir' can take the following values \n - * DCAN_TX_DIR - Message object set to transmit a message \n - * DCAN_RX_DIR - Message object set to receive a message \n - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - Interface register 1 is used \n - * DCAN_IF2_REG - Interface register 2 is used \n - * - * \return None. - * - **/ -void DCANMsgDirectionSet(unsigned int baseAdd, unsigned int msgDir, - unsigned int regNum) -{ - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Clear the Dir field of DCAN_IFARB register */ - HWREG(baseAdd + DCAN_IFARB(regNum)) &= ~DCAN_IFARB_DIR; - - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Set the Dir field with the user sent value */ - HWREG(baseAdd + DCAN_IFARB(regNum)) |= (msgDir & DCAN_IFARB_DIR); -} - -/** - * \brief This API will write data bytes to the IF Data registers. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param dataPtr Pointer used to fetch data bytes. - * \param regNum Interface register number used. - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - IF register 1 is used \n - * DCAN_IF2_REG - IF register 2 is used \n - * - * \return None. - * - **/ -void DCANDataWrite(unsigned int baseAdd, unsigned int* dataPtr, - unsigned int regNum) -{ - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Write the lower 4 data bytes to IFDATA register */ - HWREG(baseAdd + DCAN_IFDATA(regNum)) = *dataPtr++; - - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Write the higher 4 data bytes to IFDATB register */ - HWREG(baseAdd + DCAN_IFDATB(regNum)) = *dataPtr; -} - -/** - * \brief This API will read the data bytes from the IF Data registers. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param regNum Interface register number used. - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - IF register 1 is used \n - * DCAN_IF2_REG - IF register 2 is used \n - * DCAN_IF3_REG - IF register 3 is used \n - * - * \return None. - * - **/ -void DCANDataRead(unsigned int baseAdd, unsigned int* data, - unsigned int regNum) -{ - /* Read the data bytes from the DCAN_IFDATA register */ - *data++ = HWREG(baseAdd + DCAN_IFDATA(regNum)); - - /* Read the data bytes from the DCAN_IFDATB register */ - *data = HWREG(baseAdd + DCAN_IFDATB(regNum)); -} - -/** - * \brief This API will set the data length code. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param dlc Data length code. - * \param regNum Interface register number used. - * - * 'dlc' can take the below values \n - * dlc can range between 1-8 for 1-8 data bytes \n - * dlc value lying between 9-15 will configure it for 8 data bytes \n - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - IF register 1 is used \n - * DCAN_IF2_REG - IF register 2 is used \n - * - * \return None. - * - **/ -void DCANDataLengthCodeSet(unsigned int baseAdd, unsigned int dlc, - unsigned int regNum) -{ - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Clear the DLC field of DCAN_IFMCTL register */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) &= ~DCAN_IFMCTL_DATALENGTHCODE; - - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Set the DLC field with the user sent value */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) |= (dlc & DCAN_IFMCTL_DATALENGTHCODE); -} - -/** - * \brief This API will configure the setting for remote enable. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param remEnable Configure remote enable. - * \param regNum Interface register number used. - * - * 'remEnable' can take the following values \n - * DCAN_REMOTE_ENABLE - At the reception of a remote frame TxRqst is set \n - * DCAN_REMOTE_DISABLE - At the reception of a remote frame TxRqst is not - * changed \n - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - IF register 1 is used \n - * DCAN_IF2_REG - IF register 2 is used \n - * - * \return None. - * - **/ -void DCANRemoteEnableControl(unsigned int baseAdd, unsigned int remEnable, - unsigned int regNum) -{ - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Clear the RmtEn field of DCAN_IFMCTL register */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) &= ~DCAN_IFMCTL_RMTEN; - - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Set the remote enable field with the user sent value */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) |= (remEnable & DCAN_IFMCTL_RMTEN); -} - -/** - * \brief This API will enable the Message object interrupts of the DCAN - * peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param intFlags Enable the message object interrupts - * represented by intFlags. - * \param regNum Interface register number used. - * - * 'intFlags' can take the following values \n - * DCAN_TRANSMIT_INT - Enable the transmit interrupt \n - * DCAN_RECEIVE_INT - Enable the receive interrupt \n - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - IF register 1 is used \n - * DCAN_IF2_REG - IF register 2 is used \n - * - * \return None. - * - **/ -void DCANMsgObjIntEnable(unsigned int baseAdd, unsigned int intFlags, - unsigned int regNum) -{ - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Enable Message object interrupts */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) |= (intFlags & - (DCAN_IFMCTL_TXIE | - DCAN_IFMCTL_RXIE)); -} - -/** - * \brief This API will disable the Message object interrupts of the DCAN - * peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param intFlags Disable the message object interrupts - * represented by intFlags. - * \param regNum Interface register number used. - * - * 'intFlags' can take the following values \n - * DCAN_TRANSMIT_INT - Disable the transmit interrupt \n - * DCAN_RECEIVE_INT - Disable the receive interrupt \n - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - IF register 1 is used \n - * DCAN_IF2_REG - IF register 2 is used \n - * - * \return None. - * - **/ -void DCANMsgObjIntDisable(unsigned int baseAdd, unsigned int intFlags, - unsigned int regNum) -{ - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Enable Message object interrupts */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) &= ~(intFlags & - (DCAN_IFMCTL_TXIE | - DCAN_IFMCTL_RXIE)); -} - -/** - * \brief This API will configure the end of block settings for the DCAN - * peripheral. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param eob Configure End of block. - * \param regNum Interface register number used. - * - * 'eob' can take the following values \n - * DCAN_END_OF_BLOCK_ENABLE - Enable end of block \n - * DCAN_END_OF_BLOCK_DISABLE - Disable end of block \n - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - IF register 1 is used \n - * DCAN_IF2_REG - IF register 2 is used \n - * - * \return None. - * - **/ -void DCANFIFOEndOfBlockControl(unsigned int baseAdd, unsigned int eob, - unsigned int regNum) -{ - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Clear the EOB field of DCAN_IFMCTL register */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) &= ~DCAN_IFMCTL_EOB; - - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Set the EOB field with the user sent value */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) |= (eob & DCAN_IFMCTL_EOB); -} - -/** - * \brief This API will configure the mask settings for a message object. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param idMsk Identifier mask. - * \param msgDir Mask message direction. - * \param extId Mask extended identifier. - * \param regNum Interface register number used. - * - * 'idMsk' can take the following value \n - * DCAN_IDENTIFIER_MSK(mask, idType) \n - * where 0 <= mask <= 0x1FFFFFFF \n - * - * 'idType' can take the following values \n - * DCAN_ID_MSK_11_BIT - 11 bit identifier mask is used \n - * DCAN_ID_MSK_29_BIT - 29 bit identifier mask is used \n - * - * 'msgDir' can take the following values \n - * DCAN_MSK_MSGDIR_ENABLE - Message direction bit is used for - * acceptance filtering \n - * DCAN_MSK_MSGDIR_DISABLE - Message direction bit has no effect on - * acceptance filtering \n - * - * 'extId' can take the following values \n - * DCAN_MSK_EXT_ID_ENABLE - The IDE bit is used for acceptance filtering \n - * DCAN_MSK_EXT_ID_DISABLE - The IDE bit is not used for acceptance - * filtering \n - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - IF register 1 is used \n - * DCAN_IF2_REG - IF register 2 is used \n - * - * \return None. - * - **/ -void DCANMsgObjectMskConfig(unsigned int baseAdd, unsigned int idMsk, - unsigned int msgDir, unsigned int extId, - unsigned int regNum) -{ - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Write to the DCAN_IFMSK register */ - HWREG(baseAdd + DCAN_IFMSK(regNum)) = ((idMsk & DCAN_IF1MSK_MSK) | - (msgDir & DCAN_IFMSK_MDIR) | - (extId & DCAN_IFMSK_MXTD)); -} - -/** - * \brief This API will configure IF3 register set so that it is - * automatically updated with the received value in message RAM. - * Where n = 12,34,56,78. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param msgNum Message object number for which IF3 register - * set has to be updated. - * - * \return None. - * - * \note Values for 'msgNum' can range from \n - * 1 <= msgNum <= 128. - * IF3 Update enable should not be set for transmit objects. - * - **/ -void DCANIF3RegUpdateEnableSet(unsigned int baseAdd, unsigned int msgNum) -{ - unsigned int regNum; - unsigned int offSet; - - regNum = (msgNum - 1) / 32; - offSet = (msgNum - 1) % 32; - - /* Set the DCAN_IF3UPD register with the proper value */ - HWREG(baseAdd + DCAN_IF3UPD(regNum)) |= (1 << offSet); -} - -/** - * \brief This API will set the observation flag bits in the IF3 observation - * register which are used to determine which data sections of the IF3 - * interface register set have to be read in order to complete a DMA - * read cycle. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param obsFlags Flags which are to be set. - * - * 'obsFlags' can take the follwing values \n - * DCAN_MASK_DATA - Set Mask data read observation \n - * DCAN_ARB_DATA - Set Arbitration data read observation \n - * DCAN_CTRL_DATA - Set Ctrl read observation \n - * DCAN_DAT_A_DATA - Set Data A read observation \n - * DCAN_DAT_B_DATA - Set Data B read observation \n - * - * \return None. - * - **/ -void DCANIF3ObservationFlagSet(unsigned int baseAdd, unsigned int obsFlags) -{ - /* Set the appropriate flags in the DCAN_IF3OBS register */ - HWREGB(baseAdd + DCAN_IF3OBS) |= (obsFlags & (DCAN_IF3OBS_MASK | - DCAN_IF3OBS_ARB | DCAN_IF3OBS_CTRL | - DCAN_IF3OBS_DATAA | DCAN_IF3OBS_DATAB)); -} - -/** - * \brief This API will clear the observation flag bits in the IF3 observation - * register which are used to determine which data sections of the IF3 - * interface register set have to be read in order to complete a DMA - * read cycle. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param obsFlags Flags which are to be cleared. - * - * 'obsFlags' can take the following values \n - * DCAN_MASK_DATA - Clear Mask data read observation \n - * DCAN_ARB_DATA - Clear Arbitration data read observation \n - * DCAN_CTRL_DATA - Clear Ctrl read observation \n - * DCAN_DAT_A_DATA - Clear Data A read observation \n - * DCAN_DAT_B_DATA - Clear Data B read observation \n - * - * \return None. - * - **/ -void DCANIF3ObservationFlagClear(unsigned int baseAdd, unsigned int obsFlags) -{ - /* Set the appropriate flags in the DCAN_IF3OBS register */ - HWREGB(baseAdd + DCAN_IF3OBS) &= ~(obsFlags & (DCAN_IF3OBS_MASK | - DCAN_IF3OBS_ARB | DCAN_IF3OBS_CTRL | - DCAN_IF3OBS_DATAA| DCAN_IF3OBS_DATAB)); -} - -/** - * \brief This API will return observation flag status from the DCAN_IF3OBS - * register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return Returns the observation flag status from the DCAN_IF3OBS register. - * The following macros can be used to check the status \n - * DCAN_IF3_MASK_STATUS - IF3 status of Mask data read access \n - * DCAN_IF3_ARB_STATUS - IF3 status of Arbitration data read access \n - * DCAN_IF3_CTRL_STATUS - IF3 status of Control bits read access \n - * DCAN_IF3_DAT_A_STATUS - IF3 status of Data A read access \n - * DCAN_IF3_DAT_B_STATUS - IF3 status of Data B read access \n - * DCAN_IF3_UPDATE_STATUS - IF3 Update data status \n - * - **/ -unsigned char DCANIF3ObservationFlagStatGet(unsigned int baseAdd) -{ - /* Return the observation flag status from the DCAN_IF3OBS register */ - return(HWREGB(baseAdd + DCAN_IF3OBS + 1)); -} - -/** - * \brief This API will return the status from the DCAN_IF3MSK register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return Returns the status of DCAN_IF3MSK register. - * The following macros can be used to check the status \n - * DCAN_ID_MSK_READ - Read Identifier mask \n - * DCAN_MSK_MSG_DIR_READ - Read mask message direction \n - * DCAN_MSK_EXT_ID_READ - Read mask extended identifier \n - * - **/ -unsigned int DCANIF3MaskStatusGet(unsigned int baseAdd) -{ - /* Return the status of DCAN_IF3MSK register */ - return(HWREG(baseAdd + DCAN_IFMSK(DCAN_IF3_REG))); -} - -/** - * \brief This API will return the status from the DCAN_IF3ARB register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * - * \return Returns the status of DCAN_IF3ARB register. - * The following macros can be used to check the status \n - * DCAN_MSG_ID_READ - Read message Identifier \n - * DCAN_MSG_DIR_READ - Read message direction \n - * DCAN_EXT_ID_READ - Read extended identifier \n - * DCAN_MSGVAL_READ - Read message valid status \n - * - **/ -unsigned int DCANIF3ArbStatusGet(unsigned int baseAdd) -{ - /* Return the status of DCAN_IF3ARB register */ - return(HWREG(baseAdd + DCAN_IFARB(DCAN_IF3_REG))); -} - -/** - * \brief This API will return the status from the DCAN_IFMCTL register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param regNum Interface register used. - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - Interface register 1 is used \n - * DCAN_IF2_REG - Interface register 2 is used \n - * DCAN_IF3_REG - Interface register 3 is used \n - * - * \return Returns the status of DCAN_IFMCTL register. - * The following macros can be used to check the status \n - * DCAN_DAT_LEN_CODE_READ - Read data length code \n - * DCAN_END_OF_BLOCK_READ - Read end of block bit \n - * DCAN_TXRQST_READ - Read transmit request bit \n - * DCAN_RMT_ENABLE_READ - Read remote enable bit \n - * DCAN_RX_INT_ENABLE_READ - Read Rx interrupt enable bit \n - * DCAN_TX_INT_ENABLE_READ - Read Tx interrupt enable bit \n - * DCAN_UMASK_READ - Read use acceptance mask bit \n - * DCAN_INTPND_READ - Read interrupt pending status \n - * DCAN_MSG_LOST_READ - Read message lost status \n - * DCAN_NEWDAT_READ - Read new data status \n - * - **/ -unsigned int DCANIFMsgCtlStatusGet(unsigned int baseAdd, unsigned int regNum) -{ - /* Return the status of DCAN_IFMCTl register */ - return(HWREG(baseAdd + DCAN_IFMCTL(regNum))); -} - -/** - * \brief This API will configure the DCAN TX pin as a general purpose pin - * or as a functional pin. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param txPinMode Mode used for DCAN Tx pin. - * - * 'txPinMode' can take the following values \n - * DCAN_TX_PIN_GIO_MODE - Tx pin is used as a GIO pin \n - * DCAN_TX_PIN_FUNC_MODE - Tx pin is used as a functional pin of DCAN - * core \n - * - * \return None. - * - * \note If DCAN Tx pin is to be used as a GIO pin then the Init bit in CAN - * control register must be set. If Tx pin is in GIO mode and the Init - * bit gets reset then the DCAN Tx pin will be automatically used as a - * functional pin of DCAN. In functional mode Tx pin will be used - * as output. - * - **/ -void DCANTxPinModeConfig(unsigned int baseAdd, unsigned int txPinMode) -{ - /* Clear the Func field of DCAN_TIOC register */ - HWREG(baseAdd + DCAN_TIOC) &= ~DCAN_TIOC_FUNC; - - /* Set the Func field with the user sent value */ - HWREG(baseAdd + DCAN_TIOC) |= (txPinMode & DCAN_TIOC_FUNC); -} - -/** - * \brief This API will configure the polarity for DCAN TX pin when it is - * used as an input pin. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param pinLogic Logic used for Tx pin. - * - * 'pinLogic' can take the following values \n - * DCAN_TX_PIN_IN_LOGIC_LOW - Tx pin used as input with low logic \n - * DCAN_TX_PIN_IN_LOGIC_HIGH - Tx pin used as input with high logic \n - * - * \return None. - * - * \note Please ensure to configure the DCAN Tx pin as GIO before calling - * this API. This API is valid only if 'Init' bit of CAN control - * register is set. The CAN controller can go to functional mode if - * 'Init' bit becomes reset even if this API is used. In functional - * mode Tx pin will be used as output. - * - **/ -void DCANTxPinInputDirConfig(unsigned int baseAdd, unsigned int pinLogic) -{ - /* Configure the Tx pin of DCAN as input */ - HWREG(baseAdd + DCAN_TIOC) &= ~DCAN_TIOC_DIR; - - /* Clear the In field of DCAN_TIOC register */ - HWREG(baseAdd + DCAN_TIOC) &= ~DCAN_TIOC_IN; - - /* Set the In field with the user sent value */ - HWREG(baseAdd + DCAN_TIOC) |= (pinLogic & DCAN_TIOC_IN); -} - -/** - * \brief This API will configure the polarity for DCAN TX pin when it is - * used as an output pin. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param pinLogic Logic used for Tx pin. - * - * 'pinLogic' can take the following values \n - * DCAN_TX_PIN_OUT_LOGIC_LOW - Tx pin used as output with low logic \n - * DCAN_TX_PIN_OUT_LOGIC_HIGH - Tx pin used as output with high logic \n - * - * \return None. - * - * \note Please ensure to configure the DCAN Tx pin as GIO before calling - * this API. This API is valid only if 'Init' bit of CAN control - * register is set. The CAN controller can go to functional mode if - * 'Init' bit becomes reset even if this API is used. In functional - * mode Tx pin will be used as output. - * - **/ -void DCANTxPinOutputDirConfig(unsigned int baseAdd, unsigned int pinLogic) -{ - /* Configure the Tx pin of DCAN as output */ - HWREG(baseAdd + DCAN_TIOC) |= DCAN_TIOC_DIR; - - /* Clear the Out field of DCAN_TIOC register */ - HWREG(baseAdd + DCAN_TIOC) &= ~DCAN_TIOC_OUT; - - /* Set the Out field with the user sent value */ - HWREG(baseAdd + DCAN_TIOC) |= (pinLogic & DCAN_TIOC_OUT); -} - -/** - * \brief This API will configure the DCAN RX pin as a general purpose pin - * or as a functional pin. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param rxPinMode Mode used for DCAN Rx pin. - * - * 'rxPinMode' can take the following values \n - * DCAN_RX_PIN_GIO_MODE - Rx pin is used as a GIO pin \n - * DCAN_RX_PIN_FUNC_MODE - Rx pin is used as a functional pin of DCAN - * core \n - * - * \return None. - * - * \note If DCAN Rx pin is to be used as a GIO pin then the Init bit in CAN - * control register must be set. If Rx pin is in GIO mode and the Init - * bit gets reset then the DCAN Rx pin will be automatically used as a - * functional pin of DCAN core. In functional mode Rx pin will be used - * as output. - * - **/ -void DCANRxPinModeConfig(unsigned int baseAdd, unsigned int rxPinMode) -{ - /* Clear the Func field of DCAN_TIOC register */ - HWREG(baseAdd + DCAN_RIOC) &= ~DCAN_RIOC_FUNC; - - /* Set the Func field with the user sent value */ - HWREG(baseAdd + DCAN_RIOC) |= (rxPinMode & DCAN_RIOC_FUNC); -} - -/** - * \brief This API will configure the polarity for DCAN RX pin when it is - * used as an input pin. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param pinLogic Logic used for Rx pin. - * - * 'pinLogic' can take the following values \n - * DCAN_RX_PIN_IN_LOGIC_LOW - Rx pin used as input with low logic \n - * DCAN_RX_PIN_IN_LOGIC_HIGH - Rx pin used as input with high logic \n - * - * \return None. - * - * \note Please ensure to configure the DCAN Rx pin as GIO before calling - * this API. This API is valid only if 'Init' bit of CAN control - * register is set. The CAN controller can go to functional mode if - * 'Init' bit becomes reset even if this API is used. In functional - * mode Rx pin will be used as output. - * - **/ -void DCANRxPinInputDirConfig(unsigned int baseAdd, unsigned int pinLogic) -{ - /* Configure the Rx pin of DCAN as input */ - HWREG(baseAdd + DCAN_RIOC) &= ~DCAN_RIOC_DIR; - - /* Clear the In field of DCAN_RIOC register */ - HWREG(baseAdd + DCAN_RIOC) &= ~DCAN_RIOC_IN; - - /* Set the In field with the user sent value */ - HWREG(baseAdd + DCAN_RIOC) |= (pinLogic & DCAN_RIOC_IN); -} - -/** - * \brief This API will configure the polarity for DCAN RX pin when it is - * used as an output pin. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param pinLogic Logic used for Rx pin. - * - * 'pinLogic' can take the following values \n - * DCAN_RX_PIN_OUT_LOGIC_LOW - Rx pin used as output with low logic \n - * DCAN_RX_PIN_OUT_LOGIC_HIGH - Rx pin used as output with high logic \n - * - * \return None. - * - * \note Please ensure to configure the DCAN Rx pin as GIO before calling - * this API. This API is valid only if 'Init' bit of CAN control - * register is set. The CAN controller can go to functional mode if - * 'Init' bit becomes reset even if this API is used. In functional - * mode Rx pin will be used as output. - * - **/ -void DCANRxPinOutputDirConfig(unsigned int baseAdd, unsigned int pinLogic) -{ - /* Configure the Rx pin of DCAN as output */ - HWREG(baseAdd + DCAN_RIOC) |= DCAN_RIOC_DIR; - - /* Clear the Out field of DCAN_RIOC register */ - HWREG(baseAdd + DCAN_RIOC) &= ~DCAN_RIOC_OUT; - - /* Set the Out field with the user sent value */ - HWREG(baseAdd + DCAN_RIOC) |= (pinLogic & DCAN_RIOC_OUT); -} - -/** - * \brief This API will clear the IntPnd bit of DCAN_IFMCTL register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param regNum Interface register set used. - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - Interface register set 1 is used \n - * DCAN_IF2_REG - Interface register set 2 is used \n - * - * \return None. - * - **/ -void DCANClrIntPnd(unsigned int baseAdd, unsigned int regNum) -{ - /* Wait in loop until busy bit is cleared */ - while(DCANIFBusyStatusGet(baseAdd, regNum)); - - /* Clear the IntPnd bit of DCAN_IFMCTL register */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) &= ~(DCAN_IFMCTL_INTPND); -} - -/** - * \brief This API will set/clear the NewDat bit of DCAN_IFMCTL register. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param newDat Set/Clear NewDat bit. - * \param regNum Interface register set used. - * - * 'newDat' can take the following values \n - * DCAN_NEW_DAT_SET - Set NewDat bit \n - * DCAN_NEW_DAT_CLR - Clear NewDat bit \n - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - Interface register set 1 is used \n - * DCAN_IF2_REG - Interface register set 2 is used \n - * - * \return None. - * - * \note If TxRqst/NewDat is set by using the API 'DCANCommandRegSet' then - * TxRqst/NewDat will be set to '1' independent of the value set - * using this API. - * - **/ -void DCANNewDataControl(unsigned int baseAdd, unsigned int newDat, - unsigned int regNum) -{ - /* Clear the NewDat bit of DCAN_IFMCTL register */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) &= ~(DCAN_IFMCTL_NEWDAT); - - /* Set the NewDat bit with user sent value */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) |= (newDat & DCAN_IFMCTL_NEWDAT); -} - -/** - * \brief This API will control the Acceptance mask feature. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param uMask Acceptance mask control. - * \param regNum Interface register set used. - * - * 'uMask' can take the following values \n - * DCAN_MASK_USED - Acceptance mask used \n - * DCAN_MASK_IGNORED - Acceptance mask ignored \n - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - Interface register set 1 is used \n - * DCAN_IF2_REG - Interface register set 2 is used \n - * - * \return None. - * - **/ -void DCANUseAcceptanceMaskControl(unsigned int baseAdd, unsigned int uMask, - unsigned int regNum) -{ - /* Clear the UMask bit of DCAN_IFMCTL register */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) &= ~(DCAN_IFMCTL_UMASK); - - /* Set the UMask bit of DCAN_IFMCTL register with the user sent value */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) |= (uMask & DCAN_IFMCTL_UMASK); -} - -/** - * \brief This API will control the Transmission request feature. - * - * \param baseAdd Base Address of the DCAN Module Registers. - * \param txRqst Transmit request control. - * \param regNum Interface register set used. - * - * 'txRqst' can take the following values \n - * DCAN_TRANSMIT_REQUESTED - Transmission requested \n - * DCAN_TRANSMIT_NOT_REQUESTED - Transmission not requested \n - * - * 'regNum' can take the following values \n - * DCAN_IF1_REG - Interface register set 1 is used \n - * DCAN_IF2_REG - Interface register set 2 is used \n - * - * \return None. - * - * \note If TxRqst/NewDat is set by using the API 'DCANCommandRegSet' then - * TxRqst/NewDat will be set to '1' independent of the value set - * using this API. - * - **/ -void DCANTransmitRequestControl(unsigned int baseAdd, unsigned int txRqst, - unsigned int regNum) -{ - /* Clear the TxRqst bit of DCAN_IFMCTL register */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) &= ~(DCAN_IFMCTL_TXRQST); - - /* Set the TxRqst bit with the user sent value */ - HWREG(baseAdd + DCAN_IFMCTL(regNum)) |= (txRqst & DCAN_IFMCTL_TXRQST); -} - -/****************************** END OF FILE ***********************************/ diff --git a/lib/tiam1808/drivers/elm.c b/lib/tiam1808/drivers/elm.c deleted file mode 100644 index d574eb798..000000000 --- a/lib/tiam1808/drivers/elm.c +++ /dev/null @@ -1,725 +0,0 @@ -/** - * \file elm.c - * - * \brief ELM APIs. - * - * This file contains the device abstraction layer APIs for ELM. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#include "hw_elm.h" -#include "hw_types.h" -#include "elm.h" - -/******************************************************************************* -* INTERNAL API DEFINITIONS -*******************************************************************************/ -/** -* \brief This function reads the IP revision code of ELM.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \return ipRev IP revision code of ELM.\n -*/ -unsigned int ELMRevisionGet(unsigned int baseAddr) -{ - unsigned int ipRev; - - ipRev = (HWREG(baseAddr + ELM_REVISION) & ELM_REVISION_REVISION); - - return (ipRev); -} - -/** -* \brief This function configs the Internal OCP clock gating strategy.\n -* -* \param baseaddr Memory address of ELM.\n -* -* \param configVal config value for OCP clk gating.\n -* This can take one of the following values :\n -* ELM_AUTOGATING_OCP_FREE -- OCP clock is free-running\n -* ELM_AUTOGATING_OCP_GATING -- Automatic internal OCP -* clock gating strategy is -* applied based on the OCP -* interface activity.\n -* -* \return none.\n -*/ -void ELMCAutoGatingConfig(unsigned int baseAddr, unsigned int configVal) -{ - HWREG(baseAddr + ELM_SYSCONFIG) &= ~ELM_SYSCONFIG_AUTOGATING; - HWREG(baseAddr + ELM_SYSCONFIG)= ((configVal << - ELM_SYSCONFIG_AUTOGATING_SHIFT) - & ELM_SYSCONFIG_AUTOGATING); -} - -/** -* \brief This function sets the idle mode for ELM.\n -* -* \param baseaddr Memory address of ELM.\n -* -* \param mode Idle mode.\n -* This can take one of the following values :\n -* ELM_IDLEMODE_FORCEIDLE -- for force-idle. \n -* ELM_IDLEMODE_NOIDLE -- for no-idle. \n -* ELM_IDLEMODE_SMARTIDLE -- for smart-idle.\n -* -* \return none.\n -*/ -void ELMCIdleModeSelect(unsigned int baseAddr, unsigned int mode) -{ - HWREG(baseAddr + ELM_SYSCONFIG) &= ~ELM_SYSCONFIG_SIDLEMODE; - HWREG(baseAddr + ELM_SYSCONFIG) |= ((mode << - ELM_SYSCONFIG_SIDLEMODE_SHIFT) - & ELM_SYSCONFIG_SIDLEMODE); -} - -/** -* \brief This function Resets the ELM.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \return None.\n -*/ - -void ELMModuleReset(unsigned int baseAddr) -{ - HWREG(baseAddr + ELM_SYSCONFIG)= (ELM_SYSCONFIG_SOFTRESET_RESET << - ELM_SYSCONFIG_SOFTRESET_SHIFT); -} - -/** -* \brief This function sets the OCP Clock activity when module is in IDLE -* mode.\n -* -* \param baseaddr Memory address of ELM.\n -* -* \param configVal Config value.\n -* This can take one of the following values :\n -* ELM_CLOCKACTIVITYOCP_OCP_OFF -- OCP clock is swith off\n -* ELM_CLOCKACTIVITYOCP_OCP_ON -- OCP Clock is -* maintained during -* wake up period.\n -* -* \return none.\n -*/ -void ELMOCPClkActivityConfig(unsigned int baseAddr, unsigned int configVal) -{ - HWREG(baseAddr + ELM_SYSCONFIG) &= ~ELM_SYSCONFIG_CLOCKACTIVITYOCP; - HWREG(baseAddr + ELM_SYSCONFIG) |= ((configVal << - ELM_SYSCONFIG_CLOCKACTIVITYOCP_SHIFT) - & ELM_SYSCONFIG_CLOCKACTIVITYOCP); -} - -/** -* \brief This function gets the software resets status of ELM.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \return status Reset status : \n -* 0 : Module reset is on-going.\n -* 1 : Module reset is completed.\n -*/ - -unsigned int ELMModuleResetStatusGet(unsigned int baseAddr) -{ - unsigned int resetStat; - - resetStat = (HWREG(baseAddr + ELM_SYSSTATUS) & ELM_SYSSTATUS_RESETDONE); - - return (resetStat); -} - -/** -* \brief This function gets Interrupt status.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \param flag Flag for which interrupt status has to get.\n -* This can take one of the following values :\n -* ELM_LOC_VALID_0_STATUS : Error-location -* status for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_1_STATUS : Error-location -* status for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_2_STATUS : Error-location -* status for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_3_STATUS : Error-location -* status for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_4_STATUS : Error-location -* status for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_5_STATUS : Error-location -* status for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_6_STATUS : Error-location -* status for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_7_STATUS : Error-location -* status for syndrome -* polynomial 0.\n -* ELM_PAGE_VALID_STATUS : Error-location -* status for a full -* page. \n -* -* \return intSts Interrupt Status. Return value meaning depends on the -* param flag. \n -* if flag is ELM_LOC_VALID_i_STATUS where i = 0 to 7, -* then\n -* 0 : No syndrome processed or process in progress.\n -* 1 : Error-location process completed.\n -* -* if flag is ELM_PAGE_VALID_STATUS, then\n -* 0 : Error locations invalid for all polynomials -* enabled.\n -* 1 : All error locations valid.\n -* -* -*/ -unsigned int ELMIntStatusGet(unsigned int baseAddr, unsigned int flag) -{ - - unsigned int retVal; - - retVal = 0; - - switch(flag) - { - case ELM_LOC_VALID_0_STATUS: - retVal = ((HWREG(baseAddr + ELM_IRQSTATUS) & - ELM_IRQSTATUS_LOC_VALID_0) >> - ELM_IRQSTATUS_LOC_VALID_0_SHIFT ); - break; - case ELM_LOC_VALID_1_STATUS: - retVal = ((HWREG(baseAddr + ELM_IRQSTATUS) & - ELM_IRQSTATUS_LOC_VALID_1) >> - ELM_IRQSTATUS_LOC_VALID_1_SHIFT ); - break; - case ELM_LOC_VALID_2_STATUS: - retVal = ((HWREG(baseAddr + ELM_IRQSTATUS) & - ELM_IRQSTATUS_LOC_VALID_2) >> - ELM_IRQSTATUS_LOC_VALID_2_SHIFT ); - break; - case ELM_LOC_VALID_3_STATUS: - retVal = ((HWREG(baseAddr + ELM_IRQSTATUS) & - ELM_IRQSTATUS_LOC_VALID_3) >> - ELM_IRQSTATUS_LOC_VALID_3_SHIFT ); - break; - case ELM_LOC_VALID_4_STATUS: - retVal = ((HWREG(baseAddr + ELM_IRQSTATUS) & - ELM_IRQSTATUS_LOC_VALID_4) >> - ELM_IRQSTATUS_LOC_VALID_4_SHIFT ); - break; - case ELM_LOC_VALID_5_STATUS: - retVal = ((HWREG(baseAddr + ELM_IRQSTATUS) & - ELM_IRQSTATUS_LOC_VALID_5) >> - ELM_IRQSTATUS_LOC_VALID_5_SHIFT ); - break; - case ELM_LOC_VALID_6_STATUS: - retVal = ((HWREG(baseAddr + ELM_IRQSTATUS) & - ELM_IRQSTATUS_LOC_VALID_6) >> - ELM_IRQSTATUS_LOC_VALID_6_SHIFT ); - break; - case ELM_LOC_VALID_7_STATUS: - retVal = ((HWREG(baseAddr + ELM_IRQSTATUS) & - ELM_IRQSTATUS_LOC_VALID_7) >> - ELM_IRQSTATUS_LOC_VALID_7_SHIFT ); - break; - case ELM_PAGE_VALID_STATUS: - retVal = ((HWREG(baseAddr + ELM_IRQSTATUS) & - ELM_IRQSTATUS_PAGE_VALID) >> - ELM_IRQSTATUS_PAGE_VALID_SHIFT ); - break; - } - - return (retVal); -} - -/** -* \brief This function clears the interrupt.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \param flag Flag for which interrupt status has to clear.\n -* This can take one of the following values :\n -* ELM_LOC_VALID_0_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_1_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_2_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_3_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_4_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_5_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_6_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_7_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_PAGE_VALID_STATUS : Error-location -* interrupt for a full -* page.\n -* -* \return None. \n -* -*/ -void ELMIntStatusClear(unsigned int baseAddr, unsigned int flag) -{ - switch(flag) - { - case ELM_LOC_VALID_0_STATUS: - HWREG(baseAddr + ELM_IRQSTATUS) |= ELM_IRQSTATUS_LOC_VALID_0; - break; - case ELM_LOC_VALID_1_STATUS: - HWREG(baseAddr + ELM_IRQSTATUS) |= ELM_IRQSTATUS_LOC_VALID_1; - break; - case ELM_LOC_VALID_2_STATUS: - HWREG(baseAddr + ELM_IRQSTATUS) |= ELM_IRQSTATUS_LOC_VALID_2; - break; - case ELM_LOC_VALID_3_STATUS: - HWREG(baseAddr + ELM_IRQSTATUS) |= ELM_IRQSTATUS_LOC_VALID_3; - break; - case ELM_LOC_VALID_4_STATUS: - HWREG(baseAddr + ELM_IRQSTATUS) |= ELM_IRQSTATUS_LOC_VALID_4; - break; - case ELM_LOC_VALID_5_STATUS: - HWREG(baseAddr + ELM_IRQSTATUS) |= ELM_IRQSTATUS_LOC_VALID_5; - break; - case ELM_LOC_VALID_6_STATUS: - HWREG(baseAddr + ELM_IRQSTATUS) |= ELM_IRQSTATUS_LOC_VALID_6; - break; - case ELM_LOC_VALID_7_STATUS: - HWREG(baseAddr + ELM_IRQSTATUS) |= ELM_IRQSTATUS_LOC_VALID_7; - break; - case ELM_PAGE_VALID_STATUS: - HWREG(baseAddr + ELM_IRQSTATUS) |= ELM_IRQSTATUS_PAGE_VALID; - break; - - } -} - -/** -* \brief This function configs i.e enables or disable the interrupts.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \param intflag intFlag for which interrupt has to config.\n -* This can take one of the following values :\n -* ELM_LOC_VALID_0_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_1_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_2_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_3_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_4_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_5_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_6_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_LOC_VALID_7_STATUS : Error-location -* interrupt for syndrome -* polynomial 0.\n -* ELM_PAGE_VALID_STATUS : Error-location -* interrupt for a full -* page. \n -* -* \param configVal Config Value.\n -* This can take one of the following values :\n -* ELM_INT_ENALBLE : To enble the interrupt\n -* ELM_INT_DISALBLE : To disable the -* interrupt.\n -* \return None. \n -* -*/ -void ELMIntConfig(unsigned int baseAddr, unsigned int intFlag, - unsigned int configVal) -{ - switch(intFlag) - { - case ELM_LOC_VALID_0_STATUS: - if(configVal == ELM_INT_ENALBLE) - { - HWREG(baseAddr + ELM_IRQENABLE) |= - ELM_IRQENABLE_LOCATION_MASK_0; - } - else - { - HWREG(baseAddr + ELM_IRQENABLE) &= - ~ELM_IRQENABLE_LOCATION_MASK_0; - } - break; - case ELM_LOC_VALID_1_STATUS: - if(configVal == ELM_INT_ENALBLE) - { - HWREG(baseAddr + ELM_IRQENABLE) |= - ELM_IRQENABLE_LOCATION_MASK_1; - } - else - { - HWREG(baseAddr + ELM_IRQENABLE) &= - ~ELM_IRQENABLE_LOCATION_MASK_1; - } - break; - case ELM_LOC_VALID_2_STATUS: - if(configVal == ELM_INT_ENALBLE) - { - HWREG(baseAddr + ELM_IRQENABLE) |= - ELM_IRQENABLE_LOCATION_MASK_2; - } - else - { - HWREG(baseAddr + ELM_IRQENABLE) &= - ~ELM_IRQENABLE_LOCATION_MASK_2; - } - break; - case ELM_LOC_VALID_3_STATUS: - if(configVal == ELM_INT_ENALBLE) - { - HWREG(baseAddr + ELM_IRQENABLE) |= - ELM_IRQENABLE_LOCATION_MASK_3; - } - else - { - HWREG(baseAddr + ELM_IRQENABLE) &= - ~ELM_IRQENABLE_LOCATION_MASK_3; - } - break; - case ELM_LOC_VALID_4_STATUS: - if(configVal == ELM_INT_ENALBLE) - { - HWREG(baseAddr + ELM_IRQENABLE) |= - ELM_IRQENABLE_LOCATION_MASK_4; - } - else - { - HWREG(baseAddr + ELM_IRQENABLE) &= - ~ELM_IRQENABLE_LOCATION_MASK_4; - } - break; - case ELM_LOC_VALID_5_STATUS: - if(configVal == ELM_INT_ENALBLE) - { - HWREG(baseAddr + ELM_IRQENABLE) |= - ELM_IRQENABLE_LOCATION_MASK_5; - } - else - { - HWREG(baseAddr + ELM_IRQENABLE) &= - ~ELM_IRQENABLE_LOCATION_MASK_5; - } - break; - case ELM_LOC_VALID_6_STATUS: - if(configVal == ELM_INT_ENALBLE) - { - HWREG(baseAddr + ELM_IRQENABLE) |= - ELM_IRQENABLE_LOCATION_MASK_6; - } - else - { - HWREG(baseAddr + ELM_IRQENABLE) &= - ~ELM_IRQENABLE_LOCATION_MASK_6; - } - break; - case ELM_LOC_VALID_7_STATUS: - if(configVal == ELM_INT_ENALBLE) - { - HWREG(baseAddr + ELM_IRQENABLE) |= - ELM_IRQENABLE_LOCATION_MASK_7; - } - else - { - HWREG(baseAddr + ELM_IRQENABLE) &= - ~ELM_IRQENABLE_LOCATION_MASK_7; - } - break; - case ELM_PAGE_VALID_STATUS: - if(configVal == ELM_INT_ENALBLE) - { - HWREG(baseAddr + ELM_IRQENABLE) |= ELM_IRQENABLE_PAGE_MASK; - } - else - { - HWREG(baseAddr + ELM_IRQENABLE) &= ~ELM_IRQENABLE_PAGE_MASK; - } - break; - } - -} - -/** -* \brief This function sets the Error correction level for BCH alogorithm.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \param bchECCLevel BCH error correction level.\n -* This can take one of the following values :\n -* ELM_ECC_BCH_LEVEL_16BITS : For Upto 16 bits error -* correction.\n -* ELM_ECC_BCH_LEVEL_8BITS : For Upto 8 bits error -* correction.\n -* ELM_ECC_BCH_LEVEL_4BITS : For Upto 4 bits error -* correction.\n -* -* \return None. \n -* -*/ -void ELMErrCorrectionLevelSet(unsigned int baseAddr, unsigned int bchECCLevel) -{ - HWREG(baseAddr + ELM_LOCATION_CONFIG) |= ( bchECCLevel << - ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_SHIFT); - -} - -/** -* \brief This function sets the size of the buffers for which -* the error-location engine is used.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \param eccSize eccSize in number of nibbles (i.e 4-bits entities).\n -* -* \return None. \n -* -*/ -void ELMECCSizeSet(unsigned int baseAddr, unsigned int eccSize) -{ - HWREG(baseAddr + ELM_LOCATION_CONFIG) |= ( eccSize << - ELM_LOCATION_CONFIG_ECC_SIZE_SHIFT); -} - -/** -* \brief This function sets mode of the ELM module.\n -* -* \param mode mode of the ELM.\n -* This can take one of the following values :\n -* ELM_MODE_PAGE -- For page mode.\n -* ELM_MODE_CONTINUOUS -- For continuous mode.\n -* -* \param sectorNum Sector number or syndrome polynomial number which has -* to select as part of the page in page mode.\n -* This can take one of the following values :\n -* ELM_PAGEMODE_SECTOR_0 -- For selecting syndrome -* polynomial 0 as part of the -* page in page mode.\n -* ELM_PAGEMODE_SECTOR_1 -- For selecting syndrome -* polynomial 1 as part of the -* page in page mode.\n -* ELM_PAGEMODE_SECTOR_2 -- For selecting syndrome -* polynomial 2 as part of the -* page in page mode.\n -* ELM_PAGEMODE_SECTOR_3 -- For selecting syndrome -* polynomial 3 as part of the -* page in page mode.\n -* ELM_PAGEMODE_SECTOR_4 -- For selecting syndrome -* polynomial 4 as part of the -* page in page mode.\n -* ELM_PAGEMODE_SECTOR_5 -- For selecting syndrome -* polynomial 5 as part of the -* page in page mode.\n -* ELM_PAGEMODE_SECTOR_6 -- For selecting syndrome -* polynomial 6 as part of the -* page in page mode.\n -* ELM_PAGEMODE_SECTOR_7 -- For selecting syndrome -* polynomial 7 as part of the -* page in page mode.\n - -* \return None. \n -* -*/ -void ELMModeSet(unsigned int baseAddr, unsigned int mode, - unsigned int sectorNum) -{ - if(mode == ELM_MODE_CONTINUOUS) - { - HWREG(baseAddr + ELM_PAGE_CTRL) = ( mode ); - } - else - { - HWREG(baseAddr + ELM_PAGE_CTRL) = ( mode << sectorNum ); - } -} - - -/** -* \brief This function sets the fragments of syndrome polynomial for -* error-location processing.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \param synFrgmtId Syndrome fragment ID.\n -* This can take one of the following values :\n -* ELM_SYNDROME_FRGMT_0 - For syndrome fragment 0.\n -* ELM_SYNDROME_FRGMT_1 - For syndrome fragment 1.\n -* ELM_SYNDROME_FRGMT_2 - For syndrome fragment 2.\n -* ELM_SYNDROME_FRGMT_3 - For syndrome fragment 3.\n -* ELM_SYNDROME_FRGMT_4 - For syndrome fragment 4.\n -* ELM_SYNDROME_FRGMT_5 - For syndrome fragment 5.\n -* ELM_SYNDROME_FRGMT_6 - For syndrome fragment 6.\n -* \param synFrgmtVal Syndrome fragment value.\n -* -* \return None. \n -* -*/ -void ELMSyndromeFrgmtSet(unsigned int baseAddr, unsigned int synFrgmtId, - unsigned int synFrgmtVal) -{ - if(synFrgmtId != ELM_SYNDROME_FRGMT_6) - { - HWREG(baseAddr + ELM_SYNDROME_FRAGMENT(synFrgmtId)) = ( synFrgmtVal ); - } - else - { - HWREG(baseAddr + ELM_SYNDROME_FRAGMENT(synFrgmtId)) = - ( synFrgmtVal & ELM_SYNDROME_FRAGMENT_6_SYNDROME_6 ); - } -} - -/** -* \brief This function starts the error-location processing for the polynomial -* set in the syndrome fragment registers.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \return None. \n -* -*/ -void ELMErrLocProcessingStart(unsigned int baseAddr) -{ - HWREG(baseAddr + ELM_SYNDROME_FRAGMENT(ELM_SYNDROME_FRGMT_6)) = - ( ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID ); -} - -/** -* \brief This function gets the error-location processing status.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \return status. \n -* 0 : ECC error-location process failed.\n -* 1 : ECC error-location process passed.\n -* -*/ -unsigned int ELMErrLocProcessingStatusGet(unsigned int baseAddr) -{ - unsigned int status; - - status = ((HWREG(baseAddr + ELM_LOCATION_STATUS) & - ELM_LOCATION_STATUS_ECC_CORRECTABLE) >> - ELM_LOCATION_STATUS_ECC_CORRECTABLE_SHIFT); - - return (status); -} - -/** -* \brief This function gets the number of errors detected and located -* during error-location processing.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \return Number of errors detected and located.\n -* -*/ -unsigned int ELMNumOfErrsGet(unsigned int baseAddr) -{ - unsigned int numOfErrs; - - numOfErrs = (HWREG(baseAddr + ELM_LOCATION_STATUS) & - ELM_LOCATION_STATUS_ECC_NB_ERRORS); - - return (numOfErrs); -} - -/** -* \brief This function gets the Error-location bit address for the error -* number passed.\n -* -* \param baseAddr Memory address of ELM.\n -* -* \param errNum Error number.\n -* This can take one of the following values :\n -* ELM_ERROR_NUM_0 - For 0th error.\n -* ELM_ERROR_NUM_1 - For 1th error.\n -* ELM_ERROR_NUM_2 - For 2th error.\n -* ELM_ERROR_NUM_3 - For 3th error.\n -* ELM_ERROR_NUM_4 - For 4th error.\n -* ELM_ERROR_NUM_5 - For 5th error.\n -* ELM_ERROR_NUM_6 - For 6th error.\n -* ELM_ERROR_NUM_7 - For 7th error.\n -* ELM_ERROR_NUM_8 - For 8th error.\n -* ELM_ERROR_NUM_9 - For 9th error.\n -* ELM_ERROR_NUM_10 - For 10th error.\n -* ELM_ERROR_NUM_11 - For 11th error.\n -* ELM_ERROR_NUM_12 - For 12th error.\n -* ELM_ERROR_NUM_13 - For 13th error.\n -* ELM_ERROR_NUM_14 - For 14th error.\n -* ELM_ERROR_NUM_15 - For 15th error.\n -* -* \return Bit address for the error number.\n -* -*/ -unsigned int ELMErrLocBitAddrGet(unsigned int baseAddr, unsigned int errNum) -{ - unsigned int bitAddr; - - bitAddr = (HWREG(baseAddr + ELM_ERROR_LOCATION(errNum)) & - ELM_ERROR_LOCATION_0_ECC_ERROR_LOCATION); - - return (bitAddr); -} -/***************************** End Of File ***********************************/ diff --git a/lib/tiam1808/drivers/emac.c b/lib/tiam1808/drivers/emac.c deleted file mode 100644 index 97a1919eb..000000000 --- a/lib/tiam1808/drivers/emac.c +++ /dev/null @@ -1,494 +0,0 @@ -/** - * \file emac.c - * - * \brief EMAC APIs. - * - * This file contains the device abstraction layer APIs for EMAC. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -/* HW Macros and Peripheral Defines */ -#include "hw_types.h" -#include "hw_emac.h" -#include "hw_emac_ctrl.h" - -/* Driver APIs */ -#include "emac.h" - -/******************************************************************************* -* INTERNAL MACRO DEFINITIONS -*******************************************************************************/ -#define EMAC_CONTROL_RESET (0x01u) -#define EMAC_SOFT_RESET (0x01u) -#define EMAC_MAX_HEADER_DESC (8u) -#define EMAC_UNICAST_DISABLE (0xFFu) - -/******************************************************************************* -* API FUNCTION DEFINITIONS -*******************************************************************************/ -/** - * \brief Enables the TXPULSE Interrupt Generation. - * - * \param emacBase Base address of the EMAC Module registers. - * \param emacCtrlBase Base address of the EMAC CONTROL module registers - * \param ctrlCore Control core for which the interrupt to be enabled. - * \param channel Channel number for which interrupt to be enabled - * - * \return None - * - **/ -void EMACTxIntPulseEnable(unsigned int emacBase, unsigned int emacCtrlBase, - unsigned int ctrlCore, unsigned int channel) -{ - HWREG(emacBase + EMAC_TXINTMASKSET) |= (1 << channel); - - HWREG(emacCtrlBase + EMAC_CTRL_CnTXEN(ctrlCore)) |= (1 << channel); -} - -/** - * \brief Disables the TXPULSE Interrupt Generation. - * - * \param emacBase Base address of the EMAC Module registers. - * \param emacCtrlBase Base address of the EMAC CONTROL module registers - * \param ctrlCore Control core for which the interrupt to be disabled. - * \param channel Channel number for which interrupt to be disabled - * - * \return None - * - **/ -void EMACTxIntPulseDisable(unsigned int emacBase, unsigned int emacCtrlBase, - unsigned int ctrlCore, unsigned int channel) -{ - HWREG(emacBase + EMAC_TXINTMASKCLEAR) |= (1 << channel); - - HWREG(emacCtrlBase + EMAC_CTRL_CnTXEN(ctrlCore)) &= ~(1 << channel); -} - -/** - * \brief Enables the RXPULSE Interrupt Generation. - * - * \param emacBase Base address of the EMAC Module registers. - * \param emacCtrlBase Base address of the EMAC CONTROL module registers - * \param ctrlCore Control core for which the interrupt to be enabled. - * \param channel Channel number for which interrupt to be enabled - * - * \return None - * - **/ -void EMACRxIntPulseEnable(unsigned int emacBase, unsigned int emacCtrlBase, - unsigned int ctrlCore, unsigned int channel) -{ - HWREG(emacBase + EMAC_RXINTMASKSET) |= (1 << channel); - - HWREG(emacCtrlBase + EMAC_CTRL_CnRXEN(ctrlCore)) |= (1 << channel); -} - -/** - * \brief Disables the RXPULSE Interrupt Generation. - * - * \param emacBase Base address of the EMAC Module registers. - * \param emacCtrlBase Base address of the EMAC CONTROL module registers - * \param ctrlCore Control core for which the interrupt to be disabled. - * \param channel Channel number for which interrupt to be disabled - * - * \return None - * - **/ -void EMACRxIntPulseDisable(unsigned int emacBase, unsigned int emacCtrlBase, - unsigned int ctrlCore, unsigned int channel) -{ - HWREG(emacBase + EMAC_RXINTMASKCLEAR) |= (1 << channel); - - HWREG(emacCtrlBase + EMAC_CTRL_CnRXEN(ctrlCore)) &= ~(1 << channel); -} -/** - * \brief This API sets the RMII speed. The RMII Speed can be 10 Mbps or - * 100 Mbps - * - * \param emacBase Base address of the EMAC Module registers. - * \param speed speed for setting. - * speed can take the following values. \n - * EMAC_RMIISPEED_10MBPS - 10 Mbps \n - * EMAC_RMIISPEED_100MBPS - 100 Mbps. - * - * \return None - * - **/ -void EMACRMIISpeedSet(unsigned int emacBase, unsigned int speed) -{ - HWREG(emacBase + EMAC_MACCONTROL) &= ~EMAC_MACCONTROL_RMIISPEED; - - HWREG(emacBase + EMAC_MACCONTROL) |= speed; -} - -/** - * \brief This API enables the MII control block - * - * \param emacBase Base address of the EMAC Module registers. - * - * \return None - * - **/ -void EMACMIIEnable(unsigned int emacBase) -{ - HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_GMIIEN; -} - -/** - * \brief This API sets the duplex mode of operation(full/half) for MAC. - * - * \param emacBase Base address of the EMAC Module registers. - * \param duplexMode duplex mode of operation. - * duplexMode can take the following values. \n - * EMAC_DUPLEX_FULL - Full Duplex \n - * EMAC_DUPLEX_HALF - Half Duplex. - * - * \return None - * - **/ -void EMACDuplexSet(unsigned int emacBase, unsigned int duplexMode) -{ - HWREG(emacBase + EMAC_MACCONTROL) &= ~EMAC_MACCONTROL_FULLDUPLEX; - - HWREG(emacBase + EMAC_MACCONTROL) |= duplexMode; -} - -/** - * \brief API to enable the transmit in the TX Control Register - * After the transmit is enabled, any write to TXHDP of - * a channel will start transmission - * - * \param emacBase Base Address of the EMAC Module Registers. - * - * \return None - * - **/ -void EMACTxEnable(unsigned int emacBase) -{ - HWREG(emacBase + EMAC_TXCONTROL) = EMAC_TXCONTROL_TXEN; -} - -/** - * \brief API to enable the receive in the RX Control Register - * After the transmit is enabled, and write to RXHDP of - * a channel, the data can be received in the destination - * specified by the corresponding RX buffer descriptor. - * - * \param emacBase Base Address of the EMAC Module Registers. - * - * \return None - * - **/ -void EMACRxEnable(unsigned int emacBase) -{ - HWREG(emacBase + EMAC_RXCONTROL) = EMAC_RXCONTROL_RXEN; -} - -/** - * \brief API to write the TX HDP register. If transmit is enabled, - * write to the TX HDP will immediately start transmission. - * The data will be taken from the buffer pointer of the TX buffer - * descriptor written to the TX HDP - * - * \param emacBase Base Address of the EMAC Module Registers.\n - * \param descHdr Address of the TX buffer descriptor - * \param channel Channel Number - * - * \return None - * - **/ -void EMACTxHdrDescPtrWrite(unsigned int emacBase, unsigned int descHdr, - unsigned int channel) -{ - HWREG(emacBase + EMAC_TXHDP(channel)) = descHdr; -} - -/** - * \brief API to write the RX HDP register. If receive is enabled, - * write to the RX HDP will enable data reception to point to - * the corresponding RX buffer descriptor's buffer pointer. - * - * \param emacBase Base Address of the EMAC Module Registers.\n - * \param descHdr Address of the RX buffer descriptor - * \param channel Channel Number - * - * \return None - * - **/ -void EMACRxHdrDescPtrWrite(unsigned int emacBase, unsigned int descHdr, - unsigned int channel) -{ - HWREG(emacBase + EMAC_RXHDP(channel)) = descHdr; -} - -/** - * \brief This API Initializes the EMAC and EMAC Control modules. The - * EMAC Control module is reset, the CPPI RAM is cleared. also, - * all the interrupts are disabled. This API doesnot enable any - * interrupt or operation of the EMAC. - * - * \param emacCtrlBase Base Address of the EMAC Control module - * registers.\n - * \param emacBase Base address of the EMAC module registers - * - * \return None - * - **/ -void EMACInit(unsigned int emacCtrlBase, unsigned int emacBase) -{ - unsigned int cnt; - - /* Reset the EMAC Control Module. This clears the CPPI RAM also */ - HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) = EMAC_CONTROL_RESET; - - while(HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) & EMAC_CONTROL_RESET); - - /* Reset the EMAC Control Module. This clears the CPPI RAM also */ - HWREG(emacBase + EMAC_SOFTRESET) = EMAC_SOFT_RESET; - - while(HWREG(emacBase + EMAC_SOFTRESET) & EMAC_SOFT_RESET); - - HWREG(emacBase + EMAC_MACCONTROL)= 0; - HWREG(emacBase + EMAC_RXCONTROL)= 0; - HWREG(emacBase + EMAC_TXCONTROL)= 0; - - /* Initialize all the header descriptor pointer registers */ - for(cnt = 0; cnt< EMAC_MAX_HEADER_DESC; cnt++) - { - HWREG(emacBase + EMAC_RXHDP(cnt)) = 0; - HWREG(emacBase + EMAC_TXHDP(cnt)) = 0; - HWREG(emacBase + EMAC_RXCP(cnt)) = 0; - HWREG(emacBase + EMAC_TXCP(cnt)) = 0; - HWREG(emacBase + EMAC_RXFREEBUFFER(cnt)) = 0xFF; - } - /* Clear the interrupt enable for all the channels */ - HWREG(emacBase + EMAC_TXINTMASKCLEAR) = 0xFF; - HWREG(emacBase + EMAC_RXINTMASKCLEAR) = 0xFF; - - HWREG(emacBase + EMAC_MACHASH1) = 0; - HWREG(emacBase + EMAC_MACHASH2) = 0; - - HWREG(emacBase + EMAC_RXBUFFEROFFSET) = 0; -} - -/** - * \brief Sets the MAC Address in MACSRCADDR registers. - * - * \param emacBase Base Address of the EMAC module registers. - * \param macAddr Start address of a MAC address array. - * The array[0] shall be the LSB of the MAC address - * - * \return None - * - **/ -void EMACMACSrcAddrSet(unsigned int emacBase, unsigned char *macAddr) -{ - HWREG(emacBase + EMAC_MACSRCADDRHI) = macAddr[5] |(macAddr[4] << 8) - |(macAddr[3] << 16) |(macAddr[2] << 24); - HWREG(emacBase + EMAC_MACSRCADDRLO) = macAddr[1] | (macAddr[0] << 8); -} - -/** - * \brief Sets the MAC Address in MACADDR registers. - * - * \param emacBase Base Address of the EMAC module registers. - * \param channel Channel Number - * \param matchFilt Match or Filter - * \param macAddr Start address of a MAC address array. - * The array[0] shall be the LSB of the MAC address - * matchFilt can take the following values \n - * EMAC_MACADDR_NO_MATCH_NO_FILTER - Address is not used to match - * or filter incoming packet. \n - * EMAC_MACADDR_FILTER - Address is used to filter incoming packets \n - * EMAC_MACADDR_MATCH - Address is used to match incoming packets \n - * - * \return None - * - **/ -void EMACMACAddrSet(unsigned int emacBase, unsigned int channel, - unsigned char *macAddr, unsigned int matchFilt) -{ - HWREG(emacBase + EMAC_MACINDEX) = channel; - - HWREG(emacBase + EMAC_MACADDRHI) = macAddr[5] |(macAddr[4] << 8) - |(macAddr[3] << 16) |(macAddr[2] << 24); - HWREG(emacBase + EMAC_MACADDRLO) = macAddr[1] | (macAddr[0] << 8) - | matchFilt | (channel << 16); -} - -/** - * \brief Acknowledges an interrupt processed to the EMAC Control Core. - * - * \param emacBase Base Address of the EMAC module registers. - * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control - * module. - * eoiFlag can take the following values \n - * EMAC_INT_CORE0_TX - Core 0 TX Interrupt - * EMAC_INT_CORE1_TX - Core 1 TX Interrupt - * EMAC_INT_CORE2_TX - Core 2 TX Interrupt - * EMAC_INT_CORE0_RX - Core 0 RX Interrupt - * EMAC_INT_CORE1_RX - Core 1 RX Interrupt - * EMAC_INT_CORE2_RX - Core 2 RX Interrupt - * \return None - * - **/ -void EMACCoreIntAck(unsigned int emacBase, unsigned int eoiFlag) -{ - /* Acknowledge the EMAC Control Core */ - HWREG(emacBase + EMAC_MACEOIVECTOR) = eoiFlag; -} - -/** - * \brief Writes the the TX Completion Pointer for a specific channel - * - * \param emacBase Base Address of the EMAC module registers. - * \param channel Channel Number. - * \param comPtr Completion Pointer Value to be written - * - * \return None - * - **/ -void EMACTxCPWrite(unsigned int emacBase, unsigned int channel, unsigned int comPtr) -{ - HWREG(emacBase + EMAC_TXCP(channel)) = comPtr; -} - -/** - * \brief Writes the the RX Completion Pointer for a specific channel - * - * \param emacBase Base Address of the EMAC module registers. - * \param channel Channel Number. - * \param comPtr Completion Pointer Value to be written - * - * \return None - * - **/ -void EMACRxCPWrite(unsigned int emacBase, unsigned int channel, unsigned int comPtr) -{ - HWREG(emacBase + EMAC_RXCP(channel)) = comPtr; -} - -/** - * \brief Acknowledges an interrupt processed to the EMAC module. After - * processing an interrupt, the last processed buffer descriptor is - * written to the completion pointer. Also this API acknowledges - * the EMAC Control Module that the RX interrupt is processed for - * a specified core - * - * \param emacBase Base Address of the EMAC module registers. - * \param channel Channel Number - * \param comPtr Completion Pointer value. This shall be the buffer - * descriptor address last processed. - * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control - module. - * eoiFlag can take the following values \n - * EMAC_INT_CORE0_RX - Core 0 RX Interrupt - * EMAC_INT_CORE1_RX - Core 1 RX Interrupt - * EMAC_INT_CORE2_RX - Core 2 RX Interrupt - * \return None - * - **/ -void EMACRxIntAckToClear(unsigned int emacBase, unsigned int channel, - unsigned int comPtr, unsigned eoiFlag) -{ - HWREG(emacBase + EMAC_RXCP(channel)) = comPtr; - - /* Acknowledge the EMAC Control Core */ - HWREG(emacBase + EMAC_MACEOIVECTOR) = eoiFlag; -} - -/** - * \brief Enables a specific channel to receive broadcast frames - * - * \param emacBase Base Address of the EMAC module registers. - * \param channel Channel Number. - * - * \return None - * - **/ -void EMACRxBroadCastEnable(unsigned int emacBase, unsigned int channel) -{ - HWREG(emacBase + EMAC_RXMBPENABLE) &= ~EMAC_RXMBPENABLE_RXBROADCH; - - HWREG(emacBase + EMAC_RXMBPENABLE) |= - EMAC_RXMBPENABLE_RXBROADEN | - (channel << EMAC_RXMBPENABLE_RXBROADCH_SHIFT); -} - -/** - * \brief Enables unicast for a specific channel - * - * \param emacBase Base Address of the EMAC module registers. - * \param channel Channel Number. - * - * \return None - * - **/ -void EMACRxUnicastSet(unsigned int emacBase, unsigned int channel) -{ - HWREG(emacBase + EMAC_RXUNICASTSET) |= (1 << channel); -} - -/** - * \brief Set the free buffers for a specific channel - * - * \param emacBase Base Address of the EMAC module registers. - * \param channel Channel Number. - * \param nBuf Number of free buffers - * - * \return None - * - **/ -void EMACNumFreeBufSet(unsigned int emacBase, unsigned int channel, - unsigned int nBuf) -{ - HWREG(emacBase + EMAC_RXFREEBUFFER(channel)) = nBuf; -} - -/** - * \brief Gets the interrupt vectors of EMAC, which are pending - * - * \param emacBase Base Address of the EMAC module registers. - * - * \return Vectors - * - **/ -unsigned int EMACIntVectorGet(unsigned int emacBase) -{ - return (HWREG(emacBase + EMAC_MACINVECTOR)); -} - -/***************************** End Of File ***********************************/ diff --git a/lib/tiam1808/drivers/hs_mmcsd.c b/lib/tiam1808/drivers/hs_mmcsd.c index 959d48e94..c2a2a3edb 100644 --- a/lib/tiam1808/drivers/hs_mmcsd.c +++ b/lib/tiam1808/drivers/hs_mmcsd.c @@ -41,7 +41,7 @@ */ -#include "soc_AM335x.h" +#include "soc_AM1808.h" #include "hw_types.h" #include "hs_mmcsd.h" #include "hw_hs_mmcsd.h" @@ -154,7 +154,7 @@ void HSMMCSDSystemConfig(unsigned int baseAddr, unsigned int config) * \param baseAddr Base Address of the MMC/SD controller Registers. * \param width SD/MMC bus width * - * width can take the values \n + * width can take the values \n * HS_MMCSD_BUS_WIDTH_8BIT \n * HS_MMCSD_BUS_WIDTH_4BIT \n * HS_MMCSD_BUS_WIDTH_1BIT \n @@ -166,13 +166,13 @@ void HSMMCSDBusWidthSet(unsigned int baseAddr, unsigned int width) { switch (width) { - case HS_MMCSD_BUS_WIDTH_8BIT: + case HS_MMCSD_BUS_WIDTH_8BIT: HWREG(baseAddr + MMCHS_CON) |= MMCHS_CON_DW8; break; case HS_MMCSD_BUS_WIDTH_4BIT: HWREG(baseAddr + MMCHS_CON) &= ~MMCHS_CON_DW8; - HWREG(baseAddr + MMCHS_HCTL) |= + HWREG(baseAddr + MMCHS_HCTL) |= (MMCHS_HCTL_DTW_4_BITMODE << MMCHS_HCTL_DTW_SHIFT); break; @@ -191,7 +191,7 @@ void HSMMCSDBusWidthSet(unsigned int baseAddr, unsigned int width) * \param baseAddr Base Address of the MMC/SD controller Registers. * \param volt SD/MMC bus voltage * - * volt can take the values \n + * volt can take the values \n * HS_MMCSD_BUS_VOLT_1P8 \n * HS_MMCSD_BUS_VOLT_3P0 \n * HS_MMCSD_BUS_VOLT_3P3 \n @@ -311,7 +311,7 @@ unsigned int HSMMCSDIsIntClockStable(unsigned int baseAddr, unsigned int retry) * \param baseAddr Base Address of the MMC/SD controller Registers. * \param volt Supported bus voltage * - * volt can take the values (or a combination of)\n + * volt can take the values (or a combination of)\n * HS_MMCSD_SUPPORT_VOLT_1P8 \n * HS_MMCSD_SUPPORT_VOLT_3P0 \n * HS_MMCSD_SUPPORT_VOLT_3P3 \n @@ -359,7 +359,7 @@ void HSMMCSDDataTimeoutSet(unsigned int baseAddr, unsigned int timeout) { HWREG(baseAddr + MMCHS_SYSCTL) &= ~(MMCHS_SYSCTL_DTO); HWREG(baseAddr + MMCHS_SYSCTL) |= timeout; -} +} /** * \brief Set output bus frequency @@ -414,13 +414,13 @@ int HSMMCSDBusFreqSet(unsigned int baseAddr, unsigned int freq_in, { return -1; } - + /* Enable clock to the card */ HWREG(baseAddr + MMCHS_SYSCTL) |= MMCHS_SYSCTL_CEN; } return 0; -} +} /** * \brief Sends INIT stream to the card @@ -510,7 +510,7 @@ void HSMMCSDIntrEnable(unsigned int baseAddr, unsigned int flag) } /** - * \brief Gets the status bits from the controller + * \brief Gets the status bits from the controller * * \param baseAddr Base Address of the MMC/SD controller Registers. * \param flag Specific status required; @@ -527,7 +527,7 @@ unsigned int HSMMCSDIntrStatusGet(unsigned int baseAddr, unsigned int flag) } /** - * \brief Clear the status bits from the controller + * \brief Clear the status bits from the controller * * \param baseAddr Base Address of the MMC/SD controller Registers. * \param flag Specific status required; @@ -598,7 +598,7 @@ unsigned int HSMMCSDIsXferComplete(unsigned int baseAddr, unsigned int retry) * * \param baseAddr Base Address of the MMC/SD controller Registers * \param blklen Command to be passed to the controller/card - * + * * \note: blklen should be within the limits specified by the controller/card * * \return none diff --git a/lib/tiam1808/drivers/lan8710a.c b/lib/tiam1808/drivers/lan8710a.c deleted file mode 100644 index 02627e4d5..000000000 --- a/lib/tiam1808/drivers/lan8710a.c +++ /dev/null @@ -1,366 +0,0 @@ -/** - * \file lan8710a.c - * - * \brief APIs for configuring LAN8710A. - * - * This file contains the device abstraction APIs for PHY LAN8270A. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -/* HW Macros */ -#include "hw_types.h" - -/* Driver APIs */ -#include "mdio.h" -#include "lan8710a.h" - -/******************************************************************************* -* API FUNCTION DEFINITIONS -*******************************************************************************/ -/** - * \brief Reads the PHY ID. - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * - * \return 32 bit PHY ID (ID1:ID2) - * - **/ -unsigned int Lan8710aIDGet(unsigned int mdioBaseAddr, unsigned int phyAddr) -{ - unsigned int id = 0; - unsigned short data; - - /* read the ID1 register */ - MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_ID1, &data); - - /* update the ID1 value */ - id = data << PHY_ID_SHIFT; - - /* read the ID2 register */ - MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_ID2, &data); - - /* update the ID2 value */ - id |= data; - - /* return the ID in ID1:ID2 format */ - return id; -} - -/** - * \brief Reads a register from the the PHY - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * \param regIdx Index of the register to be read - * \param regValAdr address where value of the register will be written - * - * \return status of the read - * - **/ -unsigned int Lan8710aRegRead(unsigned int mdioBaseAddr, unsigned int phyAddr, - unsigned int regIdx, unsigned short *regValAdr) -{ - return (MDIOPhyRegRead(mdioBaseAddr, phyAddr, regIdx, regValAdr)); -} - -/** - * \brief Writes a register with the input - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * \param regIdx Index of the register to be read - * \param regValAdr value to be written - * - * \return None - * - **/ -void Lan8710aRegWrite(unsigned int mdioBaseAddr, unsigned int phyAddr, - unsigned int regIdx, unsigned short regVal) -{ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, regIdx, regVal); -} - -/** - * \brief Resets the PHY - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * - * \return None - * - **/ -void Lan8710aReset(unsigned int mdioBaseAddr, unsigned int phyAddr) -{ - /* Reset the phy */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, PHY_SOFTRESET); -} - -/** - * \brief Enables Loop Back mode - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * - * \return status after enabling. \n - * TRUE if loop back is enabled \n - * FALSE if not able to enable - * - **/ -unsigned int Lan8710aLoopBackEnable(unsigned int mdioBaseAddr, unsigned int phyAddr) -{ - unsigned short data; - - if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE ) - { - return FALSE; - } - - data |= PHY_LPBK_ENABLE; - - /* Enable loop back */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data); - - return TRUE; -} - -/** - * \brief Disables Loop Back mode - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * - * \return status after enabling. \n - * TRUE if loop back is disabled \n - * FALSE if not able to disable - * - **/ -unsigned int Lan8710aLoopBackDisable(unsigned int mdioBaseAddr, unsigned int phyAddr) -{ - unsigned short data; - - if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE ) - { - return FALSE; - } - - data &= ~(PHY_LPBK_ENABLE); - - /* Disable loop back */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data); - - return TRUE; -} - -/** - * \brief Configures the PHY for a given speed and duplex mode. This - * API will first reset the PHY. Then it sets the desired speed - * and duplex mode for the PHY. - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * \param speed Speed to be enabled - * \param duplexMode Duplex Mode - * - * \return status after configuring \n - * TRUE if configuration successful - * FALSE if configuration failed - * - **/ -unsigned int Lan8710aConfigure(unsigned int mdioBaseAddr, unsigned int phyAddr, - unsigned short speed, unsigned short duplexMode) -{ - unsigned short data; - - data = PHY_SOFTRESET; - - /* Reset the phy */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data); - - /* wait till the reset bit is auto cleared */ - while(data) - { - /* Read the reset */ - if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE) - { - return FALSE; - } - } - - /* Set the configurations */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, (speed | duplexMode)); - - return TRUE; -} - -/** - * \brief This function does Autonegotiates with the EMAC device connected - * to the PHY. It will wait till the autonegotiation completes. - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * \param advVal Autonegotiation advertisement value - * advVal can take the following any OR combination of the values \n - * LAN8710A_100BTX - 100BaseTX - * LAN8710A_100BTX_FD - Full duplex capabilty for 100BaseTX - * LAN8710A_10BT - 10BaseT - * LAN8710A_10BT_FD - Full duplex capability for 10BaseT - * - * \return status after autonegotiation \n - * TRUE if autonegotiation successful - * FALSE if autonegotiation failed - * - **/ -unsigned int Lan8710aAutoNegotiate(unsigned int mdioBaseAddr, - unsigned int phyAddr, unsigned short advVal) -{ - volatile unsigned short data, anar; - - if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE ) - { - return FALSE; - } - - data |= PHY_AUTONEG_ENABLE; - - /* Enable Auto Negotiation */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data); - - if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE ) - { - return FALSE; - } - - /* Write Auto Negotiation capabilities */ - MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_AUTONEG_ADV, &anar); - anar &= ~0xff10; - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_AUTONEG_ADV, (anar |advVal)); - - data |= PHY_AUTONEG_RESTART; - - /* Start Auto Negotiation */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data); - - /* Get the auto negotiation status*/ - if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BSR, &data) != TRUE) - { - return FALSE; - } - - /* Wait till auto negotiation is complete */ - while(PHY_AUTONEG_INCOMPLETE == (data & PHY_AUTONEG_STATUS)) - { - MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BSR, &data); - } - - /* Check if the PHY is able to perform auto negotiation */ - if(data & PHY_AUTONEG_ABLE) - { - return TRUE; - } - - return FALSE; -} - -/** - * \brief Reads the Link Partner Ability register of the PHY. - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * \param ptnerAblty The partner abilities of the EMAC - * - * \return status after reading \n - * TRUE if reading successful - * FALSE if reading failed - **/ -unsigned int Lan8710aPartnerAbilityGet(unsigned int mdioBaseAddr, - unsigned int phyAddr, - unsigned short *ptnerAblty) -{ - return (MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_ABLTY, - ptnerAblty)); -} - -/** - * \brief Reads the link status of the PHY. - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * \param retries The number of retries before indicating down status - * - * \return link status after reading \n - * TRUE if link is up - * FALSE if link is down \n - * - * \note This reads both the basic status register of the PHY and the - * link register of MDIO for double check - **/ -unsigned int Lan8710aLinkStatusGet(unsigned int mdioBaseAddr, - unsigned int phyAddr, - volatile unsigned int retries) -{ - volatile unsigned short linkStatus; - volatile unsigned int retVal = TRUE; - - while (retVal == TRUE) - { - /* First read the BSR of the PHY */ - MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BSR, &linkStatus); - - if(linkStatus & PHY_LINK_STATUS) - { - /* Check if MDIO LINK register is updated */ - linkStatus = MDIOPhyLinkStatusGet(mdioBaseAddr); - - if(linkStatus & (1 << phyAddr)) - { - break; - } - else - { - (retries != 0) ? retries-- : (retVal = FALSE); - } - } - else - { - (retries != 0) ? retries-- : (retVal = FALSE); - } - } - - return retVal; -} - -/**************************** End Of File ***********************************/ diff --git a/lib/tiam1808/drivers/lidd.c b/lib/tiam1808/drivers/lidd.c deleted file mode 100644 index b7281673d..000000000 --- a/lib/tiam1808/drivers/lidd.c +++ /dev/null @@ -1,252 +0,0 @@ -/** - * \file lidd.c - * - * \brief LIDD device abstraction layer - * - * This file contains the device abstraction layer APIs for LIDD mode of LCDC - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -/* HW Macros */ -#include "hw_types.h" - -/* Driver APIs */ -#include "lidd.h" - - -/******************************************************************************* -* DAL API DEFINITIONS -*******************************************************************************/ -/** -* \brief This function configures clkdiv to generate required frequency of -* of device clock and selects the LIDD mode of operation \n -* -* \param baseAddr is the base address of LCD controller \n -* \param freq is the required device I/O clock frequency.\n -* \param moduleFreq is the module i/p freq to LCD module from PLL.\n -* -* \return none. -* -* NOTE: This is the first API to be called -**/ -void LIDDClkConfig(unsigned int baseAddr, unsigned int freq, - unsigned int moduleFreq) -{ - HWREG(baseAddr + LCDC_LCD_CTRL) = ((moduleFreq / freq) & 0xFF) \ - << LCDC_LCD_CTRL_CLKDIV_SHIFT; -} - -/** - * \brief This function returns the status of the LCD controller - * - * \param baseAddr is the base address of LCD controller \n - * - * \return LCD status bit mask -**/ -unsigned int LIDDStatusGet(unsigned int baseAddr) -{ - return (HWREG(baseAddr + LCDC_LCD_STAT)); -} - -/** - * \brief This function configures the mode of LIDD operation - * - * \param baseAddr is the base address of the LCD controller \n - * \param mode is the mode in which the LIDD interface is configured \n - * - * type can take the following values - * LIDD_MODE_SYNC_MPU68\n - * LIDD_MODE_ASYNC_MPU68\n - * LIDD_MODE_SYNC_MPU80\n - * LIDD_MODE_ASYNC_MPU80\n - * LIDD_MODE_HITACHI\n - * - * \return none - * - * NOTE: LIDDModeSet, LIDDPolaritySet, LIDDDMAConfigSet act on same register. - * Hence to start with, first LIDDModeSet is to be called and then the others - **/ - -void LIDDModeSet(unsigned int baseAddr, unsigned int mode) -{ - HWREG(baseAddr + LCDC_LIDD_CTRL) = mode & LCDC_LIDD_CTRL_LIDD_MODE_SEL; -} - -/** - * \brief This function configures the mode of polarity for CS/Strobe/Enable signals - * - * \param baseAddr is the base address of the LCD controller - * \param polarity is the polarity for the CS/Strobe/Enable signals - * - * \return none - * - * NOTE:\n - * (1) combined polarity should be provided using LIDD_CS_STROBE_POLARITY(...) \n - * (2) LIDDModeSet, LIDDPolaritySet, LIDDDMAConfigSet act on same register.\n - * Hence to start with, first LIDDModeSet is to be called and then the others - **/ -void LIDDPolaritySet(unsigned int baseAddr, unsigned int polarity) -{ - HWREG(baseAddr + LCDC_LIDD_CTRL) |= polarity; -} - -/** - * \brief This function enables/disbles the DMA and DMA DONE interrupt - * - * \param baseAddr is the base address of the LCD controller \n - * \param dmaEnable is a flag, when 0 disables the DMA, 1 enables the DMA - * \param doneEnable is a flag, when 0 disables DONE and 1 enables DONE interrupt - * - * \return none - * - * NOTE: \n - * (1) If DMA is disabled then DONE is also disabled and doneEnable is ignored - * (2) LIDDModeSet, LIDDPolaritySet, LIDDDMAConfigSet act on same register.\n - * Hence to start with, first LIDDModeSet is to be called and then the others - **/ -void LIDDDMAConfigSet(unsigned int baseAddr, unsigned int dmaEnable, - unsigned int doneEnable) -{ - if (1 == dmaEnable) - { - HWREG(baseAddr + LCDC_LIDD_CTRL) |= LCDC_LIDD_CTRL_LIDD_DMA_EN; - if (1 == doneEnable) - { - HWREG(baseAddr + LCDC_LIDD_CTRL) |= LCDC_LIDD_CTRL_DONE_INT_EN; - } - } - else - { - /* If DMA is disabled then DONE is also disabled */ - HWREG(baseAddr + LCDC_LIDD_CTRL) &= ~(LCDC_LIDD_CTRL_DONE_INT_EN |\ - LCDC_LIDD_CTRL_LIDD_DMA_EN); - } -} - -/** - * \brief This function configures the CS to which the DMA should transfer - * - * \param baseAddr is the base address of the LCD controller \n - * \param cs is the CS to which the DMA should transfer\n - * - * \return none - * - * NOTE:\n - * (1) LIDDModeSet, LIDDPolaritySet, LIDDDMAConfigSet, LIDDDMACSSet act on same \n - * register. Hence to start with, first LIDDModeSet is to be called and \n - * then the others - **/ -void LIDDDMACSSet(unsigned int baseAddr, unsigned int cs) -{ - /* CS can only be 0 or 1 */ - cs &= 0x1; - HWREG(baseAddr + LCDC_LIDD_CTRL) |= ((cs << LCDC_LIDD_CTRL_DMA_CS0_CS1_SHIFT) & \ - LCDC_LIDD_CTRL_DMA_CS0_CS1) ; -} - -/** - * \brief This function configures the timing parameters for the strobe signals - * on the given chip select - * - * \param baseAddr is the base address of the LCD controller\n - * \param cs is the chip select for which the timing is configured\n - * \param conf is the strobe timing configuration for cs - * - * \return none - * - * NOTE:\n - * The strobe timing configuration includes, r/w set up times, r/w strobe times\n - * and the turnaround times . These make up to 7 parameters which are combined into\n - * one register value by LIDD_CS_CONF(...). LIDD_CS_CONF(...) should be used to\n - * specify the combined timing configuration for CS - **/ -void LIDDCSTimingConfig(unsigned int baseAddr, unsigned int cs, unsigned int conf) -{ - /* CS can only be 0 or 1 */ - HWREG(baseAddr + LCDC_LIDD_CS_CONF(cs & 0x1)) = conf; -} - -/** - * \brief This function sets the address index for a chip select - * - * \param baseAddr is the base address of the LCD controller \n - * \param cs is the chip select which is to be affected \n - * \param index is the address index to be set - * - * \return none - **/ -void LIDDAddrIndexSet(unsigned int baseAddr, unsigned int cs, unsigned int index) -{ - HWREG(baseAddr + LCDC_LIDD_CS_ADDR(cs & 0x1)) = index & LCDC_LIDD_CS0_ADDR_ADR_INDX; -} - -/** - * \brief This function sets the data for a chip select - * - * \param baseAddr is the base address of the LCD controller \n - * \param cs is the chip select which is to be affected \n - * \param data is the data to be set - * - * \return none - **/ -void LIDDDataWrite(unsigned int baseAddr, unsigned int cs, unsigned int data) -{ - HWREG(baseAddr + LCDC_LIDD_CS_DATA(cs & 0x1)) = data & LCDC_LIDD_CS0_DATA_DATA; -} - -/** - * \brief This function sets a data of a given length - * - * \param baseAddr is the base address of the LCD controller \n - * \param cs is the chip select which is to be affected \n - * \param start is the starting address index \n - * \param data the pointer to the data buffer \n - * \param len the length of the data - * - * \return none - **/ -void LIDDStringWrite(unsigned int baseAddr, unsigned int cs, unsigned int start, - char *data, unsigned int len) -{ - unsigned int i; - for (i =0; i < len; i++) - { - HWREG(baseAddr + LCDC_LIDD_CS_ADDR(cs & 0x1)) = \ - ((start + i) & LCDC_LIDD_CS0_ADDR_ADR_INDX); - HWREG(baseAddr + LCDC_LIDD_CS_DATA(cs & 0x1)) = \ - (*(data + i) & LCDC_LIDD_CS0_DATA_DATA); - } -} diff --git a/lib/tiam1808/drivers/mailbox.c b/lib/tiam1808/drivers/mailbox.c deleted file mode 100644 index 126fd8f44..000000000 --- a/lib/tiam1808/drivers/mailbox.c +++ /dev/null @@ -1,328 +0,0 @@ -/** - * \file mailbox.c - * - * \brief This file contains the device abstraction layer APIs for the - * mailbox module. These are used for IPC communication. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#include "hw_types.h" -#include "mailbox.h" - -/************************************************************************** - API FUNCTION DEFINITIONS -***************************************************************************/ - -/** - * \brief This function resets the mailbox - * - * \param baseAdd Memory address of the mailbox instance used. - * \return None - */ - -void MBresetMailbox(unsigned int baseAdd) -{ - /* Start the soft reset sequence */ - HWREG(baseAdd + MAILBOX_SYSCONFIG) = - (MAILBOX_SYSCONFIG_SOFTRESET_MANUAL << - MAILBOX_SYSCONFIG_SOFTRESET_SHIFT); - - /* Wait till the reset is complete */ - while(HWREG(baseAdd + MAILBOX_SYSCONFIG) & - (MAILBOX_SYSCONFIG_SOFTRESET << MAILBOX_SYSCONFIG_SOFTRESET_SHIFT)); -} - - -/** - * \brief This function configures the idle mode of the mailbox - * - * \param baseAdd Memory address of the mailbox instance used. - * \param idleMode Idle mode to be configured. Possible values are - * 0x0: Force-idle. An idle request is acknowledged unconditionally - * 0x1: No-idle. An idle request is never acknowledged - * 0x2: Smart-idle. Acknowledgement to an idle request is given based - * on the internal activity of the module - * \return None - */ - -void MBconfigIdleMode(unsigned int baseAdd, unsigned int idleMode) -{ - /* Configure idle mode */ - HWREG(baseAdd + MAILBOX_SYSCONFIG) = - (idleMode << MAILBOX_SYSCONFIG_SIDLEMODE_SHIFT); -} - - -/** - * \brief This function gets the first message in the queue - * - * \param baseAdd Memory address of the mailbox instance used. - * \param queueId Queue to be read - * \param *msgPtr Message pointer in which the message will be returned - * - * \return Validity The return value indicates whether the message is valid - */ - -unsigned int MBgetMessage(unsigned int baseAdd, unsigned int queueId, unsigned int *msgPtr) -{ - /* Check if queue is not empty */ - if((HWREG(baseAdd + MAILBOX_MESSAGESTATUS(queueId)) & - (MAILBOX_MESSAGESTATUS_NBOFMSGMBM << - MAILBOX_MESSAGESTATUS_NBOFMSGMBM_SHIFT)) > 0) - { - /* Read message */ - *msgPtr = HWREG(baseAdd + MAILBOX_MESSAGE(queueId)); - return MESSAGE_VALID; - } - else - { - /* Queue empty*/ - return MESSAGE_INVALID; - } -} - - -/** - * \brief This function writes message in the queue - * - * \param baseAdd Memory address of the mailbox instance used. - * \param queueId Queue to be written - * \param msg Message which has to be sent - * - * \return status The return value indicates whether the message is - * written to the queue. Possible values are, - * 0 - Written successfully - * 0 - Queue full - */ - -unsigned int MBsendMessage(unsigned int baseAdd, unsigned int queueId, unsigned int msg) -{ - - unsigned int fifoFullMask = (MAILBOX_FIFOSTATUS_FIFOFULLMBM << - MAILBOX_FIFOSTATUS_FIFOFULLMBM_SHIFT); - - /* Check if queue is not full */ - if((HWREG(baseAdd + MAILBOX_FIFOSTATUS(queueId)) & fifoFullMask) != fifoFullMask) - { - /* Write message */ - HWREG(baseAdd + MAILBOX_MESSAGE(queueId)) = msg; - return (!fifoFullMask); - } - else - { - /* Queue full */ - return (fifoFullMask); - } -} - - -/** - * \brief This function enables the new message interrupt for a user for given queue - * - * \param baseAdd Memory address of the mailbox instance used. - * \param userId User for whom the new meaasge should be intimated - * \param queueId Queue to be monitored for new message - * - * \return None - */ - -void MBenableNewMsgInt(unsigned int baseAdd, unsigned int userId, unsigned int queueId) -{ - HWREG(baseAdd + MAILBOX_IRQENABLE_SET(userId)) = - (MAILBOX_IRQENABLE_SET_NEWMSGSTATUSUUMB(queueId) << - MAILBOX_IRQENABLE_SET_NEWMSGSTATUSUUMB_SHIFT(queueId)); -} - - -/** - * \brief This function enables the queue not full interrupt for a user for given queue - * - * \param baseAdd Memory address of the mailbox instance used. - * \param userId User for whom the event should be intimated - * \param queueId Queue to be monitored for non-full condition - * - * \return None - */ - -void MBenableQueueNotFullInt(unsigned int baseAdd, unsigned int userId, unsigned int queueId) -{ - HWREG(baseAdd + MAILBOX_IRQENABLE_SET(userId)) = - (MAILBOX_IRQENABLE_SET_NOTFULLSTATUSUUMB(queueId) << - MAILBOX_IRQENABLE_SET_NOTFULLSTATUSUUMB_SHIFT(queueId)); -} - - -/** - * \brief This function disables the new message interrupt for a user for given queue - * - * \param baseAdd Memory address of the mailbox instance used. - * \param userId User for whom the new meaasge event should be disabled - * \param queueId Queue to be monitored for new message - * - * \return None - */ - -void MBdisableNewMsgInt(unsigned int baseAdd, unsigned int userId, unsigned int queueId) -{ - HWREG(baseAdd + MAILBOX_IRQENABLE_CLR(userId)) = - (MAILBOX_IRQENABLE_CLR_NEWMSGSTATUSUUMB(queueId) << - MAILBOX_IRQENABLE_CLR_NEWMSGSTATUSUUMB_SHIFT(queueId)); -} - - -/** - * \brief This function disables the queue not full interrupt for a user for given queue - * - * \param baseAdd Memory address of the mailbox instance used. - * \param userId User for whom the event should be disabled - * \param queueId Queue for which the non-full event to be disabled - * - * \return None - */ - -void MBdisableQueueNotFullInt(unsigned int baseAdd, unsigned int userId, unsigned int queueId) -{ - HWREG(baseAdd + MAILBOX_IRQENABLE_CLR(userId)) = - (MAILBOX_IRQENABLE_CLR_NOTFULLSTATUSUUMB(queueId) << - MAILBOX_IRQENABLE_CLR_NOTFULLSTATUSUUMB_SHIFT(queueId)); -} - -/** - * \brief This function gets the new message status - * - * \param baseAdd Memory address of the mailbox instance used. - * \param userId User for whom the event should be checked - * \param queueId Queue for which the event should be checked - * - * \return status status of new message - */ - -unsigned int MBgetNewMsgStatus(unsigned int baseAdd, unsigned int userId, unsigned int queueId) -{ - return ((HWREG(baseAdd + MAILBOX_IRQSTATUS_CLR(userId)) & - MAILBOX_IRQSTATUS_CLR_NEWMSGSTATUSUUMB(queueId)) >> - MAILBOX_IRQSTATUS_CLR_NEWMSGSTATUSUUMB_SHIFT(queueId)); -} - - -/** - * \brief This function gets the queue not-full status - * - * \param baseAdd Memory address of the mailbox instance used. - * \param userId User for whom the event should be checked - * \param queueId Queue for which the event should be checked - * - * \return status Queue not full status - */ - -unsigned int MBgetQueueNotFullStatus(unsigned int baseAdd, unsigned int userId, unsigned int queueId) -{ - return ((HWREG(baseAdd + MAILBOX_IRQSTATUS_CLR(userId)) & - MAILBOX_IRQSTATUS_CLR_NOTFULLSTATUSUUMB(queueId)) >> - MAILBOX_IRQSTATUS_CLR_NOTFULLSTATUSUUMB_SHIFT(queueId)); -} - - -/** - * \brief This function clears the queue not-full status - * - * \param baseAdd Memory address of the mailbox instance used. - * \param userId User for whom the event should be cleared - * \param queueId Queue for which the event should be cleared - * - * \return None - */ - -void MBclrNewMsgStatus(unsigned int baseAdd, unsigned int userId, unsigned int queueId) -{ - HWREG(baseAdd + MAILBOX_IRQSTATUS_CLR(userId)) = - (MAILBOX_IRQSTATUS_CLR_NEWMSGSTATUSUUMB(queueId) << - MAILBOX_IRQSTATUS_CLR_NEWMSGSTATUSUUMB_SHIFT(queueId)); -} - - -/** - * \brief This function clears the queue not-full status - * - * \param baseAdd Memory address of the mailbox instance used. - * \param userId User for whom the event should be cleared - * \param queueId Queue for which the event should be cleared - * - * \return None - */ - -void MBclrQueueNotFullStatus(unsigned int baseAdd, unsigned int userId, unsigned int queueId) -{ - HWREG(baseAdd + MAILBOX_IRQSTATUS_CLR(userId)) = - (MAILBOX_IRQSTATUS_CLR_NOTFULLSTATUSUUMB(queueId) << - MAILBOX_IRQSTATUS_CLR_NOTFULLSTATUSUUMB_SHIFT(queueId)); -} - - -/** - * \brief This function gets the raw new message status - * - * \param baseAdd Memory address of the mailbox instance used. - * \param userId User for whom the event should be checked - * \param queueId Queue for which the event should be checked - * - * \return status status of new message - */ - -unsigned int MBgetRawNewMsgStatus(unsigned int baseAdd, unsigned int userId, unsigned int queueId) -{ - return ((HWREG(baseAdd + MAILBOX_IRQSTATUS_CLR(userId)) & - MAILBOX_IRQSTATUS_CLR_NEWMSGSTATUSUUMB(queueId)) >> - MAILBOX_IRQSTATUS_CLR_NEWMSGSTATUSUUMB_SHIFT(queueId)); -} - - -/** - * \brief This function gets the raw queue not-full status - * - * \param baseAdd Memory address of the mailbox instance used. - * \param userId User for whom the event should be checked - * \param queueId Queue for which the event should be checked - * - * \return status Queue not full status - */ - -unsigned int MBgetRawQueueNotFullStatus(unsigned int baseAdd, unsigned int userId, unsigned int queueId) -{ - return ((HWREG(baseAdd + MAILBOX_IRQSTATUS_CLR(userId)) & - MAILBOX_IRQSTATUS_CLR_NOTFULLSTATUSUUMB(queueId)) >> - MAILBOX_IRQSTATUS_CLR_NOTFULLSTATUSUUMB_SHIFT(queueId)); -} diff --git a/lib/tiam1808/drivers/phy.c b/lib/tiam1808/drivers/phy.c deleted file mode 100644 index 2c8dd5a64..000000000 --- a/lib/tiam1808/drivers/phy.c +++ /dev/null @@ -1,375 +0,0 @@ -/** - * \file phy.c - * - * \brief APIs for configuring ethernet PHYs - * - * This file contains the device abstraction APIs for ethernet PHYs. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#include "hw_types.h" -#include "mdio.h" -#include "phy.h" - -#define PHY_ADV_VAL_MASK (0xff10) - -/******************************************************************************* -* API FUNCTION DEFINITIONS -*******************************************************************************/ -/** - * \brief Reads the PHY ID. - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * - * \return 32 bit PHY ID (ID1:ID2) - * - **/ -unsigned int PhyIDGet(unsigned int mdioBaseAddr, unsigned int phyAddr) -{ - unsigned int id = 0; - unsigned short data; - - /* read the ID1 register */ - MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_ID1, &data); - - /* update the ID1 value */ - id = data << PHY_ID_SHIFT; - - /* read the ID2 register */ - MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_ID2, &data); - - /* update the ID2 value */ - id |= data; - - /* return the ID in ID1:ID2 format */ - return id; -} - -/** - * \brief Reads a register from the the PHY - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * \param regIdx Index of the register to be read - * \param regValAdr address where value of the register will be written - * - * \return status of the read - * - **/ -unsigned int PhyRegRead(unsigned int mdioBaseAddr, unsigned int phyAddr, - unsigned int regIdx, unsigned short *regValAdr) -{ - return (MDIOPhyRegRead(mdioBaseAddr, phyAddr, regIdx, regValAdr)); -} - -/** - * \brief Writes a register with the input - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * \param regIdx Index of the register to be read - * \param regValAdr value to be written - * - * \return None - * - **/ -void PhyRegWrite(unsigned int mdioBaseAddr, unsigned int phyAddr, - unsigned int regIdx, unsigned short regVal) -{ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, regIdx, regVal); -} - -/** - * \brief Resets the PHY - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * - * \return None - * - **/ -void PhyReset(unsigned int mdioBaseAddr, unsigned int phyAddr) -{ - /* Reset the phy */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, PHY_SOFTRESET); -} - -/** - * \brief Enables Loop Back mode - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * - * \return status after enabling. \n - * TRUE if loop back is enabled \n - * FALSE if not able to enable - * - **/ -unsigned int PhyLoopBackEnable(unsigned int mdioBaseAddr, unsigned int phyAddr) -{ - unsigned short data; - - if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE ) - { - return FALSE; - } - - data |= PHY_LPBK_ENABLE; - - /* Enable loop back */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data); - - return TRUE; -} - -/** - * \brief Disables Loop Back mode - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * - * \return status after enabling. \n - * TRUE if loop back is disabled \n - * FALSE if not able to disable - * - **/ -unsigned int PhyLoopBackDisable(unsigned int mdioBaseAddr, unsigned int phyAddr) -{ - unsigned short data; - - if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE ) - { - return FALSE; - } - - data &= ~(PHY_LPBK_ENABLE); - - /* Disable loop back */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data); - - return TRUE; -} - -/** - * \brief Configures the PHY for a given speed and duplex mode. This - * API will first reset the PHY. Then it sets the desired speed - * and duplex mode for the PHY. - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * \param speed Speed to be enabled - * \param duplexMode Duplex Mode - * - * \return status after configuring \n - * TRUE if configuration successful - * FALSE if configuration failed - * - **/ -unsigned int PhyConfigure(unsigned int mdioBaseAddr, unsigned int phyAddr, - unsigned short speed, unsigned short duplexMode) -{ - unsigned short data; - - data = PHY_SOFTRESET; - - /* Reset the phy */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data); - - /* wait till the reset bit is auto cleared */ - while(data) - { - /* Read the reset */ - if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE) - { - return FALSE; - } - } - - /* Set the configurations */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, (speed | duplexMode)); - - return TRUE; -} - -/** - * \brief This function ask the phy device to start auto negotiation. - * - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * \param advVal Autonegotiation advertisement value - * \param gigAdvVal Gigabit capability advertisement value - * advVal can take the following any OR combination of the values \n - * PHY_100BTX - 100BaseTX \n - * PHY_100BTX_FD - Full duplex capabilty for 100BaseTX \n - * PHY_10BT - 10BaseT \n - * PHY_10BT_FD - Full duplex capability for 10BaseT \n - * gigAdvVal can take one of the following values \n - * PHY_NO_1000BT - No 1000Base-T capability\n - * PHY_1000BT_FD - Full duplex capabilty for 1000 Base-T \n - * PHY_1000BT_HD - Half duplex capabilty for 1000 Base-T - * - * \return status after autonegotiation \n - * TRUE if autonegotiation started - * FALSE if autonegotiation not started - * - **/ -unsigned int PhyAutoNegotiate(unsigned int mdioBaseAddr, unsigned int phyAddr, - unsigned short *advPtr, unsigned short *gigAdvPtr) -{ - volatile unsigned short data; - volatile unsigned short anar; - - if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE ) - { - return FALSE; - } - - data |= PHY_AUTONEG_ENABLE; - - /* Enable Auto Negotiation */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data); - - if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE ) - { - return FALSE; - } - - /* Write Auto Negotiation capabilities */ - MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_AUTONEG_ADV, &anar); - anar &= ~PHY_ADV_VAL_MASK; - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_AUTONEG_ADV, (anar |(*advPtr))); - - /* Write the gigabit capabilities */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_1000BT_CONTROL, (*gigAdvPtr)); - - data |= PHY_AUTONEG_RESTART; - - /* Start Auto Negotiation */ - MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data); - - /* Get the auto negotiation status*/ - if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BSR, &data) != TRUE) - { - return FALSE; - } - - return TRUE; -} - -/** - * \brief Returns the status of Auto Negotiation completion. - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * - * \return Auto negotiation completion status \n - * TRUE if auto negotiation is completed - * FALSE if auto negotiation is not completed - **/ -unsigned int PhyAutoNegStatusGet(unsigned int mdioBaseAddr, unsigned int phyAddr) -{ - volatile unsigned short data; - - MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BSR, &data); - - /* Auto negotiation completion status */ - if(PHY_AUTONEG_INCOMPLETE == (data & (PHY_AUTONEG_STATUS))) - { - return TRUE; - } - - return FALSE; -} - -/** - * \brief Reads the Link Partner Ability register of the PHY. - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * \param ptnerAblty The partner abilities of the EMAC - * - * \return status after reading \n - * TRUE if reading successful - * FALSE if reading failed - **/ -unsigned int PhyPartnerAbilityGet(unsigned int mdioBaseAddr, - unsigned int phyAddr, - unsigned short *ptnerAblty) -{ - return (MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_ABLTY, - ptnerAblty)); -} - -/** - * \brief Reads the link status of the PHY. - * - * \param mdioBaseAddr Base Address of the MDIO Module Registers. - * \param phyAddr PHY Adress. - * \param retries The number of retries before indicating down status - * - * \return link status after reading \n - * TRUE if link is up - * FALSE if link is down \n - * - * \note This reads both the basic status register of the PHY and the - * link register of MDIO for double check - **/ -unsigned int PhyLinkStatusGet(unsigned int mdioBaseAddr, - unsigned int phyAddr, - volatile unsigned int retries) -{ - volatile unsigned short linkStatus; - - retries++; - while (retries) - { - /* First read the BSR of the PHY */ - MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BSR, &linkStatus); - - if(linkStatus & PHY_LINK_STATUS) - { - return TRUE; - } - - retries--; - } - - return FALSE; -} - -/**************************** End Of File ***********************************/ diff --git a/lib/tiam1808/drivers/raster.c b/lib/tiam1808/drivers/raster.c deleted file mode 100644 index d7f595a54..000000000 --- a/lib/tiam1808/drivers/raster.c +++ /dev/null @@ -1,1221 +0,0 @@ -/** - * \file raster.c - * - * \brief Raster LCD APIs. - * - * This file contains the device abstraction layer APIs for Raster LCD. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#include "hw_lcdc.h" -#include "hw_types.h" -#include "raster.h" - -/******************************************************************************* -* INTERNAL API DEFINITIONS -*******************************************************************************/ -/** -* \brief This function configures clkdiv to generate required frequency of -* of pixel clock and selects the raster control.\n -* -* \param baseAddr is the Memory address of LCD.\n -* \param pClk is the required Pixel Clock frequency.\n -* \param modulck is the input clk to LCD module from PLL.\n -* -* \return none. -**/ -void RasterClkConfig(unsigned int baseAddr, unsigned int pClk, - unsigned int moduleClk) -{ - unsigned int clkDiv; - - clkDiv = moduleClk / pClk ; - - HWREG(baseAddr + LCDC_LCD_CTRL) = LCDC_LCD_CTRL_MODESEL; - - HWREG(baseAddr + LCDC_LCD_CTRL) |= (clkDiv << LCDC_LCD_CTRL_CLKDIV_SHIFT); -} - -/** -* \brief This function returns the Reversion Id of LCD controller. -* -* \param baseAddr is the Memory address of LCD. -* -**/ -unsigned int RasterIdGet(unsigned int baseAddr) -{ - return(HWREG(baseAddr + LCDC_PID)); -} - -/** -* \brief This function enables auto under flow feature. -* -* \param baseAddr is the Memory address of LCD.\n -* -* \return none. -**/ -void RasterAutoUnderFlowEnable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_LCD_CTRL) |= LCDC_LCD_CTRL_AUTO_UFLOW_RESTART; -} - -/** -* \brief This function disables auto under flow feature. -* -* \param baseAddr is the Memory address of LCD.\n -* -* \return none. -**/ -void RasterAutoUnderFlowDisable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_LCD_CTRL) &= ~LCDC_LCD_CTRL_AUTO_UFLOW_RESTART; -} - -/** -* \brief This function will Enable Raster Control.\n -* -* \param baseAddr is the Memory address of the LCD.\n -* -* \return none. -**/ -void RasterEnable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_RASTER_CTRL) |= LCDC_RASTER_CTRL_RASTER_EN; -} - -/** -* \brief This function will Disable Raster Control.\n -* -* \param baseAddr is the Memory address of the LCD.\n -* -* \return none. -**/ -void RasterDisable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_RASTER_CTRL) &= ~LCDC_RASTER_CTRL_RASTER_EN; -} - -/** -* \brief This function will configures LCD to MonoChrome or color mode, -* TFT or STN mode and palette loading mode.\n -* -* \param baseAddr is the Memory address of the LCD.\n -* \param displayMode is the vlaue to select either TFT or STN mode.\n -* -* displayMode can take following value.\n -* -* RASTER_DISPLAY_MODE_TFT - TFT mode is selected.\n -* RASTER_DISPLAY_MODE_STN - STN mode is selected.\n -* -* Below mentioned macros are only applicable to AM335x. -* -* RASTER_DISPLAY_MODE_TFT_PACKED - TFT mode is selected with -* 24 bit packed data support. -* RASTER_DISPLAY_MODE_TFT_UNPACKED - TFT mode is selected with -* 24 bit unpacked data support. -* -* \param displayType is the value to select either color or monochrome mode.\n -* -* displayType can take following value.\n -* -* RASTER_MONOCHROME - monochrome mode is selected.\n -* RASTER_COLOR - color mode is selected.\n -* -* \param paletteMode is the value to select type of palette loading.\n -* -* paletteMode can take following values.\n -* -* RASTER_PALETTE_DATA - palette and data is loaded.\n -* RASTER_PALETTE - only palette is loaded.\n -* RASTER_DATA - only data is loaded.\n -* -* \param flag Optional argument depending on the display mode and type -* -* flag can take following values.\n -* -* RASTER_RIGHT_ALIGNED - Right aligned output pixel data -* RASTER_EXTRAPOLATE - Extrapolated (to RGB565) output pixel data -* RASTER_MONO8B - Output 8 bit mono pixel data -* RASTER_MONO4B - Output 4 bit mono pixel data -* -* \return none. -**/ -void RasterModeConfig(unsigned int baseAddr, unsigned int displayMode, - unsigned int paletteMode, unsigned int displayType, - unsigned flag) -{ - /* Configures raster to TFT or STN Mode */ - HWREG(baseAddr + LCDC_RASTER_CTRL) = displayMode | paletteMode | displayType; - - if(displayMode == RASTER_DISPLAY_MODE_TFT) - { - if(flag == RASTER_RIGHT_ALIGNED) - { - /* Output pixel data for 1,2,4 and 8 bpp is converted to 565 format */ - HWREG(baseAddr + LCDC_RASTER_CTRL) &= ~(LCDC_RASTER_CTRL_TFT_ALT_MAP); - } - else - { - /* Output pixel data for 1,2,4 and 8 bpp will be right aligned */ - HWREG(baseAddr + LCDC_RASTER_CTRL) |= LCDC_RASTER_CTRL_TFT_ALT_MAP; - } - } - else - { - if(flag == RASTER_MONO8B) - { - HWREG(baseAddr + LCDC_RASTER_CTRL) |= LCDC_RASTER_CTRL_MONO8B; - } - else - { - HWREG(baseAddr + LCDC_RASTER_CTRL) &= ~LCDC_RASTER_CTRL_MONO8B; - } - } -} - -/** -* \brief This function orders the frame buffer data from -* least to most significant bit bit/nibble/byte/word/ -* -* \param baseAddr is the Memory address of the LCD module.\n -* -* \return None. -**/ -void RasterLSBDataOrderSelect(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_RASTER_CTRL) &= ~LCDC_RASTER_CTRL_RD_ORDER; -} - -/** -* \brief This function orders the frame buffer data from -* most to least significant bit bit/nibble/byte/word/ -* -* \param baseAddr is the Memory address of the LCD module.\n -* -* \return None. -**/ -void RasterMSBDataOrderSelect(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_RASTER_CTRL) |= LCDC_RASTER_CTRL_RD_ORDER; -} - -/** -* \brief This function enables interrupts in LCD controller.\n -* -* \param baseAddr is the Memory address of the LCD module. -* -* \param flag is the value specifies the which interrupts to be -* enabled.\n -* -* flag can take following values.\n -* -* Below mentioned macros are only applicable to AM1808. -* -* RASTER_ACBIAS_COUNT_INT - ACBias Count interrupt.\n -* RASTER_FRAME_DONE_INT - Frame done interrupt.\n -* RASTER_PALETTE_LOADED_INT - Palette loaded interrupt.\n -* RASTER_SYNC_LOST_INT - Sync lost interrupt.\n -* RASTER_FIFO_UNDRFLOW_INT - FIFO underflow interrupt.\n -* -* Below mentioned API are only for AM335x raster.\n -* -* RASTER_DONE_INT - Raster Done interrupt \n. -* RASTER_END_OF_FRAME0_INT - End of frame0 interrupt \n. -* RASTER_END_OF_FRAME1_INT - End of frame1 interrupt \n. -* -* \return None. -**/ -void RasterIntEnable(unsigned int baseAddr, unsigned int flag) -{ - unsigned int version = 0; - - version = LCDVersionGet(); - - if(RASTER_REV_AM335X == version) - { - HWREG(baseAddr + LCDC_IRQENABLE_SET) |= flag; - } - else if(RASTER_REV_AM1808 == version) - { - HWREG(baseAddr + LCDC_RASTER_CTRL) |= flag; - } - else - { - ;/* Do nothing */ - } -} - -/** -* \brief This function disables interrupts in LCD controller.\n -* -* \param baseAddr is the Memory address of the LCD module.\n -* -* \param flag is the value specifies the which interrupts to be -* enabled.\n -* -* flag can take following values.\n -* -* RASTER_ACBIAS_COUNT_INT - ACBias Count interrupt.\n -* RASTER_FRAME_DONE_INT - Frame done interrupt.\n -* RASTER_PALETTE_LOADED_INT - Palette loaded interrupt.\n -* RASTER_SYNC_LOST_INT - Sync lost interrupt.\n -* RASTER_FIFO_UNDRFLOW_INT - FIFO underflow interrupt.\n -* -* Below mentioned API are only for AM335x raster.\n -* -* RASTER_DONE_INT - Raster Done interrupt \n. -* RASTER_END_OF_FRAME0_INT - End of frame0 interrupt \n. -* RASTER_END_OF_FRAME1_INT - End of frame1 interrupt \n. -* -* \return None. -**/ -void RasterIntDisable(unsigned int baseAddr, unsigned int flag) -{ - unsigned int version; - - version = LCDVersionGet(); - - if(RASTER_REV_AM335X == version) - { - HWREG(baseAddr + LCDC_IRQENABLE_CLEAR) = flag; - } - else if(RASTER_REV_AM1808 == version) - { - HWREG(baseAddr + LCDC_RASTER_CTRL) &= ~flag; - } - else - { - ;/* Do nothing */ - } -} - -/** -* \brief This function enable nibble mode. -* -* \param baseAddr is the Memory Address of the LCD module -* -* \return None. -**/ -void RasterNibbleModeEnable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_RASTER_CTRL) |= LCDC_RASTER_CTRL_NIB_MODE; -} - -/** -* \brief This function disable nibble mode. -* -* \param baseAddr is the Memory Address of the LCD module. -* -* \return None. -**/ -void RasterNibbleModeDisable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_RASTER_CTRL) &= ~LCDC_RASTER_CTRL_NIB_MODE; -} - -/** -* \brief This function configures input FIFO delay. -* -* \param baseAddr is the Memory address of LCD module. -* -* \return None -**/ -void RasterFIFODMADelayConfig(unsigned int baseAddr, unsigned int delay) -{ - - HWREG(baseAddr + LCDC_RASTER_CTRL) &= ~LCDC_RASTER_CTRL_FIFO_DMA_DELAY; - HWREG(baseAddr + LCDC_RASTER_CTRL) |= (delay << \ - LCDC_RASTER_CTRL_FIFO_DMA_DELAY_SHIFT); -} -/** -* \brief This function configuers horizontal timing parametes and number of -* pixel per line. -* -* \param baseAddr is the Memory address of the LCD module -* -* \param numOfppl is a value which determine no of pixel required per line. -* -* \param hsw is a value which detemines the width of HSYNC. -* -* \param hfp horizontal front porch. -* -* \para hbp horizontal back porch. -**/ -void RasterHparamConfig(unsigned int baseAddr, unsigned int numOfppl, - unsigned int hsw, unsigned int hfp, - unsigned hbp) -{ - unsigned int ppl; - unsigned int version; - - version = LCDVersionGet(); - - if(RASTER_REV_AM335X == version) - { - ppl = numOfppl - 1; - - ppl = (ppl & 0x000003f0) | ((ppl & 0x00000400) >> 8); - - HWREG(baseAddr + LCDC_RASTER_TIMING_0) = ppl; - } - else if(RASTER_REV_AM1808 == version) - { - - ppl = (numOfppl / 16) - 1; - - HWREG(baseAddr + LCDC_RASTER_TIMING_0) = (ppl << - LCDC_RASTER_TIMING_0_PPL_SHIFT); - } - else - { - ;/* Do nothing */ - } - - HWREG(baseAddr + LCDC_RASTER_TIMING_0) |= ((hsw - 1) << - LCDC_RASTER_TIMING_0_HSW_SHIFT); - - HWREG(baseAddr + LCDC_RASTER_TIMING_0) |= ((hfp - 1) << - LCDC_RASTER_TIMING_0_HFP_SHIFT); - - HWREG(baseAddr + LCDC_RASTER_TIMING_0) |= ((hbp - 1) << - LCDC_RASTER_TIMING_0_HBP_SHIFT); -} - -/** -* \brief This function configuers vertical timing parameters and number of -* lines per panel. -* -* \param baseAddr is the Memory address of the LCD module -* -* \param lpp is a value which determine the lines per panel. -* -* \param vsw is a value which detemines the width of VSYNC. -* -* \param vfp vertical front porch. -* -* \para vbp vertical back porch. -**/ -void RasterVparamConfig(unsigned int baseAddr, unsigned int lpp, - unsigned int vsw, unsigned int vfp, - unsigned vbp) -{ - unsigned int version; - - version = LCDVersionGet(); - - if(RASTER_REV_AM335X == version) - { - - HWREG(baseAddr + LCDC_RASTER_TIMING_1) = ((lpp - 1) & 0x3ff); - - HWREG(baseAddr + LCDC_RASTER_TIMING_2) &= 0xfbffffff; - - HWREG(baseAddr + LCDC_RASTER_TIMING_2) |= (((lpp - 1) & 0x400) >> 10) - << LCDC_RASTER_TIMING_2_LPP_B10_SHIFT; - } - else if(RASTER_REV_AM1808 == version) - { - - HWREG(baseAddr + LCDC_RASTER_TIMING_1) = ((lpp - 1) << - LCDC_RASTER_TIMING_1_LPP_SHIFT); - } - else - { - ;/* Do nothing */ - } - - HWREG(baseAddr + LCDC_RASTER_TIMING_1) |= ((vsw - 1) << - LCDC_RASTER_TIMING_1_VSW_SHIFT); - - HWREG(baseAddr + LCDC_RASTER_TIMING_1) |= (vfp << - LCDC_RASTER_TIMING_1_VFP_SHIFT); - - HWREG(baseAddr + LCDC_RASTER_TIMING_1) |= (vbp << - LCDC_RASTER_TIMING_1_VBP_SHIFT); -} -/** -* \brief This function configures the polartiy of various timing parameters of -* LCD Controller. -* -* \param baseAddr is the Memory Address of the LCD Module. -* -* \param flag is the value which detemines polarity of various timing -* parameter of LCD controller.\n -* -* flag can take following values.\n -* -* RASTER_FRAME_CLOCK_HIGH - active high frame clock.\n -* RASTER_FRAME_CLOCK_LOW - active low frame clock.\n -* RASTER_LINE_CLOCK_HIGH - active high line clock.\n -* RASTER_LINE_CLOCK_LOW - active low line clock.\n -* RASTER_PIXEL_CLOCK_HIGH - active high pixel clock.\n -* RASTER_PIXEL_CLOCK_LOW - active low pixel clock.\n -* RASTER_AC_BIAS_HIGH - active high ac bias.\n -* RASTER_AC_BIAS_LOW - active low ac bias.\n -* RASTER_SYNC_EDGE_RISING - rising sync edge.\n -* RASTER_SYNC_EDGE_FALLING- falling sync edge.\n -* RASTER_SYNC_CTRL_ACTIVE - active sync control.\n -* RASTER_SYNC_CTRL_INACTIVE-inactive sync control.\n -* -* \param acb_i is the value which specify the number of AC Bias -* (LCD_AC_ENB_CS) output transition counts before -* setting the AC bias interrupt bit in register LCD_STAT. -* -* \param acb is value which defines the number of Line Clock -* (LCD_HSYNC) cycles to count before transitioning -* signal LCD_AC_ENB_CS. -* -* \return None. -* -**/ -void RasterTiming2Configure(unsigned int baseAddr, unsigned int flag, - unsigned int acb_i, unsigned int acb) -{ - HWREG(baseAddr + LCDC_RASTER_TIMING_2) |= flag; - - HWREG(baseAddr + LCDC_RASTER_TIMING_2) |= (acb_i << \ - LCDC_RASTER_TIMING_2_ACB_I_SHIFT); - - HWREG(baseAddr + LCDC_RASTER_TIMING_2) |= (acb << \ - LCDC_RASTER_TIMING_2_ACB_SHIFT); - -} -/** -* \brief This function configures DMA present inside LCD controller. -* -* \param baseAddr is the Memory address of LCD module. -* -* \param frmMode is the value which detemines either to use single frame -* or double frame buffer.\n -* -* frmMode can take following values.\n -* -* RASTER_SINGLE_FRAME_BUFFER - single frame buffer.\n -* RASTER_DOUBLE_FRAME_BUFFER - double frame buffer.\n -* -* \param bustSz is the value which detemines burst size of DMA.\n -* -* bustSz can take following values.\n -* -* RASTER_BURST_SIZE_1 - burst size of DMA is one.\n -* RASTER_BURST_SIZE_2 - burst size of DMA is two.\n -* RASTER_BURST_SIZE_4 - burst size of DMA is four.\n -* RASTER_BURST_SIZE_16 - burst size of DMA is sixteen.\n -* -* \param fifoTh is the value which detemines when the input FIFO can be -* read by raster controller.\n -* -* fifoTh can take following values.\n -* -* RASTER_FIFO_THRESHOLD_8 - DMA FIFO Threshold is eight.\n -* RASTER_FIFO_THRESHOLD_16 - DMA FIFO Threshold is sixteen.\n -* RASTER_FIFO_THRESHOLD_32 - DMA FIFO Threshold is thirtytwo.\n -* RASTER_FIFO_THRESHOLD_64 - DMA FIFO Threshold is sixtyfour.\n -* RASTER_FIFO_THRESHOLD_128 - DMA FIFO Threshold is one twenty -* eight.\n -* RASTER_FIFO_THRESHOLD_256 - DMA FIFO Threshold is two -* fifty six.\n -* RASTER_FIFO_THRESHOLD_512 - DMA FIFO Threshold is five -* twelve.\n -* -* \param endian is value determines whether to use big endian for data -* reordering or not.\n -* -* endian can take following values.\n -* -* RASTER_BIG_ENDIAN_ENABLE - big endian enabled.\n -* RASTER_BIG_ENDIAN_ENABLE - big endian disabled.\n -* -* \return None -**/ -void RasterDMAConfig(unsigned int baseAddr, unsigned int frmMode, - unsigned int bustSz, unsigned int fifoTh, - unsigned int endian) -{ - HWREG(baseAddr + LCDC_LCDDMA_CTRL) = frmMode | bustSz | fifoTh | endian; -} - -/** -* \brief This function enables byte swap with in a half word of the dma transfer. -* -* \param baseAddr is the Memory address of the LCD module. -* -* \return None. -* -* This API is only supported for AM335x raster. -**/ -void RasterByteSwapEnable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_LCDDMA_CTRL) |= LCDC_LCDDMA_CTRL_BYTE_SWAP; -} - -/** -* \brief This function disables byte swap with in a half word of the dma transfer. -* -* \param baseAddr is the Memory address of the LCD module. -* -* \return None. -* -* This API is only supported for AM335x raster. -**/ -void RasterByteSwapDisable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_LCDDMA_CTRL) &= ~LCDC_LCDDMA_CTRL_BYTE_SWAP; -} - -/** -* \brief This function enables the end of frame interrupt. -* -* \param baseAddr is the Memory address of the LCD module. -* -* \return None. -* -* This API is valid only for am1808 raster.It should not be used -* for programing of am33xx raster.To Enable End of frame 0/1 interrupt -* in AM335x raster one can use "RasterIntEnable()". -* -**/ -void RasterEndOfFrameIntEnable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_LCDDMA_CTRL) |= LCDC_LCDDMA_CTRL_EOF_INTEN; -} -/** -* \brief This function disables the end of frame interrupt. -* -* \param baseAddr is the Memory address of the LCD module. -* -* \return None. -* -* This API is valid only for am1808 raster.It should not be used -* for programing of am33xx raster.To Disable End of frame 0/1 interrupt -* in AM335x raster one can use "RasterIntDisable API" -* -**/ -void RasterEndOfFrameIntDisable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_LCDDMA_CTRL) &= ~LCDC_LCDDMA_CTRL_EOF_INTEN; -} - -/** -* \brief This function returns status of the specified interrupts.\n -* -* \param baseAddr is the Memory address of the LCD module.\n -* -* \param flag is the value determines status of which interrupts to be -* returned.\n -* -* flag can take following values.\n -* -* RASTER_ACBIAS_COUNT_INT_STAT - ACBias Count interrupt status.\n -* RASTER_PALETTE_LOADED_INT_STAT - Palette loaded interrupt status.\n -* RASTER_SYNC_LOST_INT_STAT - Sync lost interrupt status.\n -* RASTER_FIFO_UNDRFLOW_INT_STAT - FIFO underflow interrupt status.\n -* RASTER_FRAME_DONE_INT_STAT - frame done interrupt status.\n -* RASTER_END_OF_FRAME0_INT_STAT - end of frame 0 interrupt status.\n -* RASTER_END_OF_FRAME1_INT_STAT - end of frame 1 interrupt status.\n -* -* This flag should used for Raster under AM335x -* -* RASTER_DONE_INT - Raster Done interrupt.\n -* -* \returns Interrupt status of Raster for AM335x or am1808 based on revid. -**/ -unsigned int RasterIntStatus(unsigned int baseAddr, unsigned int flag) -{ - unsigned int status = 0; - unsigned int version; - - version = LCDVersionGet(); - - if(RASTER_REV_AM335X == version) - { - status = HWREG(baseAddr + LCDC_IRQSTATUS) & flag; - } - else if(RASTER_REV_AM1808 == version) - { - status = HWREG(baseAddr + LCDC_LCD_STAT) & flag; - } - else - { - ;/* Do nothing */ - } - - return status; -} - -/** -* \brief This function returns raw status of the specified interrupts.\n -* -* \param baseAddr is the Memory address of the LCD module.\n -* -* \param flag is the value determines status of which interrupts to be -* returned.\n -* -* flag can take following values.\n -* -* RASTER_ACBIAS_COUNT_INT_STAT - ACBias Count interrupt status.\n -* RASTER_PALETTE_LOADED_INT_STAT - Palette loaded interrupt status.\n -* RASTER_SYNC_LOST_INT_STAT - Sync lost interrupt status.\n -* RASTER_FIFO_UNDRFLOW_INT_STAT - FIFO underflow interrupt status.\n -* RASTER_FRAME_DONE_INT_STAT - frame done interrupt status.\n -* RASTER_END_OF_FRAME0_INT_STAT - end of frame 0 interrupt status.\n -* RASTER_END_OF_FRAME1_INT_STAT - end of frame 1 interrupt status.\n -* -* This flag should used for Raster under AM335x -* -* RASTER_DONE_INT - Frame Done interrupt.\n -* -* \return Interrupt raw status of Raster for only AM335x. -* -* If this function is used to read interrupt status of Raster for am1808,it will -* return -1. -* -* This API is only supported for AM335x raster. -**/ -int RasterIntRawStatus(unsigned int baseAddr, unsigned int flag) -{ - int status; - unsigned int version; - - version = LCDVersionGet(); - - if(RASTER_REV_AM335X == version) - { - status = HWREG(baseAddr + LCDC_IRQSTATUS_RAW) & flag; - } - else - { - status = -1; - } - return status; -} - -/** -* \brief This function asserts specified interrupts.\n -* -* \param baseAddr is the Memory address of the LCD module.\n -* -* \param flag is the value determines which interrupts to be -* asserted.\n -* -* flag can take following values.\n -* -* RASTER_ACBIAS_COUNT_INT_STAT - ACBias Count interrupt status.\n -* RASTER_PALETTE_LOADED_INT_STAT - Palette loaded interrupt status.\n -* RASTER_SYNC_LOST_INT_STAT - Sync lost interrupt status.\n -* RASTER_FIFO_UNDRFLOW_INT_STAT - FIFO underflow interrupt status.\n -* RASTER_FRAME_DONE_INT_STAT - frame done interrupt status.\n -* RASTER_END_OF_FRAME0_INT_STAT - end of frame 0 interrupt status.\n -* RASTER_END_OF_FRAME1_INT_STAT - end of frame 1 interrupt status.\n -* -* -* This API is only supported for am33xx raster. -**/ -void RasterIntRawStatusSet(unsigned int baseAddr, unsigned int flag) -{ - HWREG(baseAddr + LCDC_IRQSTATUS_RAW) |= flag; -} - -/** -* \brief This function configures base and ceiling value for -* Frame buffer one or Frame buffer two. -* -* \param baseAddr is the Memory Address of the LCD Module -* -* \param base is the base address of array which contain -* pixels of image to be dispalyed on lcd. -* -* \param ceiling is the end address of the array which contain -* pixels of image to be displayed on lcd. -* -* \param flag is the value which determines whether to write -* base and ceiling to Frame Buffer one or Fram buffer two. -* -* passing zero(i.e. 0) as argument configures base and ceiling for -* frame buffer zero(i.e FB0). -* -* passing one(i.e. 0) as argument configures base and ceiling for -* frame buffer one(i.e FB1). -* -* \return None. -* -**/ -void RasterDMAFBConfig(unsigned int baseAddr, unsigned int base, - unsigned int ceiling, unsigned int flag) -{ - if(flag == 0) - { - HWREG(baseAddr + LCDC_LCDDMA_FB0_BASE) = base; - HWREG(baseAddr + LCDC_LCDDMA_FB0_CEILING) = ceiling; - } - else - { - HWREG(baseAddr + LCDC_LCDDMA_FB1_BASE) = base; - HWREG(baseAddr + LCDC_LCDDMA_FB1_CEILING) = ceiling; - } -} -/** -* \brief This function clear status interrupt status register. -* -* \param baseAddr is the Memory Address of the LCD Module. -* -* \param flag is the value which detemines status of which -* interrupt to be cleared.\n -* -* flag can take following values.\n -* -* RASTER_ACBIAS_COUNT_INT_STAT - ACBias Count interrupt status.\n -* RASTER_PALETTE_LOADED_INT_STAT - Palette loaded interrupt status.\n -* RASTER_SYNC_LOST_INT_STAT - Sync lost interrupt status.\n -* RASTER_FIFO_UNDRFLOW_INT_STAT - FIFO underflow interrupt status.\n -* RASTER_FRAME_DONE_INT_STAT - frame done interrupt status.\n -* RASTER_END_OF_FRAME0_INT_STAT - end of frame 0 interrupt status.\n -* RASTER_END_OF_FRAME1_INT_STAT - end of frame 1 interrupt status.\n -* RASTER_DONE_INT - Raster Done interrupt.\n -* -* \return Interrupt status of Raster for AM335x or am1808 based on rev id. -* -**/ -unsigned int RasterClearGetIntStatus(unsigned int baseAddr, - unsigned int flag) -{ - unsigned int saveStatus = 0; - unsigned int version; - - version = LCDVersionGet(); - - if(RASTER_REV_AM335X == version) - { - saveStatus = HWREG(baseAddr + LCDC_IRQSTATUS) & flag; - - HWREG(baseAddr + LCDC_IRQSTATUS) = saveStatus; - } - else if(RASTER_REV_AM1808 == version) - { - saveStatus = HWREG(baseAddr + LCDC_LCD_STAT) & flag; - - HWREG(baseAddr + LCDC_LCD_STAT) = saveStatus; - } - else - { - ;/*Do nothing */ - } - - return (saveStatus); -} -/** -* \brief This function enables raster subpanel feature -* -* \baseAddr is the Memory Address of the LCD Module. -* -* \return none -* -**/ -void RasterSubPanelEnable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_RASTER_SUBPANEL) |= LCDC_RASTER_SUBPANEL_SPEN; -} - -/** -* \brief This function disables raster subpanel feature -* -* \baseAddr is the Memory Address of the LCD Module. -* -* \return none -* -**/ -void RasterSubPanelDisable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_RASTER_SUBPANEL) &= ~LCDC_RASTER_SUBPANEL_SPEN; -} - -/** -* \brief This function configures raster subpanel feature -* -* \baseAddr is the Memory Address of the LCD Module. -* -* \hols is the value indicates the position of subpanel compared to the -* LPPT(lines per panel threshold) value. -* -* \lppt lines per panel threshold defines the number of lines to be -* refreshed -* -* \dpd DPD(default pixel data) defines the default value of the pixel -* data sent to the panel for the lines until LPPT is reached or -* after passing the LPPT. -* -* \return none -* -**/ -void RasterSubPanelConfig(unsigned int baseAddr, unsigned int hols, - unsigned int lppt, unsigned int dpd) -{ - unsigned int version; - - version = LCDVersionGet(); - - if(RASTER_REV_AM335X == version) - { - HWREG(baseAddr + LCDC_RASTER_SUBPANEL) &= 0xffff0000; - - HWREG(baseAddr + LCDC_RASTER_SUBPANEL) = ((dpd & 0xffff)); - - HWREG(baseAddr + LCDC_RASTER_SUBPANEL2) &= 0xff00ffff; - - HWREG(baseAddr + LCDC_RASTER_SUBPANEL2) = ((dpd & 0xff0000) >> 15); - - HWREG(baseAddr + LCDC_RASTER_SUBPANEL) &= 0xfc00ffff; - - HWREG(baseAddr + LCDC_RASTER_SUBPANEL) |= ((lppt & 0x3ff) << - LCDC_RASTER_SUBPANEL_LPPT_SHIFT); - - HWREG(baseAddr + LCDC_RASTER_SUBPANEL2) &= 0xfffffeff; - - HWREG(baseAddr + LCDC_RASTER_SUBPANEL2) |= ((lppt & 0x400) >> 11) - << LCDC_RASTER_SUBPANEL_LPPT_B10_SHIFT; - - } - else if(RASTER_REV_AM1808 == version) - { - - HWREG(baseAddr + LCDC_RASTER_SUBPANEL) &= 0xfc00ffff; - - HWREG(baseAddr + LCDC_RASTER_SUBPANEL) |= (lppt << - LCDC_RASTER_SUBPANEL_LPPT_SHIFT); - - HWREG(baseAddr + LCDC_RASTER_SUBPANEL) &= 0xffff000f; - HWREG(baseAddr + LCDC_RASTER_SUBPANEL) |= (dpd<< - LCDC_RASTER_SUBPANEL_DPD_SHIFT); - } - else - { - ;/* Do nothing */ - } - - HWREG(baseAddr + LCDC_RASTER_SUBPANEL) &= 0xDfffffff; - HWREG(baseAddr + LCDC_RASTER_SUBPANEL) |= (hols << - LCDC_RASTER_SUBPANEL_HOLS_SHIFT); - -} - -/** -* \brief This function Enables the clock for the DMA submodule,LIDD submodule and -* for the core(which encompasses the Raster active matrix and Passive matrix). -* -* \baseAddr is the Memory Address of the LCD Module. -* -* \return none -* -* This API is only supported for AM335x raster. -**/ -void RasterClocksEnable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_CLKC_ENABLE) = (LCDC_CLKC_ENABLE_CORE | - LCDC_CLKC_ENABLE_DMA | - LCDC_CLKC_ENABLE_LIDD); -} - -/** -* \brief This function enables software clock for the raster,which encompasses -* the raster active matrix and passive matrix logic. -* -* \baseAddr is the Memory Address of the LCD Module. -* -* \return none -* -* This API is only supported for AM335x raster. -**/ -void RasterSoftWareClkEnable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_CLKC_ENABLE) |= LCDC_CLKC_ENABLE_CORE; -} - -/** -* \brief This function disables software clock for the raster,which encompasses -* the raster active matrix and passive matrix logic. -* -* \baseAddr is the Memory Address of the LCD Module. -* -* \return none -* -* This API is only supported for AM335x raster. -**/ -void RasterSoftWareClkDisable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_CLKC_ENABLE) &= ~LCDC_CLKC_ENABLE_CORE; -} - -/** -* \brief This function enables software clock for the DMA submodule. -* -* \baseAddr is the Memory Address of the LCD Module. -* -* \return none -* -* This API is only supported for AM335x raster. -**/ -void RasterDMASoftWareClkEnable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_CLKC_ENABLE) |= LCDC_CLKC_ENABLE_DMA; -} - -/** -* \brief This function disables software clock for the DMA submodule. -* -* \baseAddr is the Memory Address of the LCD Module. -* -* \return none -* -* This API is only supported for AM335x raster. -**/ -void RasterDMASoftWareClkDisable(unsigned int baseAddr) -{ - HWREG(baseAddr + LCDC_CLKC_ENABLE) &= ~LCDC_CLKC_ENABLE_DMA; -} - -/** -* \brief This function dose Software Resets for LCD module or DMA submodule or -* Core which encompasses Raster Active Matrix and Passive Matrix -* logic based on the "flag" argument passed to this function. -* -* \baseAddr is the Memory Address of the LCD Module. -* \flag It is the value which determines which module to be software -* reseted.\n -* -* flag can take following macros.\n -* -* RASTER_CORE_RESET - Software reset for core.\n -* RASTER_DMA_RESET - Software reset for DMA module.\n -* RASTER_LCD_MODULE_RESET - Software reset for LCD module.\n -* -* \return none -* -* This API is only supported for AM335x raster. -**/ -void RasterSoftWareResetControlEnable(unsigned int baseAddr, unsigned int flag) -{ - if(RASTER_CORE_RESET == flag) - { - HWREG(baseAddr + LCDC_CLKC_RESET) |= LCDC_CLKC_RESET_CORE; - } - else if(RASTER_DMA_RESET == flag) - { - HWREG(baseAddr + LCDC_CLKC_RESET) |= LCDC_CLKC_RESET_DMA; - } - else if(RASTER_LCD_MODULE_RESET == flag) - { - HWREG(baseAddr + LCDC_CLKC_RESET) |= LCDC_CLKC_RESET_MAIN; - } - else - { - ;/* Do nothing */ - } -} - -/** -* \brief This function disables Software Resets for LCD module or DMA submodule -* or Core which encompasses Raster Active Matrix and Passive Matrix -* logic based on the "flag" argument passed to this function. -* -* \baseAddr is the Memory Address of the LCD Module. -* \flag It is the value which determines which module to be software -* reseted.\n -* -* flag can take following macros.\n -* -* RASTER_CORE_RESET - Software reset for core.\n -* RASTER_DMA_RESET - Software reset for DMA module.\n -* RASTER_LCD_MODULE_RESET - Software reset for LCD module.\n -* -* \return none -* -* This API is only supported for AM335x raster. -**/ -void RasterSoftWareResetControlDisable(unsigned int baseAddr, unsigned int flag) -{ - if(RASTER_CORE_RESET == flag) - { - HWREG(baseAddr + LCDC_CLKC_RESET) &= ~LCDC_CLKC_RESET_CORE; - } - else if(RASTER_DMA_RESET == flag) - { - HWREG(baseAddr + LCDC_CLKC_RESET) &= ~LCDC_CLKC_RESET_DMA; - } - else if(RASTER_LCD_MODULE_RESET == flag) - { - HWREG(baseAddr + LCDC_CLKC_RESET) &= ~LCDC_CLKC_RESET_MAIN; - } - else - { - ;/*Do nothing */ - } -} - -/** -* \brief This function Acknowledges interrupt. -* -* \param baseAddr is the Memory address of the LCD instace used. -* \param flag is the value,which when written to EOI register -* acknowledges interrupt. -* -* \returns None -* -* This API is only supported for AM335x raster. -* -**/ -void RasterEndOfInterrupt(unsigned int baseAddr, unsigned int flag) -{ - HWREG(baseAddr + LCDC_IRQEOI_VECTOR) = flag; -} - -/** -* \brief This function sets the priority for the L3 OCP Master Bus. -* -* \param baseAddr is the Memory address of the LCD instace used. -* \param flag is the value which sets the priority. -* -* \returns None -* -* This API is only supported for AM335x raster. -**/ -void RasterDmaMasterPrioritySet(unsigned int baseAddr, unsigned int flag) -{ - HWREG(baseAddr + LCDC_LCDDMA_CTRL) = flag; -} - -/** -* \brief This function configures raster in different standby modes based -* on the flag argument passed to it. -* -* \param baseAddr is the Memory address of the LCD instace used. -* \param flag is the value which determines type of standby -* mode.\n -* -* flag can take following values.\n -* -* RASTER_FORCE_STAND_BY.\n -* RASTER_NO_STAND_BY.\n -* RASTER_SMART_STAND_BY.\n -* RASTER_SMART_STAND_BY_WAKE_UP.\n -* -* \returns None -* -* This API is only supported for AM335x raster. -**/ -void RasterStandbyModeConfig(unsigned int baseAddr, unsigned int flag) -{ - HWREG(baseAddr + LCDC_SYSCONFIG) &= 0xffffffcf; - HWREG(baseAddr + LCDC_SYSCONFIG) |= flag; -} - -/** -* \brief This function configures raster in different Idle modes based -* on the flag argument passed to it. -* -* \param baseAddr is the Memory address of the LCD instace used. -* \param flag is the value which determines type of Idle -* mode.\n -* -* flag can take following macros.\n -* -* RASTER_FORCE_IDLE_MODE.\n -* RASTER_NO_IDLE_MODE.\n -* RASTER_SMART_IDLE_MODE.\n -* RASTER_SMART_IDLE_WAKE_UP.\n -* -* \returns None -* -* This API is only supported for AM335x raster. -**/ -void RasterIdleModeConfig(unsigned int baseAddr, unsigned int flag) -{ - HWREG(baseAddr + LCDC_SYSCONFIG) &= 0xfffffff3; - HWREG(baseAddr + LCDC_SYSCONFIG) |= flag; -} - -/** -* \brief This function saves the context of Raster registers. -* This is useful in power management, where the power supply to raster -* controller will be cut off. -* -* \param baseAddr Memory address of the LCD instace used -* \param contextPtr The pointer to the structure where the context has to be -* saved. -* \returns None -**/ -void RasterContextSave(unsigned int baseAddr, RASTERCONTEXT *contextPtr) -{ - contextPtr->clkcEnable = HWREG(baseAddr + LCDC_CLKC_ENABLE); - contextPtr->lcdCtrl = HWREG(baseAddr + LCDC_LCD_CTRL); - contextPtr->lcddmaCtrl = HWREG(baseAddr + LCDC_LCDDMA_CTRL); - contextPtr->rasterTiming2 = HWREG(baseAddr + LCDC_RASTER_TIMING_2); - contextPtr->rasterTiming0 = HWREG(baseAddr + LCDC_RASTER_TIMING_0); - contextPtr->rasterTiming1 = HWREG(baseAddr + LCDC_RASTER_TIMING_1); - contextPtr->rasterCtrl = HWREG(baseAddr + LCDC_RASTER_CTRL); - contextPtr->irqEnableSet = HWREG(baseAddr + LCDC_IRQENABLE_SET); - contextPtr->lcddmaFb0Base = HWREG(baseAddr + LCDC_LCDDMA_FB0_BASE); - contextPtr->lcddmaFb0Ceiling = HWREG(baseAddr + LCDC_LCDDMA_FB0_CEILING); - contextPtr->lcddmaFb1Base = HWREG(baseAddr + LCDC_LCDDMA_FB1_BASE); - contextPtr->lcddmaFb1Ceiling = HWREG(baseAddr + LCDC_LCDDMA_FB1_CEILING); -} - -/** -* \brief This function restores the context of Raster registers. -* This is useful in power management, where the power supply to raster -* controller will be cut off. -* -* \param baseAddr Memory address of the LCD instace used -* \param contextPtr The pointer to the structure where the context has to be -* restored from -* \returns None -**/ -void RasterContextRestore(unsigned int baseAddr, RASTERCONTEXT *contextPtr) -{ - HWREG(baseAddr + LCDC_CLKC_ENABLE) = contextPtr->clkcEnable; - HWREG(baseAddr + LCDC_LCD_CTRL) = contextPtr->lcdCtrl; - HWREG(baseAddr + LCDC_LCDDMA_CTRL) = contextPtr->lcddmaCtrl; - HWREG(baseAddr + LCDC_RASTER_TIMING_2) = contextPtr->rasterTiming2; - HWREG(baseAddr + LCDC_RASTER_TIMING_0) = contextPtr->rasterTiming0; - HWREG(baseAddr + LCDC_RASTER_TIMING_1) = contextPtr->rasterTiming1; - HWREG(baseAddr + LCDC_RASTER_CTRL) = contextPtr->rasterCtrl; - HWREG(baseAddr + LCDC_IRQENABLE_SET) = contextPtr->irqEnableSet; - HWREG(baseAddr + LCDC_LCDDMA_FB0_BASE) = contextPtr->lcddmaFb0Base; - HWREG(baseAddr + LCDC_LCDDMA_FB0_CEILING) = contextPtr->lcddmaFb0Ceiling; - HWREG(baseAddr + LCDC_LCDDMA_FB1_BASE) = contextPtr->lcddmaFb1Base; - HWREG(baseAddr + LCDC_LCDDMA_FB1_CEILING) = contextPtr->lcddmaFb1Ceiling; -} - -/***************************** End Of File ***********************************/ diff --git a/lib/tiam1808/drivers/tsc_adc.c b/lib/tiam1808/drivers/tsc_adc.c deleted file mode 100644 index 3d372c74c..000000000 --- a/lib/tiam1808/drivers/tsc_adc.c +++ /dev/null @@ -1,1684 +0,0 @@ -/** - * \file tsc_adc.c - * - * \brief TOUCH SCREEN APIs. - * - * This file contains the device abstraction layer APIs for - * Touch Screen. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#include "hw_types.h" -#include "tsc_adc.h" - -/************************************************************************* - API FUNCTION DEFINITIONS -*************************************************************************/ - -/** - * \brief This API gets the revision information of the Touch Screen Module. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * - * \return returns the revision ID. - * - **/ -unsigned int TSCADCGetRevision(unsigned int baseAdd) -{ - return (HWREG(baseAdd + TSC_ADC_SS_REVISION )); -} - -/** - * \brief This API sets the idle mode of TSCADC Module. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param idleMode idle mode to set.\n - * - * idle mode can take following macros.\n - * - * 0 - TSCADC_FORCE_IDLE - * 1 - TSCADC_NO_IDLE - * 2 - TSCADC_SMART_IDLE - * 3 - TSCADC_SMART_IDLE_WAKEUP - * - * \return None - * - **/ -void TSCADCIdleModeSet(unsigned int baseAdd, unsigned int idleMode) -{ - HWREG(baseAdd + TSC_ADC_SS_SYSCONFIG) &= - ~TSC_ADC_SS_SYSCONFIG_IDLEMODE; - - HWREG(baseAdd + TSC_ADC_SS_SYSCONFIG) |= (idleMode << - TSC_ADC_SS_SYSCONFIG_IDLEMODE_SHIFT); -} - -/** - * \brief This API sets the EOI Control for TSCADC Module. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param irq_EOC End Of Control Interrupt. - * - * \return None - * - **/ -void TSCADCEOIControl(unsigned int baseAdd, unsigned int irq_EOC) -{ - HWREG(baseAdd + TSC_ADC_SS_IRQ_EOI) = irq_EOC; -} - -/** - * \brief This function asserts the specified interrupts. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param intFlag It determines which interrupts needs to be asserted.\n - * - * intFlag can take following macro values.\n - * - * TSCADC_ASYNC_HW_PEN_EVENT_INT.\n - * TSCADC_SYNC_PEN_EVENT_INT.\n - * TSCADC_FIFO0_UNDER_FLOW_INT.\n - * TSCADC_FIFO1_UNDER_FLOW_INT.\n - * TSCADC_END_OF_SEQUENCE_INT.\n - * TSCADC_FIFO0_THRESHOLD_INT.\n - * TSCADC_FIFO1_THRESHOLD_INT.\n - * TSCADC_FIFO0_OVER_RUN_INT.\n - * TSCADC_FIFO1_OVER_RUN_INT.\n - * TSCADC_OUT_OF_RANGE_INT.\n - * TSCADC_PEN_UP_EVENT_INT.\n - * - * \return None - * - **/ -void TSCADCRawIntStatusSet(unsigned int baseAdd, unsigned int intFlag) -{ - HWREG(baseAdd + TSC_ADC_SS_IRQSTATUS_RAW) |= intFlag; -} - -/** - * \brief This API returns the required interrupt pending status. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param intFlag It is status of the required interrupts to be read.\n - * - * intFlag can take following macro values.\n - * - * TSCADC_ASYNC_HW_PEN_EVENT_INT.\n - * TSCADC_SYNC_PEN_EVENT_INT.\n - * TSCADC_FIFO0_UNDER_FLOW_INT.\n - * TSCADC_FIFO1_UNDER_FLOW_INT.\n - * TSCADC_END_OF_SEQUENCE_INT.\n - * TSCADC_FIFO0_THRESHOLD_INT.\n - * TSCADC_FIFO1_THRESHOLD_INT.\n - * TSCADC_FIFO0_OVER_RUN_INT.\n - * TSCADC_FIFO1_OVER_RUN_INT.\n - * TSCADC_OUT_OF_RANGE_INT.\n - * TSCADC_PEN_UP_EVENT_INT.\n - * - * \return Raw status of the specified interrupts. - * - **/ -unsigned int TSCADCRawIntStatusRead(unsigned int baseAdd, unsigned int intFlag) -{ - return ((HWREG(baseAdd + TSC_ADC_SS_IRQSTATUS_RAW) & intFlag)); -} - -/** - * \brief This API returns the pending interrupt status. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * - **/ -unsigned int TSCADCRawIntStatus(unsigned int baseAdd) -{ - return ((HWREG(baseAdd + TSC_ADC_SS_IRQSTATUS_RAW))); -} - -/** - * \brief This API clears the status of the specified interrupts. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param intFlag It determines which interrupts status need to be - * cleared.\n - * - * intFlag can take following macro values.\n - * - * TSCADC_ASYNC_HW_PEN_EVENT_INT.\n - * TSCADC_SYNC_PEN_EVENT_INT.\n - * TSCADC_FIFO0_UNDER_FLOW_INT.\n - * TSCADC_FIFO1_UNDER_FLOW_INT.\n - * TSCADC_END_OF_SEQUENCE_INT.\n - * TSCADC_FIFO0_THRESHOLD_INT.\n - * TSCADC_FIFO1_THRESHOLD_INT.\n - * TSCADC_FIFO0_OVER_RUN_INT.\n - * TSCADC_FIFO1_OVER_RUN_INT.\n - * TSCADC_OUT_OF_RANGE_INT.\n - * TSCADC_PEN_UP_EVENT_INT.\n - * - * \return None - * - **/ -void TSCADCIntStatusClear(unsigned int baseAdd, unsigned int intFlag) -{ - HWREG(baseAdd + TSC_ADC_SS_IRQSTATUS) = intFlag; -} - -/** - * \brief This API returns the status of the specified interrupts. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param intFlag It specifies the interrupts whose status needs to - * returned. - * - * intFlag can take following macro values.\n - * - * TSCADC_ASYNC_HW_PEN_EVENT_INT.\n - * TSCADC_SYNC_PEN_EVENT_INT.\n - * TSCADC_FIFO0_UNDER_FLOW_INT.\n - * TSCADC_FIFO1_UNDER_FLOW_INT.\n - * TSCADC_END_OF_SEQUENCE_INT.\n - * TSCADC_FIFO0_THRESHOLD_INT.\n - * TSCADC_FIFO1_THRESHOLD_INT.\n - * TSCADC_FIFO0_OVER_RUN_INT.\n - * TSCADC_FIFO1_OVER_RUN_INT.\n - * TSCADC_OUT_OF_RANGE_INT.\n - * TSCADC_PEN_UP_EVENT_INT.\n - * - * \return The interrupt status of specified interrupts. - * - **/ -unsigned int TSCADCIntStatusRead(unsigned int baseAdd, unsigned int intFlag) -{ - return ((HWREG(baseAdd + TSC_ADC_SS_IRQSTATUS) & intFlag)); -} - -/** - * \brief This API returns the interrupt status. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * - * \return The status of the interrupts. - * - **/ -unsigned int TSCADCIntStatus(unsigned int baseAdd) -{ - return (HWREG(baseAdd + TSC_ADC_SS_IRQSTATUS)); -} - -/** - * \brief This API enables the interrupt for the given event. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param event event for which the interrupt to be enabled. - * - * event can take following macro values.\n - * - * TSCADC_ASYNC_HW_PEN_EVENT_INT.\n - * TSCADC_SYNC_PEN_EVENT_INT.\n - * TSCADC_FIFO0_UNDER_FLOW_INT.\n - * TSCADC_FIFO1_UNDER_FLOW_INT.\n - * TSCADC_END_OF_SEQUENCE_INT.\n - * TSCADC_FIFO0_THRESHOLD_INT.\n - * TSCADC_FIFO1_THRESHOLD_INT.\n - * TSCADC_FIFO0_OVER_RUN_INT.\n - * TSCADC_FIFO1_OVER_RUN_INT.\n - * TSCADC_OUT_OF_RANGE_INT.\n - * TSCADC_PEN_UP_EVENT_INT.\n - * - * \return None - * - **/ -void TSCADCEventInterruptEnable(unsigned int baseAdd, unsigned int event) -{ - HWREG(baseAdd + TSC_ADC_SS_IRQENABLE_SET) |= event; -} - -/** - * \brief This API disables the interrupt for the given event. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param event Event for which the interrupt to be disabled. - * - * event can take following macro values.\n - * - * TSCADC_ASYNC_HW_PEN_EVENT_INT.\n - * TSCADC_SYNC_PEN_EVENT_INT.\n - * TSCADC_FIFO0_UNDER_FLOW_INT.\n - * TSCADC_FIFO1_UNDER_FLOW_INT.\n - * TSCADC_END_OF_SEQUENCE_INT.\n - * TSCADC_FIFO0_THRESHOLD_INT.\n - * TSCADC_FIFO1_THRESHOLD_INT.\n - * TSCADC_FIFO0_OVER_RUN_INT.\n - * TSCADC_FIFO1_OVER_RUN_INT.\n - * TSCADC_OUT_OF_RANGE_INT.\n - * TSCADC_PEN_UP_EVENT_INT.\n - * - * \return None - * - **/ -void TSCADCEventInterruptDisable(unsigned int baseAdd, unsigned int event) -{ - HWREG(baseAdd + TSC_ADC_SS_IRQENABLE_CLR) = event; -} - -/** - * \brief This API enables/disables the Wake Up Generation for HW Pen event. - * Enabling the Wake Up Generation shall generate an asynchronous - * Wake UP using the SWAKEup Protocol if it detects a touch - * even if the Module and the clocks are off. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param enableWakeUp Whether Wake Up Generation for HW Pen Event - * is to be enabled.\n - * - * enableWakeUp can take following values.\n - * - * TSCADC_WAKEUP_DISABLE - Wakeup is disabled.\n - * TSCADC_WAKEUP_ENABLE - Wakeup is enabled .\n - * - * \return None - * - **/ -void TSCADCWakeUpPenEventConfig(unsigned int baseAdd, unsigned int enableWakeUp) -{ - HWREG(baseAdd + TSC_ADC_SS_IRQWAKEUP) = enableWakeUp; -} - -/** - * \brief This API enables the DMA for the given FIFO. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param fifoSel FIFO for which the DMA to be enabled.\n - * - * fifoSel can take following macros.\n - * - * TSCADC_FIFO_0.\n - * TSCADC_FIFO_1.\n - * - * \return None - * - **/ -void TSCADCDMAFIFOEnable(unsigned int baseAdd, unsigned char fifoSel) -{ - HWREG(baseAdd + TSC_ADC_SS_DMAENABLE_SET) |= 0x1 << fifoSel; -} - -/** - * \brief This API Disables the DMA for the given FIFO. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param fifoSel FIFO for which the DMA to be Disabled. - * - * fifoSel can take following macros.\n - * - * TSCADC_FIFO_0.\n - * TSCADC_FIFO_1.\n - * - * \return None - * - **/ -void TSCADCDMAFIFODisable(unsigned int baseAdd, unsigned char fifoSel) -{ - HWREG(baseAdd + TSC_ADC_SS_DMAENABLE_CLR) |= 0x1 << fifoSel; -} - -/** - * \brief This API reads the DMA enable status for the given FIFO. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param fifoSel FIFO for which the DMA status to be read. - * - * fifoSel can take following values.\n - * - * TSCADC_FIFO_0.\n - * TSCADC_FIFO_1.\n - * - * \return returns the DMA Enable Status - * TRUE - Enabled - * FALSE - Disabled - * - **/ -unsigned int TSCADCIsDMAFIFOEnabled(unsigned int baseAdd, unsigned int fifoSel) -{ - return ((HWREG(baseAdd + TSC_ADC_SS_DMAENABLE_SET) >> fifoSel) & 0x1); -} - -/** - * \brief This API enables/disables the HW event preemption. - * - * \param baseAdd Base Address of the TouchScreen Module - * Registers. - * \param enableHWEventPreempt whether Hardware Event Preemption is to - * be enabled. - * - * enableHWEventPreempt can take following macros.\n - * - * 0 - Preemption is disabled.\n - * 1 - Preemption is Enabled.\n - * - * \return None - * - **/ -void TSCADCConfigHWEventPrempt(unsigned int baseAdd, unsigned int enableHWEventPreempt) -{ - HWREG(baseAdd + TSC_ADC_SS_CTRL) &= - ~TSC_ADC_SS_CTRL_HW_EVENT_MAPPING; - - HWREG(baseAdd + TSC_ADC_SS_CTRL) |= enableHWEventPreempt << - TSC_ADC_SS_CTRL_HW_EVENT_MAPPING_SHIFT; -} - -/** - * \brief This API maps the HW event to Pen Touch or Hardware Event Input - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param hwEvent Input Event to which the HW event is to be mapped. Possible - * Events are.\n - * - * hwEvent can take following macros.\n - * - * TSCADC_HW_INPUT_EVENT.\n - * TSCADC_PEN_TOUCH.\n - * - * \return None - * - **/ -void TSCADCHWEventMapSet(unsigned int baseAdd, unsigned int hwEvent) -{ - HWREG(baseAdd + TSC_ADC_SS_CTRL) &= ~TSC_ADC_SS_CTRL_HW_EVENT_MAPPING; - HWREG(baseAdd + TSC_ADC_SS_CTRL) |= hwEvent << - TSC_ADC_SS_CTRL_HW_EVENT_MAPPING_SHIFT; -} - -/** - * \brief This API Enables/Disables the Touch Screen Transistors - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param enableTSTransistor whether the Touch Screen Transistors are to be - * Enabled.\n - * - * enableTSTransistor can take following values.\n - * - * TSCADC_TRANSISTOR_DISABLE - Disables the transistor.\n - * TSCADC_TRANSISTOR_ENABLE - Enables the transistor.\n - * - * \return None - * - **/ -void TSCADCTSTransistorConfig(unsigned int baseAdd, unsigned int enableTSTransistor) -{ - HWREG(baseAdd + TSC_ADC_SS_CTRL) &= ~TSC_ADC_SS_CTRL_TOUCH_SCREEN_ENABLE; - - HWREG(baseAdd + TSC_ADC_SS_CTRL) |= enableTSTransistor << - TSC_ADC_SS_CTRL_TOUCH_SCREEN_ENABLE_SHIFT; -} - -/** - * \brief This API configures the Touch Screen for 4 Wire/5 Wire mode - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param tsMode Selects the TS mode to be configured.\n - * - * tsMode can take following macros.\n - * - * TSCADC_FOUR_WIRE_MODE.\n - * TSCADC_FIVE_WIRE_MODE.\n - * TSCADC_GENERAL_PURPOSE_MODE.\n - * - * \return None - * - **/ -void TSCADCTSModeConfig(unsigned int baseAdd, unsigned int tsMode) -{ - HWREG(baseAdd + TSC_ADC_SS_CTRL) &= ~TSC_ADC_SS_CTRL_AFE_PEN_CTRL; - - HWREG(baseAdd + TSC_ADC_SS_CTRL) |= tsMode << - TSC_ADC_SS_CTRL_AFE_PEN_CTRL_SHIFT; -} - -/** - * \brief This API sets the ADC Power Down - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * - * \return None - * - **/ -void TSCADCSetADCPowerDown(unsigned int baseAdd) -{ - HWREG(baseAdd + TSC_ADC_SS_CTRL) &= ~TSC_ADC_SS_CTRL_POWER_DOWN; - HWREG(baseAdd + TSC_ADC_SS_CTRL) |= 1 << TSC_ADC_SS_CTRL_POWER_DOWN; -} - -/** - * \brief This API sets the ADC Power Up - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * - * \return None - * - **/ -void TSCADCSetADCPowerUp(unsigned int baseAdd) -{ - HWREG(baseAdd + TSC_ADC_SS_CTRL) &= ~TSC_ADC_SS_CTRL_POWER_DOWN; -} - -/** - * \brief This API select the ADC BIAS for the AFE - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param adcBiasSel Select internal or external ADC Bias. - * - * adcBiasSel can take following values.\n - * - * TSCADC_INTERNAL_AC_BIAS - Internal ac bias.\n - * TSCADC_EXTERNAL_AC_BIAS - External ac bias.\n - * \return None - * - **/ -void TSCADCBiasConfig(unsigned int baseAdd, unsigned int adcBiasSel) -{ - HWREG(baseAdd + TSC_ADC_SS_CTRL) &= ~TSC_ADC_SS_CTRL_ADC_BIAS_SELECT; - HWREG(baseAdd + TSC_ADC_SS_CTRL) |= adcBiasSel << - TSC_ADC_SS_CTRL_ADC_BIAS_SELECT_SHIFT; -} - -/** - * \brief This API enables the protection of Step Config Registers. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * - * \return None - * - **/ -void TSCADCStepConfigProtectionEnable(unsigned int baseAdd) -{ - HWREG(baseAdd + TSC_ADC_SS_CTRL) &= - ~TSC_ADC_SS_CTRL_STEPCONFIG_WRITEPROTECT_N; -} - -/** - * \brief This API disables the protection of Step Config Registers. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * - * \return None - * - **/ -void TSCADCStepConfigProtectionDisable(unsigned int baseAdd) -{ - HWREG(baseAdd + TSC_ADC_SS_CTRL) |= - TSC_ADC_SS_CTRL_STEPCONFIG_WRITEPROTECT_N; -} - -/** - * \brief This API enables/disables the channel ID store along with the - * captured ADC data - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param enableStepIDTag Whether or not step ID is to be stored. - * - * \return None - * - **/ -void TSCADCStepIDTagConfig(unsigned int baseAdd, unsigned int enableStepIDTag) -{ - HWREG(baseAdd + TSC_ADC_SS_CTRL) &= ~TSC_ADC_SS_CTRL_STERP_ID_TAG; - HWREG(baseAdd + TSC_ADC_SS_CTRL) |= enableStepIDTag << - TSC_ADC_SS_CTRL_STERP_ID_TAG_SHIFT; -} - -/** - * \brief This API Enables/Disables the TSCADC Module - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param enableModule Whether the module is to be enabled. - * - * enableModule can take following values.\n - * - * TSCADC_MODULE_DISABLE - Disables module.\n - * TSCADC_MODULE_ENABLE - Enables the module.\n - * - * \return None - * - **/ -void TSCADCModuleStateSet(unsigned int baseAdd, unsigned int enableModule) -{ - HWREG(baseAdd + TSC_ADC_SS_CTRL) &= ~TSC_ADC_SS_CTRL_ENABLE; - HWREG(baseAdd + TSC_ADC_SS_CTRL) |= enableModule; -} - -/** - * \brief This API reads the PEN_IRQ Status of the Sequencer - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param penIRQSel Penirq for which the status is to be read. - * - * penIRQSel can take following macros.\n - * - * TSCADC_PEN_IRQ_0.\n - * TSCADC_PEN_IRQ_1.\n - * - * \return returns the IRQ status - * - **/ -unsigned int TSCADCSequencerPenIrqStatusRead(unsigned int baseAdd, - unsigned int penIRQSel) -{ - if (TSCADC_PEN_IRQ_0 == penIRQSel) - { - return ((HWREG(baseAdd + TSC_ADC_SS_ADCSTAT) & - TSC_ADC_SS_ADCSTAT_PEN_IRQ0) - >> TSC_ADC_SS_ADCSTAT_PEN_IRQ0_SHIFT); - } - else - { - return ((HWREG(baseAdd + TSC_ADC_SS_ADCSTAT) & - TSC_ADC_SS_ADCSTAT_PEN_IRQ1) - >> TSC_ADC_SS_ADCSTAT_PEN_IRQ1_SHIFT); - } -} - -/** - * \brief This API reads the Sequencer Busy Status - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * - * \return returns the Sequencer Status - * - **/ -unsigned int TSCADCSequencerFSMBusyStatus(unsigned int baseAdd) -{ - return ((HWREG(baseAdd + TSC_ADC_SS_ADCSTAT) & - TSC_ADC_SS_ADCSTAT_FSM_BUSY ) >> - TSC_ADC_SS_ADCSTAT_FSM_BUSY_SHIFT); -} - -/** - * \brief This API reads the STEP ID currently being executed by - * the sequencer - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * - * \return returns the Step ID - * - **/ -unsigned int TSCADCSequencerCurrentStepID(unsigned int baseAdd) -{ - return (HWREG(baseAdd + TSC_ADC_SS_ADCSTAT) & TSC_ADC_SS_ADCSTAT_STEPID); -} - -/** - * \brief This API sets the Minimum amd Maximum values for ADC output data - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param lowVal Minimum threshold value for ADC Output. - * \param highVal Maximum threshold value for ADC output. - * - * \return none - * - **/ -void TSCADCOutputRangeConfig(unsigned int baseAdd, unsigned short lowVal, - unsigned short highVal) -{ - HWREG(baseAdd + TSC_ADC_SS_ADCRANGE) &= - ~TSC_ADC_SS_ADCRANGE_LOW_RANGE_DATA; - - HWREG(baseAdd + TSC_ADC_SS_ADCRANGE) |= lowVal; - - HWREG(baseAdd + TSC_ADC_SS_ADCRANGE) &= - ~TSC_ADC_SS_ADCRANGE_HIGH_RANGE_DATA; - - HWREG(baseAdd + TSC_ADC_SS_ADCRANGE) |= highVal << - TSC_ADC_SS_ADCRANGE_HIGH_RANGE_DATA_SHIFT; -} - -/** - * \brief This API sets the AFE clock - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param clkDiv Divider Value. - * - * \return none - * - **/ -void TSCADCConfigureAFEClock(unsigned int baseAdd, unsigned int moduleClk, - unsigned int inputClk) -{ - unsigned int clkDiv; - - clkDiv = moduleClk / inputClk; - - HWREG(baseAdd + TSC_ADC_SS_ADC_CLKDIV) &= - ~TSC_ADC_SS_ADC_CLKDIV_ADC_CLK_DIV; - - HWREG(baseAdd + TSC_ADC_SS_ADC_CLKDIV) = (clkDiv - 1); -} - -/** - * \brief This API Controls spare in values sent to AFE and captures spare out - * from AFE - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param spareOutputVal Spare Output Pins. - * \param spareInputVal Spare Input Pins. - * - * \return none - * - **/ -void TSCADCConfigureMisc(unsigned int baseAdd, unsigned char spareInputVal, - unsigned char spareOutputVal) -{ - HWREG(baseAdd + TSC_ADC_SS_ADC_MISC) &= - ~TSC_ADC_SS_ADC_MISC_AFE_SPARE_INPUT; - - HWREG(baseAdd + TSC_ADC_SS_ADC_MISC) |= spareInputVal; - - HWREG(baseAdd + TSC_ADC_SS_ADC_MISC) &= - ~TSC_ADC_SS_ADC_MISC_AFE_SPARE_OUTPUT; - - HWREG(baseAdd + TSC_ADC_SS_ADC_MISC) |= spareOutputVal << - TSC_ADC_SS_ADC_MISC_AFE_SPARE_OUTPUT_SHIFT; -} - -/** - * \brief This API Enables/Disables the given step. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param stepEn_Dis Enables/Disables the Step.\n - * - * stepEn_Dis can take '0' or '1' - * - * 0 - Disables the step.\n - * 1 - Enables the step.\n - * - * \param stepSel Select the step.\n - * - * stepSel can take any value bteween 1 to 16.\n - * - * \return none - * - **/ -void TSCADCConfigureStepEnable(unsigned int baseAdd, unsigned int stepSel, - unsigned int stepEn_Dis) -{ - HWREG(baseAdd + TSC_ADC_SS_STEPENABLE) &= ~(1 << stepSel); - HWREG(baseAdd + TSC_ADC_SS_STEPENABLE) |= stepEn_Dis << stepSel; -} - -/** - * \brief This API configures ADC to single ended or differential operation - * mode. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param mode It is the value which determines whether to - * configure ADC to single ended or differential - * operation mode. - * - * mode can take following macros. - * - * TSCADC_ADC_SINGLE_ENDED_OPER_MODE.\n - * TSCADC_ADC_DIFFERENTIAL_OPER_MODE.\n - * - * \return none - * - **/ -void TSCADCIdleStepOperationModeControl(unsigned int baseAdd, unsigned int mode) -{ - if(mode) - { - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) |= - TSC_ADC_SS_IDLECONFIG_DIFF_CNTRL; - } - else - { - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) &= - ~TSC_ADC_SS_IDLECONFIG_DIFF_CNTRL; - } -} - -/** - * \brief This API configure the reference volatage and Input to Idle Step - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param adcNegativeRef Selects the ADC Negative Reference Voltage.\n - * - * adcNegativeRef can take following values.\n - * - * TSCADC_NEGATIVE_REF_VSSA.\n - * TSCADC_NEGATIVE_REF_XNUR.\n - * TSCADC_NEGATIVE_REF_YNLR.\n - * TSCADC_NEGATIVE_REF_ADCREFM.\n - * - * \param adcPositiveInput Selects the Positive Analog Input Source.\n - * - * adcPositiveInput can take following values.\n - * - * TSCADC_POSITIVE_INP_CHANNEL1.\n - * TSCADC_POSITIVE_INP_CHANNEL2.\n - * TSCADC_POSITIVE_INP_CHANNEL3.\n - * TSCADC_POSITIVE_INP_CHANNEL4.\n - * TSCADC_POSITIVE_INP_CHANNEL5.\n - * TSCADC_POSITIVE_INP_CHANNEL6.\n - * TSCADC_POSITIVE_INP_CHANNEL7.\n - * TSCADC_POSITIVE_INP_CHANNEL8.\n - * TSCADC_POSITIVE_INP_ADCREFM.\n - * - * \param adcNegativeInput Selects the Negative Analog Input Source.\n - * - * adcNegativeInput can take following values.\n - * - * TSCADC_NEGATIVE_INP_CHANNEL1.\n - * TSCADC_NEGATIVE_INP_CHANNEL2.\n - * TSCADC_NEGATIVE_INP_CHANNEL3.\n - * TSCADC_NEGATIVE_INP_CHANNEL4.\n - * TSCADC_NEGATIVE_INP_CHANNEL5.\n - * TSCADC_NEGATIVE_INP_CHANNEL6.\n - * TSCADC_NEGATIVE_INP_CHANNEL8.\n - * TSCADC_NEGATIVE_INP_ADCREFRM.\n - * - * \param adcPositiveRef Selects the ADC Positive Reference Voltage.\n - * - * adcPositiveRef can take following values.\n - * - * TSCADC_POSITIVE_REF_VDDA.\n - * TSCADC_POSITIVE_REF_XNUR.\n - * TSCADC_POSITIVE_REF_YNLR.\n - * TSCADC_POSITIVE_REF_ADCREFP.\n - * - * \return none - * - **/ -void TSCADCIdleStepConfig(unsigned int baseAdd, unsigned int adcNegativeRef, - unsigned int adcPositiveInp, unsigned int adcNegativeInp, - unsigned int adcPositiveRef) -{ - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) &= - ~TSC_ADC_SS_IDLECONFIG_SEL_RFM_SWC; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) |= adcNegativeRef << - TSC_ADC_SS_IDLECONFIG_SEL_RFM_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) &= ~TSC_ADC_SS_IDLECONFIG_SEL_INP_SWC; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) |= adcPositiveInp << - TSC_ADC_SS_IDLECONFIG_SEL_INP_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) &= - ~TSC_ADC_SS_IDLECONFIG_SEL_INM_SWM; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) |= adcNegativeInp << - TSC_ADC_SS_IDLECONFIG_SEL_INM_SWM_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) &= - ~TSC_ADC_SS_IDLECONFIG_SEL_RFP_SWC; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) |= adcPositiveRef << - TSC_ADC_SS_IDLECONFIG_SEL_RFP_SWC_SHIFT; -} - -/** - * \brief This API configure the Idle Step Transistor Biasing for - * xnpsw,xppsw and yppsw pins through which analog supply - * is provided to the touch screen. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param xnpsw XNPSW pin SW configuration.\n - * - * xnpsw can take following values.\n - * - * TSCADC_XPPSW_PIN_ON.\n - * TSCADC_XPPSW_PIN_OFF.\n - * - * \param xnpsw YPPSW pin SW configuration.\n - * - * yppsw can take following values.\n - * - * TSCADC_XNPSW_PIN_ON.\n - * TSCADC_XNPSW_PIN_OFF.\n - * - * \param yppsw YPPSW pin SW configuration.\n - * - * xppsw can take following values.\n - * - * TSCADC_YPPSW_PIN_ON.\n - * TSCADC_YPPSW_PIN_OFF.\n - * - * \return none - * - **/ -void TSCADCIdleStepAnalogSupplyConfig(unsigned int baseAdd, unsigned int xppsw, - unsigned int xnpsw, unsigned int yppsw) -{ - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) &= ~TSC_ADC_SS_IDLECONFIG_XPPSW_SWC; - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) &= ~TSC_ADC_SS_IDLECONFIG_XNPSW_SWC; - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) &= ~TSC_ADC_SS_IDLECONFIG_YPPSW_SWC; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) |= xppsw << - TSC_ADC_SS_IDLECONFIG_XPPSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) |= xnpsw << - TSC_ADC_SS_IDLECONFIG_XNPSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) |= yppsw << - TSC_ADC_SS_IDLECONFIG_YPPSW_SWC_SHIFT; -} - - -/** - * \brief This API configure the Idle Step Transistor Biasing for - * xnnsw, ypnsw, ynnsw and wpnsw pins through which analog ground - * is provided to the touch screen. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param xnnsw XNNSW pin SW configuration.\n - * - * xnnsw can take following values.\n - * - * TSCADC_XNNSW_PIN_ON.\n - * TSCADC_XNNSW_PIN_OFF.\n - * - * \param ypnsw YPNSW pin SW configuration.\n - * - * ypnsw can take following values.\n - * - * TSCADC_YPNSW_PIN_ON.\n - * TSCADC_YPNSW_PIN_OFF.\n - * - * \param ynnsw YNNSW pin SW configuration.\n - * - * ynnsw can take following values.\n - * - * TSCADC_YNNSW_PIN_ON.\n - * TSCADC_YNNSW_PIN_OFF.\n - * - * \param wpnsw WPNSW pin SW configuration.\n - * - * wpnsw can take following values.\n - * - * TSCADC_WPNSW_PIN_ON.\n - * TSCADC_WPNSW_PIN_OFF.\n - * - * \return none - * - **/ -void TSCADCIdleStepAnalogGroundConfig(unsigned int baseAdd, unsigned int xnnsw, - unsigned int ypnsw, unsigned int ynnsw, - unsigned int wpnsw) -{ - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) &= ~TSC_ADC_SS_IDLECONFIG_XNNSW_SWC; - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) &= ~TSC_ADC_SS_IDLECONFIG_YPNSW_SWC; - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) &= ~TSC_ADC_SS_IDLECONFIG_YNNSW_SWC; - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) &= ~TSC_ADC_SS_IDLECONFIG_WPNSW_SWC; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) |= xnnsw << - TSC_ADC_SS_IDLECONFIG_XNNSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) |= ypnsw << - TSC_ADC_SS_IDLECONFIG_YPNSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) |= ynnsw << - TSC_ADC_SS_IDLECONFIG_YNNSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_IDLECONFIG) |= wpnsw << - TSC_ADC_SS_IDLECONFIG_WPNSW_SWC_SHIFT; -} - - -/** - * \brief This API configures ADC to single ended or differential operation - * mode. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param mode It is the value which determines whether to - * configure ADC to single ended or differential - * operation mode. - * - * mode can take following macros. - * - * TSCADC_ADC_SINGLE_ENDED_OPER_MODE.\n - * TSCADC_ADC_DIFFERENTIAL_OPER_MODE.\n - * - * \return none - * - **/ -void TSCADCChargeStepOperationModeControl(unsigned int baseAdd, unsigned int mode) -{ - if(mode) - { - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) |= - TSC_ADC_SS_TS_CHARGE_STEPCONFIG_DIFF_CNTRL; - } - else - { - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) &= - ~TSC_ADC_SS_TS_CHARGE_STEPCONFIG_DIFF_CNTRL; - } -} - - -/** - * \brief This API configures the Touch Screen ChargeStep - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param adcNegativeRef Selects the ADC Negative Reference Voltage.\n - * - * adcNegativeRef can take following values.\n - * - * TSCADC_NEGATIVE_REF_VSSA.\n - * TSCADC_NEGATIVE_REF_XNUR.\n - * TSCADC_NEGATIVE_REF_YNLR.\n - * TSCADC_NEGATIVE_REF_ADCREFM.\n - * - * \param adcPositiveInput Selects the Positive Analog Input Source.\n - * - * adcPositiveInput can take following values.\n - * - * TSCADC_POSITIVE_INP_CHANNEL1.\n - * TSCADC_POSITIVE_INP_CHANNEL2.\n - * TSCADC_POSITIVE_INP_CHANNEL3.\n - * TSCADC_POSITIVE_INP_CHANNEL4.\n - * TSCADC_POSITIVE_INP_CHANNEL5.\n - * TSCADC_POSITIVE_INP_CHANNEL6.\n - * TSCADC_POSITIVE_INP_CHANNEL7.\n - * TSCADC_POSITIVE_INP_CHANNEL8.\n - * TSCADC_POSITIVE_INP_ADCREFM.\n - * - * \param adcNegativeInput Selects the Negative Analog Input Source.\n - * - * adcNegativeInput can take following values.\n - * - * TSCADC_NEGATIVE_INP_CHANNEL1.\n - * TSCADC_NEGATIVE_INP_CHANNEL2.\n - * TSCADC_NEGATIVE_INP_CHANNEL3.\n - * TSCADC_NEGATIVE_INP_CHANNEL4.\n - * TSCADC_NEGATIVE_INP_CHANNEL5.\n - * TSCADC_NEGATIVE_INP_CHANNEL6.\n - * TSCADC_NEGATIVE_INP_CHANNEL8.\n - * TSCADC_NEGATIVE_INP_ADCREFRM.\n - * - * \param adcPositiveRef Selects the ADC Positive Reference Voltage.\n - * - * adcPositiveRef can take following values.\n - * - * TSCADC_POSITIVE_REF_VDDA.\n - * TSCADC_POSITIVE_REF_XPUL.\n - * TSCADC_POSITIVE_REF_YPLL.\n - * TSCADC_POSITIVE_REF_ADCREFP.\n - * - * \return none - * - **/ -void TSCADCChargeStepConfig(unsigned int baseAdd, unsigned int adcNegativeRef, - unsigned int adcPositiveInp,unsigned int adcNegativeInp, - unsigned int adcPositiveRef) -{ - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) &= - ~TSC_ADC_SS_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) |= adcNegativeRef << - TSC_ADC_SS_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) &= - ~TSC_ADC_SS_TS_CHARGE_STEPCONFIG_SEL_INP_SWC; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) |= adcPositiveInp << - TSC_ADC_SS_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) &= - ~TSC_ADC_SS_TS_CHARGE_STEPCONFIG_SEL_INM_SWM; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) |= adcNegativeInp << - TSC_ADC_SS_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) &= - ~TSC_ADC_SS_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) |= adcPositiveRef << - TSC_ADC_SS_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_SHIFT; -} - -/** - * \brief This API configure the TouchScreen ChargeStep Transistor Biasing for - * xnpsw,xppsw and yppsw pins through which analog supply - * is provided to the touch screen. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param xnpsw XNPSW pin SW configuration.\n - * - * xnpsw can take following values.\n - * - * TSCADC_XPPSW_PIN_ON.\n - * TSCADC_XPPSW_PIN_OFF.\n - * - * \param xnppsw XNPSW pin SW configuration.\n - * - * xnpsw can take following values.\n - * - * TSCADC_XNPSW_PIN_ON.\n - * TSCADC_XNPSW_PIN_OFF.\n - * - * \param yppsw YPPSW pin SW configuration.\n - * - * yppsw can take following values.\n - * - * TSCADC_YPPSW_PIN_ON.\n - * TSCADC_YPPSW_PIN_OFF.\n - * - * \return none - * - **/ -void TSCADCChargeStepAnalogSupplyConfig(unsigned int baseAdd, unsigned int xppsw, - unsigned int xnpsw, unsigned int yppsw) -{ - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) &= - ~ TSC_ADC_SS_TS_CHARGE_STEPCONFIG_XPPSW_SWC; - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) &= - ~ TSC_ADC_SS_TS_CHARGE_STEPCONFIG_XNPSW_SWC; - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) &= - ~ TSC_ADC_SS_TS_CHARGE_STEPCONFIG_YPPSW_SWC; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) |= xppsw << - TSC_ADC_SS_TS_CHARGE_STEPCONFIG_XPPSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) |= xnpsw << - TSC_ADC_SS_TS_CHARGE_STEPCONFIG_XNPSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) |= yppsw << - TSC_ADC_SS_TS_CHARGE_STEPCONFIG_YPPSW_SWC_SHIFT; -} - -/** - * \brief This API configure the TouchScreen ChargeStep Transistor Biasing for - * xnnsw, ypnsw, ynnsw and wpnsw pins through which analog ground - * is provided to the touch screen. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param xnnsw XNNSW pin SW configuration.\n - * - * xnnsw can take following values.\n - * - * TSCADC_XNNSW_PIN_ON.\n - * TSCADC_XNNSW_PIN_OFF.\n - * - * \param ypnsw YPNSW pin SW configuration.\n - * - * ypnsw can take following values.\n - * - * TSCADC_YPNSW_PIN_ON.\n - * TSCADC_YPNSW_PIN_OFF.\n - * - * \param ynnsw YNNSW pin SW configuration.\n - * - * ynnsw can take following values.\n - * - * TSCADC_YNNSW_PIN_ON.\n - * TSCADC_YNNSW_PIN_OFF.\n - * - * \param wpnsw WPNSW pin SW configuration.\n - * - * wpnsw can take following values.\n - * - * TSCADC_WPNSW_PIN_ON.\n - * TSCADC_WPNSW_PIN_OFF.\n - * - * \return none - * - **/ -void TSCADCChargeStepAnalogGroundConfig(unsigned int baseAdd, unsigned int xnnsw, - unsigned int ypnsw, unsigned int ynnsw, - unsigned int wpnsw) -{ - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) &= - ~TSC_ADC_SS_TS_CHARGE_STEPCONFIG_XNNSW_SWC; - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) &= - ~TSC_ADC_SS_TS_CHARGE_STEPCONFIG_YPNSW_SWC; - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) &= - ~TSC_ADC_SS_TS_CHARGE_STEPCONFIG_YNNSW_SWC; - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) &= - ~TSC_ADC_SS_TS_CHARGE_STEPCONFIG_WPNSW_SWC; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) |= xnnsw << - TSC_ADC_SS_TS_CHARGE_STEPCONFIG_XNNSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) |= ypnsw << - TSC_ADC_SS_TS_CHARGE_STEPCONFIG_YPNSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) |= ynnsw << - TSC_ADC_SS_TS_CHARGE_STEPCONFIG_YNNSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_STEPCONFIG) |= wpnsw << - TSC_ADC_SS_TS_CHARGE_STEPCONFIG_WPNSW_SWC_SHIFT; -} - -/** - * \brief This API configures the open delay for Touch Screen ChargeStep - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param delayVal Open delay value - * - * \return none - * - **/ -void TSCADCTSChargeStepOpenDelayConfig(unsigned int baseAdd, - unsigned int openDelay) -{ - HWREG(baseAdd + TSC_ADC_SS_TS_CHARGE_DELAY) = openDelay; -} - -/** - * \brief This API configures ADC to single ended or differential operation - * mode. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param mode It is the value which determines whether to - * configure ADC to single ended or differential - * operation mode. - * - * mode can take following macros. - * - * TSCADC_SINGLE_ENDED_OPER_MODE.\n - * TSCADC_DIFFERENTIAL_OPER_MODE.\n - * - * \param stepSelect It is the value which determines which step config - * register to be configured.\n - * - * - * stepSelect can take any value between 0 to 15.\n - * - * - * \return none - * - **/ -void TSCADCTSStepOperationModeControl(unsigned int baseAdd, unsigned int mode, - unsigned int stepSelect) -{ - if(mode) - { - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) |= - TSC_ADC_SS_STEPCONFIG_DIFF_CNTRL; - } - else - { - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) &= - ~TSC_ADC_SS_STEPCONFIG_DIFF_CNTRL; - } -} - -/** - * \brief This API configures the reference voltage and input for - * given Step (other than Idle and Touch Screen charge Step) - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * - * \param stepSelect Step to be configured. - * - * \param adcNegativeRef Selects the ADC Negative Reference Voltage.\n - * - * adcNegativeRef can take following values.\n - * - * TSCADC_NEGATIVE_REF_VSSA.\n - * TSCADC_NEGATIVE_REF_XNUR.\n - * TSCADC_NEGATIVE_REF_YNLR.\n - * TSCADC_NEGATIVE_REF_ADCREFM.\n - * - * \param adcPositiveInput Selects the Positive Analog Input Source.\n - * - * adcPositiveInput can take following values.\n - * - * TSCADC_POSITIVE_INP_CHANNEL1.\n - * TSCADC_POSITIVE_INP_CHANNEL2.\n - * TSCADC_POSITIVE_INP_CHANNEL3.\n - * TSCADC_POSITIVE_INP_CHANNEL4.\n - * TSCADC_POSITIVE_INP_CHANNEL5.\n - * TSCADC_POSITIVE_INP_CHANNEL6.\n - * TSCADC_POSITIVE_INP_CHANNEL7.\n - * TSCADC_POSITIVE_INP_CHANNEL8.\n - * TSCADC_POSITIVE_INP_ADCREFM.\n - * - * \param adcNegativeInput Selects the Negative Analog Input Source.\n - * - * adcNegativeInput can take following values.\n - * - * TSCADC_NEGATIVE_INP_CHANNEL1.\n - * TSCADC_NEGATIVE_INP_CHANNEL2.\n - * TSCADC_NEGATIVE_INP_CHANNEL3.\n - * TSCADC_NEGATIVE_INP_CHANNEL4.\n - * TSCADC_NEGATIVE_INP_CHANNEL5.\n - * TSCADC_NEGATIVE_INP_CHANNEL6.\n - * TSCADC_NEGATIVE_INP_CHANNEL8.\n - * TSCADC_NEGATIVE_INP_ADCREFM.\n - * - * \param adcPositiveRef Selects the ADC Positive Reference Voltage.\n - * - * adcPositiveRef can take following values.\n - * - * TSCADC_POSITIVE_REF_VDDA.\n - * TSCADC_POSITIVE_REF_XNUR.\n - * TSCADC_POSITIVE_REF_YNLR.\n - * TSCADC_POSITIVE_REF_ADCREFP.\n - * - * \return none - * - * Note: stepSelect can take any integer value b/w 0 to 15 - * - **/ -void TSCADCTSStepConfig(unsigned int baseAdd, unsigned int stepSelect, - unsigned int adcNegativeRef, unsigned int adcPositiveInp, - unsigned int adcNegativeInp, unsigned int adcPositiveRef) -{ - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) &= - ~TSC_ADC_SS_STEPCONFIG_SEL_RFM_SWC; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) |= - adcNegativeRef << TSC_ADC_SS_STEPCONFIG_SEL_RFM_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) &= - ~TSC_ADC_SS_STEPCONFIG_SEL_INP_SWC; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) |= - adcPositiveInp << TSC_ADC_SS_STEPCONFIG_SEL_INP_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) &= - ~TSC_ADC_SS_STEPCONFIG_SEL_INM_SWM; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) |= - adcNegativeInp << TSC_ADC_SS_STEPCONFIG_SEL_INM_SWM_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) &= - ~TSC_ADC_SS_STEPCONFIG_SEL_RFP_SWC; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) |= - adcPositiveRef << TSC_ADC_SS_STEPCONFIG_SEL_RFP_SWC_SHIFT; -} - -/** - * \brief This API configure the TouchScreen Step Transistor Biasing for - * xnpsw,xppsw and yppsw pins through which analog supply - * is provided to the touch screen. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param stepSelect Step to be configured - * - * \param xppsw XPPSW pin SW configuration.\n - * - * xppsw can take following values.\n - * - * TSCADC_XPPSW_PIN_ON.\n - * TSCADC_XPPSW_PIN_OFF.\n - * - * \param xnpsw XNPSW pin SW configuration.\n - * - * xnpsw can take following values.\n - * - * TSCADC_XNPSW_PIN_ON.\n - * TSCADC_XNPSW_PIN_OFF.\n - * - * \param yppsw YPPSW pin SW configuration.\n - * - * yppsw can take following values.\n - * - * TSCADC_YPPSW_PIN_ON.\n - * TSCADC_YPPSW_PIN_OFF.\n - * - * \return none - * - * Note: stepSelect can take any integer value b/w 0 to 15 - **/ -void TSCADCTSStepAnalogSupplyConfig(unsigned int baseAdd, unsigned int xppsw, - unsigned int xnpsw, unsigned int yppsw, - unsigned int stepSelect) -{ - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) &= - ~TSC_ADC_SS_STEPCONFIG_XPPSW_SWC; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) &= - ~TSC_ADC_SS_STEPCONFIG_XNPSW_SWC; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) &= - ~TSC_ADC_SS_STEPCONFIG_YPPSW_SWC; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) |= xppsw << - TSC_ADC_SS_STEPCONFIG_XPPSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) |= xnpsw << - TSC_ADC_SS_STEPCONFIG_XNPSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) |= yppsw << - TSC_ADC_SS_STEPCONFIG_YPPSW_SWC_SHIFT; -} - -/** - * \brief This API configure the TouchScreen Step Transistor Biasing for - * xnnsw, ypnsw, ynnsw and wpnsw pins through which analog ground - * is provided to the touch screen. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param stepSelect Step to be configured. - * - * \param xnnsw XNNSW pin SW configuration.\n - * - * xnnsw can take following values.\n - * - * TSCADC_XNNSW_PIN_ON.\n - * TSCADC_XNNSW_PIN_OFF.\n - * - * \param ypnsw YPNSW pin SW configuration.\n - * - * ypnsw can take following values.\n - * - * TSCADC_YPNSW_PIN_ON.\n - * TSCADC_YPNSW_PIN_OFF.\n - * - * \param ynnsw YNNSW pin SW configuration.\n - * - * ynnsw can take following values.\n - * - * TSCADC_YNNSW_PIN_ON.\n - * TSCADC_YNNSW_PIN_OFF.\n - * - * \param wpnsw WPNSW pin SW configuration.\n - * - * wpnsw can take following values.\n - * - * TSCADC_WPNSW_PIN_ON.\n - * TSCADC_WPNSW_PIN_OFF.\n - * - * \return none - * - * Note: stepSelect can take any integer value b/w 0 to 15 - **/ -void TSCADCTSStepAnalogGroundConfig(unsigned int baseAdd, unsigned int xnnsw, - unsigned int ypnsw, unsigned int ynnsw, - unsigned int wpnsw, unsigned int stepSelect) -{ - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) &= - ~TSC_ADC_SS_STEPCONFIG_XNNSW_SWC; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) &= - ~TSC_ADC_SS_STEPCONFIG_YPNSW_SWC; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) &= - ~TSC_ADC_SS_STEPCONFIG_YNNSW_SWC; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) &= - ~TSC_ADC_SS_STEPCONFIG_WPNSW_SWC; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) |= xnnsw << - TSC_ADC_SS_STEPCONFIG_XNNSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) |= ypnsw << - TSC_ADC_SS_STEPCONFIG_YPNSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) |= ynnsw << - TSC_ADC_SS_STEPCONFIG_YNNSW_SWC_SHIFT; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSelect)) |= wpnsw << - TSC_ADC_SS_STEPCONFIG_WPNSW_SWC_SHIFT; -} - -/** - * \brief This API Enables the ADC Out of Range check - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param stepSel Step to be configured - * - * \return none - * - **/ -void TSCADCTSStepOutOfRangeCheckEnable(unsigned int baseAdd, unsigned int stepSel) -{ - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSel)) |= - TSC_ADC_SS_STEPCONFIG_RANGE_CHECK; -} - -/** - * \brief This API Disables the ADC Out of Range check - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param stepSel Step to be configured - * - * \return none - * - **/ -void TSCADCTSStepOutOfRangeCheckDisable(unsigned int baseAdd, unsigned int stepSel) -{ - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSel)) &= - ~TSC_ADC_SS_STEPCONFIG_RANGE_CHECK; -} - -/** - * \brief This API selects the FIFO to store the ADC data - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param stepSel Step to be configured - * \param FIFOSel Selects the FIFO.\n - * - * FIFOSel can take following macros.\n - * - * TSCADC_FIFO_0.\n - * TSCADC_FIFO_1.\n - * - * \return none - * - **/ -void TSCADCTSStepFIFOSelConfig(unsigned int baseAdd, unsigned int stepSel, - unsigned int FIFOSel) -{ - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSel)) &= - ~TSC_ADC_SS_STEPCONFIG_FIFO_SELECT; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSel)) |= - FIFOSel << TSC_ADC_SS_STEPCONFIG_FIFO_SELECT_SHIFT; -} - -/** - * \brief This API Configures the number of samples to average - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param stepSel Step to be configured - * \param average Number of Samples to average.\n - * - * average can take following values.\n - * - * TSCADC_TWO_SAMPLES_AVG.\n - * TSCADC_FOUR_SAMPLES_AVG.\n - * TSCADC_EIGHT_SAMPLES_AVG.\n - * TSCADC_SIXTEEN_SAMPLES_AVG.\n - * - * \return none - * - **/ -void TSCADCTSStepAverageConfig(unsigned int baseAdd, unsigned int stepSel, - unsigned int average) -{ - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSel)) - &= ~TSC_ADC_SS_STEPCONFIG_AVERAGING; - - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSel)) - |= average << TSC_ADC_SS_STEPCONFIG_AVERAGING_SHIFT; -} - -/** - * \brief This API Configures the Step Config Mode - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param stepSel Step to be configured - * \param mode Selects the Step Mode. - * - * mode can take following macros.\n - * - * TSCADC_ONE_SHOT_SOFTWARE_ENABLED.\n - * TSCADC_CONTINIOUS_SOFTWARE_ENABLED.\n - * TSCADC_ONE_SHOT_HARDWARE_SYNC.\n - * TSCADC_CONTINIOUS_HARDWARE_SYNC.\n - * - * \return none - * - **/ -void TSCADCTSStepModeConfig(unsigned int baseAdd, unsigned int stepSel, - unsigned int mode) -{ - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSel)) - &= ~TSC_ADC_SS_STEPCONFIG_MODE; - HWREG(baseAdd + TSC_ADC_SS_STEPCONFIG(stepSel)) - |= mode << TSC_ADC_SS_STEPCONFIG_MODE_SHIFT; -} - -/** - * \brief This API Configures the Step Config Sample Delay - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param stepSel Step to be configured - * \param delay Sample Delay value - * - * \return none - * - **/ -void TSCADCTSStepSampleDelayConfig(unsigned int baseAdd, unsigned int stepSel, - unsigned int delay) -{ - HWREG(baseAdd + TSC_ADC_SS_STEPDELAY(stepSel)) &= - ~TSC_ADC_SS_STEPDELAY_SAMPLE_DELAY; - HWREG(baseAdd + TSC_ADC_SS_STEPDELAY(stepSel)) |= delay << - TSC_ADC_SS_STEPDELAY_SAMPLE_DELAY_SHIFT; -} - -/** - * \brief This API Configures the Step Config Open Delay - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param stepSel Step to be configured - * \param delay Open Delay value - * - * \return none - * - **/ -void TSCADCTSStepOpenDelayConfig(unsigned int baseAdd, unsigned int stepSel, - unsigned int delay) -{ - HWREG(baseAdd + TSC_ADC_SS_STEPDELAY(stepSel)) &= - ~TSC_ADC_SS_STEPDELAY_OPEN_DELAY; - HWREG(baseAdd + TSC_ADC_SS_STEPDELAY(stepSel)) |= delay; -} - -/** - * \brief This API gets the Channel ID which captured the data. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param FIFOSel Selects the FIFO - * - * \return returns the channel ID - * - **/ -unsigned int TSCADCFIFOChannelIDRead(unsigned int baseAdd, unsigned int FIFOSel) -{ - return ((HWREG(baseAdd + TSC_ADC_SS_FIFODATA(FIFOSel)) & - TSC_ADC_SS_FIFODATA_ADCCHLNID) - >> TSC_ADC_SS_FIFODATA_ADCCHLNID_SHIFT); -} - -/** - * \brief This API gets the ADC Sampled data - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param FIFOSel Selects the FIFO.\n - * - * \return returns the channel ID - * - **/ -unsigned int TSCADCFIFOADCDataRead(unsigned int baseAdd, unsigned int FIFOSel) -{ - return (HWREG(baseAdd + TSC_ADC_SS_FIFODATA(FIFOSel)) & - TSC_ADC_SS_FIFODATA_ADC_DATA); -} - -/** - * \brief This API gets the Number Of Words Currently in FIFO. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param FIFOSel Selects the FIFO - * - * \return returns the channel ID - * - **/ -unsigned int TSCADCFIFOWordCountRead(unsigned int baseAdd, unsigned int FIFOSel) -{ - return(HWREG(baseAdd + TSC_ADC_SS_FIFOCOUNT(FIFOSel))); -} - -/** - * \brief This API sets the FIFO threshold Level to generate interrupt request. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * - * \param FIFOSel It is the value which determines the whether to - * to configure the threshold level for FIFO0 or - * FIFO1.\n - * - * FIFOSel can take following macros.\n - * - * TSCADC_FIFO_0.\n - * TSCADC_FIFO_1.\n - * - * \param numberOfSamples It is the threshold level to be configured. - * - * \return none - * - **/ -void TSCADCFIFOIRQThresholdLevelConfig(unsigned int baseAdd, unsigned char FIFOSel, - unsigned char numberOfSamples) -{ - HWREG(baseAdd + TSC_ADC_SS_FIFOTHRESHOLD(FIFOSel)) = numberOfSamples - 1; -} - -/** - * \brief This API sets the FIFO threshold level to generate the DMA request. - * - * \param baseAdd Base Address of the TouchScreen Module Registers. - * \param numberOfSamples Selects the FIFO - * - * \return none - * - **/ -void TSCADCFIFODMAThresholdLevelConfig(unsigned int baseAdd, - unsigned int FIFOSel, - unsigned int numberOfSamples) -{ - HWREG(baseAdd + TSC_ADC_SS_DMAREQ(FIFOSel)) = numberOfSamples - 1; -} diff --git a/lib/tiam1808/drivers/uart_irda_cir.c b/lib/tiam1808/drivers/uart_irda_cir.c deleted file mode 100644 index 28762e023..000000000 --- a/lib/tiam1808/drivers/uart_irda_cir.c +++ /dev/null @@ -1,2658 +0,0 @@ -/** - * \file uart_irda_cir.c - * - * \brief This file contains the Device Abstraction Layer(DAL) APIs - * for UART, IrDA(Infrared Data Association), CIR(Consumer Infrared), - * modes of operation of UART. These APIs are used for configuration - * of instance, transmission and reception of data. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#include "uart_irda_cir.h" -#include "hw_types.h" - -/***************************************************************************** -** FUNCTION DEFINITIONS -*****************************************************************************/ - -/** - * \brief This API configures the operating mode for the UART instance. - * The different operating modes are: - * - UART(16x, 13x, 16x Auto-Baud)\n - * - IrDA(SIR, MIR, FIR)\n - * - CIR\n - * - Disabled state(default state)\n - * - * \param baseAdd Memory address of the UART instance being used. - * \param modeFlag A value which holds the mode number. This mode - * number is referred from the MODESELECT field in MDR1. - * - * 'modeFlag' can take one of the following values: - * - UART16x_OPER_MODE - to switch to UART 16x operating mode\n - * - UART_SIR_OPER_MODE - to swith to IrDA SIR operating mode\n - * - UART16x_AUTO_BAUD_OPER_MODE - to switch to UART 16x Auto Baud operating - * mode\n - * - UART13x_OPER_MODE - to switch to UART 13x operating mode\n - * - UART_MIR_OPER_MODE - to switch to IrDA MIR operating mode\n - * - UART_FIR_OPER_MODE - to switch to IrDA FIR operating mode\n - * - UART_CIR_OPER_MODE - to switch to CIR operating mode\n - * - UART_DISABLED_MODE - to switch to Disabled state\n - * - * \return The mode number in the MODESELECT field of MDR1 before it - * was modified. - */ - -unsigned int UARTOperatingModeSelect(unsigned int baseAdd, - unsigned int modeFlag) -{ - unsigned int operMode = 0; - - operMode = (HWREG(baseAdd + UART_MDR1) & UART_MDR1_MODE_SELECT); - - /* Clearing the MODESELECT field in MDR1. */ - HWREG(baseAdd + UART_MDR1) &= ~(UART_MDR1_MODE_SELECT); - /* Programming the MODESELECT field in MDR1. */ - HWREG(baseAdd + UART_MDR1) |= (modeFlag & UART_MDR1_MODE_SELECT); - - return operMode; -} - -/** - * \brief This API computes the divisor value for the specified operating - * mode. Not part of this API, the divisor value returned is written - * to the Divisor Latches to configure the Baud Rate. - * - * \param moduleClk The frequency of the input clock to the UART module - * \param modeFlag A value which represents the current operating mode - * \param baudRate The required baud rate of communication in bits - * per second(bps) - * \param mirOverSampRate Over-sampling rate for MIR mode.This is applicable - * only when MIR mode of operation is chosen. - * Otherwise, this value is not considered. - * - * 'modeFlag' can take one of the following values:\n - * - UART16x_OPER_MODE - indicating 16x operating mode\n - * - UART13x_OPER_MODE - indicating 13x operating mode\n - * - UART_SIR_OPER_MODE - indicating SIR operating mode\n - * - UART_MIR_OPER_MODE - indicating MIR operating mode\n - * - UART_FIR_OPER_MODE - indicating FIR operating mode\n - * - * 'mirOverSampRate' can take one of the following values: - * - UART_MIR_OVERSAMPLING_RATE_41 - for an over-sampling rate of 41\n - * - UART_MIR_OVERSAMPLING_RATE_42 - for an over-smapling rate of 42\n - * - * \return The divisor value computed for the specified mode. - * - * \note Refer to the section in the user guide that specifies the baud rate - * computation method to find the supported values of baud rates. - */ - -unsigned int UARTDivisorValCompute(unsigned int moduleClk, - unsigned int baudRate, - unsigned int modeFlag, - unsigned int mirOverSampRate) -{ - unsigned int divisorValue = 0; - - modeFlag &= UART_MDR1_MODE_SELECT; - - switch(modeFlag) - { - case UART16x_OPER_MODE: - case UART_SIR_OPER_MODE: - divisorValue = (moduleClk)/(16 * baudRate); - break; - - case UART13x_OPER_MODE: - divisorValue = (moduleClk)/(13 * baudRate); - break; - - case UART_MIR_OPER_MODE: - divisorValue = (moduleClk)/(mirOverSampRate * baudRate); - break; - - case UART_FIR_OPER_MODE: - divisorValue = 0; - break; - - default: - break; - } - - return divisorValue; -} - -/** - * \brief This API is used to write the specified divisor value to Divisor - * Latch registers DLL and DLH. - * - * \param baseAdd Memory address of the UART instance being used. - * \param divisorValue The 14-bit value whose least 8 bits go to DLL - * and highest 6 bits go to DLH. - * - * \return A concatenated value of DLH and DLL registers(DLH:DLL, a 14-bit - * value) before they are modified in the current API. - */ - -unsigned int UARTDivisorLatchWrite(unsigned int baseAdd, - unsigned int divisorValue) -{ - volatile unsigned int enhanFnBitVal = 0; - volatile unsigned int sleepMdBitVal = 0; - volatile unsigned int lcrRegValue = 0; - volatile unsigned int operMode = 0; - unsigned int divRegVal = 0; - - /* Switching to Register Configuration Mode B. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Collecting the current value of EFR[4] and later setting it. */ - enhanFnBitVal = HWREG(baseAdd + UART_EFR) & UART_EFR_ENHANCED_EN; - HWREG(baseAdd + UART_EFR) |= UART_EFR_ENHANCED_EN; - - /* Switching to Register Operational Mode. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - /* - ** Collecting the current value of IER[4](SLEEPMODE bit) and later - ** clearing it. - */ - sleepMdBitVal = HWREG(baseAdd + UART_IER) & UART_IER_SLEEP_MODE_IT; - HWREG(baseAdd + UART_IER) &= ~(UART_IER_SLEEP_MODE_IT); - - /* Switching to Register Configuration Mode B. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Collecting the current value of Divisor Latch Registers. */ - divRegVal = HWREG(baseAdd + UART_DLL) & 0xFF; - divRegVal |= ((HWREG(baseAdd + UART_DLH) & 0x3F) << 8); - - /* Switch the UART instance to Disabled state. */ - operMode = UARTOperatingModeSelect(baseAdd, UART_MDR1_MODE_SELECT_DISABLED); - - /* Writing to Divisor Latch Low(DLL) register. */ - HWREG(baseAdd + UART_DLL) = (divisorValue & 0x00FF); - - /* Writing to Divisor Latch High(DLH) register. */ - HWREG(baseAdd + UART_DLH) = ((divisorValue & 0x3F00) >> 8); - - /* Restoring the Operating Mode of UART. */ - UARTOperatingModeSelect(baseAdd, operMode); - - /* Switching to Register Operational Mode. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - /* Restoring the value of IER[4] to its original value. */ - HWREG(baseAdd + UART_IER) |= sleepMdBitVal; - - /* Switching to Register Configuration Mode B. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Restoring the value of EFR[4] to its original value. */ - HWREG(baseAdd + UART_EFR) &= ~(UART_EFR_ENHANCED_EN); - HWREG(baseAdd + UART_EFR) |= enhanFnBitVal; - - /* Restoring the value of LCR Register. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return divRegVal; -} - -/** - * \brief This API enables write access to Divisor Latch registers DLL and - * DLH. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return None. - */ - -void UARTDivisorLatchEnable(unsigned int baseAdd) -{ - /* Enable access to Divisor Latch registers by setting LCR[7] bit. */ - HWREG(baseAdd + UART_LCR) |= (UART_LCR_DIV_EN); -} - -/** - * \brief This API disables write access to Divisor Latch registers DLL and - * DLH. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return None. - * - * \note Disabling write access to Divisor Latch Registers enables access to - * MCR, FCR, IER, BLR, EBLR, RHR registers. - */ -void UARTDivisorLatchDisable(unsigned int baseAdd) -{ - /* Disabling access to Divisor Latch registers by clearing LCR[7] bit. */ - HWREG(baseAdd + UART_LCR) &= ~(UART_LCR_DIV_EN); -} - - -/** - * \brief This API configures the specified Register Configuration mode for - * the UART. - * - * \param baseAdd Memory address of the UART instance being used. - * \param modeFlag This specifies the register configuration mode to be - * enabled. - * - * 'modeFlag' can take one of the following values: - * - UART_REG_CONFIG_MODE_A - to enable Register Configuration Mode A\n - * - UART_REG_CONFIG_MODE_B - to enable Register Configuration Mode B\n - * - UART_REG_OPERATIONAL_MODE - to enable Register Operational Mode\n - * - * \return The contents of the Line Control Register(LCR) before it was - * modified. - * - * \note Since the UART module registers that can be accessed at any time - * depends on the value in the Line Control Register(LCR), three - * register configuration modes have been defined, each corresponding - * to a specific state of the LCR. The three register configuration - * modes are:\n - * - Configuration Mode A: LCR[7] = 1 and LCR[7:0] != 0xBF.\n - * - Configuration Mode B: LCR[7:0] = 0xBF.\n - * - Operational Mode : LCR[7] = 0.\n - * - * Refer to the Register Listing in the UART/IrDA/CIR peripheral - * document for more information.\n - * - */ - -unsigned int UARTRegConfigModeEnable(unsigned int baseAdd, unsigned int modeFlag) -{ - unsigned int lcrRegValue = 0; - - /* Preserving the current value of LCR. */ - lcrRegValue = HWREG(baseAdd + UART_LCR); - - switch(modeFlag) - { - case UART_REG_CONFIG_MODE_A: - case UART_REG_CONFIG_MODE_B: - HWREG(baseAdd + UART_LCR) = (modeFlag & 0xFF); - break; - - case UART_REG_OPERATIONAL_MODE: - HWREG(baseAdd + UART_LCR) &= 0x7F; - break; - - default: - break; - } - - return lcrRegValue; -} - - -/** - * \brief This API is used to restore the UART to the specified Register - * Configuration Mode. - * - * \param baseAdd Memory address of the UART instance being used. - * \param lcrRegValue The value to be loaded to the Line Control Register(LCR). - * - * \return None - * - * \note The API UARTRegConfigModeEnable() and the current API are used - * hand-in-hand. While UARTRegConfigModeEnable() switches the UART to - * the requested operating mode, the current API restores the UART to - * that register configuration mode prevalent before - * UARTRegConfigModeEnable() was called. - */ - -void UARTRegConfModeRestore(unsigned int baseAdd, unsigned int lcrRegValue) -{ - /* Programming the Line Control Register(LCR). */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; -} - -/** - * \brief This API is used to introduce or to remove a Break condition. - * - * \param baseAdd Memory address of the UART instance being used. - * \param breakState This specifies whether the break condition should be - * introduced or removed. - * - * 'breakState' can take one of the following two values: - * - UART_BREAK_COND_DISABLE - to disable the Break condition if it has - * already been enabled\n - * - UART_BREAK_COND_ENABLE - to enable the Break condition\n - * - * \return None - * - * \note When the Break Condition is imposed, the Transmitter output line TX - * goes low to alert the communication terminal. - */ - -void UARTBreakCtl(unsigned int baseAdd, unsigned int breakState) -{ - /* Clearing the BREAK_EN bit in LCR. */ - HWREG(baseAdd + UART_LCR) &= ~(UART_LCR_BREAK_EN); - - /* Programming the BREAK_EN bit in LCR. */ - HWREG(baseAdd + UART_LCR) |= (breakState & UART_LCR_BREAK_EN); -} - -/** - * \brief This API configures the Line Characteristics for the - * UART instance. The Line Characteristics include: - * - Word length per frame\n - * - Number of Stop Bits per frame\n - * - Parity feature configuration\n - * - * \param baseAdd Memory address of the UART instance being used. - * \param wLenStbFlag Bit mask value of the bits pertaining to word - * length selection and stop bits selection in LCR. - * \param parityFlag Bit mask value of the bits pertaining to parity - * feature selection in LCR. - * - * 'wLenStbFlag' can take one of the following macros: - * - (UART_FRAME_WORD_LENGTH_n | UART_FRAME_NUM_STB_1), where - * n = 5,6,7 or 8. -- This signifies that 1 stop bit and - * one among 5,6,7 and 8 bits are chosen as the word length - * per frame. - * - (UART_FRAME_WORD_LENGTH_n | UART_FRAME_NUM_STB_1_5_2), where - * n = 5,6,7 or 8. -- This signifies that the word length and - * number of stop bits per frame could be one among the below - * four choices: - * --- WL = 5 STB = 1.5 - * --- WL = 6,7 or 8 STB = 2 - * - * 'parityFlag' can take one of the following macros: - * - (UART_ODD_PARITY) - signifying that odd parity be enabled and the parity - * bit be represented by a default manner\n - * - (UART_EVEN_PARITY) - signifying that even parity be enabled and the - * parity bit be represented by a default manner\n - * - (UART_ODD_PARITY_REPR_1) - signifying that odd parity be enabled and the - * parity bit be represented by a logic 1\n - * - (UART_EVEN_PARITY_REPR_0)- signifying that even parity be enabled and the - * parity bit be represented by a logic 0\n - * - (UART_PARITY_NONE) - signifying that no parity be enabled\n - * - * \return None. - */ - -void UARTLineCharacConfig(unsigned int baseAdd, - unsigned int wLenStbFlag, - unsigned int parityFlag) -{ - /* Clearing the CHAR_LENGTH and NB_STOP fields in LCR.*/ - HWREG(baseAdd + UART_LCR) &= ~(UART_LCR_NB_STOP | UART_LCR_CHAR_LENGTH); - /* Programming the CHAR_LENGTH and NB_STOP fields in LCR. */ - HWREG(baseAdd + UART_LCR) |= (wLenStbFlag & - (UART_LCR_NB_STOP | UART_LCR_CHAR_LENGTH)); - - /* Clearing the PARITY_EN, PARITY_TYPE1 and PARITY_TYPE2 fields in LCR. */ - HWREG(baseAdd + UART_LCR) &= ~(UART_LCR_PARITY_TYPE2 | - UART_LCR_PARITY_TYPE1 | - UART_LCR_PARITY_EN); - /* Programming the PARITY_EN, PARITY_TYPE1 and PARITY_TYPE2 fields in LCR.*/ - HWREG(baseAdd + UART_LCR) |= (parityFlag & (UART_LCR_PARITY_TYPE2 | - UART_LCR_PARITY_TYPE1 | - UART_LCR_PARITY_EN)); - -} - -/** - * \brief This API configures the Parity feature for the UART. - * - * \param baseAdd Memory address of the UART instance being used - * \param parityFlag This specifies the parity configuration to be - * programmed to the Line Control Register(LCR) - * - * 'parityFlag' can take one of the following values: - * - (UART_ODD_PARITY) - signifying that odd parity be enabled and the parity - * bit be represented in a default manner\n - * - (UART_EVEN_PARITY) - signifying that even parity be enabled and the - * parity bit be represented in a default manner\n - * - (UART_ODD_PARITY_REPR_1) - signifying that odd parity be enabled and the - * parity bit be represented by a logic 1\n - * - (UART_EVEN_PARITY_REPR_0)- signifying that even parity be enabled and the - * parity bit be represented by a logic 0\n - * - (UART_PARITY_NONE) - signifying that no parity be enabled\n - * - * \return None - */ - -void UARTParityModeSet(unsigned int baseAdd, unsigned int parityFlag) -{ - HWREG(baseAdd + UART_LCR) &= ~((UART_LCR_PARITY_TYPE2 | - UART_LCR_PARITY_TYPE1 | - UART_LCR_PARITY_EN)); - - /* Programming the PARITY_TYPE2, PARITY_TYPE1 and PARITY_EN fields of LCR. */ - HWREG(baseAdd + UART_LCR) |= (parityFlag & (UART_LCR_PARITY_TYPE2 | - UART_LCR_PARITY_TYPE1 | - UART_LCR_PARITY_EN)); -} - -/** - * \brief This API reads the Parity configuration being set in the UART. - * - * \param baseAdd Memory address of the UART instance being used - * - * \return This returs one of the following values: - * - (UART_ODD_PARITY) - signifying that odd parity is enabled and the parity - * bit is represented in a default manner\n - * - (UART_EVEN_PARITY) - signifying that even parity is enabled and the - * parity bit is represented in a default manner\n - * - (UART_ODD_PARITY_REPR_1) - signifying that odd parity is enabled and the - * parity bit is represented by a logic 1\n - * - (UART_EVEN_PARITY_REPR_0)- signifying that even parity is enabled and the - * parity bit is represented by a logic 0\n - * - (UART_PARITY_NONE) - signifying that no parity is enabled\n - * - */ - -unsigned int UARTParityModeGet(unsigned int baseAdd) -{ - return (HWREG(baseAdd + UART_LCR) & (UART_LCR_PARITY_TYPE2 | - UART_LCR_PARITY_TYPE1 | - UART_LCR_PARITY_EN)); -} - -/** - * \brief This API configures the FIFO settings for the UART instance. - * Specifically, this does the following configurations: - * 1> Configures the Transmitter and Receiver FIFO Trigger Level - * granularity\n - * 2> Configures the Transmitter and Receiver FIFO Trigger Level\n - * 3> Configures the bits which clear/not clear the TX and RX FIFOs\n - * 4> Configures the DMA mode of operation\n - * - * \param baseAdd Memory address of the UART instance being used. - * \param fifoConfig This specifies the desired FIFO configurations. - * Use the macro UART_FIFO_CONFIG to pass the required - * FIFO settings. - * - * The parameters of UART_FIFO_CONFIG can take the following values:\n - * -- txGra - the Transmitter FIFO trigger level granularity\n - * -- rxGra - the Receiver FIFO trigger level granularity\n - * These can take one of the following two values:\n - * - UART_TRIG_LVL_GRANULARITY_1 - for a granularity of 1,\n - * - UART_TRIG_LVL_GRANULARITY_4 - for a granularity of 4.\n - * - * -- txTrig - the Transmitter FIFO trigger level\n - * - * For 'txGra' being UART_TRIG_LVL_GRANULARITY_4, this can take one of the - * values from one of the following two sets: - * Set 1> UART_FCR_TX_TRIG_LVL_n, where n = 8,16,32,56. - * These are programmed to the FCR[5:4] in FCR register. - * Set 2> m , where (1 <= m <= 15). - * The trigger level would then be (m * 4). - * For example: If m = 9, then trigger level = 36. - * The value 'm' is programmed into TLR[3:0] field in TLR register. - * - * For granularity being UART_TRIG_LVL_GRANULARITY_1, this can take - * any decimal value from 1 to 63. - * - * -- rxTrig - the Receiver FIFO Trigger level\n - * - * For granularity being UART_TRIG_LVL_GRANULARITY_4, this can - * take one of the macro from one of the following two sets: - * Set 1> UART_FCR_RX_TRIG_LVL_n, where n = 8,16,56,60. - * These are programmed into FCR[7:6] field in FCR register. - * Set 2> m , where (1 <= m <= 15). - * The trigger level would then be (m * 4). - * For example: If m = 7, then trigger level = 28. - * The value 'm' is programmed to the TLR[7:4] field of TLR. - * - * For granularity being UART_TRIG_LVL_GRANULARITY_1, this can take - * any decimal value from 1 to 63. - * - * -- txClr - the Transmitter FIFO clear flag\n - * -- rxClr - the Receiver FIFO clear flag\n - * - * These can take the following values: - * 0 - to not clear the FIFO\n - * 1 - to clear the FIFO. Clearing the FIFO also results in resetting the - * FIFO counter logic to 0.\n - * - * -- dmaEnPath - specifies whether DMA Mode settings should be configured - * through FCR or SCR. This can take one of the following two values: - * UART_DMA_EN_PATH_FCR - to configure DMA through FCR\n - * UART_DMA_EN_PATH_SCR - to configure DMA through SCR\n - * - * -- dmaMode - specifies the DMA Mode to be used\n - * This can take one of the following four values: - * - UART_DMA_MODE_m_ENABLE, where m = 0, 1, 2 or 3. - * - * \return The value that was written to the FIFO Control Register(FCR). - * - * \note 1> FIFO Control Register(FCR) is a write-only register and its - * contents cannot be read. Hence, it is not possible for a - * read-modify-write operation on this register. Therefore it is - * expected that the FIFO configuration is done at once for both - * TX and RX directions and always the entire FCR related information is - * required during modification of the FIFO settings. - * Also the FIFO related settings are valid only when the FIFO is - * enabled. This means that FIFO mode of operation should be enabled for - * FIFO related settings to take effect. - */ - -unsigned int UARTFIFOConfig(unsigned int baseAdd, - unsigned int fifoConfig) -{ - unsigned int txGra = (fifoConfig & UART_FIFO_CONFIG_TXGRA) >> 26; - unsigned int rxGra = (fifoConfig & UART_FIFO_CONFIG_RXGRA) >> 22; - - unsigned int txTrig = (fifoConfig & UART_FIFO_CONFIG_TXTRIG) >> 14; - unsigned int rxTrig = (fifoConfig & UART_FIFO_CONFIG_RXTRIG) >> 6; - - unsigned int txClr = (fifoConfig & UART_FIFO_CONFIG_TXCLR) >> 5; - unsigned int rxClr = (fifoConfig & UART_FIFO_CONFIG_RXCLR) >> 4; - - unsigned int dmaEnPath = (fifoConfig & UART_FIFO_CONFIG_DMAENPATH) >> 3; - unsigned int dmaMode = (fifoConfig & UART_FIFO_CONFIG_DMAMODE); - - unsigned int tcrTlrBitVal = 0; - unsigned int tlrValue = 0; - unsigned int fcrValue = 0; - - tcrTlrBitVal = UARTSubConfigTCRTLRModeEn(baseAdd); - - /* Enabling FIFO mode of operation. */ - fcrValue |= UART_FCR_FIFO_EN; - - /* Setting the Receiver FIFO trigger level. */ - if(UART_TRIG_LVL_GRANULARITY_1 != rxGra) - { - /* Clearing the RXTRIGGRANU1 bit in SCR. */ - HWREG(baseAdd + UART_SCR) &= ~(UART_SCR_RX_TRIG_GRANU1); - - /* Clearing the RX_FIFO_TRIG_DMA field of TLR register. */ - HWREG(baseAdd + UART_TLR) &= ~(UART_TLR_RX_FIFO_TRIG_DMA); - - fcrValue &= ~(UART_FCR_RX_FIFO_TRIG); - - /* - ** Checking if 'rxTrig' matches with the RX Trigger level values - ** in FCR. - */ - if((UART_FCR_RX_TRIG_LVL_8 == rxTrig) || - (UART_FCR_RX_TRIG_LVL_16 == rxTrig) || - (UART_FCR_RX_TRIG_LVL_56 == rxTrig) || - (UART_FCR_RX_TRIG_LVL_60 == rxTrig)) - { - fcrValue |= (rxTrig & UART_FCR_RX_FIFO_TRIG); - } - else - { - /* RX Trigger level will be a multiple of 4. */ - /* Programming the RX_FIFO_TRIG_DMA field of TLR register. */ - HWREG(baseAdd + UART_TLR) |= ((rxTrig << - UART_TLR_RX_FIFO_TRIG_DMA_SHIFT) & - UART_TLR_RX_FIFO_TRIG_DMA); - } - } - else - { - /* 'rxTrig' now has the 6-bit RX Trigger level value. */ - - rxTrig &= 0x003F; - - /* Collecting the bits rxTrig[5:2]. */ - tlrValue = (rxTrig & 0x003C) >> 2; - - /* Collecting the bits rxTrig[1:0] and writing to 'fcrValue'. */ - fcrValue |= (rxTrig & 0x0003) << UART_FCR_RX_FIFO_TRIG_SHIFT; - - /* Setting the RXTRIGGRANU1 bit of SCR register. */ - HWREG(baseAdd + UART_SCR) |= UART_SCR_RX_TRIG_GRANU1; - - /* Programming the RX_FIFO_TRIG_DMA field of TLR register. */ - HWREG(baseAdd + UART_TLR) |= (tlrValue << UART_TLR_RX_FIFO_TRIG_DMA_SHIFT); - - } - - /* Setting the Transmitter FIFO trigger level. */ - if(UART_TRIG_LVL_GRANULARITY_1 != txGra) - { - /* Clearing the TXTRIGGRANU1 bit in SCR. */ - HWREG(baseAdd + UART_SCR) &= ~(UART_SCR_TX_TRIG_GRANU1); - - /* Clearing the TX_FIFO_TRIG_DMA field of TLR register. */ - HWREG(baseAdd + UART_TLR) &= ~(UART_TLR_TX_FIFO_TRIG_DMA); - - fcrValue &= ~(UART_FCR_TX_FIFO_TRIG); - - /* - ** Checking if 'txTrig' matches with the TX Trigger level values - ** in FCR. - */ - if((UART_FCR_TX_TRIG_LVL_8 == (txTrig)) || - (UART_FCR_TX_TRIG_LVL_16 == (txTrig)) || - (UART_FCR_TX_TRIG_LVL_32 == (txTrig)) || - (UART_FCR_TX_TRIG_LVL_56 == (txTrig))) - { - fcrValue |= (txTrig & UART_FCR_TX_FIFO_TRIG); - } - else - { - /* TX Trigger level will be a multiple of 4. */ - /* Programming the TX_FIFO_TRIG_DMA field of TLR register. */ - HWREG(baseAdd + UART_TLR) |= ((txTrig << - UART_TLR_TX_FIFO_TRIG_DMA_SHIFT) & - UART_TLR_TX_FIFO_TRIG_DMA); - } - } - else - { - /* 'txTrig' now has the 6-bit TX Trigger level value. */ - - txTrig &= 0x003F; - - /* Collecting the bits txTrig[5:2]. */ - tlrValue = (txTrig & 0x003C) >> 2; - - /* Collecting the bits txTrig[1:0] and writing to 'fcrValue'. */ - fcrValue |= (txTrig & 0x0003) << UART_FCR_TX_FIFO_TRIG_SHIFT; - - /* Setting the TXTRIGGRANU1 bit of SCR register. */ - HWREG(baseAdd + UART_SCR) |= UART_SCR_TX_TRIG_GRANU1; - - /* Programming the TX_FIFO_TRIG_DMA field of TLR register. */ - HWREG(baseAdd + UART_TLR) |= (tlrValue << UART_TLR_TX_FIFO_TRIG_DMA_SHIFT); - } - - if(UART_DMA_EN_PATH_FCR == dmaEnPath) - { - /* Configuring the UART DMA Mode through FCR register. */ - HWREG(baseAdd + UART_SCR) &= ~(UART_SCR_DMA_MODE_CTL); - - dmaMode &= 0x1; - - /* Clearing the bit corresponding to the DMA_MODE in 'fcrValue'. */ - fcrValue &= ~(UART_FCR_DMA_MODE); - - /* Setting the DMA Mode of operation. */ - fcrValue |= (dmaMode << UART_FCR_DMA_MODE_SHIFT); - } - else - { - dmaMode &= 0x3; - - /* Configuring the UART DMA Mode through SCR register. */ - HWREG(baseAdd + UART_SCR) |= UART_SCR_DMA_MODE_CTL; - - /* Clearing the DMAMODE2 field in SCR. */ - HWREG(baseAdd + UART_SCR) &= ~(UART_SCR_DMA_MODE_2); - - /* Programming the DMAMODE2 field in SCR. */ - HWREG(baseAdd + UART_SCR) |= (dmaMode << UART_SCR_DMA_MODE_2_SHIFT); - } - - /* Programming the bits which clear the RX and TX FIFOs. */ - fcrValue |= (rxClr << UART_FCR_RX_FIFO_CLEAR_SHIFT); - fcrValue |= (txClr << UART_FCR_TX_FIFO_CLEAR_SHIFT); - - /* Writing 'fcrValue' to the FIFO Control Register(FCR). */ - UARTFIFORegisterWrite(baseAdd, fcrValue); - - /* Restoring the value of TCRTLR bit in MCR. */ - UARTTCRTLRBitValRestore(baseAdd, tcrTlrBitVal); - - return fcrValue; -} - -/** - * \brief This API enables the DMA mode of operation for the UART instance. - * - * \param baseAdd Memory address of the UART instance being used. - * \param dmaModeFlag This specifies the DMA mode to be enabled for the - * UART instance. - * - * 'dmaModeFlag' can take one of the following four values: - * - UART_DMA_MODE_0_ENABLE - to enable DMA Mode 0(No DMA)\n - * - UART_DMA_MODE_1_ENABLE - to enable DMA Mode 1(DMA for both TX and RX)\n - * - UART_DMA_MODE_2_ENABLE - to enable DMA Mode 2(DMA only for RX)\n - * - UART_DMA_MODE_3_ENABLE - to enable DMA Mode 3(DMA only for TX)\n - * - * \return None - * - * \note This API enables the specified DMA modes always in SCR and FCR is - * not used. This is because SCR[2:1] allows the program to enable any - * of the four available DMA modes while FCR[3] allows the program to - * use either DMA Mode 0 or DMA Mode 1.\n - */ - - -void UARTDMAEnable(unsigned int baseAdd, unsigned int dmaModeFlag) -{ - /* Setting the DMAMODECTL bit in SCR to 1. */ - HWREG(baseAdd + UART_SCR) |= (UART_SCR_DMA_MODE_CTL); - - /* Clearing the DMAMODE2 field in SCR. */ - HWREG(baseAdd + UART_SCR) &= ~(UART_SCR_DMA_MODE_2); - - /* Programming the DMAMODE2 field in SCR. */ - HWREG(baseAdd + UART_SCR) |= ((dmaModeFlag << UART_SCR_DMA_MODE_2_SHIFT) & - UART_SCR_DMA_MODE_2); -} - -/** - * \brief This API disables the DMA mode of operation. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return None - */ - -void UARTDMADisable(unsigned int baseAdd) -{ - HWREG(baseAdd + UART_SCR) |= (UART_SCR_DMA_MODE_CTL); - /* Programming DMAMODE2 field of SCR to DMA mode 0. */ - HWREG(baseAdd + UART_SCR) &= ~(UART_SCR_DMA_MODE_2); -} - -/** - * \brief This function does the following operations: - * 1> Enable the transmit and receive FIFOs. - * 2> Clears the transmitter FIFO and resets the transmitter FIFO - * counter. - * 3> Clears the receiver FIFO and resets the receiver FIFO counter. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return None - * - * 1> The pre-requisite to modify the FIFO_EN bit in FCR is that the - * Divisor Latch Registers should hold zero value(resulting in - * stopping the baud clock).\n */ - -void UARTFIFOEnable(unsigned int baseAdd) -{ - unsigned int divLatchRegVal = 0; - unsigned int lcrRegValue = 0; - unsigned int fifoConfig = 0; - - /* Switching to Configuration Mode A. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_A); - - /* Clearing the contents of Divisor Latch Registers. */ - divLatchRegVal = UARTDivisorLatchWrite(baseAdd, 0x0000); - - /* - ** Enabling the FIFO mode of operation. - ** Also clearing the TX and RX FIFOs and resetting the corresponding FIFO - ** counters to zero. - */ - fifoConfig = (UART_FCR_FIFO_EN | UART_FCR_TX_FIFO_CLEAR | - UART_FCR_RX_FIFO_CLEAR); - - HWREG(baseAdd + UART_FCR) = fifoConfig; - - /* Programming the Divisor Latch Registers. */ - UARTDivisorLatchWrite(baseAdd, divLatchRegVal); - - /* Reinstating the value of LCR register. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; -} - -/** - * \brief This API disables the FIFO mode of operation. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return None - * - * \note Refer to the note section of the function UARTFIFOEnable() - * for more information. - */ - -void UARTFIFODisable(unsigned int baseAdd) -{ - unsigned int divLatchRegVal = 0; - unsigned int lcrRegValue = 0; - unsigned int fifoConfig = 0; - - /* Switching to Configuration Mode A. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_A); - - /* Clearing the contents of Divisor Latch Registers. */ - divLatchRegVal = UARTDivisorLatchWrite(baseAdd, 0x0000); - - /* Disabling the FIFO mode of operation. */ - fifoConfig &= ~(UART_FCR_FIFO_EN); - HWREG(baseAdd + UART_FCR) = fifoConfig; - - /* Programming the Divisor Latch Registers with the collected value. */ - UARTDivisorLatchWrite(baseAdd, divLatchRegVal); - - /* Reinstating the value of LCR register. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; -} - -/** - * \brief This API is used to write a specified value to the FIFO Control - * Register(FCR). - * - * \param baseAdd Memory address of the UART instance being used. - * \param fcrValue This specifies the value to be written to the - * FCR. - * - * 'fcrValue' can be determined using a parameterized macro named - * 'UART_FCR_PROGRAM'. - * The parameters of 'UART_FCR_PROGRAM' are described below: - * - rxFIFOTrig - specifies the Receiver FIFO Trigger Level\n - * - txFIFOTrig - specifies the Transmitter FIFO Trigger Level\n - * - dmaMode - specifies the DMA Mode of operation to be selected:\n - * Write 0 - for DMA Mode 0\n - * 1 - for DMA Mode 1\n - * - txClr - specifies whether or not to clear the Transmitter FIFO - * and resetting the counter logic to 0.\n - * - rxClr - specifies whether or not to clear the Receiver FIFO and resetting - * the counter logic to 0. - * - fifoEn - specifies whether to enable the FIFO mode for the UART or not\n - * 0 - to enable Non-FIFO mode of operation\n - * 1 - to enable FIFO mode of operation\n - * - * \return None - * - * \note 1> The FIFO_EN and DMA_MODE bits of FCR can be written to only when - * the Baud Clock is not running(DLL and DLH register are cleared - * to 0). Modifying DLL and DLH registers in turn requires that the - * UART be operated in Disabled Mode(MDR1[2:0] = 0x7).\n - * 2> Writing to 'TX_FIFO_TRIG' field in FCR requires that the - * ENHANCEDEN bit in EFR(EFR[4]) be set to 1.\n - * Prior to writing to the FCR, this API does the above two operations. - * It also restores the respective bit values after FCR has been - * written to.\n - */ - -void UARTFIFORegisterWrite(unsigned int baseAdd, unsigned int fcrValue) -{ - unsigned int divLatchRegVal = 0; - unsigned int lcrRegValue = 0; - - /* Switching to Configuration Mode A. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_A); - - /* Clearing the contents of Divisor Latch Registers. */ - divLatchRegVal = UARTDivisorLatchWrite(baseAdd, 0x0000); - - /* Writing the 'fcrValue' to the FCR register. */ - HWREG(baseAdd + UART_FCR) = fcrValue; - - /* Programming the Divisor Latch Registers with the collected value. */ - UARTDivisorLatchWrite(baseAdd, divLatchRegVal); - - /* Reinstating the value of LCR register. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; -} - -/** - * \brief This API sets a certain bit in Enhanced Feature Register(EFR) which - * shall avail the UART to use some Enhanced Features. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return The value of ENHANCEDEN bit in EFR before it is modified in this API. - * - * \note This API switches UART to Configuration Mode B, sets the ENHANCEDEN - * bit in EFR and reverts the UART back to the original mode of - * operation. - * - */ - -unsigned int UARTEnhanFuncEnable(unsigned int baseAdd) -{ - unsigned int enhanFnBitVal = 0; - unsigned int lcrRegValue = 0; - - /* Enabling Configuration Mode B of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Collecting the current value of ENHANCEDEN bit of EFR. */ - enhanFnBitVal = (HWREG(baseAdd + UART_EFR) & UART_EFR_ENHANCED_EN); - - /* Setting the ENHANCEDEN bit in EFR register. */ - HWREG(baseAdd + UART_EFR) |= UART_EFR_ENHANCED_EN; - - /* Programming LCR with the collected value. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return enhanFnBitVal; -} - -/** - * \brief This API restores the ENHANCEDEN bit value of EFR register(EFR[4]) - * to the corresponding bit value in 'enhanFnBitVal' passed as a - * parameter to this API. - * - * \param baseAdd Memory address of the UART instance being used. - * \param enhanFnBitVal The 4th bit of this 32-bit value shall hold a value - * to which the ENHANCEDEN bit of EFR (EFR[4]) has to - * be restored to. - * - * \return None. - * - * \note The APIs UARTEnhanFuncEnable() and the current one are used - * hand-in-hand. While UARTEnhanFuncEnable() collects the EFR[4] bit - * value before modifying it, UARTEnhanFuncBitValRestore() can be used - * to restore EFR[4] bit value after the necessary operation is complete. - * This API switches the UART to Configuration Mode B, does the needful - * and reverts it back to original mode of operation. - * - */ - -void UARTEnhanFuncBitValRestore(unsigned int baseAdd, - unsigned int enhanFnBitVal) -{ - unsigned int lcrRegValue = 0; - - /* Enabling Configuration Mode B of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Restoring the value of EFR[4]. */ - HWREG(baseAdd + UART_EFR) &= ~(UART_EFR_ENHANCED_EN); - HWREG(baseAdd + UART_EFR) |= (enhanFnBitVal & UART_EFR_ENHANCED_EN); - - /* Programming LCR with the collected value. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; -} - - -/** - * \brief This API enables the MSR_SPR Sub-Configuration Mode of operation. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return The value of the TCRTLR bit in MCR (MCR[6]) before it is modified - * in this API. - * - * \note 1> Each Register configuration mode(A, B and operational) has - * further sub-configuration modes corresponding to accesses to - * offset addresses 0x18 and 0x1C. They are:\n - * For Register Configuration Mode A:\n - * 1> MSR_SPR: EFR[4] = 0 or MCR[6] = 0\n - * 2> TCR_TLR: EFR[4] = 1 and MCR[6] = 1\n - * For Register Configuration Mode B:\n - * 1> TCR_TLR - EFR[4] = 1 and MCR[6] = 1\n - * 2> XOFF - EFR[4] = 0 or MCR[6] = 0\n - * - * For Register Operational Mode:\n - * 1> MSR_SPR - EFR[4] = 0 or MCR[6] = 0\n - * 2> TCR_TLR - EFR[4] = 1 and MCR[6] = 1\n - * - * In any configuration mode, enabling one of the sub-configuration - * mode would disable access to the registers of the other - * sub-configuration mode.\n - * - * 2> The current API enables access to Modem Status Register(MSR) and - * Scratch Pad Register(SPR). This is applicable for Register - * Configuration Mode A and Operational mode of operation.\n - */ - -unsigned int UARTSubConfigMSRSPRModeEn(unsigned int baseAdd) -{ - unsigned int enhanFnBitVal = 0; - unsigned int tcrTlrValue = 0; - unsigned int lcrRegValue = 0; - - /* Switching to Configuration Mode B of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Collecting the current value of EFR[4] and later setting it. */ - enhanFnBitVal = HWREG(baseAdd + UART_EFR) & UART_EFR_ENHANCED_EN; - HWREG(baseAdd + UART_EFR) |= UART_EFR_ENHANCED_EN; - - /* Switching to Configuration Mode A of operation. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_A); - - /* Collecting the bit value of MCR[6]. */ - tcrTlrValue = (HWREG(baseAdd + UART_MCR) & UART_MCR_TCR_TLR); - - /* Clearing the TCRTLR bit in MCR register. */ - HWREG(baseAdd + UART_MCR) &= ~(UART_MCR_TCR_TLR); - - /* Switching to Configuration Mode B of operation. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Restoring the value of EFR[4]. */ - HWREG(baseAdd + UART_EFR) &= ~(UART_EFR_ENHANCED_EN); - HWREG(baseAdd + UART_EFR) |= enhanFnBitVal; - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return tcrTlrValue; -} - -/** - * \brief This API enables the TCR_TLR Sub_Configuration Mode of operation. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return The value of the TCRTLR bit in MCR (MCR[6]) before it is modified - * in this API. - * - * \note The current API enables access to Transmission Control Register(TCR) - * and Trigger Level Register(TLR). This is applicable for all the - * three register configuration modes. - * Refer to the comments of UARTSubConfigMSRSPRModeEn() API for more - * details. - */ - -unsigned int UARTSubConfigTCRTLRModeEn(unsigned int baseAdd) -{ - unsigned int enhanFnBitVal = 0; - unsigned int tcrTlrValue = 0; - unsigned int lcrRegValue = 0; - - /* Switching to Register Configuration Mode B. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Collecting the current value of EFR[4] and later setting it. */ - enhanFnBitVal = HWREG(baseAdd + UART_EFR) & UART_EFR_ENHANCED_EN; - HWREG(baseAdd + UART_EFR) |= UART_EFR_ENHANCED_EN; - - /* Switching to Register Configuration Mode A. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_A); - - /* Collecting the bit value of MCR[6]. */ - tcrTlrValue = (HWREG(baseAdd + UART_MCR) & UART_MCR_TCR_TLR); - - /* Setting the TCRTLR bit in Modem Control Register(MCR). */ - HWREG(baseAdd + UART_MCR) |= (UART_MCR_TCR_TLR); - - /* Switching to Register Configuration Mode B. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Restoring the value of EFR[4] to its original value. */ - HWREG(baseAdd + UART_EFR) &= ~(UART_EFR_ENHANCED_EN); - HWREG(baseAdd + UART_EFR) |= enhanFnBitVal; - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return tcrTlrValue; -} - -/** - * \brief This API enables the XOFF Sub-Configuration Mode of operation. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return The value of the TCRTLR bit in MCR (MCR[6]) before it is modified - * in this API. - * - * \note The current API enables access to the XOFF (XOFF1 and XOFF2) - * registers. The XOFF registers can be accessed in Register - * Configuration Mode B of operation. - * Refer to the comments of UARTSubConfigMSRSPRModeEn() API for more - * details. - */ - -unsigned int UARTSubConfigXOFFModeEn(unsigned int baseAdd) -{ - unsigned int enhanFnBitVal = 0; - unsigned int tcrTlrValue = 0; - unsigned int lcrRegValue = 0; - - /* Switching to Register Configuration Mode B. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Collecting the current value of EFR[4] and later setting it. */ - enhanFnBitVal = HWREG(baseAdd + UART_EFR) & UART_EFR_ENHANCED_EN; - HWREG(baseAdd + UART_EFR) |= UART_EFR_ENHANCED_EN; - - /* Switching to Configuration Mode A of operation. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_A); - - /* Collecting the bit value of TCRTLR(MCR[6]). */ - tcrTlrValue = (HWREG(baseAdd + UART_MCR) & UART_MCR_TCR_TLR); - - /* Clearing the TCRTLR bit in MCR register. */ - HWREG(baseAdd + UART_MCR) &= ~(UART_MCR_TCR_TLR); - - /* Switching to Register Configuration Mode B. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Restoring the value of EFR[4] to its original value. */ - HWREG(baseAdd + UART_EFR) &= ~(UART_EFR_ENHANCED_EN); - HWREG(baseAdd + UART_EFR) |= enhanFnBitVal; - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return tcrTlrValue; -} - -/** - * \brief This API restores the TCRTLR bit(MCR[6]) value in Modem Control - * Register(MCR) to the corresponding bit value in 'tcrTlrBitVal' - * passed as a parameter to this API. - * - * \param baseAdd Memory address of the UART instance being used. - * \param tcrTlrBitVal The 6th bit in this 32-bit value shall hold a value - * to which the TCRTLR bit(MCR[6]) of MCR has to be - * restored to. - * - * \return None. - */ - -void UARTTCRTLRBitValRestore(unsigned int baseAdd, - unsigned int tcrTlrBitVal) -{ - unsigned int enhanFnBitVal = 0; - unsigned int lcrRegValue = 0; - - /* Switching to Register Configuration Mode B. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Collecting the current value of EFR[4] and later setting it. */ - enhanFnBitVal = HWREG(baseAdd + UART_EFR) & UART_EFR_ENHANCED_EN; - HWREG(baseAdd + UART_EFR) |= UART_EFR_ENHANCED_EN; - - /* Switching to Configuration Mode A of operation. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_A); - - /* Programming MCR[6] with the corresponding bit value in 'tcrTlrBitVal'. */ - HWREG(baseAdd + UART_MCR) &= ~(UART_MCR_TCR_TLR); - HWREG(baseAdd + UART_MCR) |= (tcrTlrBitVal & UART_MCR_TCR_TLR); - - /* Switching to Register Configuration Mode B. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Restoring the value of EFR[4] to its original value. */ - HWREG(baseAdd + UART_EFR) &= ~(UART_EFR_ENHANCED_EN); - HWREG(baseAdd + UART_EFR) |= enhanFnBitVal; - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; -} - -/** - * \brief This API enables the specified interrupts in the UART mode of - * operation. - * - * \param baseAdd Memory address of the UART instance being used. - * \param intFlag Bit mask value of the bits corresponding to Interrupt - * Enable Register(IER). This specifies the UART interrupts - * to be enabled. - * - * 'intFlag' can take one or a combination of the following macros: - * - UART_INT_CTS - to enable Clear-To-Send interrupt, - * - UART_INT_RTS - to enable Request-To-Send interrupt, - * - UART_INT_XOFF - to enable XOFF interrupt, - * - UART_INT_SLEEPMODE - to enable Sleep Mode, - * - UART_INT_MODEM_STAT - to enable Modem Status interrupt, - * - UART_INT_LINE_STAT - to enable Line Status interrupt, - * - UART_INT_THR - to enable Transmitter Holding Register Empty interrupt, - * - UART_INT_RHR_CTI - to enable Receiver Data available interrupt and - * Character timeout indication interrupt. - * - * \return None. - * - * \note This API modifies the contents of UART Interrupt Enable Register - * (IER). Modifying the bits IER[7:4] requires that EFR[4] be set. - * This API does the needful before it accesses IER. - * Moreover, this API should be called when UART is operating in - * UART 16x Mode, UART 13x Mode or UART 16x Auto-baud mode.\n - * - */ - -void UARTIntEnable(unsigned int baseAdd, unsigned int intFlag) -{ - unsigned int enhanFnBitVal = 0; - unsigned int lcrRegValue = 0; - - /* Switching to Register Configuration Mode B. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Collecting the current value of EFR[4] and later setting it. */ - enhanFnBitVal = HWREG(baseAdd + UART_EFR) & UART_EFR_ENHANCED_EN; - HWREG(baseAdd + UART_EFR) |= UART_EFR_ENHANCED_EN; - - /* Switching to Register Operational Mode of operation. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - /* - ** It is suggested that the System Interrupts for UART in the - ** Interrupt Controller are enabled after enabling the peripheral - ** interrupts of the UART using this API. If done otherwise, there - ** is a risk of LCR value not getting restored and illicit characters - ** transmitted or received from/to the UART. The situation is explained - ** below. - ** The scene is that the system interrupt for UART is already enabled and - ** the current API is invoked. On enabling the interrupts corresponding - ** to IER[7:4] bits below, if any of those interrupt conditions - ** already existed, there is a possibility that the control goes to - ** Interrupt Service Routine (ISR) without executing the remaining - ** statements in this API. Executing the remaining statements is - ** critical in that the LCR value is restored in them. - ** However, there seems to be no risk in this API for enabling interrupts - ** corresponding to IER[3:0] because it is done at the end and no - ** statements follow that. - */ - - /************* ATOMIC STATEMENTS START *************************/ - - /* Programming the bits IER[7:4]. */ - HWREG(baseAdd + UART_IER) |= (intFlag & 0xF0); - - /* Switching to Register Configuration Mode B. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Restoring the value of EFR[4] to its original value. */ - HWREG(baseAdd + UART_EFR) &= ~(UART_EFR_ENHANCED_EN); - HWREG(baseAdd + UART_EFR) |= enhanFnBitVal; - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - /************** ATOMIC STATEMENTS END *************************/ - - /* Programming the bits IER[3:0]. */ - HWREG(baseAdd + UART_IER) |= (intFlag & 0x0F); -} - -/** - * \brief This API disables the specified interrupts in the UART mode of - * operation. - * - * \param baseAdd Memory address of the UART instance being used. - * \param intFlag Bit mask value of the bits corresponding to Interrupt - * Enable Register(IER). This specifies the UART interrupts - * to be disabled. - * - * 'intFlag' can take one or a combination of the following macros: - * - UART_INT_CTS - to disable Clear-To-Send interrupt, - * - UART_INT_RTS - to disable Request-To-Send interrupt, - * - UART_INT_XOFF - to disable XOFF interrupt, - * - UART_INT_SLEEPMODE - to disable Sleep Mode, - * - UART_INT_MODEM_STAT - to disable Modem Status interrupt, - * - UART_INT_LINE_STAT - to disable Line Status interrupt, - * - UART_INT_THR - to disable Transmitter Holding Register Empty interrupt, - * - UART_INT_RHR_CTI - to disable Receiver Data available interrupt and - * Character timeout indication interrupt. - * - * \return None - * - * \note The note section of UARTIntEnable() also applies to this API. - */ - -void UARTIntDisable(unsigned int baseAdd, unsigned int intFlag) -{ - unsigned int enhanFnBitVal = 0; - unsigned int lcrRegValue = 0; - - /* Switching to Register Configuration Mode B. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Collecting the current value of EFR[4] and later setting it. */ - enhanFnBitVal = HWREG(baseAdd + UART_EFR) & UART_EFR_ENHANCED_EN; - HWREG(baseAdd + UART_EFR) |= UART_EFR_ENHANCED_EN; - - /* Switching to Register Operational Mode of operation. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - HWREG(baseAdd + UART_IER) &= ~(intFlag & 0xFF); - - /* Switching to Register Configuration Mode B. */ - UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Restoring the value of EFR[4] to its original value. */ - HWREG(baseAdd + UART_EFR) &= ~(UART_EFR_ENHANCED_EN); - HWREG(baseAdd + UART_EFR) |= enhanFnBitVal; - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; -} - -/** - * \brief This API checks whether the TX FIFO (or THR in non-FIFO mode) - * is empty or not. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return TRUE - if the Transmitter FIFO(or THR in non-FIFO mode) is empty. - * FALSE - if the Transmitter FIFO(or THR in non-FIFO mode) is - * not empty.\n - */ - -unsigned int UARTSpaceAvail(unsigned int baseAdd) -{ - unsigned int lcrRegValue = 0; - unsigned int retVal = FALSE; - - /* Switching to Register Operational Mode of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - /* - ** Checking if either TXFIFOE or TXSRE bits of Line Status Register(LSR) - ** are set. TXFIFOE bit is set if TX FIFO(or THR in non-FIFO mode) is - ** empty. TXSRE is set if both the TX FIFO(or THR in non-FIFO mode) and - ** the transmitter shift register are empty. - */ - - if(HWREG(baseAdd + UART_LSR) & (UART_LSR_TX_SR_E | UART_LSR_TX_FIFO_E)) - { - retVal = TRUE; - } - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return retVal; -} - -/** - * \brief This API checks if the RX FIFO (or RHR in non-FIFO mode) has atleast - * one byte of data to be read. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return TRUE - if there is atleast one data byte present in the RX FIFO - * (or RHR in non-FIFO mode)\n - * FALSE - if there are no data bytes present in the RX FIFO(or RHR - * in non-FIFO mode)\n - */ - -unsigned int UARTCharsAvail(unsigned int baseAdd) -{ - unsigned int lcrRegValue = 0; - unsigned int retVal = FALSE; - - /* Switching to Register Operational Mode of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - /* Checking if the RHR(or RX FIFO) has atleast one byte to be read. */ - if(HWREG(baseAdd + UART_LSR) & UART_LSR_RX_FIFO_E) - { - retVal = TRUE; - } - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return retVal; -} - -/** - * \brief This API attempts to write a byte into Transmitter Holding - * Register (THR). It checks only once if the transmitter is empty. - * - * \param baseAdd Memory address of the UART instance being used. - * \param byteWrite Byte to be written into the THR register. - * - * \return TRUE if the transmitter FIFO(or THR register in non-FIFO mode) - * was empty and the character was written. Else it returns FALSE. - */ - -unsigned int UARTCharPutNonBlocking(unsigned int baseAdd, - unsigned char byteWrite) -{ - unsigned int lcrRegValue = 0; - unsigned int retVal = FALSE; - - /* Switching to Register Operational Mode of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - /* - ** Checking if either THR alone or both THR and Transmitter Shift Register - ** are empty. - */ - if(HWREG(baseAdd + UART_LSR) & (UART_LSR_TX_SR_E | UART_LSR_TX_FIFO_E)) - { - HWREG(baseAdd + UART_THR) = byteWrite; - retVal = TRUE; - } - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return retVal; -} - - -/** - * \brief This API reads a byte from the Receiver Buffer Register - * (RBR). It checks once if any character is ready to be read. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return If the RX FIFO(or RHR) was found to have atleast one byte of - * data, then this API reads and returns that byte. Else it - * returns -1. - */ - -signed char UARTCharGetNonBlocking(unsigned int baseAdd) -{ - unsigned int lcrRegValue = 0; - signed char retVal = -1; - - /* Switching to Register Operational Mode of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - /* Checking if the RX FIFO(or RHR) has atleast one byte of data. */ - if(HWREG(baseAdd + UART_LSR) & UART_LSR_RX_FIFO_E) - { - retVal = (signed char)HWREG(baseAdd + UART_RHR); - } - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return retVal; -} - -/** - * \brief This API waits indefinitely for the arrival of a byte in - * the receiver FIFO. Once a byte has arrived, it returns that - * byte. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return This returns the read byte. - */ - -signed char UARTCharGet(unsigned int baseAdd) -{ - unsigned int lcrRegValue = 0; - signed char retVal = 0; - - /* Switching to Register Operational Mode of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - /* Waits indefinitely until a byte arrives in the RX FIFO(or RHR). */ - while(0 == (HWREG(baseAdd + UART_LSR) & UART_LSR_RX_FIFO_E)); - - retVal = ((signed char)HWREG(baseAdd + UART_RHR)); - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return retVal; -} - -/** - * \brief This API waits indefinitely until the Transmitter FIFO - * (THR register in non-FIFO mode) and Transmitter Shift - * Register are empty. On empty, it writes a byte to the THR. - * - * \param baseAdd Memory address of the UART instance being used - * \param byteTx The byte to be transmitted by the UART. - * - * \return None - */ - -void UARTCharPut(unsigned int baseAdd, unsigned char byteTx) -{ - unsigned int lcrRegValue = 0; - - /* Switching to Register Operational Mode of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - /* - ** Waits indefinitely until the THR and Transmitter Shift Registers are - ** empty. - */ - while((UART_LSR_TX_SR_E | UART_LSR_TX_FIFO_E) != - (HWREG(baseAdd + UART_LSR) & (UART_LSR_TX_SR_E | UART_LSR_TX_FIFO_E))); - - HWREG(baseAdd + UART_THR) = byteTx; - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; -} - -/** - * \brief This API reads the receiver data error status. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return This returns the error status. This can be one or a combination - * of the below values: - * - UART_OVERRUN_ERROR - indicating Overrun error occured\n - * - UART_PARITY_ERROR - indicating Parity error occured\n - * - UART_FRAMING_ERROR - indicating Framing error occured\n - * - UART_BREAK_DETECTED_ERROR - indicating a Break condition was - * detected\n - * - UART_FIFO_PE_FE_BI_DETECTED - indicating that atleast one parity - * error, framing error or a break indication is present in the - * RX FIFO\n - */ - -unsigned int UARTRxErrorGet(unsigned int baseAdd) -{ - unsigned int lcrRegValue = 0; - unsigned int retVal = 0; - - /* Switching to Register Operational Mode of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - retVal = (HWREG(baseAdd + UART_LSR) & (UART_LSR_RX_FIFO_STS | - UART_LSR_RX_BI | - UART_LSR_RX_FE | - UART_LSR_RX_PE | - UART_LSR_RX_OE)); - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return retVal; -} - -/** - * \brief This API determines the UART Interrupt Status. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return This returns one or a combination of the following macros: - * - UART_INTID_MODEM_STAT - indicating the occurence of a Modem Status - * interrupt\n - * - UART_INTID_TX_THRES_REACH - indicating that the TX FIFO Threshold - * number of bytes can be written to the TX FIFO. - * - UART_INTID_RX_THRES_REACH - indicating that the RX FIFO has - * reached its programmed Trigger Level\n - * - UART_INTID_RX_LINE_STAT_ERROR - indicating the occurence of a - * receiver Line Status error\n - * - UART_INTID_CHAR_TIMEOUT - indicating the occurence of a Receiver - * Timeout\n - * - UART_INTID_XOFF_SPEC_CHAR_DETECT - indicating the detection of XOFF - * or a Special character\n - * - UART_INTID_MODEM_SIG_STATE_CHANGE - indicating that atleast one of - * the Modem signals among CTSn, RTSn and DSRn have changed states - * from active(low) to inactive(high)\n - */ - -unsigned int UARTIntIdentityGet(unsigned int baseAdd) -{ - unsigned int lcrRegValue = 0; - unsigned int retVal = 0; - - /* Switching to Register Operational Mode of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - retVal = (HWREG(baseAdd + UART_IIR) & UART_IIR_IT_TYPE); - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return retVal; -} - -/** - * \brief This API determines whether any UART interrupt condition is - * still alive and is pending to be serviced. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return UART_INT_PENDING - if servicing an interrupt is still pending\n - * UART_N0_INT_PENDING - if there are no interrupts to be serviced\n - */ - -unsigned int UARTIntPendingStatusGet(unsigned int baseAdd) -{ - unsigned int retVal = UART_N0_INT_PENDING; - unsigned int lcrRegValue = 0; - - /* Switching to Register Operational Mode of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - /* Checking if an Interrupt is pending. */ - if(!(HWREG(baseAdd + UART_IIR) & UART_IIR_IT_PENDING)) - { - retVal = UART_INT_PENDING; - } - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return retVal; -} - -/** - * \brief This API determines whether FIFO mode of operation is enabled - * for the UART instance or not. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return TRUE - if FIFO mode of operation is enabled\n - * FALSE - if FIFO mode of operation is disabled\n - */ - -unsigned int UARTFIFOEnableStatusGet(unsigned int baseAdd) -{ - unsigned int lcrRegValue = 0; - unsigned int retVal = FALSE; - - /* Switching to Register Operational Mode of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_OPERATIONAL_MODE); - - if(HWREG(baseAdd + UART_IIR) & UART_IIR_FCR_MIRROR) - { - retVal = TRUE; - } - - /* Restoring the value of LCR. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return retVal; -} - -/** - * \brief This API controls the use of Auto-RTS and Auto-CTS features which - * are used in Hardware Flow Control Mode of operation. The - * Auto-RTS and Auto-CTS functions can be individually enabled or - * disabled. - * - * \param baseAdd Memory address of the UART instance being used. - * \param autoCtsControl This specifies whether to enable or disable - * Auto-CTS functionality - * \param autoRtsControl This specifies whether to enable of disable - * Auto-RTS functionality - * - * 'autoCtsControl' can take one of the following values: - * - UART_AUTO_CTS_DISABLE - to disable Auto-CTS functionality\n - * - UART_AUTO_CTS_ENABLE - to enable Auto-CTS functionality\n - * - * 'autoRtsControl' can take either of the following values: - * - UART_AUTO_RTS_DISABLE - to disable Auto-RTS functionality\n - * - UART_AUTO_RTS_ENABLE - to enable Auto-RTS functionality\n - * - * \return None. - * - * \note This API switches UART to Configuration Mode B, programs - * AUTOCTSEN and AUTORTSEN bits in EFR and reverts the UART back - * to the original mode of operation. - */ - -void UARTAutoRTSAutoCTSControl(unsigned int baseAdd, - unsigned int autoCtsControl, - unsigned int autoRtsControl) -{ - unsigned int lcrRegValue = 0; - - /* Switching to Configuration Mode B of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Clearing AUTOCTSEN and AUTORTSEN bits in EFR. */ - HWREG(baseAdd + UART_EFR) &= ~(UART_EFR_AUTO_CTS_EN | - UART_EFR_AUTO_RTS_EN); - - /* Programming AUTOCTSEN and AUTORTSEN bits in EFR. */ - HWREG(baseAdd + UART_EFR) |= (autoCtsControl & UART_EFR_AUTO_CTS_EN); - HWREG(baseAdd + UART_EFR) |= (autoRtsControl & UART_EFR_AUTO_RTS_EN); - - /* Restoring LCR with the collected value. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; -} - -/** - * \brief This API controls the feature of detecting a Special Character - * arriving in the receiver. - * - * \param baseAdd Memory address of the UART instance being used. - * \param controlFlag This specifies whether to enable or disable detection - * of Special Character. - * - * 'controlFlag' can take either of the following two values:\n - * - UART_SPECIAL_CHAR_DETECT_DISABLE - to disable detection of Special - * Character\n - * - UART_SPECIAL_CHAR_DETECT_ENABLE - to enable detection of Special - * Character\n - * - * \return None. - * - * \note This API switches the UART to Configuration Mode B, programs - * SPECIALCHARDETECT field in EFR and reverts the UART back to - * the original mode of operation. - * - */ - -void UARTSpecialCharDetectControl(unsigned int baseAdd, - unsigned int controlFlag) -{ - unsigned int lcrRegValue = 0; - - /* Switch to Configuration Mode B of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - HWREG(baseAdd + UART_EFR) &= ~(UART_EFR_SPECIAL_CHAR_DETECT); - - /* Programming the SPECIALCHARDETECT bit in EFR. */ - HWREG(baseAdd + UART_EFR) |= (controlFlag & UART_EFR_SPECIAL_CHAR_DETECT); - - /* Restoring LCR with the collected value. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; -} - -/** - * \brief This API configures the options for Software Flow Control. - * - * \param baseAdd Memory address of the UART instance being used. - * \param swFlowCtrl This specifies one of the options available for - * software flow control. - * - * 'swFlowCtrl' can take one of the following values: - * - UART_NO_SOFTWARE_FLOW_CONTROL - To disable Software Flow control\n - * - UART_TX_RX_XON1_XOFF1 - Transmitter transmits XON1, XOFF1; - * Receiver expects XON1, XOFF1\n - * - UART_TX_RX_XON2_XOFF2 - Transmitter transmits XON2, XOFF2; - * Receiver expects XON2, XOFF2\n - * - UART_TX_RX_XON1_XOFF1_XON2_XOFF2 - Transmitter transmits XON1,XON2, - * XOFF1 and XOFF2; Receiver expects XON1,XON2, - * XOFF1, XOFF2\n - * - * \return None. - * - * \note This API switches the UART to Configuration Mode B, programs - * SWFLOWCONTROL field in EFR and reverts the UART back to the - * original mode of operation. - */ - -void UARTSoftwareFlowCtrlOptSet(unsigned int baseAdd, - unsigned int swFlowCtrl) -{ - unsigned int lcrRegValue = 0; - - /* Switching to Configuration Mode B of operation. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Clearing the SWFLOWCONTROL field in EFR. */ - HWREG(baseAdd + UART_EFR) &= ~(UART_EFR_SW_FLOW_CONTROL); - - /* Configuring the SWFLOWCONTROL field in EFR. */ - HWREG(baseAdd + UART_EFR) |= (swFlowCtrl & UART_EFR_SW_FLOW_CONTROL); - - /* Restoring LCR with the collected value. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; -} - - -/** - * \brief Used only in UART mode, this API is used to control the pulse - * shaping feature. Pulse shaping feature could either be enabled - * or disabled in UART mode. - * - * \param baseAdd Memory address of the UART instance being used. - * \param shapeControl This specifies whether to enable or disable Pulse - * shaping feature in UART mode - * - * 'shapeControl' can take either of the two following values:\n - * - UART_PULSE_NORMAL - to disable Pulse Shaping feature which is the Normal - * and default configuration\n - * - UART_PULSE_SHAPING - to enable Pulse Shaping feature\n - * - * \return None - */ - -void UARTPulseShapingControl(unsigned int baseAdd, unsigned int shapeControl) -{ - /* Clearing the UARTPULSE bit in MDR2. */ - HWREG(baseAdd + UART_MDR2) &= ~(UART_MDR2_UART_PULSE); - - /* Programming the UARTPULSE bit in MDR2. */ - HWREG(baseAdd + UART_MDR2) |= (shapeControl & UART_MDR2_UART_PULSE); -} - -/** - * \brief This API performs a module reset of the UART module. It also - * waits until the reset process is complete. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return None. - * - * \note This API accesses the System Configuration Register(SYSC) and - * System Status Register(SYSS) to perform module reset and to - * wait until the same is complete. - */ - -void UARTModuleReset(unsigned int baseAdd) -{ - /* Performing Software Reset of the module. */ - HWREG(baseAdd + UART_SYSC) |= (UART_SYSC_SOFTRESET); - - /* Wait until the process of Module Reset is complete. */ - while(!(HWREG(baseAdd + UART_SYSS) & UART_SYSS_RESETDONE)); -} - -/** - * \brief This API can be used to control the Power Management - * request/acknowledgement process. - * - * \param baseAdd Memory address of the UART instance being used. - * \param modeFlag This specifies the Power Management - * request/acknowledgement process to be followed - * - * 'modeFlag' can take one of the following values: - * - UART_IDLEMODE_FORCE_IDLE - to enable Force Idle mode\n - * - UART_IDLEMODE_NO_IDLE - to enable No-Idle mode\n - * - UART_IDLEMODE_SMART_IDLE - to enable Smart Idle mode\n - * - UART_IDLEMODE_SMART_IDLE_WAKEUP - to enable Smart Idle Wakeup mode\n - * - * \return None - */ - -void UARTIdleModeConfigure(unsigned int baseAdd, unsigned int modeFlag) -{ - /* Clearing the IDLEMODE field in SYSC. */ - HWREG(baseAdd + UART_SYSC) &= ~(UART_SYSC_IDLEMODE); - - /* Programming the IDLEMODE field in SYSC. */ - HWREG(baseAdd + UART_SYSC) |= (modeFlag & UART_SYSC_IDLEMODE); -} - -/** - * \brief This API is used to control(enable/disable) the Wake-Up feature - * of the UART. - * - * \param baseAdd Memory address of the UART instance being used. - * \param controlFlag This specifies whether the Wake Up feature should - * be enabled or disabled for the UART instance - * - * 'controlFlag' can take one of the following two values: - * - UART_WAKEUP_ENABLE - to enable Wake-Up feature\n - * - UART_WAKEUP_DISABLE - to disable Wake-Up feature\n - * - * \return None - */ - -void UARTWakeUpControl(unsigned int baseAdd, unsigned int controlFlag) -{ - /* Clearing the ENAWAKEUP bit in SYSC register. */ - HWREG(baseAdd + UART_SYSC) &= ~(UART_SYSC_ENAWAKEUP); - - /* Programming the ENAWAKEUP feature in SYSC register. */ - HWREG(baseAdd + UART_SYSC) |= (controlFlag & UART_SYSC_ENAWAKEUP); -} - -/** - * \brief This API is used to control(enable/disable) the Auto-Idle mode - * of operation of the UART. - * - * \param baseAdd Memory address of the UART instance being used. - * \param modeFlag This specifies whether to enable or disable the - * Auto-Idle mode of the UART - * - * 'modeFlag' can take one of the following two values: - * - UART_AUTO_IDLE_MODE_DISABLE - to disable Auto-Idle mode\n - * - UART_AUTO_IDLE_MODE_ENABLE - to enable Auto-Idle mode\n - * - * \return None - */ - -void UARTAutoIdleModeControl(unsigned int baseAdd, unsigned int modeFlag) -{ - /* Clearing the AUTOIDLE bit in SYSC register. */ - HWREG(baseAdd + UART_SYSC) &= ~(UART_SYSC_AUTOIDLE); - - /* Programming the AUTOIDLE bit in SYSC register. */ - HWREG(baseAdd + UART_SYSC) |= (modeFlag & UART_SYSC_AUTOIDLE); -} - - -/** - * \brief This API configures the Receiver FIFO threshold level to - * start/stop transmission during Hardware Flow Control. - * - * \param baseAdd Memory address of the UART instance being used. - * \param rtsHaltFlag The receiver FIFO threshold level on attaining - * which the RTS line is deasserted signalling the - * transmitter of its counterpart to stop trasmitting. - * \param rtsStartFlag The receiver FIFO threshold level on attaining - * which the RTS line is asserted signalling the - * transmitter of its counterpart to start transmitting. - * - * 'rtsHaltFlag' can take one among the following values:\n - * - m, where (1 <= m <= 15).\n - * The HALT trigger level would then be (m * 4).\n - * 'rtsStartFlag' can take one among the following values:\n - * - n, where (1 <= n <= 15).\n - * The RESTORE trigger level would then be (n * 4).\n - * - * For Example: If m = 8 and n = 5, then the receiver trigger levels would be:\n - * HALT = (8 * 4) = 32, RESTORE = (5 * 4) = 20.\n - * - * \return None. - * - * \note Here two things should be taken care of:\n - * 1> RX FIFO Threshold Level to Halt Transmission should be greater - * than the Threshold level to Start transmission - * i.e. TCR[3:0] > TCR[7:4].\n - * 2> In FIFO Interrupt mode with Flow Control, the RX FIFO threshold - * level to Halt Transmission (TCR[3:0]) should be greater than or - * equal to the Receiver FIFO trigger level(TLR[7:4] or FCR[7:6]).\n - */ - -void UARTFlowCtrlTrigLvlConfig(unsigned int baseAdd, - unsigned int rtsHaltFlag, - unsigned int rtsStartFlag) -{ - /* Clearing the RXFIFOTRIGHALT field in TCR. */ - HWREG(baseAdd + UART_TCR) &= ~(UART_TCR_RX_FIFO_TRIG_HALT); - /* Programming the RXFIFOTRIGHALT field in TCR. */ - HWREG(baseAdd + UART_TCR) |= (rtsHaltFlag & UART_TCR_RX_FIFO_TRIG_HALT); - - /* Clearing the RXFIFOTRIGSTART field in TCR. */ - HWREG(baseAdd + UART_TCR) &= ~(UART_TCR_RX_FIFO_TRIG_START); - /* Programming the RXFIFOTRIGSTART field in TCR. */ - HWREG(baseAdd + UART_TCR) |= ((rtsStartFlag << - UART_TCR_RX_FIFO_TRIG_START_SHIFT) & - UART_TCR_RX_FIFO_TRIG_START); -} - -/** - * \brief This API programs the XON1/ADDR1 and XOFF1 registers. - * - * \param baseAdd Memory address of the UART instance being used. - * \param xon1Value The XON1 character. - * \param xoff1Value The XOFF1 character. - * - * \return None. - * - * \note In UART mode, the character in XON1/ADDR1 register is the XON1 - * character. In IrDA mode, this is the address ADDR1. - */ - -void UARTXON1XOFF1ValProgram(unsigned int baseAdd, - unsigned char xon1Value, - unsigned char xoff1Value) -{ - /* Programming the XON1 register. */ - HWREG(baseAdd + UART_XON1_ADDR1) = xon1Value; - - /* Programming the XOFF1 register. */ - HWREG(baseAdd + UART_XOFF1) = xoff1Value; -} - -/** - * \brief This API programs the XON2/ADDR2 and XOFF2 registers. - * - * \param baseAdd Memory address of the UART instance being used. - * \param xon2Value The XON2 character. - * \param xoff2Value The XOFF2 character. - * - * \return None. - * - * \note In UART mode, the character in XON2/ADDR2 register is the XON2 - * character. In IrDA mode, this is the address ADDR2. - * - */ - -void UARTXON2XOFF2ValProgram(unsigned int baseAdd, - unsigned char xon2Value, - unsigned char xoff2Value) -{ - /* Programming the XON2 register. */ - HWREG(baseAdd + UART_XON2_ADDR2) = xon2Value; - - /* Programming the XOFF2 register. */ - HWREG(baseAdd + UART_XOFF2) = xoff2Value; -} - - -/** - * \brief This API controls(enables/disables) the XON-any feature in Modem - * Control Register(MCR). - * - * \param baseAdd Memory address of the UART instance being used. - * \param controlFlag This specifies whether to enable or disable XON any - * feature - * - * 'xonAnyControl' can take one of the following values: - * - UART_XON_ANY_ENABLE - to enable XON any functionality\n - * - UART_XON_ANY_DISABLE - to disable XON any functionality\n - * - * \return None. - * - * \note When XON-any feature is enabled, the transmission will resume after - * receiving any character after recognizing the XOFF character. The - * XON-any character is written into the RX FIFO even if it is a - * software flow character.\n - */ - -void UARTXONAnyFeatureControl(unsigned int baseAdd, unsigned int controlFlag) -{ - unsigned int lcrRegValue = 0; - unsigned int enhanFnBitVal = 0; - - /* Switching to Register Configuration Mode B. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B); - - /* Collecting the value of EFR[4] and later setting the same to 1. */ - enhanFnBitVal = (HWREG(baseAdd + UART_EFR) & UART_EFR_ENHANCED_EN); - HWREG(baseAdd + UART_EFR) |= UART_EFR_ENHANCED_EN; - - /* Clearing the XONEN bit in MCR. */ - HWREG(baseAdd + UART_MCR) &= ~(UART_MCR_XON_EN); - - /* Programming the XONEN bit in MCR. */ - HWREG(baseAdd + UART_MCR) |= (controlFlag & UART_MCR_XON_EN); - - /* - ** Clearing the bit value of EFR[4] and later restoring it to the - ** original value. - */ - HWREG(baseAdd + UART_EFR) &= ~(UART_EFR_ENHANCED_EN); - HWREG(baseAdd + UART_EFR) |= enhanFnBitVal; - - /* Restoring LCR to the original value. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; -} - -/** - * \brief This API controls(enables/disables) the Loopback mode of operation - * for the UART instance. - * - * \param baseAdd Memory address of the UART instance being used - * \param controlFlag This specifies whether to enable or disable Loopback - * mode of operation - * - * 'controlFlag' can take one of the following values: - * - UART_LOOPBACK_MODE_ENABLE - to enable Loopback mode of operation\n - * - UART_LOOPBACK_MODE_DISABLE - to disable Loopback mode and thus resulting - * in switching to Normal operating mode\n - * - * \return None - */ - -void UARTLoopbackModeControl(unsigned int baseAdd, unsigned int controlFlag) -{ - /* Clearing the LOOPBACKEN bit in MCR. */ - HWREG(baseAdd + UART_MCR) &= ~(UART_MCR_LOOPBACK_EN); - - /* Programming the LOOPBACKEN bit in MCR. */ - HWREG(baseAdd + UART_MCR) |= (controlFlag & UART_MCR_LOOPBACK_EN); -} - -/** - * \brief This API switches the specified Modem Control Signals to active - * state. The Modem Control signals in context are DCD, RI, RTS and - * DTR. - * - * \param baseAdd Memory address of the UART instance being used. - * \param modeFlag This specifies the signals that are required to be - * switched to active state. Bits MCR[3:0] hold control - * for switching Modem Control Signals to active/inactive - * state. - * - * 'modeFlag' can take one or a combination of the following values:\n - * - UART_DCD_CONTROL - specifying to force DCDn input to active state(low)\n - * - UART_RI_CONTROL - specifying to force RIn input to active state(low)\n - * - UART_RTS_CONTROL - specifying to force RTSn output to active state (low)\n - * - UART_DTR_CONTROL - specifying to force DTRn output to active state (low)\n - * - * \return None. - */ - -void UARTModemControlSet(unsigned int baseAdd, unsigned int modeFlag) -{ - /* Programming the specified bits of MCR. */ - HWREG(baseAdd + UART_MCR) |= (modeFlag & (UART_MCR_CD_STS_CH | - UART_MCR_RI_STS_CH | - UART_MCR_RTS | - UART_MCR_DTR)); - -} - -/** - * \brief This API switches the specified Modem Control signals to inactive - * state. The Modem Control signals in context are DCD, RI, RTS and - * DTR. - * - * \param baseAdd Memory address of the UART instance being used. - * \param modeFlag This specifies the signals that are required to be - * switched to inactive state. Bits MCR[3:0] hold control - * for switching Modem Control Signals to active/inactive - * state. - - * - * 'modeFlag' can take one or a combination of the following values:\n - * - UART_DCD_CONTROL - specifying to force DCDn input to inactive state(high)\n - * - UART_RI_CONTROL - specifying to force RIn input to inactive state (high)\n - * - UART_RTS_CONTROL - specifying to force RTSn output to inactive state(high)\n - * - UART_DTR_CONTROL - specifying to force DTRn output to inactive state(high)\n - * - * \return None - */ - -void UARTModemControlClear(unsigned int baseAdd, unsigned int modeFlag) -{ - /* Clearing the specified bits in MCR. */ - HWREG(baseAdd + UART_MCR) &= ~(modeFlag & (UART_MCR_CD_STS_CH | - UART_MCR_RI_STS_CH | - UART_MCR_RTS | - UART_MCR_DTR)); -} - -/** - * \brief This API reads the values on Modem Signal Lines. The Modem Signals - * in context are: - * 1> Data Carrier Detect(DCD)\n - * 2> Ring Indicator(RI)\n - * 3> Data Set Ready(DSR)\n - * 4> Clear To Send(CTS)\n - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return The value returned could be one of the following macros, a - * combination or all of it.\n - * - UART_DCD_VALUE - indicating DCDn line is active(low)\n - * - UART_RI_VALUE - indicating RIn line is active(low)\n - * - UART_DSR_VALUE - indicating DSRn line is active(low)\n - * - UART_CTS_VALUE - indicating CTSn line is active(low)\n - */ - -unsigned int UARTModemStatusGet(unsigned int baseAdd) -{ - /* - ** Reading MSR[7:4] bits. These values indicate the complement of the - ** signal levels on the Modem input lines. - */ - - return(HWREG(baseAdd + UART_MSR) & (UART_MSR_NCD_STS | - UART_MSR_NRI_STS | - UART_MSR_NDSR_STS | - UART_MSR_NCTS_STS)); -} - -/** - * \brief This API determines if the values on Modem Signal Lines have - * changed since the last read of Modem Status Register(MSR). - * The Modem Signals in context are DCD, RI, DSR, CTS. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return The value returned could be one of the following macros, a - * combination or all of it. - * - UART_DCD_STS_CHANGED - indicating that DCDn input changed state - * since the last read of MSR\n - * - UART_RI_STS_CHANGED - indicating that RIn input changed state - * since the last read of MSR\n - * - UART_DSR_STS_CHANGED - indicating that DSRn input changed state - * since the last read of MSR\n - * - UART_CTS_STS_CHANGED - indicating that CTSn input changed state - * since the last read of MSR\n - */ - -unsigned int UARTModemStatusChangeCheck(unsigned int baseAdd) -{ - /* - ** Reading MSR[3:0] bits that indicate the change of state of Modem signal - ** lines. - */ - return(HWREG(baseAdd + UART_MSR) & (UART_MSR_DCD_STS | - UART_MSR_RI_STS | - UART_MSR_DSR_STS | - UART_MSR_CTS_STS)); -} - -/** - * \brief This API reads the RESUME register which clears the internal flags. - * - * \param baseAdd Memory address of the UART instance being used - * - * \return None - * - * \note When conditions like TX Underrun/RX Overrun errors occur, the - * transmission/reception gets halted and some internal flags are set. - * Clearing these flags would resume the halted operation. - */ - -void UARTResumeOperation(unsigned int baseAdd) -{ - /* Dummy read of RESUME register. */ - HWREG(baseAdd + UART_RESUME); -} - - -/** - * \brief This API enables the Wake-Up capability for the specified events. - * On enabling Wake-Up capability for them, the occurence of the - * corresponding event shall wake up the system. - * - * \param baseAdd Memory address of the UART instance being used. - * \param wakeUpFlag This specifies the event(s) for which Wake-Up - * capability needs to be enabled. - * - * 'wakeUpFlag' can take one or a combination of the following values: - * - UART_WAKEUP_TX_INTERRUPT - enabling THR, TXDMA and TXSTATUS - * interrupts to wake up the system\n - * - UART_WAKEUP_RLS_INTERRUPT - enabling the Receiver Line Status - * interrupt to wake up the system\n - * - UART_WAKEUP_RHR_INTERRUPT - enabling the RHR interrupt(RX FIFO - * threshold level reached) to wake up the system\n - * - UART_WAKEUP_RX_ACTIVITY - enabling any activity on the Receiver line - * (RX) to wake up the system\n - * - UART_WAKEUP_DCD_ACTIVITY - enabling any activity on DCD line to wake - * up the system\n - * - UART_WAKEUP_RI_ACTIVITY - enabling any activity on RI line to wake up - * the system\n - * - UART_WAKEUP_DSR_ACTIVITY - enabling any acivity on DSR line to wake up - * the system\n - * - UART_WAKEUP_CTS_ACTIVITY - enabling any activity on CTS line to wake up - * the system\n - * - * \return None - */ - -void UARTWakeUpEventsEnable(unsigned int baseAdd, unsigned int wakeUpFlag) -{ - /* Programming the Wake-Up configuration fields in WER. */ - HWREG(baseAdd + UART_WER) |= (wakeUpFlag & - (UART_WER_EVENT_7_TX_WAKEUP_EN | - UART_WER_EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT | - UART_WER_EVENT_5_RHR_INTERRUPT | - UART_WER_EVENT_4_RX_ACTIVITY | - UART_WER_EVENT_3_DCD_CD_ACTIVITY | - UART_WER_EVENT_2_RI_ACTIVITY | - UART_WER_EVENT_1_DSR_ACTIVITY | - UART_WER_EVENT_0_CTS_ACTIVITY)); -} - -/** - * \brief This API disables the Wake-Up capability for the specified events. - * On disabling Wake-Up capability for them, the occurence of the - * corresponding event shall not wake up the system. - * - * \param baseAdd Memory address of the UART instance being used. - * \param wakeUpFlag This specifies the event(s) for which Wake-Up - * capability needs to be disabled. - * - * 'wakeUpFlag' can take one or a combination of the following values: - * - UART_WAKEUP_TX_INTERRUPT - disabling THR, TXDMA and TXSTATUS - * interrupts to wake up the system\n - * - UART_WAKEUP_RLS_INTERRUPT - disabling the Receiver Line Status - * interrupt to wake up the system\n - * - UART_WAKEUP_RHR_INTERRUPT - disabling the RHR interrupt(RX FIFO - * threshold level reached) to wake up the system\n - * - UART_WAKEUP_RX_ACTIVITY - disabling any activity on the Receiver line - * (RX) to wake up the system\n - * - UART_WAKEUP_DCD_ACTIVITY - disabling any activity on DCD line to wake - * up the system\n - * - UART_WAKEUP_RI_ACTIVITY - disabling any activity on RI line to wake up - * the system\n - * - UART_WAKEUP_DSR_ACTIVITY - disabling any acivity on DSR line to wake up - * the system\n - * - UART_WAKEUP_CTS_ACTIVITY - disabling any activity on CTS line to wake up - * the system\n - * - * \return None - */ - -void UARTWakeUpEventsDisable(unsigned int baseAdd, unsigned int wakeUpFlag) -{ - /* Programming the Wake-Up configuration fields in WER. */ - HWREG(baseAdd + UART_WER) &= ~(wakeUpFlag & - (UART_WER_EVENT_7_TX_WAKEUP_EN | - UART_WER_EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT | - UART_WER_EVENT_5_RHR_INTERRUPT | - UART_WER_EVENT_4_RX_ACTIVITY | - UART_WER_EVENT_3_DCD_CD_ACTIVITY | - UART_WER_EVENT_2_RI_ACTIVITY | - UART_WER_EVENT_1_DSR_ACTIVITY | - UART_WER_EVENT_0_CTS_ACTIVITY)); -} - - -/** - * \brief This API controls the feature of setting the Trigger Level - * granularity as 1 for Transmitter and Receiver FIFOs. - * - * \param baseAdd Memory address of the UART instance being used. - * \param rxFIFOGranCtrl This specifies whether the trigger level - * granularity for the RX FIFO is to be 1 or not - * \param txFIFOGranCtrl This specifies whether the trigger level - * granularity for the TX FIFO is to be 1 or not - * - * 'rxFIFOGranCtrl' can take either of the following values: - * - UART_RX_TRIG_LVL_GRAN_1_DISABLE - to disable usage of a granularity of 1 - * for RX FIFO Trigger level\n - * - UART_RX_TRIG_LVL_GRAN_1_ENABLE - to set a granularity of 1 for RX FIFO - * Trigger level\n - * - * 'txFIFOGranCtrl' can take either of the following values: - * - UART_TX_TRIG_LVL_GRAN_1_DISABLE - to disable usage of a granularity of 1 - * for TX FIFO Trigger level\n - * - UART_TX_FIFO_LVL_GRAN_1_ENABLE - to set a granularity of 1 for TX FIFO - * Trigger level\n - * - * \return None - */ - -void UARTFIFOTrigLvlGranControl(unsigned int baseAdd, - unsigned int rxFIFOGranCtrl, - unsigned int txFIFOGranCtrl) -{ - /* Clearing the RXTRIGGRANU1 and TXTRIGGRANU1 bits in SCR. */ - HWREG(baseAdd + UART_SCR) &= ~(UART_SCR_RX_TRIG_GRANU1 | - UART_SCR_TX_TRIG_GRANU1); - - /* Programming the RXTRIGGRANU1 bit in SCR. */ - HWREG(baseAdd + UART_SCR) |= (rxFIFOGranCtrl & UART_SCR_RX_TRIG_GRANU1); - - /* Programming the TXTRIGGRANU1 bit in SCR. */ - HWREG(baseAdd + UART_SCR) |= (txFIFOGranCtrl & UART_SCR_TX_TRIG_GRANU1); -} - -/** - * \brief This API controls the interrupt enable and disable feature for - * Data Set Ready(DSRn) interrupt. - * - * \param baseAdd Memory address of the UART instance being used - * \param controlFlag This specifies whether to enable or disable DSRn - * interrupt - * - * 'controlFlag' can take one of the following values: - * - UART_DSRn_INT_DISABLE - to disable DSRn interrupt\n - * - UART_DSRn_INT_ENABLE - to enable DSRn interrupt\n - * - * \return None - */ - -void UARTDSRInterruptControl(unsigned int baseAdd, unsigned int controlFlag) -{ - HWREG(baseAdd + UART_SCR) &= ~(UART_SCR_DSR_IT); - /* Programming the DSRIT bit in SCR. */ - HWREG(baseAdd + UART_SCR) |= (controlFlag & UART_SCR_DSR_IT); -} - -/** - * \brief This API is used to choose a condition under which a - * Transmit Holding Register(THR) Interrupt should occur. - * A THR interrupt can be configured to occur either when:\n - * 1> TX FIFO becoming empty OR\n - * 2> TX FIFO and TX Shift register becoming empty. - * - * \param baseAdd Memory address of the UART instance being used - * \param controlFlag This specifies the condition under which a Transmitter - * Holding Register Interrupt should occur. - * - * 'controlFlag' can take either of the following two values: - * - UART_THR_INT_NORMAL - for THR Interrupt to be raised under normal - * conditions(guided by the TX FIFO Threshold value)\n - * - UART_THR_INT_FIFO_TSR_EMPTY - for THR Interrupt to be raised when both - * Transmitter FIFO and Transmitter Shift Register are empty\n - * - * \return None - */ - -void UARTTxEmptyIntControl(unsigned int baseAdd, - unsigned int controlFlag) -{ - /* Clearing the TXEMPTYCTLIT bit in SCR. */ - HWREG(baseAdd + UART_SCR) &= ~(UART_SCR_TX_EMPTY_CTL_IT); - - /* Programming the TXEMPTYCTLIT bit in SCR. */ - HWREG(baseAdd + UART_SCR) |= (controlFlag & UART_SCR_TX_EMPTY_CTL_IT); -} - - -/** - * \brief This API controls (enables/disables) a feature where a falling - * edge on the RX, CTSn or DSRs could send a wake-up interrupt to - * the CPU. - * - * \param baseAdd Memory address of the UART instance being used. - * \param wakeUpFlag This specifies whether or not a wake-up interrupt - * should be sent to the CPU when a falling edge occurs on - * RX, CTSn or DSRn lines. - * - * 'wakeUpFlag' can take one of the following values: - * - UART_RX_CTS_DSR_WAKEUP_DISABLE - to disable generation of a Wake-Up - * interrupt due to occurence of a falling edge on RX, CTSn or DSRn lines. - * - UART_RX_CTS_DSR_WAKEUP_ENABLE - to enable generation of a Wake-Up - * interrupt due to occurence of a falling edge on RX, CTSn, DSRn lines. - * - * \return None - */ - -void UARTRXCTSDSRWakeUpConfigure(unsigned int baseAdd, unsigned int wakeUpFlag) -{ - /* Clearing the RXCTSDSRWAKEUPENABLE bit in SCR. */ - HWREG(baseAdd + UART_SCR) &= ~(UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE); - - /* Programming the RXCTSDSRWAKEUPENABLE bit in SCR. */ - HWREG(baseAdd + UART_SCR) |= (wakeUpFlag & UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE); -} - -/** - * \brief This API determines whether a falling edge occured on RX, CTSn or - * DSRn lines. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return This returns one of the following values: - * - UART_RX_CTS_DSR_NO_FALL_EDGE - indicating that no falling edge - * occured on RX, CTSn and DSRn lines\n - * - UART_RX_CTS_DSR_FALL_EDGE - indicating that a falling edge - * occured on RX, CTSn and DSRn lines\n - */ - -unsigned int UARTRXCTSDSRTransitionStatusGet(unsigned int baseAdd) -{ - return(HWREG(baseAdd + UART_SSR) & UART_SSR_RX_CTS_DSR_WAKE_UP_STS); -} - -/** - * \brief This API controls the DMA Counter Reset options. - * - * \param baseAdd Memory address of the UART instance being used - * \param controlFlag This specifies the DMA Counter Reset options - * - * 'controlFlag' can take either of the following values: - * - UART_DMA_CNTR_NO_RESET_FIFO_RESET - indicating that the DMA counter - * shall not be reset if the corresponding FIFO is reset\n - * - UART_DMA_CNTR_RESET_FIFO_RESET - indicating that the DMA counter shall - * be reset if the corresponding FIFO is reset\n - * - * \return None - */ - -void UARTDMACounterResetControl(unsigned int baseAdd, unsigned int controlFlag) -{ - /* Clearing the DMACOUNTERRST bit in SSR. */ - HWREG(baseAdd + UART_SSR) &= ~(UART_SSR_DMA_COUNTER_RST); - - /* Programming the DMACOUNTERRST bit in SSR. */ - HWREG(baseAdd + UART_SSR) |= (controlFlag & UART_SSR_DMA_COUNTER_RST); -} - -/** - * \brief This API determines whether the Transmitter FIFO is full or not. - * - * \param baseAdd Memory address of the UART instance being used - * - * \return This returns either of the following values: - * - UART_TX_FIFO_NOT_FULL - indicating that the TX FIFO is not full\n - * - UART_TX_FIFO_FULL - indicating that the TX FIFO is full\n - */ - -unsigned int UARTTxFIFOFullStatusGet(unsigned int baseAdd) -{ - return (HWREG(baseAdd + UART_SSR) & UART_SSR_TX_FIFO_FULL); -} - -/** - * \brief This API determines the Parity mode being configured by the system - * in the UART Autobauding mode. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return This returns one of the following values: - * - UART_AUTOBAUD_NO_PARITY - indicating that no parity was - * identified\n - * - UART_AUTOBAUD_PARITY_SPACE - indicating that space parity has - * been configured\n - * - UART_AUTOBAUD_EVEN_PARITY - indicating that even parity has been - * configured\n - * - UART_AUTOBAUD_ODD_PARITY - indicating that odd parity has been - * configured\n - * - * \note UASR register used in this API can be accessed only when the UART - * is in Configuration Mode A or Configuration Mode B of operation. - */ - -unsigned int UARTAutobaudParityGet(unsigned int baseAdd) -{ - unsigned int lcrRegValue = 0; - unsigned int retVal = 0; - - /* Switching to Register Configuration Mode A. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_A); - - retVal = (HWREG(baseAdd + UART_UASR) & UART_UASR_PARITY_TYPE); - - /* Restoring the value of LCR to its original value. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return retVal; -} - -/** - * \brief This API determines the word length per frame(character length) - * being configured by the system in UART Autobauding mode. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return This returns one of the following two values: - * - UART_AUTOBAUD_CHAR_LENGTH_7 - indicating word length of 7 bits\n - * - UART_AUTOBAUD_CHAR_LENGTH_8 - indicating word length of 8 bits\n - * - * \note UASR register used in this API can be accessed only when the UART - * is in Configuration Mode A or Configuration Mode B of operation. - */ - -unsigned int UARTAutobaudWordLenGet(unsigned int baseAdd) -{ - unsigned int lcrRegValue = 0; - unsigned int retVal = 0; - - /* Switching to Register Configuration Mode A. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_A); - - retVal = (HWREG(baseAdd + UART_UASR) & UART_UASR_BIT_BY_CHAR); - - /* Restoring the value of LCR to its original value. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return retVal; -} - -/** - * \brief This API determines the baud rate being configured by the system - * in UART Autobauding mode. - * - * \param baseAdd Memory address of the UART instance being used. - * - * \return This returns one of the following values: - * - UART_AUTOBAUD_SPEED_115200 - for baud rate of 115200 bps\n - * - UART_AUTOBAUD_SPEED_57600 - for baud rate of 57600 bps\n - * - UART_AUTOBAUD_SPEED_38400 - for baud rate of 38400 bps\n - * - UART_AUTOBAUD_SPEED_28800 - for baud rate of 28800 bps\n - * - UART_AUTOBAUD_SPEED_19200 - for baud rate of 19200 bps\n - * - UART_AUTOBAUD_SPEED_14400 - for baud rate of 14400 bps\n - * - UART_AUTOBAUD_SPEED_9600 - for baud rate of 9600 bps\n - * - UART_AUTOBAUD_SPEED_4800 - for baud rate of 4800 bps\n - * - UART_AUTOBAUD_SPEED_2400 - for baud rate of 2400 bps\n - * - UART_AUTOBAUD_SPEED_1200 - for baud rate of 1200 bps\n - * - UART_AUTOBAUD_NO_SPEED_IDEN - for no speed identified\n - * - * \note UASR register used in this API can be accessed only when the UART - * is in Configuration Mode A or Configuration Mode B of operation. - */ - -unsigned int UARTAutobaudSpeedGet(unsigned int baseAdd) -{ - unsigned int lcrRegValue = 0; - unsigned int retVal = 0; - - /* Switching to Register Configuration Mode A. */ - lcrRegValue = UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_A); - - retVal = (HWREG(baseAdd + UART_UASR) & UART_UASR_SPEED); - - /* Restoring the value of LCR to its original value. */ - HWREG(baseAdd + UART_LCR) = lcrRegValue; - - return retVal; -} - -/** - * \brief This API programs the Scratchpad Register with the specified - * value. - * - * \param baseAdd Memory address of the UART instance being used - * \param scratchValue This is the scratch value(temporary data) to be loaded - * to the Scratchpad Register - * - * \return None - */ - -void UARTScratchPadRegWrite(unsigned int baseAdd, unsigned int scratchValue) -{ - HWREG(baseAdd + UART_SPR) &= ~(UART_SPR_SPR_WORD); - /* Programming the SPR_WORD field of SPR. */ - HWREG(baseAdd + UART_SPR) |= (scratchValue & UART_SPR_SPR_WORD); -} - -/** - * \brief This API reads the value in Scratchpad Register. - * - * \param baseAdd Memory address of the UART instance being used - * - * \return The value in Scratchpad Register - */ - -unsigned int UARTScratchPadRegRead(unsigned int baseAdd) -{ - return (HWREG(baseAdd + UART_SPR) & UART_SPR_SPR_WORD); -} - -/** - * \brief This API reads the Revision Number of the module from the Module - * Version Register(MVR). - * - * \param baseAdd Memory address of the UART instance being used - * - * \return This returns the Major Revision Number(MVR[7:4] and Minor Revision - * Number(MVR[3:0])) of the module. - */ - -unsigned int UARTModuleVersionNumberGet(unsigned int baseAdd) -{ - return (HWREG(baseAdd + UART_MVR) & 0x00FF); -} - -/********************************* End of File ******************************/ diff --git a/lib/tiam1808/drivers/usbphyGS70.c b/lib/tiam1808/drivers/usbphyGS70.c deleted file mode 100644 index 719cb0b26..000000000 --- a/lib/tiam1808/drivers/usbphyGS70.c +++ /dev/null @@ -1,93 +0,0 @@ -/** - * \file UsbphyGS70.c - * - * \brief This file contains AM335x USB Phy related functions. - * -*/ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#include "hw_types.h" -#include "hw_usbphyGS70.h" -#include "hw_usb.h" -#if defined(am335x) -#include "soc_AM335x.h" -#elif defined(c6a811x) -#include "soc_C6A811x.h" -#endif - -/** - * \brief This function will switch on the USB Phy - * - * - * \param None - * - * \return None - * - **/ -void UsbPhyOn() -{ - unsigned int usbphycfg = 0; - - usbphycfg = HWREG(CFGCHIP2_USBPHYCTRL); - usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN); - usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN); - -#ifdef USB_MODE_HS_DISABLE - HWREGB(USB0_BASE + USB_O_POWER) &= 0xdf; -#endif /* USB_MODE_HS_DISABLE */ - - HWREG(CFGCHIP2_USBPHYCTRL) = usbphycfg; -} - - -/** - * \brief This function will switch off the USB Phy - * - * - * \param None - * - * \return None - * - **/ -void UsbPhyOff() -{ - unsigned int usbphycfg = 0; - - usbphycfg = HWREG(CFGCHIP2_USBPHYCTRL); - usbphycfg |= (USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN); - HWREG(CFGCHIP2_USBPHYCTRL) = usbphycfg; -} - diff --git a/lib/tiam1808/drivers/vpif.c b/lib/tiam1808/drivers/vpif.c deleted file mode 100644 index 06cf63586..000000000 --- a/lib/tiam1808/drivers/vpif.c +++ /dev/null @@ -1,1736 +0,0 @@ -/** - * \file vpif.c - * - * \brief This file contains the device abstraction layer APIs for VPIF. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -/* HW Macros and Peripheral Defines */ -#include "hw_types.h" -#include "hw_vpif.h" -#include "soc_OMAPL138.h" - -/* Driver APIs */ -#include "vpif.h" - - -/******************************************************************************* -* INTERNAL API DEFINITIONS -*******************************************************************************/ -/** -* \brief This function enables a specific channel interrupt or error interrupt. -* To activate an interrupt after it is enabled, use the VPIFInterruptEnableSet -* API. -* -* \param baseAddr is the Memory address of VPIF. -* \param intr is the interrupt to be enabled. -* -* \return none. -**/ -void VPIFInterruptEnable(unsigned int baseAddr, unsigned int intr) -{ - HWREG(baseAddr + INTEN) |= intr; -} -/** -* \brief This function disables a specific channel interrupt or error interrupt. -* -* \param baseAddr is the Memory address of VPIF. -* \param intr is the interrupt to be disabled. -* -* \return none. -**/ -void VPIFInterruptDisable(unsigned int baseAddr, unsigned int intr) -{ - HWREG(baseAddr + INTEN) &= ~intr; -} - -/** -* \brief This function activates a specific channel interrupt or error interrupt. -* This is only effective after the VPIFInterruptEnable API is invoked for -* the same interrupt event. -* -* \param baseAddr is the Memory address of VPIF. -* \param intr is the interrupt to be activated. -* -* \return none. -**/ -void VPIFInterruptEnableSet(unsigned int baseAddr, unsigned int intr) -{ - HWREG(baseAddr + INTSET) |= intr; -} -/** -* \brief This function deactivates/masks a specific channel interrupt or error interrupt. -* This is only effective after the VPIFInterruptEnable API is invoked for -* the same interrupt event. -* -* \param baseAddr is the Memory address of VPIF. -* \param intr is the interrupt to be deactivated/masked. -* -* \return none. -**/ -void VPIFInterruptEnableClear(unsigned int baseAddr, unsigned int intr) -{ - HWREG(baseAddr + INTCLR) |= intr; -} - -/** -* \brief This function clears the interrupt status of a given interrupt inside VPIF. -* The interrupt status at the CPU is not clearred. -* -* \param baseAddr is the Memory address of VPIF. -* \param intr is the interrupt of interest. -* -* \return none. -**/ -void VPIFInterruptStatusClear(unsigned int baseAddr, unsigned int intr) -{ - HWREG(baseAddr + INTSTATCLR) |= intr; -} - -/** -* \brief This function returns whether the interrupt of interest has happened or not. -* -* \param baseAddr is the Memory address of VPIF. -* \param intr is the interrupt of interest. -* -* \return Requested interrupt status. -**/ -unsigned int VPIFInterruptStatus(unsigned int baseAddr, unsigned int intr) -{ - return HWREG(baseAddr + INTSTAT) & intr; -} - -/** -* \brief This function clears the error status of a given error. -* -* \param baseAddr is the Memory address of VPIF. -* \param err is the err of interest. -* -* \return none. -**/ -void VPIFErrorStatusClear(unsigned int baseAddr, unsigned int err) -{ - HWREG(baseAddr + ERRSTAT) |= err; -} - -/** -* \brief This function returns whether the error of interest has happened or not. -* -* \param baseAddr is the Memory address of VPIF. -* \param err is the error of interest. -* -* \return Requested error status. -**/ -unsigned int VPIFErrorStatus(unsigned int baseAddr, unsigned int err) -{ - return HWREG(baseAddr + ERRSTAT) & err; -} - -/** -* \brief This function configures the VPIF DMA transfer size. -* -* \param baseAddr is the Memory address of VPIF. -* \param size is the transfer size. -* -* \return none. -**/ -void VPIFDMARequestSizeConfig(unsigned int baseAddr, unsigned int size) -{ - HWREG(baseAddr + REQSIZE) = size; -} -/** -* \brief This function configures the mode of opeartion during emulation halt. -* -* \param baseAddr is the Memory address of VPIF. -* \param mode is the mode of operation. -* -* \return none. -**/ -void VPIFEmulationControlSet(unsigned int baseAddr, unsigned int mode) -{ - HWREG(baseAddr + EMUCTRL) = mode; -} - -//C0CTRL & C1CTRL -/** -* \brief This function selects the edge of the pixel clock that data is captured on. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* \param mode is the edge of the pixel clock to be selected. -* -* \return none. -**/ -void VPIFCaptureClkedgeModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode) -{ - unsigned int temp; - if(channel==VPIF_CHANNEL_0) - { - temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_CLKEDGE; - HWREG(baseAddr + C0CTRL) = temp | mode; - } - else if(channel==VPIF_CHANNEL_1) - { - temp = HWREG(baseAddr + C1CTRL) & ~VPIF_C1CTRL_CLKEDGE; - HWREG(baseAddr + C1CTRL) = temp | mode; - } -} -/** -* \brief This function configures bit per pixel during raw capture mode. -* -* \param baseAddr is the Memory address of VPIF. -* \param width is the number of bits per pixel. -* -* \return none. -**/ -void VPIFCaptureRawDatawidthConfig(unsigned int baseAddr, unsigned int width) -{ - unsigned int temp; - temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_DATAWIDTH; - HWREG(baseAddr + C0CTRL) = temp | width; -} -/** -* \brief This function configures how often interrupts are generated during raw -* capture mode. An interrupt is generated every 'interval' number of lines. -* -* \param baseAddr is the Memory address of VPIF. -* \param interval is the number of lines. -* -* \return none. -**/ -void VPIFCaptureRawIntlineConfig(unsigned int baseAddr, unsigned int interval) -{ - unsigned int temp; - /* The number of lines should be smaller than the max supported lines in a frame */ - if(interval <= (VPIF_C0CTRL_INTLINE >> VPIF_C0CTRL_INTLINE_SHIFT)) - { - temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_INTLINE; - HWREG(baseAddr + C0CTRL) = temp | (interval << VPIF_C0CTRL_INTLINE_SHIFT); - } -} -/** -* \brief This function sets whether the polarity of the field id signal is inverted -* during raw capture mode. -* -* \param baseAddr is the Memory address of VPIF. -* \param mode is the polarity mode (inverted or non-inverted). -* -* \return none. -**/ -void VPIFCaptureRawFidinvSet(unsigned int baseAddr, unsigned int mode) -{ - unsigned int temp; - temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_FIDINV; - HWREG(baseAddr + C0CTRL) = temp | mode; -} -/** -* \brief This function sets whether the polarity of the vertical valid signal is -* inverted during raw capture mode. -* -* \param baseAddr is the Memory address of VPIF. -* \param mode is the polarity mode (inverted or non-inverted). -* -* \return none. -**/ -void VPIFCaptureRawVvinvSet(unsigned int baseAddr, unsigned int mode) -{ - unsigned int temp; - temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_VVINV; - HWREG(baseAddr + C0CTRL) = temp | mode; -} -/** -* \brief This function sets whether the polarity of the horizontal valid signal is -* inverted during raw capture mode. -* -* \param baseAddr is the Memory address of VPIF. -* \param mode is the polarity mode (inverted or non-inverted). -* -* \return none. -**/ -void VPIFCaptureRawHvinvSet(unsigned int baseAddr, unsigned int mode) -{ - unsigned int temp; - temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_HVINV; - HWREG(baseAddr + C0CTRL) = temp | mode; -} -/** -* \brief This function configures the storage mode of the incoming data. -* -* \param baseAddr is the Memory address of VPIF. -* \param mode is the storage mode (field-based or frame-based). -* -* \return none. -**/ -void VPIFCaptureFieldframeModeSelect(unsigned int baseAddr, unsigned int mode) -{ - /* Both capture channels are set together */ - unsigned int temp; - temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_FIELDFRAME; - HWREG(baseAddr + C0CTRL) = temp | mode; -} -/** -* \brief This function sets the display format of the incoming video. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* \param mode is the display format (interlaced or progressive). -* -* \return none. -**/ -void VPIFCaptureIntrprogModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode) -{ - unsigned int temp; - if(channel==VPIF_CHANNEL_0) - { - temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_INTRPROG; - HWREG(baseAddr + C0CTRL) = temp | mode; - } - else if(channel==VPIF_CHANNEL_1) - { - temp = HWREG(baseAddr + C1CTRL) & ~VPIF_C1CTRL_INTRPROG; - HWREG(baseAddr + C1CTRL) = temp | mode; - } -} -/** -* \brief This function enables vertical blanking capture. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* -* \return none. -**/ -void VPIFCaptureVancEnable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_0) - { - HWREG(baseAddr + C0CTRL) |= VPIF_C0CTRL_VANC; - } - else if(channel==VPIF_CHANNEL_1) - { - HWREG(baseAddr + C1CTRL) |= VPIF_C1CTRL_VANC; - } -} -/** -* \brief This function disbles vertical blanking capture. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* -* \return none. -**/ -void VPIFCaptureVancDisable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_0) - { - HWREG(baseAddr + C0CTRL) &= ~VPIF_C0CTRL_VANC; - } - else if(channel==VPIF_CHANNEL_1) - { - HWREG(baseAddr + C1CTRL) &= ~VPIF_C1CTRL_VANC; - } -} -/** -* \brief This function enables horizontal blanking capture. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* -* \return none. -**/ -void VPIFCaptureHancEnable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_0) - { - HWREG(baseAddr + C0CTRL) |= VPIF_C0CTRL_HANC; - } - else if(channel==VPIF_CHANNEL_1) - { - HWREG(baseAddr + C1CTRL) |= VPIF_C1CTRL_HANC; - } -} -/** -* \brief This function disables horizontal blanking capture. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* -* \return none. -**/ - -void VPIFCaptureHancDisable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_0) - { - HWREG(baseAddr + C0CTRL) &= ~VPIF_C0CTRL_HANC; - } - else if(channel==VPIF_CHANNEL_1) - { - HWREG(baseAddr + C1CTRL) &= ~VPIF_C1CTRL_HANC; - } -} -/** -* \brief This function configures how interrupts are generated during BT -* video capture. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* \param mode is the interrupt geneation mode (top field, bottom field, -* or both). -* -* \return none. -**/ -void VPIFCaptureIntframeConfig(unsigned int baseAddr, unsigned int channel, unsigned int mode) -{ - unsigned int temp; - if(channel==VPIF_CHANNEL_0) - { - temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_INTFRAME; - HWREG(baseAddr + C0CTRL) = temp | mode; - } - else if(channel==VPIF_CHANNEL_1) - { - temp = HWREG(baseAddr + C1CTRL) & ~VPIF_C1CTRL_INTFRAME; - HWREG(baseAddr + C1CTRL) = temp | mode; - } -} -/** -* \brief This function returns the field id of the field being captured. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* -* \return Current field id. -**/ -unsigned int VPIFCaptureFidModeRead(unsigned int baseAddr, unsigned int channel) -{ - unsigned int temp = 0; - if(channel==VPIF_CHANNEL_0) - { - temp = HWREG(baseAddr + C0CTRL) & VPIF_C0CTRL_FID; - } - else if(channel==VPIF_CHANNEL_1) - { - temp = HWREG(baseAddr + C1CTRL) & VPIF_C1CTRL_FID; - } - return temp; -} -/** -* \brief This function configures the input data format. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* \param mode is the data format (y/c muxed or non-muxed). -* -* \return none. -**/ -void VPIFCaptureYcmuxModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode) -{ - unsigned int temp; - if(channel==VPIF_CHANNEL_0) - { - temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_YCMUX; - HWREG(baseAddr + C0CTRL) = temp | mode; - } - else if(channel==VPIF_CHANNEL_1) - { - temp = HWREG(baseAddr + C1CTRL) & ~VPIF_C1CTRL_YCMUX; - HWREG(baseAddr + C1CTRL) = temp | mode; - } -} -/** -* \brief This function configures the capture mode. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* \param mode is the capture mode (raw or BT). -* -* \return none. -**/ -void VPIFCaptureCapmodeModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode) -{ - unsigned int temp; - if(channel==VPIF_CHANNEL_0) - { - temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_CAPMODE; - HWREG(baseAddr + C0CTRL) = temp | mode; - } - else if(channel==VPIF_CHANNEL_1) - { - temp = HWREG(baseAddr + C1CTRL) & ~VPIF_C1CTRL_CAPMODE; - HWREG(baseAddr + C1CTRL) = temp | mode; - } - -} -/** -* \brief This function enables capture. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* -* \return none. -**/ -void VPIFCaptureChanenEnable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_0) - { - HWREG(baseAddr + C0CTRL) |= VPIF_C0CTRL_CHANEN; - } - else if(channel==VPIF_CHANNEL_1) - { - HWREG(baseAddr + C1CTRL) |= VPIF_C1CTRL_CHANEN; - } -} -/** -* \brief This function disables capture. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* -* \return none. -**/ - -void VPIFCaptureChanenDisable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_0) - { - HWREG(baseAddr + C0CTRL) &= ~VPIF_C0CTRL_CHANEN; - } - else if(channel==VPIF_CHANNEL_1) - { - HWREG(baseAddr + C1CTRL) &= ~VPIF_C1CTRL_CHANEN; - } -} -/** -* \brief This function configures the buffer for the captured blanking data. -* The buffer address (and offset when applicable) is passed to VPIF. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* \param field is the field that the blanking data is for (top/bottom). -* \param hv is the location of the blanking data (during horizontal/vertical period). -* \param addr is the address of the VBI buffer in the memory. -* \param offset is the line offset of the buffer in the memory if it is for horizontal blanking. -* -* \return none. -**/ - -void VPIFCaptureVBIFBConfig(unsigned int baseAddr, unsigned int channel, unsigned field, unsigned hv, unsigned int addr, unsigned int offset) -{ - if(channel==VPIF_CHANNEL_0) - { - if(field==VPIF_TOP_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - HWREG(baseAddr + C0THANC) = addr; - HWREG(baseAddr + C0HANCOFFSET) = offset; - - } - if(hv==VPIF_VERTICAL) - { - HWREG(baseAddr + C0TVANC) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - HWREG(baseAddr + C0BHANC) = addr; - HWREG(baseAddr + C0HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - HWREG(baseAddr + C0BVANC) = addr; - } - } - } - if(channel==VPIF_CHANNEL_1) - { - if(field==VPIF_TOP_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - HWREG(baseAddr + C1THANC) = addr; - HWREG(baseAddr + C1HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - HWREG(baseAddr + C1TVANC) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - HWREG(baseAddr + C1BHANC) = addr; - HWREG(baseAddr + C1HANCOFFSET) = offset; - - } - if(hv==VPIF_VERTICAL) - { - HWREG(baseAddr + C1BVANC) = addr; - } - } - } -} - -/** -* \brief This function exchanges the buffer for the captured blanking data. -* A new buffer address (and offset when applicable) is passed in, and -* the old buffer address is read back. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* \param field is the field that the blanking data is for (top/bottom). -* \param hv is the location of the blanking data (during horizontal/vertical period). -* \param addr is the address of the VBI buffer in the memory. -* \param offset is the line offset of the buffer in the memory if it is for horizontal blanking. -* -* \return Previous VBI buffer address. -**/ - -unsigned int VPIFCaptureVBIFBExchange(unsigned int baseAddr, unsigned int channel, unsigned field, unsigned hv, unsigned int addr, unsigned int offset) -{ - unsigned int temp = 0; - if(channel==VPIF_CHANNEL_0) - { - if(field==VPIF_TOP_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - temp = HWREG(baseAddr + C0THANC); - HWREG(baseAddr + C0THANC) = addr; - HWREG(baseAddr + C0HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - temp = HWREG(baseAddr + C0TVANC); - HWREG(baseAddr + C0TVANC) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - temp = HWREG(baseAddr + C0BHANC); - HWREG(baseAddr + C0BHANC) = addr; - HWREG(baseAddr + C0HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - temp = HWREG(baseAddr + C0BVANC); - HWREG(baseAddr + C0BVANC) = addr; - } - } - } - if(channel==VPIF_CHANNEL_1) - { - if(field==VPIF_TOP_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - temp = HWREG(baseAddr + C1THANC); - HWREG(baseAddr + C1THANC) = addr; - HWREG(baseAddr + C1HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - temp = HWREG(baseAddr + C1TVANC); - HWREG(baseAddr + C1TVANC) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - temp = HWREG(baseAddr + C1BHANC); - HWREG(baseAddr + C1BHANC) = addr; - HWREG(baseAddr + C1HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - temp = HWREG(baseAddr + C1BVANC); - HWREG(baseAddr + C1BVANC) = addr; - } - } - } - return temp; -} -/** -* \brief This function configures the dimension of the video to be captured -* (both active portion and blanking portion). The application doesn't -* need to specify dimension information, except when non-standard BT -* video is to be captured. -* -* \param baseAddr is the Memory address of VPIF. -* \param mode is the video standard (i.e., 480I, raw, non-standard). -* \param sdChannel is the capture channel (channel 1 or channel 0). -* \param rawWidth is the bit-per-pixel of the raw video to be captured. -* \param *buf is the dimension information of the non-standard video to be captured. -* It is of type vbufParam (structure). -* -* \return none. -**/ - -void VPIFCaptureModeConfig(unsigned int baseAddr, unsigned int mode, unsigned int sdChannel, unsigned int rawWidth, VPIFVbufParam* buf) -{ /* - typedef struct vbufParam - { - unsigned int sav2eav; - unsigned int eav2sav; - unsigned int vsize; - unsigned int l1; - unsigned int l3; - unsigned int l5; - unsigned int l7; - unsigned int l9; - unsigned int l11; - } VPIFVbufParam; - */ - if(mode==VPIF_480I) - { - if(sdChannel==VPIF_CHANNEL_0) - { - HWREG(baseAddr + C0HCFG) = (268 << VPIF_C0HCFG_EAV2SAV_SHIFT) | (1440 << VPIF_C0HCFG_SAV2EAV_SHIFT); - HWREG(baseAddr + C0VCFG0) = (4 << VPIF_C0VCFG0_L1_SHIFT) | (20 << VPIF_C0VCFG0_L3_SHIFT); - HWREG(baseAddr + C0VCFG1) = (264 << VPIF_C0VCFG1_L5_SHIFT) | (266 << VPIF_C0VCFG1_L7_SHIFT); - HWREG(baseAddr + C0VCFG2) = (283 << VPIF_C0VCFG2_L9_SHIFT) | (1 << VPIF_C0VCFG2_L11_SHIFT); - HWREG(baseAddr + C0VSIZE) = 525 << VPIF_C0VSIZE_VSIZE_SHIFT; - } - if(sdChannel==VPIF_CHANNEL_1) - { - HWREG(baseAddr + C1HCFG) = (268 << VPIF_C1HCFG_EAV2SAV_SHIFT) | (1440 << VPIF_C1HCFG_SAV2EAV_SHIFT); - HWREG(baseAddr + C1VCFG0) = (4 << VPIF_C1VCFG0_L1_SHIFT) | (20 << VPIF_C1VCFG0_L3_SHIFT); - HWREG(baseAddr + C1VCFG1) = (264 << VPIF_C1VCFG1_L5_SHIFT) | (266 << VPIF_C1VCFG1_L7_SHIFT); - HWREG(baseAddr + C1VCFG2) = (283 << VPIF_C1VCFG2_L9_SHIFT) | (1 << VPIF_C1VCFG2_L11_SHIFT); - HWREG(baseAddr + C1VSIZE) = 525 << VPIF_C1VSIZE_VSIZE_SHIFT; - } - } - if(mode==VPIF_CAPTURE_RAW) - { - /* TBD */ - } - if(mode==VPIF_NONSTANDARD) - { - /* TBD */ - if(sdChannel==VPIF_CHANNEL_0) { - } - if(sdChannel==VPIF_CHANNEL_1) { - } - } - - /* TBD */ -} - -/** -* \brief This function configures the frame buffer of the captured video. -* The buffer address (and offset when applicable) is passed to VPIF. - -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* \param field is the field that the video is for (top/bottom). -* \param yc is the data component (luma/chroma). -* \param addr is the address of the frame buffer in the memory. -* \param offset is the line offset of the frame buffer in the memory. -* -* \return none. -**/ - -void VPIFCaptureFBConfig(unsigned int baseAddr, unsigned int channel, unsigned int field, unsigned yc, unsigned int addr, unsigned int offset) -{ - if(channel==VPIF_CHANNEL_0) - { - if(field==VPIF_TOP_FIELD) - { - if(yc==VPIF_LUMA) - { - HWREG(baseAddr + C0TLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - HWREG(baseAddr + C0TCHROMA) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(yc==VPIF_LUMA) - { - HWREG(baseAddr + C0BLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - HWREG(baseAddr + C0BCHROMA) = addr; - } - } - HWREG(baseAddr + C0IMGOFFSET) = offset; - } - if(channel==VPIF_CHANNEL_1) - { - if(field==VPIF_TOP_FIELD) - { - if(yc==VPIF_LUMA) - { - HWREG(baseAddr + C1TLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - HWREG(baseAddr + C1TCHROMA) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(yc==VPIF_LUMA) - { - HWREG(baseAddr + C1BLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - HWREG(baseAddr + C1BCHROMA) = addr; - } - } - HWREG(baseAddr + C1IMGOFFSET) = offset; - } -} -/** -* \brief This function exchanges the frame buffer of the captured video. -* A new buffer address (and offset when applicable) is passed to VPIF, -* and the address of the previous buffer is read back. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* \param field is the field that the video is for (top/bottom). -* \param yc is the data component (luma/chroma). -* \param addr is the address of the frame buffer in the memory. -* \param offset is the line offset of the frame buffer in the memory. -* -* \return Previuos buffer address. -**/ -unsigned int VPIFCaptureFBExchange(unsigned int baseAddr, unsigned int channel, unsigned int field, unsigned yc, unsigned int addr, unsigned int offset) -{ - unsigned int temp = 0; - if(channel==VPIF_CHANNEL_0) - { - if(field==VPIF_TOP_FIELD) - { - if(yc==VPIF_LUMA) - { - temp = HWREG(baseAddr + C0TLUMA); - HWREG(baseAddr + C0TLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - temp = HWREG(baseAddr + C0TCHROMA); - HWREG(baseAddr + C0TCHROMA) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(yc==VPIF_LUMA) - { - temp = HWREG(baseAddr + C0BLUMA); - HWREG(baseAddr + C0BLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - temp = HWREG(baseAddr + C0BCHROMA); - HWREG(baseAddr + C0BCHROMA) = addr; - } - } - HWREG(baseAddr + C0IMGOFFSET) = offset; - } - if(channel==VPIF_CHANNEL_1) - { - if(field==VPIF_TOP_FIELD) - { - if(yc==VPIF_LUMA) - { - temp = HWREG(baseAddr + C1TLUMA); - HWREG(baseAddr + C1TLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - temp = HWREG(baseAddr + C1TCHROMA); - HWREG(baseAddr + C1TCHROMA) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(yc==VPIF_LUMA) - { - temp = HWREG(baseAddr + C1BLUMA); - HWREG(baseAddr + C1BLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - temp = HWREG(baseAddr + C1BCHROMA); - HWREG(baseAddr + C1BCHROMA) = addr; - } - } - HWREG(baseAddr + C1IMGOFFSET) = offset; - } - return temp; -} - -//C2CTRL & C3CTRL -/** -* \brief This function selects the edge of the pixel clock that data is displayed on. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* \param mode is the edge of the pixel clock to be selected. -* -* \return none. -**/ -void VPIFDisplayClkedgeModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode) -{ - unsigned int temp; - if(channel==VPIF_CHANNEL_2) - { - temp = HWREG(baseAddr + C2CTRL) & ~VPIF_C2CTRL_CLKEDGE; - HWREG(baseAddr + C2CTRL) = temp | mode; - } - else if(channel==VPIF_CHANNEL_3) - { - temp = HWREG(baseAddr + C3CTRL) & ~VPIF_C3CTRL_CLKEDGE; - HWREG(baseAddr + C3CTRL) = temp | mode; - } -} -/** -* \brief This function enables the clipping on blanking data output. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayClipancEnable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) |= VPIF_C2CTRL_CLIPANC; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) |= VPIF_C3CTRL_CLIPANC; - } -} -/** -* \brief This function disables the clipping on blanking data output. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayClipancDisable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) &= ~VPIF_C2CTRL_CLIPVID; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) &= ~VPIF_C3CTRL_CLIPVID; - } -} -/** -* \brief This function enables the clipping on active video data output. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayClipvidEnable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) |= VPIF_C2CTRL_CLIPVID; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) |= VPIF_C3CTRL_CLIPVID; - } -} -/** -* \brief This function disables the clipping on active video data output. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayClipvidDisable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) &= ~VPIF_C2CTRL_CLIPVID; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) &= ~VPIF_C3CTRL_CLIPVID; - } -} -/** -* \brief This function configures the storage mode of the outgoing data. -* -* \param baseAddr is the Memory address of VPIF. -* \param mode is the storage mode (field-based or frame-based). -* -* \return none. -**/ -void VPIFDisplayFieldframeModeSelect(unsigned int baseAddr, unsigned int mode) -{ - /* Both display channels are set together */ - unsigned int temp; - temp = HWREG(baseAddr + C2CTRL) & ~VPIF_C2CTRL_FIELDFRAME; - HWREG(baseAddr + C2CTRL) = temp | mode; -} -/** -* \brief This function sets the display format of the outgoing video. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* \param mode is the display format (interlaced or progressive). -* -* \return none. -**/ -void VPIFDisplayIntrprogModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode) -{ - unsigned int temp; - if(channel==VPIF_CHANNEL_2) - { - temp = HWREG(baseAddr + C2CTRL) & ~VPIF_C2CTRL_INTRPROG; - HWREG(baseAddr + C2CTRL) = temp | mode; - } - else if(channel==VPIF_CHANNEL_3) - { - temp = HWREG(baseAddr + C3CTRL) & ~VPIF_C3CTRL_INTRPROG; - HWREG(baseAddr + C3CTRL) = temp | mode; - } -} -/** -* \brief This function enables the display of video pixels from memory. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayPixelEnable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) |= VPIF_C2CTRL_PIXEL; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) |= VPIF_C3CTRL_PIXEL; - } -} -/** -* \brief This function disables the display of video pixels from memory. -* Blank pixels (Y=0x10, C=0x80) are displayed instead. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayPixelDisable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) &= ~VPIF_C2CTRL_PIXEL; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) &= ~VPIF_C3CTRL_PIXEL; - } -} -/** -* \brief This function enables vertical blanking display. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayVancEnable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) |= VPIF_C2CTRL_VANC; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) |= VPIF_C3CTRL_VANC; - } -} -/** -* \brief This function disables vertical blanking display. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayVancDisable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) &= ~VPIF_C2CTRL_VANC; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) &= ~VPIF_C3CTRL_VANC; - } -} -/** -* \brief This function enables horizontal blanking display. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayHancEnable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) |= VPIF_C2CTRL_HANC; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) |= VPIF_C3CTRL_HANC; - } -} -/** -* \brief This function disables horizontal blanking display. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayHancDisable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) &= ~VPIF_C2CTRL_HANC; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) &= ~VPIF_C3CTRL_HANC; - } -} -/** -* \brief This function configures how interrupts are generated during BT -* video display. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* \param mode is the interrupt geneation mode (top field, bottom field, -* or both). -* -* \return none. -**/ -void VPIFDisplayIntframeConfig(unsigned int baseAddr, unsigned int channel, unsigned int mode) -{ - unsigned int temp; - if(channel==VPIF_CHANNEL_2) - { - temp = HWREG(baseAddr + C2CTRL) & ~VPIF_C2CTRL_INTFRAME; - HWREG(baseAddr + C2CTRL) = temp | mode; - } - else if(channel==VPIF_CHANNEL_3) - { - temp = HWREG(baseAddr + C3CTRL) & ~VPIF_C3CTRL_INTFRAME; - HWREG(baseAddr + C3CTRL) = temp | mode; - } -} -/** -* \brief This function returns the field id of the field being displayed. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return Current field id. -**/ -unsigned int VPIFDisplayFidModeRead(unsigned int baseAddr, unsigned int channel) -{ - unsigned int temp = 0; - if(channel==VPIF_CHANNEL_2) - { - temp = HWREG(baseAddr + C2CTRL) & VPIF_C2CTRL_FID; - } - else if(channel==VPIF_CHANNEL_3) - { - temp = HWREG(baseAddr + C3CTRL) & VPIF_C3CTRL_FID; - } - return temp; -} -/** -* \brief This function configures the output data format. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* \param mode is the data format (y/c muxed or non-muxed). -* -* \return none. -**/ -void VPIFDisplayYcmuxModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode) -{ - unsigned int temp; - if(channel==VPIF_CHANNEL_2) - { - temp = HWREG(baseAddr + C2CTRL) & ~VPIF_C2CTRL_YCMUX; - HWREG(baseAddr + C2CTRL) = temp | mode; - } - else if(channel==VPIF_CHANNEL_3) - { - temp = HWREG(baseAddr + C3CTRL) & ~VPIF_C3CTRL_YCMUX; - HWREG(baseAddr + C3CTRL) = temp | mode; - } -} -/** -* \brief This function enables display pixel clock output. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayClkenEnable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) |= VPIF_C2CTRL_CLKEN; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) |= VPIF_C3CTRL_CLKEN; - } -} -/** -* \brief This function disables display pixel clock output. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayClkenDisable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) &= ~VPIF_C2CTRL_CLKEN; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) &= ~VPIF_C3CTRL_CLKEN; - } -} -/** -* \brief This function enables display channel. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayChanenEnable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) |= VPIF_C2CTRL_CHANEN; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) |= VPIF_C3CTRL_CHANEN; - } -} -/** -* \brief This function disables display channel. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* -* \return none. -**/ -void VPIFDisplayChanenDisable(unsigned int baseAddr, unsigned int channel) -{ - if(channel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2CTRL) &= ~VPIF_C2CTRL_CHANEN; - } - else if(channel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3CTRL) &= ~VPIF_C3CTRL_CHANEN; - } -} -/** -* \brief This function configures the buffer for the displayed blanking data. -* The buffer address (and offset when applicable) is passed to VPIF. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* \param field is the field that the blanking data is for (top/bottom). -* \param hv is the location of the blanking data (during horizontal/vertical period). -* \param addr is the address of the VBI buffer in the memory. -* \param offset is the line offset of the buffer in the memory if it is for horizontal blanking. -* -* \return none. -**/ -void VPIFDisplayVBIFBConfig(unsigned int baseAddr, unsigned int channel, unsigned field, unsigned hv, unsigned int addr, unsigned int offset) -{ - if(channel==VPIF_CHANNEL_2) - { - if(field==VPIF_TOP_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - HWREG(baseAddr + C2THANC) = addr; - HWREG(baseAddr + C2HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - HWREG(baseAddr + C2TVANC) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - HWREG(baseAddr + C2BHANC) = addr; - HWREG(baseAddr + C2HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - HWREG(baseAddr + C2BVANC) = addr; - } - } - } - if(channel==VPIF_CHANNEL_3) - { - if(field==VPIF_TOP_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - HWREG(baseAddr + C3THANC) = addr; - HWREG(baseAddr + C3HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - HWREG(baseAddr + C3TVANC) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - HWREG(baseAddr + C3BHANC) = addr; - HWREG(baseAddr + C3HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - HWREG(baseAddr + C3BVANC) = addr; - } - } - } -} -/** -* \brief This function exchanges the buffer for the displayed blanking data. -* A new buffer address (and offset when applicable) is passed in, and -* the old buffer address is read back. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the capture channel (channel 1 or channel 0). -* \param field is the field that the blanking data is for (top/bottom). -* \param hv is the location of the blanking data (during horizontal/vertical period). -* \param addr is the address of the VBI buffer in the memory. -* \param offset is the line offset of the buffer in the memory if it is for horizontal blanking. -* -* \return Previous VBI buffer address. -**/ -unsigned int VPIFDisplayVBIFBExchange(unsigned int baseAddr, unsigned int channel, unsigned field, unsigned hv, unsigned int addr, unsigned int offset) -{ - unsigned int temp = 0; - if(channel==VPIF_CHANNEL_2) - { - if(field==VPIF_TOP_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - temp = HWREG(baseAddr + C2THANC); - HWREG(baseAddr + C2THANC) = addr; - HWREG(baseAddr + C2HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - temp = HWREG(baseAddr + C2TVANC); - HWREG(baseAddr + C2TVANC) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - temp = HWREG(baseAddr + C2BHANC); - HWREG(baseAddr + C2BHANC) = addr; - HWREG(baseAddr + C2HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - temp = HWREG(baseAddr + C2BVANC); - HWREG(baseAddr + C2BVANC) = addr; - } - } - } - if(channel==VPIF_CHANNEL_3) - { - if(field==VPIF_TOP_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - temp = HWREG(baseAddr + C3THANC); - HWREG(baseAddr + C3THANC) = addr; - HWREG(baseAddr + C3HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - temp = HWREG(baseAddr + C3TVANC); - HWREG(baseAddr + C3TVANC) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - temp = HWREG(baseAddr + C3BHANC); - HWREG(baseAddr + C3BHANC) = addr; - HWREG(baseAddr + C3HANCOFFSET) = offset; - } - if(hv==VPIF_VERTICAL) - { - temp = HWREG(baseAddr + C3BVANC); - HWREG(baseAddr + C3BVANC) = addr; - } - } - } - return temp; -} -/** -* \brief This function configures the dimension/location of the displayed blanking data. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* \param field is the field that the blanking data is for (top/bottom). -* \param hv is the location of the blanking data (during horizontal/vertical period). -* \param vpos is the vertical position of the blanking data in the frame. -* \param hpos is the horizontal position of the blanking data in the frame. -* \param vsize is the vertical size of the blanking data in the frame. -* \param hsize is the horizontal size of the blanking data in the frame. -* -* \return none. -**/ -void VPIFDisplayVBIFBSizeConfig(unsigned int baseAddr, unsigned int channel, unsigned field, unsigned hv, unsigned int vpos, unsigned int hpos, unsigned int vsize, unsigned int hsize) -{ - if(channel==VPIF_CHANNEL_2) - { - if(field==VPIF_TOP_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - HWREG(baseAddr + C2THANCPOS) = (vpos << VPIF_C2THANCPOS_VPOS_SHIFT) + (hpos << VPIF_C2THANCPOS_HPOS_SHIFT); - HWREG(baseAddr + C2THANCSIZE) = (vsize << VPIF_C2THANCSIZE_VSIZE_SHIFT) + (hsize << VPIF_C2THANCSIZE_HSIZE_SHIFT); - } - if(hv==VPIF_VERTICAL) - { - HWREG(baseAddr + C2TVANCPOS) = (vpos << VPIF_C2TVANCPOS_VPOS_SHIFT) + (hpos << VPIF_C2TVANCPOS_HPOS_SHIFT); - HWREG(baseAddr + C2TVANCSIZE) = (vsize << VPIF_C2TVANCSIZE_VSIZE_SHIFT) + (hsize << VPIF_C2TVANCSIZE_HSIZE_SHIFT); - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - HWREG(baseAddr + C2BHANCPOS) = (vpos << VPIF_C2BHANCPOS_VPOS_SHIFT) + (hpos << VPIF_C2BHANCPOS_HPOS_SHIFT); - HWREG(baseAddr + C2BHANCSIZE) = (vsize << VPIF_C2BHANCSIZE_VSIZE_SHIFT) + (hsize << VPIF_C2BHANCSIZE_HSIZE_SHIFT); - } - if(hv==VPIF_VERTICAL) - { - HWREG(baseAddr + C2BVANCPOS) = (vpos << VPIF_C2BVANCPOS_VPOS_SHIFT) + (hpos << VPIF_C2BVANCPOS_HPOS_SHIFT); - HWREG(baseAddr + C2BVANCSIZE) = (vsize << VPIF_C2BVANCSIZE_VSIZE_SHIFT) + (hsize << VPIF_C2BVANCSIZE_HSIZE_SHIFT); - } - } - } - if(channel==VPIF_CHANNEL_3) - { - if(field==VPIF_TOP_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - HWREG(baseAddr + C3THANCPOS) = (vpos << VPIF_C3THANCPOS_VPOS_SHIFT) + (hpos << VPIF_C3THANCPOS_HPOS_SHIFT); - HWREG(baseAddr + C3THANCSIZE) = (vsize << VPIF_C3THANCSIZE_VSIZE_SHIFT) + (hsize << VPIF_C3THANCSIZE_HSIZE_SHIFT); - } - if(hv==VPIF_VERTICAL) - { - HWREG(baseAddr + C3TVANCPOS) = (vpos << VPIF_C3TVANCPOS_VPOS_SHIFT) + (hpos << VPIF_C3TVANCPOS_HPOS_SHIFT); - HWREG(baseAddr + C3TVANCSIZE) = (vsize << VPIF_C3TVANCSIZE_VSIZE_SHIFT) + (hsize << VPIF_C3TVANCSIZE_HSIZE_SHIFT); - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(hv==VPIF_HORIZONTAL) - { - HWREG(baseAddr + C3BHANCPOS) = (vpos << VPIF_C3BHANCPOS_VPOS_SHIFT) + (hpos << VPIF_C3BHANCPOS_HPOS_SHIFT); - HWREG(baseAddr + C3BHANCSIZE) = (vsize << VPIF_C3BHANCSIZE_VSIZE_SHIFT) + (hsize << VPIF_C3BHANCSIZE_HSIZE_SHIFT); - } - if(hv==VPIF_VERTICAL) - { - HWREG(baseAddr + C3BVANCPOS) = (vpos << VPIF_C3BVANCPOS_VPOS_SHIFT) + (hpos << VPIF_C3BVANCPOS_HPOS_SHIFT); - HWREG(baseAddr + C3BVANCSIZE) = (vsize << VPIF_C3BVANCSIZE_VSIZE_SHIFT) + (hsize << VPIF_C3BVANCSIZE_HSIZE_SHIFT); - } - } - } -} -/** -* \brief This function configures the dimension of the video to be displayed -* (both active portion and blanking portion). The application doesn't -* need to specify dimension information, except when non-standard BT -* video is to be displayed. -* -* \param baseAddr is the Memory address of VPIF. -* \param mode is the video standard (i.e., 480I or non-standard). -* \param sdChannel is the display channel (channel 3 or channel 2). -* \param *buf is the dimension information of the non-standard video to be displayed. -* It is of type vbufParam (structure). -* -* \return none. -**/ -void VPIFDisplayModeConfig(unsigned int baseAddr, unsigned int mode, unsigned int sdChannel, VPIFVbufParam* buf) -{ /* - typedef struct vbufParam - { - unsigned int sav2eav; - unsigned int eav2sav; - unsigned int vsize; - unsigned int l1; - unsigned int l3; - unsigned int l5; - unsigned int l7; - unsigned int l9; - unsigned int l11; - } VPIFVbufParam; - */ - if(mode==VPIF_480I) - { - if(sdChannel==VPIF_CHANNEL_2) - { - HWREG(baseAddr + C2HCFG) = (268 << VPIF_C2HCFG_EAV2SAV_SHIFT) | (1440 << VPIF_C2HCFG_SAV2EAV_SHIFT); - HWREG(baseAddr + C2VCFG0) = (4 << VPIF_C2VCFG0_L1_SHIFT) | (20 << VPIF_C2VCFG0_L3_SHIFT); - HWREG(baseAddr + C2VCFG1) = (264 << VPIF_C2VCFG1_L5_SHIFT) | (266 << VPIF_C2VCFG1_L7_SHIFT); - HWREG(baseAddr + C2VCFG2) = (283 << VPIF_C2VCFG2_L9_SHIFT) | (1 << VPIF_C2VCFG2_L11_SHIFT); - HWREG(baseAddr + C2VSIZE) = 525 << VPIF_C2VSIZE_VSIZE_SHIFT; - } - if(sdChannel==VPIF_CHANNEL_3) - { - HWREG(baseAddr + C3HCFG) = (268 << VPIF_C3HCFG_EAV2SAV_SHIFT) | (1440 << VPIF_C3HCFG_SAV2EAV_SHIFT); - HWREG(baseAddr + C3VCFG0) = (4 << VPIF_C3VCFG0_L1_SHIFT) | (20 << VPIF_C3VCFG0_L3_SHIFT); - HWREG(baseAddr + C3VCFG1) = (264 << VPIF_C3VCFG1_L5_SHIFT) | (266 << VPIF_C3VCFG1_L7_SHIFT); - HWREG(baseAddr + C3VCFG2) = (283 << VPIF_C3VCFG2_L9_SHIFT) | (1 << VPIF_C3VCFG2_L11_SHIFT); - HWREG(baseAddr + C3VSIZE) = 525 << VPIF_C3VSIZE_VSIZE_SHIFT; - } - } - if(mode==VPIF_NONSTANDARD) - { - //TBD - if(sdChannel==VPIF_CHANNEL_2) { - } - if(sdChannel==VPIF_CHANNEL_3) { - } - } -} -/** -* \brief This function configures the frame buffer of the display video. -* The buffer address (and offset when applicable) is passed to VPIF. - -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* \param field is the field that the video is for (top/bottom). -* \param yc is the data component (luma/chroma). -* \param addr is the address of the frame buffer in the memory. -* \param offset is the line offset of the frame buffer in the memory. -* -* \return none. -**/ -void VPIFDisplayFBConfig(unsigned int baseAddr, unsigned int channel, unsigned int field, unsigned yc, unsigned int addr, unsigned int offset) -{ - if(channel==VPIF_CHANNEL_2) - { - if(field==VPIF_TOP_FIELD) - { - if(yc==VPIF_LUMA) - { - HWREG(baseAddr + C2TLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - HWREG(baseAddr + C2TCHROMA) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(yc==VPIF_LUMA) - { - HWREG(baseAddr + C2BLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - HWREG(baseAddr + C2BCHROMA) = addr; - } - } - HWREG(baseAddr + C2IMGOFFSET) = offset; - } - if(channel==VPIF_CHANNEL_3) - { - if(field==VPIF_TOP_FIELD) - { - if(yc==VPIF_LUMA) - { - HWREG(baseAddr + C3TLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - HWREG(baseAddr + C3TCHROMA) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(yc==VPIF_LUMA) - { - HWREG(baseAddr + C3BLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - HWREG(baseAddr + C3BCHROMA) = addr; - } - } - HWREG(baseAddr + C3IMGOFFSET) = offset; - } -} -/** -* \brief This function exchanges the frame buffer of the displayed video. -* A new buffer address (and offset when applicable) is passed to VPIF, -* and the address of the previous buffer is read back. -* -* \param baseAddr is the Memory address of VPIF. -* \param channel is the display channel (channel 3 or channel 2). -* \param field is the field that the video is for (top/bottom). -* \param yc is the data component (luma/chroma). -* \param addr is the address of the frame buffer in the memory. -* \param offset is the line offset of the frame buffer in the memory. -* -* \return Previuos buffer address. -**/ -unsigned int VPIFDisplayFBExchange(unsigned int baseAddr, unsigned int channel, unsigned int field, unsigned yc, unsigned int addr, unsigned int offset) -{ - unsigned int temp = 0; - if(channel==VPIF_CHANNEL_2) - { - if(field==VPIF_TOP_FIELD) - { - if(yc==VPIF_LUMA) - { - temp = HWREG(baseAddr + C2TLUMA); - HWREG(baseAddr + C2TLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - temp = HWREG(baseAddr + C2TCHROMA); - HWREG(baseAddr + C2TCHROMA) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(yc==VPIF_LUMA) - { - temp = HWREG(baseAddr + C2BLUMA); - HWREG(baseAddr + C2BLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - temp = HWREG(baseAddr + C2BCHROMA); - HWREG(baseAddr + C2BCHROMA) = addr; - } - } - HWREG(baseAddr + C2IMGOFFSET) = offset; - } - if(channel==VPIF_CHANNEL_3) - { - if(field==VPIF_TOP_FIELD) - { - if(yc==VPIF_LUMA) - { - temp = HWREG(baseAddr + C3TLUMA); - HWREG(baseAddr + C3TLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - temp = HWREG(baseAddr + C3TCHROMA); - HWREG(baseAddr + C3TCHROMA) = addr; - } - } - if(field==VPIF_BOTTOM_FIELD) - { - if(yc==VPIF_LUMA) - { - temp = HWREG(baseAddr + C3BLUMA); - HWREG(baseAddr + C3BLUMA) = addr; - } - if(yc==VPIF_CHROMA) - { - temp = HWREG(baseAddr + C3BCHROMA); - HWREG(baseAddr + C3BCHROMA) = addr; - } - } - HWREG(baseAddr + C3IMGOFFSET) = offset; - } - return temp; -} diff --git a/lib/tiam1808/tiam1808/dcan.h b/lib/tiam1808/tiam1808/dcan.h deleted file mode 100644 index 09b5585d9..000000000 --- a/lib/tiam1808/tiam1808/dcan.h +++ /dev/null @@ -1,760 +0,0 @@ -/** - * \file dcan.h - * - * \brief DCAN APIs and macros. - * - * This file contains the driver API prototypes and macro definitions for - * DCAN peripheral. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#ifndef __DCAN_H__ -#define __DCAN_H__ - -#include "hw_dcan.h" - -#ifdef __cplusplus -extern "C" { -#endif -/******************************************************************************/ -/* -** Values that can be passed to DCAN APIs -*/ - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANIntLineEnable' and 'DCANIntLineDisable'APIs -** as 'enableLine' and 'disableLine' respectively. -** 'enableLine','disableLine' can take both the values. -** For e.g. (DCAN_INT_LINE0 | DCAN_INT_LINE1) can be passed. -*/ -/* Enable/Disable Interrupt line 0 of DCAN peripheral */ -#define DCAN_INT_LINE0 (DCAN_CTL_IE0) -/* Enable/Disable Interrupt line 1 of DCAN peripheral */ -#define DCAN_INT_LINE1 (DCAN_CTL_IE1) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANIntEnable' and 'DCANIntDisable' APIs as -** 'intFlags'. -** 'intFlags' can take more than one value. -** For e.g. (DCAN_STATUS_CHANGE_INT | DCAN_ERROR_INT) can be passed. -*/ -/* Enable/Disable the Status change interrupt of DCAN peripheral */ -#define DCAN_STATUS_CHANGE_INT (0x00000004u) -/* Enable/Disable the error interrupt of DCAN peripheral */ -#define DCAN_ERROR_INT (0x00000008u) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANAutoReTransmitControl' API as 'autoReTxn'. -*/ -/* Enable Auto Re-transmission of DCAN peripheral */ -#define DCAN_AUTO_RETXN_ENABLE (0x00000000u) -/* Disable Auto Re-transmission of DCAN peripheral */ -#define DCAN_AUTO_RETXN_DISABLE (0x00000020u) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANConfigRegWriteAccessControl' API as -** 'regConfig'. -*/ -/* CPU has write access to the configuration registers */ -#define DCAN_CONF_REG_WR_ACCESS_ENABLE (DCAN_CTL_CCE) -/* CPU has no write access to the configuration registers */ -#define DCAN_CONF_REG_WR_ACCESS_DISABLE (DCAN_CTL_CCE_NOACCESS) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANTestModeControl' API as 'testMode'. -*/ -/* Enable Test mode of operation */ -#define DCAN_TEST_MODE_ENABLE (DCAN_CTL_TEST) -/* Disable Test mode of operation */ -#define DCAN_TEST_MODE_DISABLE (DCAN_CTL_TEST_NORMALMODE) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANDebugSuspendModeConfig' API as 'modeConfig'. -*/ -/* -** DCAN will wait for a started transmission or reception to be completed before -** entering debug/suspend mode. -*/ -#define DCAN_DEBUG_SUSPEND_WAIT (DCAN_CTL_IDS_WAIT) -/* -** DCAN will interrupt any transmission or reception, and enter debug/suspend -** mode immediately. -*/ -#define DCAN_DEBUG_SUSPEND_INTERRUPT (DCAN_CTL_IDS) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANAutoBusOnControl' API as 'busControl'. -*/ -/* Enable the Auto-bus-on feature */ -#define DCAN_AUTO_BUS_ON_ENABLE (DCAN_CTL_ABO) -/* Disable the Auto-bus-on feature */ -#define DCAN_AUTO_BUS_ON_DISABLE (DCAN_CTL_ABO_DISABLED) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANParityControl' API as 'paritySet'. -*/ -/* Enable Parity function */ -#define DCAN_PARITY_FUNC_ENABLE (DCAN_CTL_PMD_ENABLED << \ - DCAN_CTL_PMD_SHIFT) -/* Disable Parity function */ -#define DCAN_PARITY_FUNC_DISABLE (DCAN_CTL_PMD_DISABLED << \ - DCAN_CTL_PMD_SHIFT) - -/******************************************************************************/ -/* -** Values that can be used to return the status from 'DCANInternalDebugStatusGet' -** API. -*/ -/* Peripheral is not in debug mode */ -#define DCAN_NOT_IN_DEBUG_MODE (DCAN_CTL_INITDBG_DISABLED) -/* Peripheral is in debug mode or is ready for debug access */ -#define DCAN_IN_DEBUG_MODE (DCAN_CTL_INITDBG) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANDmaRequestLineEnable' and -** 'DCANDmaRequestLineDisable' APIs as 'ifRegFlags'. -** 'ifRegFlags' can take more than one value. -** For e.g. (DCAN_DMA_REQUEST_LINE_ENABLE_IF1 | DCAN_DMA_REQUEST_LINE_ENABLE_IF2) -** can be passed as 'ifRegFlags' -*/ -/* Enable/Disable DMA request line for IF1 */ -#define DCAN_DMA_REQUEST_LINE_IF1 (DCAN_CTL_DE1) -/* Enable/Disable DMA request line for IF2 */ -#define DCAN_DMA_REQUEST_LINE_IF2 (DCAN_CTL_DE2) -/* Enable/Disable DMA request line for IF3 */ -#define DCAN_DMA_REQUEST_LINE_IF3 (DCAN_CTL_DE3) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANPwrDwnControl' as 'pwrDwnCtl' -*/ -/* Local power down is not requested */ -#define DCAN_LOCAL_PWR_DWN_OFF (DCAN_CTL_PDR_NOTPOWERDOWN) -/* Local power down mode is requested */ -#define DCAN_LOCAL_PWR_DWN_ON (DCAN_CTL_PDR) - -/******************************************************************************/ -/* -** Values that can be passed on to 'DCANPwrDwnWkUpControl' API as 'wkUpCtl' -*/ -/* No detection of a dominant CAN bus level when in local power down mode */ -#define DCAN_WKUP_DETECTION_DISABLED (DCAN_CTL_WUBA_NODETECTION) -/* Detection of a dominant CAN bus level when in local power down is enabled */ -#define DCAN_WKUP_DETECTION_ENABLED (DCAN_CTL_WUBA) - -/******************************************************************************/ -/* -** Values that can be used to check the status of DCAN_ES register got from -** 'DCANErrAndStatusRegInfoGet' API. -*/ -/* No error is detected */ -#define DCAN_LST_ERRCODE_NO_ERR (DCAN_ES_LEC_NOERROR) -/* Stuff error is detected */ -#define DCAN_LST_ERRCODE_STUFF_ERR (DCAN_ES_LEC_STUFFERROR) -/* Form error is detected */ -#define DCAN_LST_ERRCODE_FORM_ERR (DCAN_ES_LEC_FORMERROR) -/* Ack error is detected */ -#define DCAN_LST_ERRCODE_ACK_ERR (DCAN_ES_LEC_ACKERROR) -/* Bit1 error is detected */ -#define DCAN_LST_ERRCODE_BIT1_ERR (DCAN_ES_LEC_BIT1ERROR) -/* Bit0 error is detected */ -#define DCAN_LST_ERRCODE_BIT0_ERR (DCAN_ES_LEC_BIT0ERROR) -/* CRC error detected */ -#define DCAN_LST_ERRCODE_CRC_ERR (DCAN_ES_LEC_CRCERROR) -/* No event is generated on the CAN bus since last read of DCAN_ES */ -#define DCAN_NO_EVENT_ON_CAN_BUS (DCAN_ES_LEC_NOEVENT) -/* DCAN transmitted message successfully */ -#define DCAN_TXD_MSG_SUCCESSFULLY (DCAN_ES_TXOK) -/* DCAN received message successfully */ -#define DCAN_RXD_MSG_SUCCESSFULLY (DCAN_ES_RXOK) -/* DCAN is in error passive state */ -#define DCAN_CORE_IN_ERR_PASSIVE (DCAN_ES_EPASS) -/* Atleast one of the counters have reached the error warning limit */ -#define DCAN_ERR_WARN_STATE_RCHD (DCAN_ES_EWARN) -/* DCAN is in Bus off state */ -#define DCAN_MOD_IN_BUS_OFF_STATE (DCAN_ES_BOFF) -/* Parity error detected */ -#define DCAN_PARITY_ERR_DETECTED (DCAN_ES_PER) -/* DCAN initiated system wakeup */ -#define DCAN_INITIATED_SYSTEM_WKUP (DCAN_ES_WAKEUPPND) -/* DCAN is in local power down mode */ -#define DCAN_IN_LOCAL_PWR_DWN_MODE (DCAN_ES_PDA) - -/******************************************************************************/ -/* -** Values that can be sent to 'DCANErrCntrRegStatusGet' API as 'cntrFlags'. -** 'cntrFlags' can take more than one value. -** For e.g. (DCAN_TX_ERR_CNTR | DCAN_RX_ERR_CNTR | DCAN_RX_ERR_PASSIVE) can be -** sent as 'cntrFlags'. -*/ -/* Macro used to return the status of TEC[7:0] field of DCAN_ERRC register */ -#define DCAN_TX_ERR_CNTR (DCAN_ERRC_TEC) -/* Macro used to return the status of REC[6:0] field of DCAN_ERRC register*/ -#define DCAN_RX_ERR_CNTR (DCAN_ERRC_REC) -/* Macro used to return the status of RP field of DCAN_ERRC register */ -#define DCAN_RX_ERR_PASSIVE (DCAN_ERRC_RP) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANIntRegStatusGet' API as 'intLnFlag'. -** 'intLnFlag' can take more than one value. -** For e.g. (DCAN_INT_LINE0_STAT | DCAN_INT_LINE1_STAT) can be passed as -** 'intLnFlag'. -*/ -/* Macro used to return the status of INT0ID[15:0] field of DCAN_INT register */ -#define DCAN_INT_LINE0_STAT (DCAN_INT_INT0ID) -/* Macro used to return the status of INT1ID[23:16] field of DCAN_INT register */ -#define DCAN_INT_LINE1_STAT (DCAN_INT_INT1ID) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANTestModesEnable' and 'DCANTestModesDisable' -** API as 'tstMode'. -*/ -/* Macro that can be used to enable/disable silent mode */ -#define DCAN_TST_SILENT_MD (DCAN_TEST_SILENT) -/* Macro that can be used to enable/disable loopback mode */ -#define DCAN_TST_LPBCK_MD (DCAN_TEST_LBACK) -/* Macro that can be used to enable/disable external loopback mode */ -#define DCAN_TST_EXTLPBCK_MD (DCAN_TEST_EXL) -/* Macro that can be used to enable/disable loopback with silent mode */ -#define DCAN_TST_LPBCK_SILENT_MD (DCAN_TEST_LBACK | \ - DCAN_TEST_SILENT) -/* Macro that can be used to enable/disable direct access to RAM */ -#define DCAN_TST_RAM_DIRECT_ACCESS (DCAN_TEST_RDA) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANTxPinControl' API as 'pinCtl'. -*/ -/* CAN_TX pin is controlled by CAN core */ -#define DCAN_TST_TX_NRML_OP (DCAN_TEST_TX_NORMAL) -/* Sample point can be monitored at CAN_TX pin */ -#define DCAN_TST_TX_SAMPLE_PT_MNTR (DCAN_TEST_TX_SAMPLEPOINT << \ - DCAN_TEST_TX_SHIFT) -/* CAN_TX pin drives a dominant value */ -#define DCAN_TST_TX_DRIV_DOM_VAL (DCAN_TEST_TX_DOMINANT << \ - DCAN_TEST_TX_SHIFT) -/* CAN_TX pin drives a recessive value */ -#define DCAN_TST_TX_DRIV_RSV_VAL (DCAN_TEST_TX_RECESSIVE << \ - DCAN_TEST_TX_SHIFT) - -/******************************************************************************/ -/* -** Values that can be used to check the status received from 'DCANRxPinStatusGet' -** API. -*/ -/* CAN bus is dominant */ -#define DCAN_TST_RX_IS_DOM (DCAN_TEST_RX_DOMINANT) -/* CAN bus is recessive */ -#define DCAN_TST_RX_IS_RSV (DCAN_TEST_RX) - -/******************************************************************************/ -/* -** Values that can be used to check the status received from -** 'DCANParityErrCdRegStatusGet' API. -*/ -/* Macro used to return the message number status from DCAN_PERR register */ -#define DCAN_PARITY_ERR_MSG_NUM (DCAN_PERR_MESSAGE_NUMBER) -/* Macro used to return the word number status from DCAN_PERR register */ -#define DCAN_PARITY_ERR_WRD_NUM (DCAN_PERR_WORD_NUMBER) - -/******************************************************************************/ -/* -** Value that can be used while checking the status obtained from -** 'DCANTxRqstXStatusGet' API. -** 'n' can take these values -** 1 <= n <= 8. -*/ -/* Value that can be used to check the status of DCAN_TXRQST_X register */ -#define DCAN_TXRQST_X_REG(n) (DCAN_TXRQ_X_TXRQSTREG1 << \ - (((n) - 1) * 2)) - -/******************************************************************************/ -/* -** Value that can be used while checking the status obtained from -** 'DCANNewDataXStatusGet' API. -** 'n' can take these values -** 1 <= n <= 8. -*/ -/* Value that can be used to check the status of DCAN_NWDAT_X register */ -#define DCAN_NEWDAT_X_REG(n) (DCAN_NWDAT_X_NEWDATREG1 << \ - (((n) - 1) * 2)) - -/******************************************************************************/ -/* -** Value that can be used while checking the status obtained from -** 'DCANMsgValidXStatusGet' API. -** 'n' can take these values -** 1 <= n <= 8. -*/ -/* Value that can be used to check the status of DCAN_MSGVAL_X register */ -#define DCAN_MSGVAL_X_REG(n) (DCAN_MSGVAL_X_MSGVALREG1 << \ - (((n) - 1) * 2)) - -/******************************************************************************/ -/* -** Value that can be used while checking the status obtained from -** 'DCANIntPendingXStatusGet' API. -** 'n' can take these values -** 1 <= n <= 8. -*/ -/* Value that can be used to check the status of DCAN_INTPND_X register */ -#define DCAN_INTPND_X_REG(n) (DCAN_INTPND_X_INTPNDREG1 << \ - (((n) - 1) * 2)) - -/******************************************************************************/ -/* -** Values can be used to check the status obtained from 'DCANIFBusyStatusGet' -** API. -*/ -/* Transfer between IF1/IF2 register set and message RAM is in progress */ -#define DCAN_IF_BUSY (DCAN_IFCMD_BUSY) -/* No transfer between IF1/IF2 register set and message RAM */ -#define DCAN_IF_NOT_BUSY (DCAN_IFCMD_BUSY_NOTRANSFER) - -/******************************************************************************/ -/* -** Values that can be sent to 'DCANMsgIdSet' API as 'idLength'. -*/ -/* Identifier of 11 bit size is used */ -#define DCAN_11_BIT_ID (DCAN_IFARB_XTD_11_BIT) -/* Identifier of 29 bit size is used */ -#define DCAN_29_BIT_ID (DCAN_IFARB_XTD) - -/******************************************************************************/ -/* -** Values that can be sent to 'DCANIntMuxConfig' API as 'intLine' -*/ -/* DCANINT0 line is active if corresponding IntPnd flag is one */ -#define DCAN_INT0_ACTIVE (0x00000000u) -/* DCANINT1 line is active if corresponding IntPnd flag is one */ -#define DCAN_INT1_ACTIVE (0x00000001u) - -/******************************************************************************/ -/* -** Values that can be sent to 'DCANMsgObjValidate', 'DCANMsgObjInvalidate, -** 'DCANCommandRegSet', 'DCANIFBusyStatusGet, 'DCANMsgIdSet', -** 'DCANMsgDirectionSet', 'DCANDataWrite', 'DCANDataRead', 'DCANDataLengthCodeSet', -** 'DCANRemoteEnableControl', 'DCANMsgObjIntEnable', 'DCANMsgObjIntDisable', -** 'DCANFIFOEndOfBlockControl', 'DCANMsgObjectDirectionConfig', -** 'DCANMsgObjectMskConfig', APIs as ''regNum'. -*/ -/* Interface register 1 is used */ -#define DCAN_IF1_REG (1u) -/* Interface register 2 is used */ -#define DCAN_IF2_REG (2u) -/* Interface register 3 is used */ -#define DCAN_IF3_REG (3u) - -/******************************************************************************/ -/* -** Values that can be sent to 'DCANMsgDirectionSet' API as 'msgDir'. -*/ -/* Message object set to transmit a message*/ -#define DCAN_TX_DIR (DCAN_IFARB_DIR) -/* Message object set to receive a message*/ -#define DCAN_RX_DIR (DCAN_IFARB_DIR_RECEIVE) - -/******************************************************************************/ -/* -** Values that can be sent to 'DCANRemoteEnableControl' API as 'remEnable'. -*/ -/* At the reception of a remote frame TxRqst is set */ -#define DCAN_REMOTE_ENABLE (DCAN_IFMCTL_RMTEN) -/* At the reception of a remote frame TxRqst is not changed */ -#define DCAN_REMOTE_DISABLE (DCAN_IFMCTL_RMTEN_DISABLE) - -/******************************************************************************/ -/* -** Values that can be sent to 'DCANMsgObjIntEnable' and 'DCANMsgObjIntDisable' -** APIs as 'intFlags'. -*/ -/* Enable/disable transmit interrupt */ -#define DCAN_TRANSMIT_INT (DCAN_IFMCTL_TXIE) -/* Enable/disable receive interrupt */ -#define DCAN_RECEIVE_INT (DCAN_IFMCTL_RXIE) - -/******************************************************************************/ -/* -** Values that can be sent to 'DCANFIFOEndOfBlockControl' API as 'eob'. -*/ -/* Enable end of block */ -#define DCAN_END_OF_BLOCK_ENABLE (DCAN_IFMCTL_EOB) -/* Disable end of block */ -#define DCAN_END_OF_BLOCK_DISABLE (0x00000000u) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANCommandRegSet' API as 'cmdFlags'. -** 'cmdFlags' can be passed by combining more than one macro. -** For e.g. (DCAN_DMA_ACTIVE | DCAN_DAT_A_ACCESS | DCAN_DAT_B_ACCESS) -*/ -/* Enable DMA feature */ -#define DCAN_DMA_ACTIVE (DCAN_IFCMD_DMAACTIVE) -/* Access data from IF DataA register */ -#define DCAN_DAT_A_ACCESS (DCAN_IFCMD_DATAA) -/* Access data from IF DataB register */ -#define DCAN_DAT_B_ACCESS (DCAN_IFCMD_DATAB) -/* Access the TxRqst bit */ -#define DCAN_TXRQST_ACCESS (DCAN_IFCMD_TXRQST_NEWDAT) -/* Clear the IntPnd bit */ -#define DCAN_CLR_INTPND (DCAN_IFCMD_CLRINTPND) -/* Access control bits */ -#define DCAN_ACCESS_CTL_BITS (DCAN_IFCMD_CONTROL) -/* Access Arbitration bits */ -#define DCAN_ACCESS_ARB_BITS (DCAN_IFCMD_ARB) -/* Access the mask bits */ -#define DCAN_ACCESS_MSK_BITS (DCAN_IFCMD_MASK) -/* Transfer direction is from IF registers to message RAM */ -#define DCAN_MSG_WRITE (DCAN_IFCMD_WR_RD) -/* Transfer direction is from message RAM to IF registers */ -#define DCAN_MSG_READ (0x00000000u) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCAN_IDENTIFIER_MSK' macro as idType. -*/ -/* 11 bit id is used */ -#define DCAN_ID_MSK_11_BIT (18u) -/* 29 bit id is used */ -#define DCAN_ID_MSK_29_BIT (0u) - -/******************************************************************************/ -/* -** Value that can be passed to 'DCANMsgObjectMskConfig' API as 'idMsk'. -** 'mask' can take values between 0 <= idMsk <= 0x1FFFFFFF \n -** 'idType' can take the following values \n -** DCAN_ID_MSK_11_BIT - 11 bit identifier is used \n -** DCAN_ID_MSK_29_BIT - 29 bit identifier is used \n -*/ -#define DCAN_IDENTIFIER_MSK(mask, idType) (mask << idType) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANMsgObjectMskConfig' API as 'msgDir'. -*/ -/* Message direction bit is used for acceptance filtering */ -#define DCAN_MSK_MSGDIR_ENABLE (DCAN_IFMSK_MDIR) -/* Message direction bit has no effect on acceptance filtering */ -#define DCAN_MSK_MSGDIR_DISABLE (DCAN_IFMSK_MDIR_NOTUSED) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANMsgObjectMskConfig' API as 'extId'. -*/ -/* The IDE bit is used for acceptance filtering */ -#define DCAN_MSK_EXT_ID_ENABLE (DCAN_IFMSK_MXTD) -/* The IDE bit is not used for acceptance filtering */ -#define DCAN_MSK_EXT_ID_DISABLE (DCAN_IFMSK_MXTD_NOTUSED) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANIF3ObservationFlagSet' API as 'obsFlags'. -** 'obsFlags' can take more than 1 value. -** For e.g. (DCAN_MASK_DATA | DCAN_ARB_DATA) -*/ -/* Mask data read observation */ -#define DCAN_MASK_DATA (DCAN_IF3OBS_MASK) -/* Arbitration data read observation */ -#define DCAN_ARB_DATA (DCAN_IF3OBS_ARB) -/* Ctrl read observation */ -#define DCAN_CTRL_DATA (DCAN_IF3OBS_CTRL) -/* Data A read observation */ -#define DCAN_DAT_A_DATA (DCAN_IF3OBS_DATAA) -/* Data B read observation */ -#define DCAN_DAT_B_DATA (DCAN_IF3OBS_DATAB) - -/******************************************************************************/ -/* -** Values that can be used to check the status obtained from -** 'DCANIF3ObservationFlagStatGet' API. -*/ -/* IF3 status of Mask data read access */ -#define DCAN_IF3_MASK_STATUS (DCAN_IF3OBS_IF3SM) -/* IF3 status of Arbitration data read access */ -#define DCAN_IF3_ARB_STATUS (DCAN_IF3OBS_IF3SA) -/* IF3 status of Control bits read access */ -#define DCAN_IF3_CTRL_STATUS (DCAN_IF3OBS_IF3SC) -/* IF3 status of Data A read access */ -#define DCAN_IF3_DAT_A_STATUS (DCAN_IF3OBS_IF3SDA) -/* IF3 status of Data B read access */ -#define DCAN_IF3_DAT_B_STATUS (DCAN_IF3OBS_IF3SDB) -/* IF3 Update data status */ -#define DCAN_IF3_UPDATE_STATUS (DCAN_IF3OBS_IF3UPD) - -/******************************************************************************/ -/* -** Values that can be used to check the status obtained from -** 'DCANIF3MaskStatusGet' API. -*/ -/* Read Identifier mask */ -#define DCAN_ID_MSK_READ (DCAN_IF3MSK_MSK) -/* Read mask message direction */ -#define DCAN_MSK_MSG_DIR_READ (DCAN_IF3MSK_MDIR) -/* Read mask extended identifier */ -#define DCAN_MSK_EXT_ID_READ (DCAN_IF3MSK_MXTD) - -/******************************************************************************/ -/* -** Values that can be used to check the status obtained from 'DCANIF3ArbStatusGet' -** API. -*/ -/* Read message identifier */ -#define DCAN_MSG_ID_READ (DCAN_IF3ARB_MSK) -/* Read message direction */ -#define DCAN_MSG_DIR_READ (DCAN_IF3ARB_DIR) -/* Read extended identifier */ -#define DCAN_EXT_ID_READ (DCAN_IF3ARB_XTD) -/* Read message valid status */ -#define DCAN_MSGVAL_READ (DCAN_IF3ARB_MSGVAL) - -/******************************************************************************/ -/* -** Values that can be used to check the status obtained from -** 'DCANIFMsgCtlStatusGet' API. -*/ -/* Read data length code */ -#define DCAN_DAT_LEN_CODE_READ (DCAN_IF3MCTL_DATALENGTHCODE) -/* Read end of block bit */ -#define DCAN_END_OF_BLOCK_READ (DCAN_IF3MCTL_EOB) -/* Read transmit request bit */ -#define DCAN_TXRQST_READ (DCAN_IF3MCTL_TXRQST) -/* Read remote enable bit */ -#define DCAN_RMT_ENABLE_READ (DCAN_IF3MCTL_RMTEN) -/* Read Rx interrupt enable bit */ -#define DCAN_RX_INT_ENABLE_READ (DCAN_IF3MCTL_RXIE) -/* Read Tx interrupt enable bit */ -#define DCAN_TX_INT_ENABLE_READ (DCAN_IF3MCTL_TXIE) -/* Read use acceptance mask bit */ -#define DCAN_UMASK_READ (DCAN_IF3MCTL_UMASK) -/* Read interrupt pending status */ -#define DCAN_INTPND_READ (DCAN_IF3MCTL_INTPND) -/* Read message lost status */ -#define DCAN_MSG_LOST_READ (DCAN_IF3MCTL_MSGLST) -/* Read new data status */ -#define DCAN_NEWDAT_READ (DCAN_IF3MCTL_NEWDAT) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANTxPinModeConfig' API as 'txPinMode'. -*/ -/* DCAN Tx Pin is used as general purpose pin */ -#define DCAN_TX_PIN_GIO_MODE (0x00000000u) -/* DCAN Tx Pin is used as functional pin */ -#define DCAN_TX_PIN_FUNC_MODE (0x00000008u) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANTxPinInputDirConfig' API as 'pinLogic'. -*/ -/* DCAN Tx pin is used as an input pin with logic low */ -#define DCAN_TX_PIN_IN_LOGIC_LOW (0x00000000u) -/* DCAN Tx pin is used as an input pin with logic high */ -#define DCAN_TX_PIN_IN_LOGIC_HIGH (0x00000001u) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANTxPinOutputDirConfig' API as 'pinLogic'. -*/ -/* DCAN Tx pin is used as an output pin with logic low */ -#define DCAN_TX_PIN_OUT_LOGIC_LOW (0x00000000u) -/* DCAN Tx pin is used as an output pin with logic high */ -#define DCAN_TX_PIN_OUT_LOGIC_HIGH (0x00000002u) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANRxPinModeConfig' API as 'rxPinMode'. -*/ -/* DCAN Rx Pin is used as general purpose pin */ -#define DCAN_RX_PIN_GIO_MODE (0x00000000u) -/* DCAN Rx Pin is used as functional pin */ -#define DCAN_RX_PIN_FUNC_MODE (0x00000008u) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANRxPinInputDirConfig' API as 'pinLogic'. -*/ -/* DCAN Rx pin is used as an input pin with logic low */ -#define DCAN_RX_PIN_IN_LOGIC_LOW (0x00000000u) -/* DCAN Rx pin is used as an input pin with logic high */ -#define DCAN_RX_PIN_IN_LOGIC_HIGH (0x00000001u) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANRxPinOutputDirConfig' API as 'pinLogic'. -*/ -/* DCAN Rx pin is used as an output pin with logic low */ -#define DCAN_RX_PIN_OUT_LOGIC_LOW (0x00000000u) -/* DCAN Rx pin is used as an output pin with logic high */ -#define DCAN_RX_PIN_OUT_LOGIC_HIGH (0x00000002u) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANNewDataControl' API as 'newDat'. -*/ -/* Set NewDat */ -#define DCAN_NEW_DAT_SET (DCAN_IFMCTL_NEWDAT) -/* Clear NewDat */ -#define DCAN_NEW_DAT_CLR (DCAN_IFMCTL_NEWDAT_NONEWDATA) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANUseAcceptanceMaskControl' API as 'uMask' -*/ -/* Use acceptance mask */ -#define DCAN_MASK_USED (DCAN_IFMCTL_UMASK) -/* Acceptance mask not used */ -#define DCAN_MASK_IGNORED (DCAN_IFMCTL_UMASK_IGNORED) - -/******************************************************************************/ -/* -** Values that can be passed to 'DCANTransmitRequestControl' API as 'txRqst' -*/ -/* Request for transmission */ -#define DCAN_TRANSMIT_REQUESTED (DCAN_IFMCTL_TXRQST) -/* Transmission not requested */ -#define DCAN_TRANSMIT_NOT_REQUESTED (DCAN_IFMCTL_TXRQST_NOREQUESTED) - -/******************************************************************************/ -/* DCAN API PROTOTYPES */ -/******************************************************************************/ -extern void DCANInitModeSet(unsigned int baseAdd); -extern void DCANNormalModeSet(unsigned int baseAdd); -extern void DCANBitTimingConfig(unsigned int baseAdd, - unsigned int btrValue); -extern void DCANReset(unsigned int baseAdd); -extern void DCANIntEnable(unsigned int baseAdd, unsigned int intFlags); -extern void DCANIntDisable(unsigned int baseAdd, unsigned int intFlags); -extern void DCANAutoReTransmitControl(unsigned int baseAdd, unsigned int autoReTxn); -extern void DCANConfigRegWriteAccessControl(unsigned int baseAdd, - unsigned int regConfig); -extern void DCANTestModeControl(unsigned int baseAdd, unsigned int testMode); -extern void DCANDebugSuspendModeConfig(unsigned int baseAdd, unsigned int modeConfig); -extern void DCANAutoBusOnControl(unsigned int baseAdd, unsigned int busControl); -extern void DCANParityControl(unsigned int baseAdd, unsigned int paritySet); -extern unsigned int DCANInternalDebugStatusGet(unsigned int baseAdd); -extern void DCANIntLineEnable(unsigned int baseAdd, unsigned int enableLine); -extern void DCANIntLineDisable(unsigned int baseAdd, unsigned int disableLine); -extern void DCANDmaRequestLineEnable(unsigned int baseAdd, unsigned int ifRegFlags); -extern void DCANDmaRequestLineDisable(unsigned int baseAdd, unsigned int ifRegFlags); -extern void DCANPwrDwnControl(unsigned int baseAdd, unsigned int pwrDwnCtl); -extern void DCANPwrDwnWkUpControl(unsigned int baseAdd, unsigned int wkUpCtl); -extern unsigned int DCANIntRegStatusGet(unsigned int baseAdd, unsigned int intLnFlag); -extern unsigned int DCANErrAndStatusRegInfoGet(unsigned int baseAdd); -extern void DCANParityEndOfIntSet(unsigned int baseAdd); -extern unsigned int DCANErrCntrRegStatusGet(unsigned int baseAdd, - unsigned int cntrFlags); -extern void DCANTestModesEnable(unsigned int baseAdd, unsigned int tstMode); -extern void DCANTestModesDisable(unsigned int baseAdd, unsigned int tstMode); -extern void DCANTxPinControl(unsigned int baseAdd, unsigned int pinCtl); -extern unsigned int DCANRxPinStatusGet(unsigned int baseAdd); -extern unsigned int DCANParityErrCdRegStatusGet(unsigned int baseAdd, - unsigned int statFlg); -extern void DCANAutoBusOnTimeValSet(unsigned int baseAdd, unsigned int timeVal); -extern unsigned int DCANAutoBusOnTimeValGet(unsigned int baseAdd); -extern unsigned int DCANTxRqstXStatusGet(unsigned int baseAdd); -extern unsigned int DCANTxRqstStatusGet(unsigned int baseAdd, unsigned int msgNum); -extern unsigned int DCANTxRqstStatGet(unsigned int baseAdd); -extern unsigned int DCANNewDataXStatusGet(unsigned int baseAdd); -extern unsigned int DCANNewDataStatusGet(unsigned int baseAdd, unsigned int msgNum); -extern unsigned int DCANNewDataStatGet(unsigned int baseAdd); -extern void DCANMsgObjValidate(unsigned int baseAdd, unsigned int regNum); -extern void DCANMsgObjInvalidate(unsigned baseAdd, unsigned int regNum); -extern void DCANCommandRegSet(unsigned int baseAdd, unsigned int cmdFlags, - unsigned int objNum, unsigned int regNum); -extern unsigned int DCANIntPendingXStatusGet(unsigned int baseAdd); -extern unsigned int DCANIntPendingStatusGet(unsigned int baseAdd, unsigned int msgNum); -extern unsigned int DCANMsgValidXStatusGet(unsigned int baseAdd); -extern unsigned int DCANMsgValidStatusGet(unsigned int baseAdd, unsigned int msgNum); -extern void DCANIntMuxConfig(unsigned int baseAdd, unsigned int intLine, - unsigned int msgNum); -extern unsigned int DCANIFBusyStatusGet(unsigned int baseAdd, unsigned int regNum); -extern void DCANMsgIdSet(unsigned int baseAdd, unsigned int msgId, - unsigned int idLength, unsigned int regNum); -extern void DCANMsgDirectionSet(unsigned int baseAdd, unsigned int msgDir, - unsigned int regNum); -extern void DCANDataWrite(unsigned int baseAdd, unsigned int* dataPtr, - unsigned int regNum); -extern void DCANDataRead(unsigned int baseAdd, unsigned int* data, unsigned int regNum); -extern void DCANDataLengthCodeSet(unsigned int baseAdd, unsigned int dlc, - unsigned int regNum); -extern void DCANRemoteEnableControl(unsigned int baseAdd, unsigned int remEnable, - unsigned int regNum); -extern void DCANMsgObjIntEnable(unsigned int baseAdd, unsigned int intFlags, - unsigned int regNum); -extern void DCANMsgObjIntDisable(unsigned int baseAdd, unsigned int intFlags, - unsigned int regNum); -extern void DCANFIFOEndOfBlockControl(unsigned int baseAdd, unsigned int eob, - unsigned int regNum); -extern void DCANMsgObjectMskConfig(unsigned int baseAdd, unsigned int idMsk, - unsigned int msgDir, unsigned int extId, - unsigned int regNum); -extern void DCANIF3RegUpdateEnableSet(unsigned int baseAdd, - unsigned int msgNum); -extern unsigned char DCANIF3ObservationFlagStatGet(unsigned int baseAdd); -extern void DCANIF3ObservationFlagSet(unsigned int baseAdd, unsigned int obsFlags); -extern void DCANIF3ObservationFlagClear(unsigned int baseAdd, unsigned int obsFlags); -extern unsigned int DCANIF3MaskStatusGet(unsigned int baseAdd); -extern unsigned int DCANIF3ArbStatusGet(unsigned int baseAdd); -extern unsigned int DCANIFMsgCtlStatusGet(unsigned int baseAdd, unsigned int regNum); -extern void DCANTxPinModeConfig(unsigned int baseAdd, unsigned int txPinMode); -extern void DCANTxPinInputDirConfig(unsigned int baseAdd, unsigned int pinLogic); -extern void DCANTxPinOutputDirConfig(unsigned int baseAdd, unsigned int pinLogic); -extern void DCANRxPinModeConfig(unsigned int baseAdd, unsigned int rxPinMode); -extern void DCANRxPinInputDirConfig(unsigned int baseAdd, unsigned int pinLogic); -extern void DCANRxPinOutputDirConfig(unsigned int baseAdd, unsigned int pinLogic); -extern void DCANClrIntPnd(unsigned int baseAdd, unsigned int regNum); -extern void DCANNewDataControl(unsigned int baseAdd, unsigned int newDat, - unsigned int regNum); -extern void DCANUseAcceptanceMaskControl(unsigned int baseAdd, unsigned int uMask, - unsigned int regNum); -extern void DCANTransmitRequestControl(unsigned int baseAdd, unsigned int txRqst, - unsigned int regNum); -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/tiam1808/tiam1808/elm.h b/lib/tiam1808/tiam1808/elm.h deleted file mode 100644 index dfe726a22..000000000 --- a/lib/tiam1808/tiam1808/elm.h +++ /dev/null @@ -1,196 +0,0 @@ -/** - * \file elm.h - * - * \brief Definitions used for ELM - * - * This file contains the driver API prototypes and macro definitions. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _ELM_H_ -#define _ELM_H__ - -#include "hw_elm.h" -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* -* MACRO DEFINITIONS -*******************************************************************************/ -/*****************************************************************************/ - -/* -** Macros which can be used as 'configVal' parameter to ELMCAutoGatingConfig API -** -*/ -#define ELM_AUTOGATING_OCP_FREE (0) -#define ELM_AUTOGATING_OCP_GATING (1) - -/* -** Macros which can be used as 'configVal' parameter to ELMCIdleModeSelect API. -** -*/ -#define ELM_IDLEMODE_FORCEIDLE (0) -#define ELM_IDLEMODE_NOIDLE (1) -#define ELM_IDLEMODE_SMARTIDLE (2) - -/* -** Macros which can be used as 'configVal' parameter to ELMOCPClkActivityConfig -** API. -** -*/ -#define ELM_CLOCKACTIVITYOCP_OCP_ON (1) -#define ELM_CLOCKACTIVITYOCP_OCP_OFF (0) - -/* -** Macros which can be used as 'flag' parameter to ELMIntStatusGet API. -** -*/ -#define ELM_LOC_VALID_0_STATUS (0) -#define ELM_LOC_VALID_1_STATUS (1) -#define ELM_LOC_VALID_2_STATUS (2) -#define ELM_LOC_VALID_3_STATUS (3) -#define ELM_LOC_VALID_4_STATUS (4) -#define ELM_LOC_VALID_5_STATUS (5) -#define ELM_LOC_VALID_6_STATUS (6) -#define ELM_LOC_VALID_7_STATUS (7) -#define ELM_PAGE_VALID_STATUS (8) - -/* -** Macros which can be used as 'flag' parameter to ELMIntConfig API. -** -*/ -#define ELM_INT_ENALBLE (1) -#define ELM_INT_DISALBLE (0) - -/* -** Macros which can be used as 'bchECCLevel' parameter to -** ELMErrCorrectionLevelSet API. -** -*/ -#define ELM_ECC_BCH_LEVEL_4BITS (0) -#define ELM_ECC_BCH_LEVEL_8BITS (1) -#define ELM_ECC_BCH_LEVEL_16BITS (2) - -/* -** Macros which can be used as 'mode' parameter to ELMModeSet API. -** -*/ -#define ELM_MODE_CONTINUOUS (0) -#define ELM_MODE_PAGE (1) - -/* -** Macros which can be used as 'sectorNum' parameter to ELMModeSet API. -** -*/ -#define ELM_PAGEMODE_SECTOR_0 (0) -#define ELM_PAGEMODE_SECTOR_1 (1) -#define ELM_PAGEMODE_SECTOR_2 (2) -#define ELM_PAGEMODE_SECTOR_3 (3) -#define ELM_PAGEMODE_SECTOR_4 (4) -#define ELM_PAGEMODE_SECTOR_5 (5) -#define ELM_PAGEMODE_SECTOR_6 (6) -#define ELM_PAGEMODE_SECTOR_7 (7) - -/* -** Macros which can be used as 'synFrgmtId' parameter to ELMSyndromeFrgmtSet API -** -*/ -#define ELM_SYNDROME_FRGMT_0 (0) -#define ELM_SYNDROME_FRGMT_1 (1) -#define ELM_SYNDROME_FRGMT_2 (2) -#define ELM_SYNDROME_FRGMT_3 (3) -#define ELM_SYNDROME_FRGMT_4 (4) -#define ELM_SYNDROME_FRGMT_5 (5) -#define ELM_SYNDROME_FRGMT_6 (6) - -/* -** Macros which can be used as 'errNum' parameter to ELMErrLocBitAddrGet API. -** -*/ -#define ELM_ERROR_NUM_0 (0) -#define ELM_ERROR_NUM_1 (1) -#define ELM_ERROR_NUM_2 (2) -#define ELM_ERROR_NUM_3 (3) -#define ELM_ERROR_NUM_4 (4) -#define ELM_ERROR_NUM_5 (5) -#define ELM_ERROR_NUM_6 (6) -#define ELM_ERROR_NUM_7 (7) -#define ELM_ERROR_NUM_8 (8) -#define ELM_ERROR_NUM_9 (9) -#define ELM_ERROR_NUM_10 (10) -#define ELM_ERROR_NUM_11 (11) -#define ELM_ERROR_NUM_12 (12) -#define ELM_ERROR_NUM_13 (13) -#define ELM_ERROR_NUM_14 (14) -#define ELM_ERROR_NUM_15 (15) - -/***************************************************************************** -** FUNCTION PROTOTYPES -*****************************************************************************/ - -extern void ELMModuleReset(unsigned int baseAddr); -extern unsigned int ELMRevisionGet(unsigned int baseAddr); -extern unsigned int ELMNumOfErrsGet(unsigned int baseAddr); -extern void ELMErrLocProcessingStart(unsigned int baseAddr); -extern unsigned int ELMModuleResetStatusGet(unsigned int baseAddr); -extern unsigned int ELMErrLocProcessingStatusGet(unsigned int baseAddr); -extern void ELMECCSizeSet(unsigned int baseAddr, unsigned int eccSize); -extern void ELMIntStatusClear(unsigned int baseAddr, unsigned int flag); -extern void GPMCIntStatusClear(unsigned int baseAddr, unsigned int flag); -extern void ELMCIdleModeSelect(unsigned int baseAddr, unsigned int mode); -extern unsigned int ELMIntStatusGet(unsigned int baseAddr, unsigned int flag); -extern void ELMCAutoGatingConfig(unsigned int baseAddr, - unsigned int configVal); -extern unsigned int ELMErrLocBitAddrGet(unsigned int baseAddr, - unsigned int errNum); -extern void ELMOCPClkActivityConfig(unsigned int baseAddr, - unsigned int configVal); -extern void ELMErrCorrectionLevelSet(unsigned int baseAddr, - unsigned int bchECCLevel); -extern void ELMModeSet(unsigned int baseAddr, unsigned int mode, - unsigned int sectorNum); -extern void ELMIntConfig(unsigned int baseAddr, unsigned int intFlag, - unsigned int configVal); -extern void ELMSyndromeFrgmtSet(unsigned int baseAddr, unsigned int synFrgmtId, - unsigned int synFrgmtVal); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_control_AM335x.h b/lib/tiam1808/tiam1808/hw/hw_control_AM335x.h deleted file mode 100644 index d5199f56f..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_control_AM335x.h +++ /dev/null @@ -1,7794 +0,0 @@ - - -/** - * @Component: CONTROL - * - * @Filename: ../../CredDataBase/CONTROL_cred.h - * - ============================================================================ */ -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - - -#ifndef _HW_CONTROL_H_ -#define _HW_CONTROL_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***********************************************************************\ - * Register arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundle arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundles Definition -\***********************************************************************/ - - - -/*************************************************************************\ - * Registers Definition -\*************************************************************************/ - -#define CONTROL_REVISION (0x0) -#define CONTROL_HWINFO (0x4) -#define CONTROL_SYSCONFIG (0x10) -#define CONTROL_STATUS (0x40) -#define CONTROL_BOOTSTAT (0x44) -#define CONTROL_SEC_CTRL (0x100) -#define CONTROL_SEC_SW (0x104) -#define CONTROL_SEC_EMU (0x108) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG (0x110) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2 (0x114) -#define CONTROL_SW_CFG (0x118) -#define CONTROL_SW_CCFG (0x11c) -#define CONTROL_MPK(n) (0x120 + (n * 4)) -#define CONTROL_SWRV(n) (0x140 + (n * 4)) -#define CONTROL_SEC_TAP (0x180) -#define CONTROL_SEC_TAP_CMDIN (0x184) -#define CONTROL_SEC_TAP_CMDOUT (0x188) -#define CONTROL_SEC_TAP_DATIN (0x18c) -#define CONTROL_SEC_TAP_DATOUT (0x190) -#define CONTROL_MREQDOMAIN_EXP1 (0x198) -#define CONTROL_MREQDOMAIN_EXP2 (0x19c) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0 (0x1a0) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1 (0x1a4) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF (0x1a8) -#define CONTROL_SEC_LOAD_FW_EXP_VAL (0x1ac) -#define CONTROL_SEC_CTRL_RO (0x1b4) -#define CONTROL_EMIF_OBFUSCATION_KEY (0x1b8) -#define CONTROL_SEC_CLK_CTRL (0x1bc) -#define CONTROL_MREQDOMAIN_EXP3 (0x1d4) -#define CONTROL_CEK(n) (0x200 + (n * 4)) -#define CONTROL_CEK_BCH(n) (0x210 + (n * 4)) -#define CONTROL_MSV_0 (0x224) -#define CONTROL_MSV_BCH(n) (0x228 + (n * 4)) -#define CONTROL_SEC_STATUS (0x240) -#define CONTROL_SECMEM_STATUS (0x244) -#define CONTROL_SEC_ERR_STAT_FUNC(n) (0x248 + (n * 4)) -#define CONTROL_SEC_ERR_STAT_DBUG(n) (0x250 + (n * 4)) -#define CONTROL_KEK_SW(n) (0x260 + (n * 4)) -#define CONTROL_CMPK_BCH(n) (0x280 + (n * 4)) -#define CONTROL_CMPK(n) (0x2b0 + (n * 4)) -#define CONTROL_SSM_END_FAST_SECRAM (0x300) -#define CONTROL_SSM_FIREWALL_CONTROLLER (0x304) -#define CONTROL_SSM_START_SECURE_STACKED_RAM (0x308) -#define CONTROL_SSM_END_SECURE_STACKED_RAM (0x30c) -#define CONTROL_SSM_START_SPM_STACK (0x310) -#define CONTROL_SSM_END_SPM_STACK (0x314) -#define CONTROL_SSM_START_MONITOR_RAMCODE (0x318) -#define CONTROL_SSM_END_MONITOR_RAMCODE (0x31c) -#define CONTROL_SSM_END_MONITOR_RAMDATA (0x320) -#define CONTROL_SSM_START_MONITOR_CODE (0x324) -#define CONTROL_SSM_END_MONITOR_CODE (0x328) -#define CONTROL_SSM_START_MONITOR_PERIPH (0x32c) -#define CONTROL_SSM_END_MONITOR_PERIPH (0x330) -#define CONTROL_SSM_START_MONITOR_STACK (0x334) -#define CONTROL_SSM_END_MONITOR_STACK (0x338) -#define CONTROL_SSM_START_MONITOR_RAMCODE_ETM (0x33c) -#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM (0x340) -#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM (0x344) -#define CONTROL_SSM_START_MONITOR_CODE_ETM (0x348) -#define CONTROL_SSM_END_MONITOR_CODE_ETM (0x34c) -#define CONTROL_SSM_START_MONITOR_STACK_ETM (0x350) -#define CONTROL_SSM_END_MONITOR_STACK_ETM (0x354) -#define CONTROL_SSM_START_MONITOR_SHARED_ETM (0x358) -#define CONTROL_SSM_END_MONITOR_SHARED_ETM (0x35c) -#define CONTROL_SSM_START_MONITOR_PERIPH_ETM (0x360) -#define CONTROL_SSM_END_MONITOR_PERIPH_ETM (0x364) -#define CONTROL_SSM_CPSR_MODE_ENFC (0x368) -#define CONTROL_SSM_END_L3_SECRAM (0x36c) -#define CONTROL_CORTEX_VBBLDO_CTRL (0x41c) -#define CONTROL_CORE_SLDO_CTRL (0x428) -#define CONTROL_MPU_SLDO_CTRL (0x42c) -#define CONTROL_REFCLK_LJCBLDO_CTRL (0x440) -#define CONTROL_CLK32KDIVRATIO_CTRL (0x444) -#define CONTROL_BANDGAP_CTRL (0x448) -#define CONTROL_BANDGAP_TRIM (0x44c) -#define CONTROL_PLL_CLKINPULOW_CTRL (0x458) -#define CONTROL_MOSC_CTRL (0x468) -#define CONTROL_RCOSC_CTRL (0x46c) -#define CONTROL_DEEPSLEEP_CTRL (0x470) -#define CONTROL_PE_SCRATCHPAD(n) (0x500 + (n * 4)) -#define CONTROL_DEVICE_ID (0x600) -#define CONTROL_DEV_FEATURE (0x604) -#define CONTROL_INIT_PRIORITY(n) (0x608 + (n * 4)) -#define CONTROL_MMU_CFG (0x610) -#define CONTROL_TPTC_CFG (0x614) -#define CONTROL_OCMC_CFG (0x618) -#define CONTROL_USB_CTRL(n) (0x620 + (n * 8)) -#define CONTROL_USB_STS(n) (0x624 + (n * 8)) -#define CONTROL_MAC_ID_LO(n) (0x630 + (n * 8)) -#define CONTROL_MAC_ID_HI(n) (0x634 + (n * 8)) -#define CONTROL_DCAN_RAMINIT (0x644) -#define CONTROL_USB_WKUP_CTRL (0x648) -#define CONTROL_GMII_SEL (0x650) -#define CONTROL_PWMSS_CTRL (0x664) -#define CONTROL_MREQPRIO(n) (0x670 + (n * 4)) -#define CONTROL_HW_EVENT_SEL_GRP(n) (0x690 + (n * 4)) -#define CONTROL_SMRT_CTRL (0x6a0) -#define CONTROL_SABTOOTH_HW_DEBUG_SEL (0x6a4) -#define CONTROL_SABTOOTH_HW_DBG_INFO (0x6a8) -#define CONTROL_MRGN_MODE(n) (0x6c0 + (n * 4)) -#define CONTROL_VDD_MPU_OPP(n) (0x770 + (n * 4)) -#define CONTROL_VDD_MPU_OPP_TURBO (0x77c) -#define CONTROL_VDD_CORE_OPP(n) (0x7b8 + (n * 4)) -#define CONTROL_BB_SCALE (0x7d0) -#define CONTROL_USB_VID_PID (0x7f4) -#define CONTROL_EFUSE_SMA (0x7fc) -#define CONTROL_CONF_GPMC_AD(n) (0x800 + (n * 4)) -#define CONTROL_CONF_GPMC_A(n) (0x840 + (n * 4)) -#define CONTROL_CONF_GPMC_WAIT0 (0x870) -#define CONTROL_CONF_GPMC_WPN (0x874) -#define CONTROL_CONF_GPMC_BE1N (0x878) -#define CONTROL_CONF_GPMC_CSN(n) (0x87c + (n * 4)) -#define CONTROL_CONF_GPMC_CLK (0x88c) -#define CONTROL_CONF_GPMC_ADVN_ALE (0x890) -#define CONTROL_CONF_GPMC_OEN_REN (0x894) -#define CONTROL_CONF_GPMC_WEN (0x898) -#define CONTROL_CONF_GPMC_BE0N_CLE (0x89c) -#define CONTROL_CONF_LCD_DATA(n) (0x8a0 + (n * 4)) -#define CONTROL_CONF_LCD_VSYNC (0x8e0) -#define CONTROL_CONF_LCD_HSYNC (0x8e4) -#define CONTROL_CONF_LCD_PCLK (0x8e8) -#define CONTROL_CONF_LCD_AC_BIAS_EN (0x8ec) -#define CONTROL_CONF_MMC0_DAT3 (0x8f0) -#define CONTROL_CONF_MMC0_DAT2 (0x8f4) -#define CONTROL_CONF_MMC0_DAT1 (0x8f8) -#define CONTROL_CONF_MMC0_DAT0 (0x8fc) -#define CONTROL_CONF_MMC0_CLK (0x900) -#define CONTROL_CONF_MMC0_CMD (0x904) -#define CONTROL_CONF_MII1_COL (0x908) -#define CONTROL_CONF_MII1_CRS (0x90c) -#define CONTROL_CONF_MII1_RXERR (0x910) -#define CONTROL_CONF_MII1_TXEN (0x914) -#define CONTROL_CONF_MII1_RXDV (0x918) -#define CONTROL_CONF_MII1_TXD3 (0x91c) -#define CONTROL_CONF_MII1_TXD2 (0x920) -#define CONTROL_CONF_MII1_TXD1 (0x924) -#define CONTROL_CONF_MII1_TXD0 (0x928) -#define CONTROL_CONF_MII1_TXCLK (0x92c) -#define CONTROL_CONF_MII1_RXCLK (0x930) -#define CONTROL_CONF_MII1_RXD3 (0x934) -#define CONTROL_CONF_MII1_RXD2 (0x938) -#define CONTROL_CONF_MII1_RXD1 (0x93c) -#define CONTROL_CONF_MII1_RXD0 (0x940) -#define CONTROL_CONF_RMII1_REFCLK (0x944) -#define CONTROL_CONF_MDIO_DATA (0x948) -#define CONTROL_CONF_MDIO_CLK (0x94c) -#define CONTROL_CONF_SPI0_SCLK (0x950) -#define CONTROL_CONF_SPI0_D0 (0x954) -#define CONTROL_CONF_SPI0_D1 (0x958) -#define CONTROL_CONF_SPI0_CS0 (0x95c) -#define CONTROL_CONF_SPI0_CS1 (0x960) -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT (0x964) -#define CONTROL_CONF_UART_CTSN(n) (0x968 + ((n) * 0x10)) -#define CONTROL_CONF_UART_RTSN(n) (0x96c + ((n) * 0x10)) -#define CONTROL_CONF_UART_RXD(n) (0x970 + ((n) * 0x10)) -#define CONTROL_CONF_UART_TXD(n) (0x974 + ((n) * 0x10)) -#define CONTROL_CONF_I2C0_SDA (0x988) -#define CONTROL_CONF_I2C0_SCL (0x98c) -#define CONTROL_CONF_MCASP0_ACLKX (0x990) -#define CONTROL_CONF_MCASP0_FSX (0x994) -#define CONTROL_CONF_MCASP0_AXR0 (0x998) -#define CONTROL_CONF_MCASP0_AHCLKR (0x99c) -#define CONTROL_CONF_MCASP0_ACLKR (0x9a0) -#define CONTROL_CONF_MCASP0_FSR (0x9a4) -#define CONTROL_CONF_MCASP0_AXR1 (0x9a8) -#define CONTROL_CONF_MCASP0_AHCLKX (0x9ac) -#define CONTROL_CONF_XDMA_EVENT_INTR(n) (0x9b0 + (n * 4)) -#define CONTROL_CONF_NRESETIN_OUT (0x9b8) -#define CONTROL_CONF_PORZ (0x9bc) -#define CONTROL_CONF_NNMI (0x9c0) -#define CONTROL_CONF_OSC_IN(n) (0x9c4 + (n * 0x24)) -#define CONTROL_CONF_OSC_OUT(n) (0x9c8 + (n * 0x24)) -#define CONTROL_CONF_OSC_VSS(n) (0x9cc + (n * 0x24)) -#define CONTROL_CONF_TMS (0x9d0) -#define CONTROL_CONF_TDI (0x9d4) -#define CONTROL_CONF_TDO (0x9d8) -#define CONTROL_CONF_TCK (0x9dc) -#define CONTROL_CONF_NTRST (0x9e0) -#define CONTROL_CONF_EMU(n) (0x9e4 + (n * 4)) -#define CONTROL_CONF_RTC_PORZ (0x9f8) -#define CONTROL_CONF_PMIC_POWER_EN (0x9fc) -#define CONTROL_CONF_EXT_WAKEUP (0xa00) -#define CONTROL_CONF_ENZ_KALDO_1P8V (0xa04) -#define CONTROL_CONF_USB_DM(n) (0xa08 + ((n) * 0x18)) -#define CONTROL_CONF_USB_DP(n) (0xa0c + ((n) * 0x18)) -#define CONTROL_CONF_USB_CE(n) (0xa10 + ((n) * 0x18)) -#define CONTROL_CONF_USB_ID(n) (0xa14 + ((n) * 0x18)) -#define CONTROL_CONF_USB_VBUS(n) (0xa18 + ((n) * 0x18)) -#define CONTROL_CONF_USB_DRVVBUS(n) (0xa1c + ((n) * 0x18)) -#define CONTROL_CONF_DDR_RESETN (0xa38) -#define CONTROL_CONF_DDR_CSN0 (0xa3c) -#define CONTROL_CONF_DDR_CKE (0xa40) -#define CONTROL_CONF_DDR_CK (0xa44) -#define CONTROL_CONF_DDR_NCK (0xa48) -#define CONTROL_CONF_DDR_CASN (0xa4c) -#define CONTROL_CONF_DDR_RASN (0xa50) -#define CONTROL_CONF_DDR_WEN (0xa54) -#define CONTROL_CONF_DDR_BA(n) (0xa58 + (n * 4)) -#define CONTROL_CONF_DDR_A(n) (0xa64 + (n * 4)) -#define CONTROL_CONF_DDR_ODT (0xaa4) -#define CONTROL_CONF_DDR_D(n) (0xaa8 + (n * 4)) -#define CONTROL_CONF_DDR_DQM(n) (0xae8 + (n * 4)) -#define CONTROL_CONF_DDR_DQS(n) (0xaf0 + (n * 8)) -#define CONTROL_CONF_DDR_DQSN(n) (0xaf4 + (n * 8)) -#define CONTROL_CONF_DDR_VREF (0xb00) -#define CONTROL_CONF_DDR_VTP (0xb04) -#define CONTROL_CONF_DDR_STRBEN(n) (0xb08 + (n * 4)) -#define CONTROL_CONF_AIN0 (0xb2c) -#define CONTROL_CONF_AIN1 (0xb28) -#define CONTROL_CONF_AIN2 (0xb24) -#define CONTROL_CONF_AIN3 (0xb20) -#define CONTROL_CONF_AIN4 (0xb1c) -#define CONTROL_CONF_AIN5 (0xb18) -#define CONTROL_CONF_AIN6 (0xb14) -#define CONTROL_CONF_AIN7 (0xb10) -#define CONTROL_CONF_VREFP (0xb30) -#define CONTROL_CONF_VREFN (0xb34) -#define CONTROL_CONF_AVDD (0xb38) -#define CONTROL_CONF_AVSS (0xb3c) -#define CONTROL_CONF_IFORCE (0xb40) -#define CONTROL_CONF_VSENSE (0xb44) -#define CONTROL_CONF_TESTOUT (0xb48) -#define CONTROL_CQDETECT_STATUS (0xe00) -#define CONTROL_DDR_IO_CTRL (0xe04) -#define CONTROL_VTP_CTRL (0xe0c) -#define CONTROL_VREF_CTRL (0xe14) -#define CONTROL_SERDES_REFCLK_CTL (0xe24) -#define CONTROL_TPCC_EVT_MUX_0_3 (0xf90) -#define CONTROL_TPCC_EVT_MUX_4_7 (0xf94) -#define CONTROL_TPCC_EVT_MUX_8_11 (0xf98) -#define CONTROL_TPCC_EVT_MUX_12_15 (0xf9c) -#define CONTROL_TPCC_EVT_MUX_16_19 (0xfa0) -#define CONTROL_TPCC_EVT_MUX_20_23 (0xfa4) -#define CONTROL_TPCC_EVT_MUX_24_27 (0xfa8) -#define CONTROL_TPCC_EVT_MUX_28_31 (0xfac) -#define CONTROL_TPCC_EVT_MUX_32_35 (0xfb0) -#define CONTROL_TPCC_EVT_MUX_36_39 (0xfb4) -#define CONTROL_TPCC_EVT_MUX_40_43 (0xfb8) -#define CONTROL_TPCC_EVT_MUX_44_47 (0xfbc) -#define CONTROL_TPCC_EVT_MUX_48_51 (0xfc0) -#define CONTROL_TPCC_EVT_MUX_52_55 (0xfc4) -#define CONTROL_TPCC_EVT_MUX_56_59 (0xfc8) -#define CONTROL_TPCC_EVT_MUX_60_63 (0xfcc) -#define CONTROL_TIMER_EVT_CAPT (0xfd0) -#define CONTROL_ECAP_EVT_CAPT (0xfd4) -#define CONTROL_ADC_EVT_CAPT (0xfd8) -#define CONTROL_RESET_ISO (0x1000) -#define CONTROL_SMA(n) (0x1318 + (n * 8)) -#define CONTROL_DDR_CKE_CTRL (0x131c) -#define CONTROL_M3_TXEV_EOI (0x1324) -#define CONTROL_IPC_MSG_REG(n) (0x1328 + (n * 4)) -#define CONTROL_DDR_CMD_IOCTRL(n) (0x1404 + (n * 4)) -#define CONTROL_DDR_DATA_IOCTRL(n) (0x1440 + (n * 4)) - - -#define CONTROL_CONF_PULLUDDISABLE 0x00000008 -#define CONTROL_CONF_PULLUPSEL 0x00000010 -#define CONTROL_CONF_RXACTIVE 0x00000020 -#define CONTROL_CONF_SLOWSLEW 0x00000040 -#define CONTROL_CONF_MUXMODE(n) (n) - - -/**************************************************************************\ - * Field Definition Macros -\**************************************************************************/ - -/* CONTROL_REVISION */ -#define CONTROL_REVISION_IP_REV_CUSTOM (0x000000C0u) -#define CONTROL_REVISION_IP_REV_CUSTOM_SHIFT (0x00000006u) - -#define CONTROL_REVISION_IP_REV_FUNC (0x0FFF0000u) -#define CONTROL_REVISION_IP_REV_FUNC_SHIFT (0x00000010u) - -#define CONTROL_REVISION_IP_REV_MAJOR (0x00000700u) -#define CONTROL_REVISION_IP_REV_MAJOR_SHIFT (0x00000008u) - -#define CONTROL_REVISION_IP_REV_MINOR (0x0000003Fu) -#define CONTROL_REVISION_IP_REV_MINOR_SHIFT (0x00000000u) - -#define CONTROL_REVISION_IP_REV_RTL (0x0000F800u) -#define CONTROL_REVISION_IP_REV_RTL_SHIFT (0x0000000Bu) - -#define CONTROL_REVISION_IP_REV_SCHEME (0xC0000000u) -#define CONTROL_REVISION_IP_REV_SCHEME_SHIFT (0x0000001Eu) - - -/* CONTROL_HWINFO */ -#define CONTROL_HWINFO_IP_HWINFO (0xFFFFFFFFu) -#define CONTROL_HWINFO_IP_HWINFO_SHIFT (0x00000000u) - - -/* CONTROL_SYSCONFIG */ -#define CONTROL_SYSCONFIG_FREEEMU (0x00000002u) -#define CONTROL_SYSCONFIG_FREEEMU_SHIFT (0x00000001u) - -#define CONTROL_SYSCONFIG_IDLEMODE (0x0000000Cu) -#define CONTROL_SYSCONFIG_IDLEMODE_SHIFT (0x00000002u) - -#define CONTROL_SYSCONFIG_RSVD2 (0xFFFFFFC0u) -#define CONTROL_SYSCONFIG_RSVD2_SHIFT (0x00000006u) - -#define CONTROL_SYSCONFIG_STANDBY (0x00000030u) -#define CONTROL_SYSCONFIG_STANDBY_SHIFT (0x00000004u) - - -/* CONTROL_STATUS */ -#define CONTROL_STATUS_ADMUX (0x000C0000u) -#define CONTROL_STATUS_ADMUX_SHIFT (0x00000012u) - -#define CONTROL_STATUS_BW (0x00010000u) -#define CONTROL_STATUS_BW_SHIFT (0x00000010u) - -#define CONTROL_STATUS_DEVTYPE (0x00000700u) -#define CONTROL_STATUS_DEVTYPE_SHIFT (0x00000008u) - -#define CONTROL_STATUS_RSVD2 (0xFF000000u) -#define CONTROL_STATUS_RSVD2_SHIFT (0x00000018u) - -#define CONTROL_STATUS_SYSBOOT0 (0x000000FFu) -#define CONTROL_STATUS_SYSBOOT0_SHIFT (0x00000000u) - -#define CONTROL_STATUS_SYSBOOT1 (0x00C00000u) -#define CONTROL_STATUS_SYSBOOT1_SHIFT (0x00000016u) - -#define CONTROL_STATUS_TESTMD (0x00300000u) -#define CONTROL_STATUS_TESTMD_SHIFT (0x00000014u) - -#define CONTROL_STATUS_WAITEN (0x00020000u) -#define CONTROL_STATUS_WAITEN_SHIFT (0x00000011u) - - -/* BOOTSTAT */ -#define CONTROL_BOOTSTAT_BC (0x00000001u) -#define CONTROL_BOOTSTAT_BC_SHIFT (0x00000000u) - -#define CONTROL_BOOTSTAT_BOOTERR (0x000F0000u) -#define CONTROL_BOOTSTAT_BOOTERR_SHIFT (0x00000010u) - -#define CONTROL_BOOTSTAT_RSVD2 (0xFFF00000u) -#define CONTROL_BOOTSTAT_RSVD2_SHIFT (0x00000014u) - - -/* CONTROL_SEC_CTRL */ -#define CONTROL_SEC_CTRL_BSCENABLE (0x00000200u) -#define CONTROL_SEC_CTRL_BSCENABLE_SHIFT (0x00000009u) - -#define CONTROL_SEC_CTRL_CATSCANEN (0x00000100u) -#define CONTROL_SEC_CTRL_CATSCANEN_SHIFT (0x00000008u) - -#define CONTROL_SEC_CTRL_CMPKEFUSENOTDEC (0x00002000u) -#define CONTROL_SEC_CTRL_CMPKEFUSENOTDEC_SHIFT (0x0000000Du) - -#define CONTROL_SEC_CTRL_CPEFUSELDDONE (0x00000400u) -#define CONTROL_SEC_CTRL_CPEFUSELDDONE_SHIFT (0x0000000Au) - -#define CONTROL_SEC_CTRL_CPEFUSENOTDEC (0x00001000u) -#define CONTROL_SEC_CTRL_CPEFUSENOTDEC_SHIFT (0x0000000Cu) - -#define CONTROL_SEC_CTRL_CPEFUSEWRDIS (0x00000800u) -#define CONTROL_SEC_CTRL_CPEFUSEWRDIS_SHIFT (0x0000000Bu) - -#define CONTROL_SEC_CTRL_DMLEDCOREEN (0x00000080u) -#define CONTROL_SEC_CTRL_DMLEDCOREEN_SHIFT (0x00000007u) - -#define CONTROL_SEC_CTRL_FASTOCMSECSAVE (0x30000000u) -#define CONTROL_SEC_CTRL_FASTOCMSECSAVE_SHIFT (0x0000001Cu) - -#define CONTROL_SEC_CTRL_KEKSWENABLE0 (0x00000004u) -#define CONTROL_SEC_CTRL_KEKSWENABLE0_SHIFT (0x00000002u) - -#define CONTROL_SEC_CTRL_KEKSWENABLE1 (0x00000010u) -#define CONTROL_SEC_CTRL_KEKSWENABLE1_SHIFT (0x00000004u) - -#define CONTROL_SEC_CTRL_L3OCMSECSAVE (0x0C000000u) -#define CONTROL_SEC_CTRL_L3OCMSECSAVE_SHIFT (0x0000001Au) - -#define CONTROL_SEC_CTRL_RSVD2 (0x00000060u) -#define CONTROL_SEC_CTRL_RSVD2_SHIFT (0x00000005u) - -#define CONTROL_SEC_CTRL_SECCTRLWRDISABLE (0x80000000u) -#define CONTROL_SEC_CTRL_SECCTRLWRDISABLE_SHIFT (0x0000001Fu) - -#define CONTROL_SEC_CTRL_SECUREMODEINITDONE (0x40000000u) -#define CONTROL_SEC_CTRL_SECUREMODEINITDONE_SHIFT (0x0000001Eu) - -#define CONTROL_SEC_CTRL_WDOPDISABLE (0x00000001u) -#define CONTROL_SEC_CTRL_WDOPDISABLE_SHIFT (0x00000000u) - -#define CONTROL_SEC_CTRL_WDREGENABLE (0x00000002u) -#define CONTROL_SEC_CTRL_WDREGENABLE_SHIFT (0x00000001u) - - -/* CONTROL_SEC_SW */ -#define CONTROL_SEC_SW_SW_HW_PARAMETERS (0xFFFFFFFFu) -#define CONTROL_SEC_SW_SW_HW_PARAMETERS_SHIFT (0x00000000u) - - -/* CONTROL_SEC_EMU */ -#define CONTROL_SEC_EMU_ETMSECPRIVDBGEN (0x00001000u) -#define CONTROL_SEC_EMU_ETMSECPRIVDBGEN_SHIFT (0x0000000Cu) - -#define CONTROL_SEC_EMU_GENDBGEN (0x00000FFFu) -#define CONTROL_SEC_EMU_GENDBGEN_SHIFT (0x00000000u) - -#define CONTROL_SEC_EMU_GENDBGEN_M3 (0x0000C000u) -#define CONTROL_SEC_EMU_GENDBGEN_M3_SHIFT (0x0000000Eu) - -#define CONTROL_SEC_EMU_ICESECPRIVDBGEN (0x00002000u) -#define CONTROL_SEC_EMU_ICESECPRIVDBGEN_SHIFT (0x0000000Du) - -#define CONTROL_SEC_EMU_SECEMUWRDIS (0x80000000u) -#define CONTROL_SEC_EMU_SECEMUWRDIS_SHIFT (0x0000001Fu) - - -/* SECURE_EMIF_SDRAM_CONFIG */ -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CL (0x00003C00u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CL_SHIFT (0x0000000Au) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CWL (0x00030000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CWL_SHIFT (0x00000010u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DDR_TERM (0x07000000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DDR_TERM_SHIFT (0x00000018u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DYN_ODT (0x00600000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DYN_ODT_SHIFT (0x00000015u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_EBANK (0x00000008u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_EBANK_SHIFT (0x00000003u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK (0x00000070u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK_SHIFT (0x00000004u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK_POS (0x18000000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK_POS_SHIFT (0x0000001Bu) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_NARROW_MODE (0x0000C000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_NARROW_MODE_SHIFT (0x0000000Eu) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_PAGESIZE (0x00000007u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_PAGESIZE_SHIFT (0x00000000u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_ROWSIZE (0x00000380u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_ROWSIZE_SHIFT (0x00000007u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_RSVD2 (0x00800000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_RSVD2_SHIFT (0x00000017u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_DRIVE (0x000C0000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_DRIVE_SHIFT (0x00000012u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_TYPE (0xE0000000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_TYPE_SHIFT (0x0000001Du) - - -/* SECURE_EMIF_SDRAM_CONFIG_2 */ -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_CS1_NVMEN (0x40000000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_CS1_NVMEN_SHIFT (0x0000001Eu) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_EBANK_POS (0x08000000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_EBANK_POS_SHIFT (0x0000001Bu) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBNUM (0x00000030u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBNUM_SHIFT (0x00000004u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBSIZE (0x00000007u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBSIZE_SHIFT (0x00000000u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD2 (0x07FFFFC0u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD2_SHIFT (0x00000006u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD3 (0x30000000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD3_SHIFT (0x0000001Cu) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD4 (0x80000000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD4_SHIFT (0x0000001Fu) - - -/* CONTROL_SW_CFG */ -#define CONTROL_SW_CFG_SW_CFG (0xFFFFFFFFu) -#define CONTROL_SW_CFG_SW_CFG_SHIFT (0x00000000u) - - -/* CONTROL_SW_CCFG */ -#define CONTROL_SW_CCFG_SW_CCFG (0x0000FFFFu) -#define CONTROL_SW_CCFG_SW_CCFG_SHIFT (0x00000000u) - -#define CONTROL_SW_CCFG_SW_CCFG_RED (0xFFFF0000u) -#define CONTROL_SW_CCFG_SW_CCFG_RED_SHIFT (0x00000010u) - - -/* CONTROL_MPK_0 */ -#define CONTROL_MPK_0_MPK (0xFFFFFFFFu) -#define CONTROL_MPK_0_MPK_SHIFT (0x00000000u) - - -/* CONTROL_MPK_1 */ -#define CONTROL_MPK_1_MPK (0xFFFFFFFFu) -#define CONTROL_MPK_1_MPK_SHIFT (0x00000000u) - - -/* CONTROL_MPK_2 */ -#define CONTROL_MPK_2_MPK (0xFFFFFFFFu) -#define CONTROL_MPK_2_MPK_SHIFT (0x00000000u) - - -/* CONTROL_MPK_3 */ -#define CONTROL_MPK_3_MPK (0xFFFFFFFFu) -#define CONTROL_MPK_3_MPK_SHIFT (0x00000000u) - - -/* CONTROL_MPK_4 */ -#define CONTROL_MPK_4_MPK (0xFFFFFFFFu) -#define CONTROL_MPK_4_MPK_SHIFT (0x00000000u) - - -/* CONTROL_MPK_5 */ -#define CONTROL_MPK_5_MPK (0xFFFFFFFFu) -#define CONTROL_MPK_5_MPK_SHIFT (0x00000000u) - - -/* CONTROL_MPK_6 */ -#define CONTROL_MPK_6_MPK (0xFFFFFFFFu) -#define CONTROL_MPK_6_MPK_SHIFT (0x00000000u) - - -/* CONTROL_MPK_7 */ -#define CONTROL_MPK_7_MPK (0xFFFFFFFFu) -#define CONTROL_MPK_7_MPK_SHIFT (0x00000000u) - - -/* CONTROL_SWRV_0 */ -#define CONTROL_SWRV_0_SWRV (0x0000FFFFu) -#define CONTROL_SWRV_0_SWRV_SHIFT (0x00000000u) - -#define CONTROL_SWRV_0_SWRV_RED (0xFFFF0000u) -#define CONTROL_SWRV_0_SWRV_RED_SHIFT (0x00000010u) - - -/* CONTROL_SWRV_1 */ -#define CONTROL_SWRV_1_SWRV (0x0000FFFFu) -#define CONTROL_SWRV_1_SWRV_SHIFT (0x00000000u) - -#define CONTROL_SWRV_1_SWRV_RED (0xFFFF0000u) -#define CONTROL_SWRV_1_SWRV_RED_SHIFT (0x00000010u) - - -/* CONTROL_SWRV_2 */ -#define CONTROL_SWRV_2_SWRV (0x0000FFFFu) -#define CONTROL_SWRV_2_SWRV_SHIFT (0x00000000u) - -#define CONTROL_SWRV_2_SWRV_RED (0xFFFF0000u) -#define CONTROL_SWRV_2_SWRV_RED_SHIFT (0x00000010u) - - -/* CONTROL_SWRV_3 */ -#define CONTROL_SWRV_3_SWRV (0x0000FFFFu) -#define CONTROL_SWRV_3_SWRV_SHIFT (0x00000000u) - -#define CONTROL_SWRV_3_SWRV_RED (0xFFFF0000u) -#define CONTROL_SWRV_3_SWRV_RED_SHIFT (0x00000010u) - - -/* CONTROL_SWRV_4 */ -#define CONTROL_SWRV_4_SWRV (0x0000FFFFu) -#define CONTROL_SWRV_4_SWRV_SHIFT (0x00000000u) - -#define CONTROL_SWRV_4_SWRV_RED (0xFFFF0000u) -#define CONTROL_SWRV_4_SWRV_RED_SHIFT (0x00000010u) - - -/* CONTROL_SWRV_5 */ -#define CONTROL_SWRV_5_SWRV (0x0000FFFFu) -#define CONTROL_SWRV_5_SWRV_SHIFT (0x00000000u) - -#define CONTROL_SWRV_5_SWRV_RED (0xFFFF0000u) -#define CONTROL_SWRV_5_SWRV_RED_SHIFT (0x00000010u) - - -/* CONTROL_SWRV_6 */ -#define CONTROL_SWRV_6_SWRV (0x0000FFFFu) -#define CONTROL_SWRV_6_SWRV_SHIFT (0x00000000u) - -#define CONTROL_SWRV_6_SWRV_RED (0xFFFF0000u) -#define CONTROL_SWRV_6_SWRV_RED_SHIFT (0x00000010u) - - -/* CONTROL_SEC_TAP */ -#define CONTROL_SEC_TAP_1500EN (0x00000008u) -#define CONTROL_SEC_TAP_1500EN_SHIFT (0x00000003u) - -#define CONTROL_SEC_TAP_DAPTAPEN (0x00000001u) -#define CONTROL_SEC_TAP_DAPTAPEN_SHIFT (0x00000000u) - -#define CONTROL_SEC_TAP_PART1500DIS (0x00000010u) -#define CONTROL_SEC_TAP_PART1500DIS_SHIFT (0x00000004u) - -#define CONTROL_SEC_TAP_RSVD2 (0x000001E0u) -#define CONTROL_SEC_TAP_RSVD2_SHIFT (0x00000005u) - -#define CONTROL_SEC_TAP_RSVD3 (0x7FFFFC00u) -#define CONTROL_SEC_TAP_RSVD3_SHIFT (0x0000000Au) - -#define CONTROL_SEC_TAP_SABERMPUTAPEN (0x00000200u) -#define CONTROL_SEC_TAP_SABERMPUTAPEN_SHIFT (0x00000009u) - -#define CONTROL_SEC_TAP_SECTAPWRDISABLE (0x80000000u) -#define CONTROL_SEC_TAP_SECTAPWRDISABLE_SHIFT (0x0000001Fu) - -#define CONTROL_SEC_TAP_WAKEUPTAPEN (0x00000004u) -#define CONTROL_SEC_TAP_WAKEUPTAPEN_SHIFT (0x00000002u) - - -/* CONTROL_SEC_TAP_CMDIN */ -#define CONTROL_SEC_TAP_CMDIN_CMDIN (0x000000FFu) -#define CONTROL_SEC_TAP_CMDIN_CMDIN_SHIFT (0x00000000u) - - -/* CONTROL_SEC_TAP_CMDOUT */ -#define CONTROL_SEC_TAP_CMDOUT_CMDOUT (0x000000FFu) -#define CONTROL_SEC_TAP_CMDOUT_CMDOUT_SHIFT (0x00000000u) - - -/* CONTROL_SEC_TAP_DATIN */ -#define CONTROL_SEC_TAP_DATIN_DATAIN (0x000000FFu) -#define CONTROL_SEC_TAP_DATIN_DATAIN_SHIFT (0x00000000u) - - -/* CONTROL_SEC_TAP_DATOUT */ -#define CONTROL_SEC_TAP_DATOUT_DATAOUT (0x000000FFu) -#define CONTROL_SEC_TAP_DATOUT_DATAOUT_SHIFT (0x00000000u) - - -/* CONTROL_MREQDOMAIN_EXP1 */ -#define CONTROL_MREQDOMAIN_EXP1_2DBITBLT_DOM (0x001C0000u) -#define CONTROL_MREQDOMAIN_EXP1_2DBITBLT_DOM_SHIFT (0x00000012u) - -#define CONTROL_MREQDOMAIN_EXP1_L3_EXP_DOM (0x00000007u) -#define CONTROL_MREQDOMAIN_EXP1_L3_EXP_DOM_SHIFT (0x00000000u) - -#define CONTROL_MREQDOMAIN_EXP1_LCD_CTRL_DOM (0x00038000u) -#define CONTROL_MREQDOMAIN_EXP1_LCD_CTRL_DOM_SHIFT (0x0000000Fu) - -#define CONTROL_MREQDOMAIN_EXP1_LCK (0x80000000u) -#define CONTROL_MREQDOMAIN_EXP1_LCK_SHIFT (0x0000001Fu) - -#define CONTROL_MREQDOMAIN_EXP1_MLB_DOM (0x00007000u) -#define CONTROL_MREQDOMAIN_EXP1_MLB_DOM_SHIFT (0x0000000Cu) - -#define CONTROL_MREQDOMAIN_EXP1_RSVD2 (0x78000000u) -#define CONTROL_MREQDOMAIN_EXP1_RSVD2_SHIFT (0x0000001Bu) - -#define CONTROL_MREQDOMAIN_EXP1_SGX_DOM (0x07000000u) -#define CONTROL_MREQDOMAIN_EXP1_SGX_DOM_SHIFT (0x00000018u) - -#define CONTROL_MREQDOMAIN_EXP1_WAKE_DOM (0x00E00000u) -#define CONTROL_MREQDOMAIN_EXP1_WAKE_DOM_SHIFT (0x00000015u) - - -/* CONTROL_MREQDOMAIN_EXP2 */ -#define CONTROL_MREQDOMAIN_EXP2_GEMAC_DOM (0x001C0000u) -#define CONTROL_MREQDOMAIN_EXP2_GEMAC_DOM_SHIFT (0x00000012u) - -#define CONTROL_MREQDOMAIN_EXP2_LCK (0x80000000u) -#define CONTROL_MREQDOMAIN_EXP2_LCK_SHIFT (0x0000001Fu) - -#define CONTROL_MREQDOMAIN_EXP2_P1500_DOM (0x00038000u) -#define CONTROL_MREQDOMAIN_EXP2_P1500_DOM_SHIFT (0x0000000Fu) - -#define CONTROL_MREQDOMAIN_EXP2_RSVD2 (0x7FE00000u) -#define CONTROL_MREQDOMAIN_EXP2_RSVD2_SHIFT (0x00000015u) - -#define CONTROL_MREQDOMAIN_EXP2_USB0_DOM (0x00000E00u) -#define CONTROL_MREQDOMAIN_EXP2_USB0_DOM_SHIFT (0x00000009u) - -#define CONTROL_MREQDOMAIN_EXP2_USB1_DOM (0x00007000u) -#define CONTROL_MREQDOMAIN_EXP2_USB1_DOM_SHIFT (0x0000000Cu) - - -/* L3_HW_FW_EXP_VAL_CONF0 */ -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECDBG_EN (0x00040000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECDBG_EN_SHIFT (0x00000012u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECLOCK_EN (0x00000004u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECLOCK_EN_SHIFT (0x00000002u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECDBG_EN (0x01000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECDBG_EN_SHIFT (0x00000018u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECLOCK_EN (0x00000100u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECLOCK_EN_SHIFT (0x00000008u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD2 (0x00000020u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD2_SHIFT (0x00000005u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD3 (0x00000200u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD3_SHIFT (0x00000009u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD4 (0x0003F800u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD4_SHIFT (0x0000000Bu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD5 (0x00200000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD5_SHIFT (0x00000015u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD6 (0x02000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD6_SHIFT (0x00000019u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD7 (0xF8000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD7_SHIFT (0x0000001Bu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECDBG_EN (0x00800000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECDBG_EN_SHIFT (0x00000017u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECLOCK_EN (0x00000080u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECLOCK_EN_SHIFT (0x00000007u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECDBG_EN (0x00100000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECDBG_EN_SHIFT (0x00000014u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECLOCK_EN (0x00000010u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECLOCK_EN_SHIFT (0x00000004u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECDBG_EN (0x00080000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECDBG_EN_SHIFT (0x00000013u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECLOCK_EN (0x00000008u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECLOCK_EN_SHIFT (0x00000003u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECDBG_EN (0x04000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECDBG_EN_SHIFT (0x0000001Au) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECLOCK_EN (0x00000400u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECLOCK_EN_SHIFT (0x0000000Au) - - -/* L3_HW_FW_EXP_VAL_CONF1 */ -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECDBG_EN (0x08000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECDBG_EN_SHIFT (0x0000001Bu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECLOCK_EN (0x00000800u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECLOCK_EN_SHIFT (0x0000000Bu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECDBG_EN (0x10000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECDBG_EN_SHIFT (0x0000001Cu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECLOCK_EN (0x00001000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECLOCK_EN_SHIFT (0x0000000Cu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECDBG_EN (0x02000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECDBG_EN_SHIFT (0x00000019u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECLOCK_EN (0x00000200u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECLOCK_EN_SHIFT (0x00000009u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECDBG_EN (0x01000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECDBG_EN_SHIFT (0x00000018u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECLOCK_EN (0x00000100u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECLOCK_EN_SHIFT (0x00000008u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECDBG_EN (0x00080000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECDBG_EN_SHIFT (0x00000013u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECLOCK_EN (0x00000008u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECLOCK_EN_SHIFT (0x00000003u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECDBG_EN (0x00100000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECDBG_EN_SHIFT (0x00000014u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECLOCK_EN (0x00000010u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECLOCK_EN_SHIFT (0x00000004u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECDBG_EN (0x00200000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECDBG_EN_SHIFT (0x00000015u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECLOCK_EN (0x00000020u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECLOCK_EN_SHIFT (0x00000005u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECDBG_EN (0x04000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECDBG_EN_SHIFT (0x0000001Au) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECLOCK_EN (0x00000400u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECLOCK_EN_SHIFT (0x0000000Au) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD2 (0x00000080u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD2_SHIFT (0x00000007u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD3 (0x00078000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD3_SHIFT (0x0000000Fu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD4 (0x00800000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD4_SHIFT (0x00000017u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD5 (0x80000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD5_SHIFT (0x0000001Fu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECDBG_EN (0x40000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECDBG_EN_SHIFT (0x0000001Eu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECLOCK_EN (0x00004000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECLOCK_EN_SHIFT (0x0000000Eu) - - -/* L4_HW_FW_EXP_VAL_CONF */ -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECDBG_EN (0x01000000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECDBG_EN_SHIFT (0x00000018u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECLOCK_EN (0x00000100u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECLOCK_EN_SHIFT (0x00000008u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECDBG_EN (0x00100000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECDBG_EN_SHIFT (0x00000014u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECLOCK_EN (0x00000010u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECLOCK_EN_SHIFT (0x00000004u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECDBG_EN (0x00200000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECDBG_EN_SHIFT (0x00000015u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECLOCK_EN (0x00000020u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECLOCK_EN_SHIFT (0x00000005u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECDBG_EN (0x00010000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECDBG_EN_SHIFT (0x00000010u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECLOCK_EN (0x00000001u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECLOCK_EN_SHIFT (0x00000000u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECDBG_EN (0x00020000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECDBG_EN_SHIFT (0x00000011u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECLOCK_EN (0x00000002u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECLOCK_EN_SHIFT (0x00000001u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECDBG_EN (0x10000000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECDBG_EN_SHIFT (0x0000001Cu) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECLOCK_EN (0x00001000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECLOCK_EN_SHIFT (0x0000000Cu) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECDBG_EN (0x20000000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECDBG_EN_SHIFT (0x0000001Du) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECLOCK_EN (0x00002000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECLOCK_EN_SHIFT (0x0000000Du) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD2 (0x000000C0u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD2_SHIFT (0x00000006u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD3 (0x00000E00u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD3_SHIFT (0x00000009u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD4 (0x0000C000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD4_SHIFT (0x0000000Eu) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD5 (0x000C0000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD5_SHIFT (0x00000012u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD6 (0x00C00000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD6_SHIFT (0x00000016u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD7 (0x0E000000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD7_SHIFT (0x00000019u) - - -/* CONTROL_SEC_LOAD_FW_EXP_VAL */ -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FAST_LD_EXPVAL_REQN (0x00000010u) -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FAST_LD_EXPVAL_REQN_SHIFT (0x00000004u) - -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FW_LD_EXPVAL_REQN (0x00000004u) -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FW_LD_EXPVAL_REQN_SHIFT (0x00000002u) - -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4PER_LD_EXPVAL_REQN (0x00000008u) -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4PER_LD_EXPVAL_REQN_SHIFT (0x00000003u) - -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4WKUP_LD_EXPVAL_REQN (0x00000020u) -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4WKUP_LD_EXPVAL_REQN_SHIFT (0x00000005u) - -#define CONTROL_SEC_LOAD_FW_EXP_VAL_RSVD2 (0xFFFFFFC0u) -#define CONTROL_SEC_LOAD_FW_EXP_VAL_RSVD2_SHIFT (0x00000006u) - - -/* CONTROL_SEC_CTRL_RO */ -#define CONTROL_SEC_CTRL_RO_CUSTMPK (0x00000010u) -#define CONTROL_SEC_CTRL_RO_CUSTMPK_SHIFT (0x00000004u) - -#define CONTROL_SEC_CTRL_RO_EMIF_CFG_RO_EN (0x00000002u) -#define CONTROL_SEC_CTRL_RO_EMIF_CFG_RO_EN_SHIFT (0x00000001u) - -#define CONTROL_SEC_CTRL_RO_EMIF_OBFS_EN (0x00000004u) -#define CONTROL_SEC_CTRL_RO_EMIF_OBFS_EN_SHIFT (0x00000002u) - -#define CONTROL_SEC_CTRL_RO_RSVD2 (0xFFFFFFE0u) -#define CONTROL_SEC_CTRL_RO_RSVD2_SHIFT (0x00000005u) - -#define CONTROL_SEC_CTRL_RO_SECKEYACCEN (0x00000008u) -#define CONTROL_SEC_CTRL_RO_SECKEYACCEN_SHIFT (0x00000003u) - - -/* EMIF_OBFUSCATION_KEY */ -#define CONTROL_EMIF_OBFUSCATION_KEY_OBFUSCATIONKEY (0x0000FFFFu) -#define CONTROL_EMIF_OBFUSCATION_KEY_OBFUSCATIONKEY_SHIFT (0x00000000u) - - -/* SEC_CLK_CTRL */ -#define CONTROL_SEC_CLK_CTRL_RSVD2 (0x7FFFFFC0u) -#define CONTROL_SEC_CLK_CTRL_RSVD2_SHIFT (0x00000006u) - -#define CONTROL_SEC_CLK_CTRL_SECCLKLCK (0x80000000u) -#define CONTROL_SEC_CLK_CTRL_SECCLKLCK_SHIFT (0x0000001Fu) - -#define CONTROL_SEC_CLK_CTRL_SECTIMERCLKSEL (0x00000030u) -#define CONTROL_SEC_CLK_CTRL_SECTIMERCLKSEL_SHIFT (0x00000004u) - -#define CONTROL_SEC_CLK_CTRL_SECWDCLKSEL (0x00000001u) -#define CONTROL_SEC_CLK_CTRL_SECWDCLKSEL_SHIFT (0x00000000u) - - -/* CONTROL_MREQDOMAIN_EXP3 */ -#define CONTROL_MREQDOMAIN_EXP3_LCK (0x80000000u) -#define CONTROL_MREQDOMAIN_EXP3_LCK_SHIFT (0x0000001Fu) - -#define CONTROL_MREQDOMAIN_EXP3_PRU0_DOM (0x00000007u) -#define CONTROL_MREQDOMAIN_EXP3_PRU0_DOM_SHIFT (0x00000000u) - -#define CONTROL_MREQDOMAIN_EXP3_PRU1_DOM (0x00000038u) -#define CONTROL_MREQDOMAIN_EXP3_PRU1_DOM_SHIFT (0x00000003u) - -#define CONTROL_MREQDOMAIN_EXP3_PRU2_DOM (0x000001C0u) -#define CONTROL_MREQDOMAIN_EXP3_PRU2_DOM_SHIFT (0x00000006u) - -#define CONTROL_MREQDOMAIN_EXP3_PRU3_DOM (0x00000E00u) -#define CONTROL_MREQDOMAIN_EXP3_PRU3_DOM_SHIFT (0x00000009u) - - -/* CONTROL_CEK_0 */ -#define CONTROL_CEK_0_CEK (0xFFFFFFFFu) -#define CONTROL_CEK_0_CEK_SHIFT (0x00000000u) - - -/* CONTROL_CEK_1 */ -#define CONTROL_CEK_1_CEK (0xFFFFFFFFu) -#define CONTROL_CEK_1_CEK_SHIFT (0x00000000u) - - -/* CONTROL_CEK_2 */ -#define CONTROL_CEK_2_CEK (0xFFFFFFFFu) -#define CONTROL_CEK_2_CEK_SHIFT (0x00000000u) - - -/* CONTROL_CEK_3 */ -#define CONTROL_CEK_3_CEK (0xFFFFFFFFu) -#define CONTROL_CEK_3_CEK_SHIFT (0x00000000u) - - -/* CONTROL_CEK_BCH_0 */ -#define CONTROL_CEK_BCH_0_CEK_BCH (0xFFFFFFFFu) -#define CONTROL_CEK_BCH_0_CEK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CEK_BCH_1 */ -#define CONTROL_CEK_BCH_1_CEK_BCH (0xFFFFFFFFu) -#define CONTROL_CEK_BCH_1_CEK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CEK_BCH_2 */ -#define CONTROL_CEK_BCH_2_CEK_BCH (0xFFFFFFFFu) -#define CONTROL_CEK_BCH_2_CEK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CEK_BCH_3 */ -#define CONTROL_CEK_BCH_3_CEK_BCH (0xFFFFFFFFu) -#define CONTROL_CEK_BCH_3_CEK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CEK_BCH_4 */ -#define CONTROL_CEK_BCH_4_CEK_BCH (0x0000FFFFu) -#define CONTROL_CEK_BCH_4_CEK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_MSV_0 */ -#define CONTROL_MSV_0_MSV (0xFFFFFFFFu) -#define CONTROL_MSV_0_MSV_SHIFT (0x00000000u) - - -/* CONTROL_MSV_BCH_0 */ -#define CONTROL_MSV_BCH_0_MSV_BCH (0xFFFFFFFFu) -#define CONTROL_MSV_BCH_0_MSV_BCH_SHIFT (0x00000000u) - - -/* CONTROL_MSV_BCH_1 */ -#define CONTROL_MSV_BCH_1_MSV_BCH (0xFFFFFFFFu) -#define CONTROL_MSV_BCH_1_MSV_BCH_SHIFT (0x00000000u) - - -/* CONTROL_SEC_STATUS */ -#define CONTROL_SEC_STATUS_EMURST (0x00000020u) -#define CONTROL_SEC_STATUS_EMURST_SHIFT (0x00000005u) - -#define CONTROL_SEC_STATUS_GFXDOMAINRST (0x00000200u) -#define CONTROL_SEC_STATUS_GFXDOMAINRST_SHIFT (0x00000009u) - -#define CONTROL_SEC_STATUS_GLOBALCOLDRST (0x00000001u) -#define CONTROL_SEC_STATUS_GLOBALCOLDRST_SHIFT (0x00000000u) - -#define CONTROL_SEC_STATUS_GLOBALWARMRST (0x00000002u) -#define CONTROL_SEC_STATUS_GLOBALWARMRST_SHIFT (0x00000001u) - -#define CONTROL_SEC_STATUS_ICSS0RST (0x00040000u) -#define CONTROL_SEC_STATUS_ICSS0RST_SHIFT (0x00000012u) - -#define CONTROL_SEC_STATUS_ICSS1RST (0x00080000u) -#define CONTROL_SEC_STATUS_ICSS1RST_SHIFT (0x00000013u) - -#define CONTROL_SEC_STATUS_MPUDOMAINRST (0x00000040u) -#define CONTROL_SEC_STATUS_MPUDOMAINRST_SHIFT (0x00000006u) - -#define CONTROL_SEC_STATUS_MPURST (0x00020000u) -#define CONTROL_SEC_STATUS_MPURST_SHIFT (0x00000011u) - -#define CONTROL_SEC_STATUS_PERDOMAINRST (0x00000080u) -#define CONTROL_SEC_STATUS_PERDOMAINRST_SHIFT (0x00000007u) - -#define CONTROL_SEC_STATUS_PUBWDRST (0x00000004u) -#define CONTROL_SEC_STATUS_PUBWDRST_SHIFT (0x00000002u) - -#define CONTROL_SEC_STATUS_RSVD2 (0xFFF00000u) -#define CONTROL_SEC_STATUS_RSVD2_SHIFT (0x00000014u) - -#define CONTROL_SEC_STATUS_SECWDRST (0x00000008u) -#define CONTROL_SEC_STATUS_SECWDRST_SHIFT (0x00000003u) - -#define CONTROL_SEC_STATUS_SSMVIOLATIONRST (0x00000010u) -#define CONTROL_SEC_STATUS_SSMVIOLATIONRST_SHIFT (0x00000004u) - -#define CONTROL_SEC_STATUS_WKUPDOMAINRST (0x00000100u) -#define CONTROL_SEC_STATUS_WKUPDOMAINRST_SHIFT (0x00000008u) - - -/* CONTROL_SECMEM_STATUS */ -#define CONTROL_SECMEM_STATUS_A8L1DEST (0x00000001u) -#define CONTROL_SECMEM_STATUS_A8L1DEST_SHIFT (0x00000000u) - -#define CONTROL_SECMEM_STATUS_A8L1NOTACC (0x00010000u) -#define CONTROL_SECMEM_STATUS_A8L1NOTACC_SHIFT (0x00000010u) - -#define CONTROL_SECMEM_STATUS_A8L2DEST (0x00000002u) -#define CONTROL_SECMEM_STATUS_A8L2DEST_SHIFT (0x00000001u) - -#define CONTROL_SECMEM_STATUS_A8L2NOTACC (0x00020000u) -#define CONTROL_SECMEM_STATUS_A8L2NOTACC_SHIFT (0x00000011u) - -#define CONTROL_SECMEM_STATUS_FASTSECRAMDEST (0x00000004u) -#define CONTROL_SECMEM_STATUS_FASTSECRAMDEST_SHIFT (0x00000002u) - -#define CONTROL_SECMEM_STATUS_FASTSECRAMNOTACC (0x00040000u) -#define CONTROL_SECMEM_STATUS_FASTSECRAMNOTACC_SHIFT (0x00000012u) - -#define CONTROL_SECMEM_STATUS_L3SECRAMDEST (0x00000008u) -#define CONTROL_SECMEM_STATUS_L3SECRAMDEST_SHIFT (0x00000003u) - -#define CONTROL_SECMEM_STATUS_L3SECRAMNOTACC (0x00080000u) -#define CONTROL_SECMEM_STATUS_L3SECRAMNOTACC_SHIFT (0x00000013u) - -#define CONTROL_SECMEM_STATUS_RSVD2 (0xFFF00000u) -#define CONTROL_SECMEM_STATUS_RSVD2_SHIFT (0x00000014u) - - -/* CONTROL_SEC_ERR_STAT_FUNC0 */ -#define CONTROL_SEC_ERR_STAT_FUNC0_EMIFFWERR (0x00000010u) -#define CONTROL_SEC_ERR_STAT_FUNC0_EMIFFWERR_SHIFT (0x00000004u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_GPMCFWERR (0x00000004u) -#define CONTROL_SEC_ERR_STAT_FUNC0_GPMCFWERR_SHIFT (0x00000002u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_L3RAMFWERR (0x00000001u) -#define CONTROL_SEC_ERR_STAT_FUNC0_L3RAMFWERR_SHIFT (0x00000000u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD2 (0x00000008u) -#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD2_SHIFT (0x00000003u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD3 (0x0001FFE0u) -#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD3_SHIFT (0x00000005u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD4 (0x007C0000u) -#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD4_SHIFT (0x00000012u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD5 (0xF8000000u) -#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD5_SHIFT (0x0000001Bu) - -#define CONTROL_SEC_ERR_STAT_FUNC0_SGXFWERR (0x00020000u) -#define CONTROL_SEC_ERR_STAT_FUNC0_SGXFWERR_SHIFT (0x00000011u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC0FWERR (0x01000000u) -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC0FWERR_SHIFT (0x00000018u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC1FWERR (0x02000000u) -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC1FWERR_SHIFT (0x00000019u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC2FWERR (0x04000000u) -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC2FWERR_SHIFT (0x0000001Au) - -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTCCFWERR (0x00800000u) -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTCCFWERR_SHIFT (0x00000017u) - - -/* CONTROL_SEC_ERR_STAT_FUNC1 */ -#define CONTROL_SEC_ERR_STAT_FUNC1_ADCFWERR (0x00000200u) -#define CONTROL_SEC_ERR_STAT_FUNC1_ADCFWERR_SHIFT (0x00000009u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_AES0FWERR (0x00100000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_AES0FWERR_SHIFT (0x00000014u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_CRYPTODMAFWERR (0x00080000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_CRYPTODMAFWERR_SHIFT (0x00000013u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_DBGPORTFWERR (0x00020000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_DBGPORTFWERR_SHIFT (0x00000011u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_L3EXPFWERR (0x00010000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_L3EXPFWERR_SHIFT (0x00000010u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_L4FASTFWERR (0x02000000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_L4FASTFWERR_SHIFT (0x00000019u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_L4FWFWERR (0x08000000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_L4FWFWERR_SHIFT (0x0000001Bu) - -#define CONTROL_SEC_ERR_STAT_FUNC1_L4PERFWERR (0x01000000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_L4PERFWERR_SHIFT (0x00000018u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_L4WKUPFWERR (0x04000000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_L4WKUPFWERR_SHIFT (0x0000001Au) - -#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP0FWERR (0x00000001u) -#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP0FWERR_SHIFT (0x00000000u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP1FWERR (0x00000002u) -#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP1FWERR_SHIFT (0x00000001u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_MMCHS2FWERR (0x00008000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_MMCHS2FWERR_SHIFT (0x0000000Fu) - -#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD2 (0x00000400u) -#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD2_SHIFT (0x0000000Au) - -#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD3 (0x00006000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD3_SHIFT (0x0000000Du) - -#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD4 (0x00800000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD4_SHIFT (0x00000017u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD5 (0xF0000000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD5_SHIFT (0x0000001Cu) - -#define CONTROL_SEC_ERR_STAT_FUNC1_SECMODFWERR (0x00040000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_SECMODFWERR_SHIFT (0x00000012u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_SHAFWERR (0x00400000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_SHAFWERR_SHIFT (0x00000016u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_USBFWERR (0x00000800u) -#define CONTROL_SEC_ERR_STAT_FUNC1_USBFWERR_SHIFT (0x0000000Bu) - - -/* CONTROL_SEC_ERR_STAT_DBUG0 */ -#define CONTROL_SEC_ERR_STAT_DBUG0_EMIFDBGFWERR (0x00000010u) -#define CONTROL_SEC_ERR_STAT_DBUG0_EMIFDBGFWERR_SHIFT (0x00000004u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_GPMCDBGFWERR (0x00000004u) -#define CONTROL_SEC_ERR_STAT_DBUG0_GPMCDBGFWERR_SHIFT (0x00000002u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_L3RAMDBGFWERR (0x00000001u) -#define CONTROL_SEC_ERR_STAT_DBUG0_L3RAMDBGFWERR_SHIFT (0x00000000u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD2 (0x00000008u) -#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD2_SHIFT (0x00000003u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD3 (0x0001FFE0u) -#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD3_SHIFT (0x00000005u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD4 (0x007C0000u) -#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD4_SHIFT (0x00000012u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD5 (0xF8000000u) -#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD5_SHIFT (0x0000001Bu) - -#define CONTROL_SEC_ERR_STAT_DBUG0_SGXDBGFWERR (0x00020000u) -#define CONTROL_SEC_ERR_STAT_DBUG0_SGXDBGFWERR_SHIFT (0x00000011u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC0DBGFWERR (0x01000000u) -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC0DBGFWERR_SHIFT (0x00000018u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC1DBGFWERR (0x02000000u) -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC1DBGFWERR_SHIFT (0x00000019u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC2DBGFWERR (0x04000000u) -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC2DBGFWERR_SHIFT (0x0000001Au) - -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTCCDBGFWERR (0x00800000u) -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTCCDBGFWERR_SHIFT (0x00000017u) - - -/* CONTROL_SEC_ERR_STAT_DBUG1 */ -#define CONTROL_SEC_ERR_STAT_DBUG1_ADCDBGFWERR (0x00000200u) -#define CONTROL_SEC_ERR_STAT_DBUG1_ADCDBGFWERR_SHIFT (0x00000009u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_AES0DBGFWERR (0x00100000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_AES0DBGFWERR_SHIFT (0x00000014u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_CRYPTODMADBGFWERR (0x00080000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_CRYPTODMADBGFWERR_SHIFT (0x00000013u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_DBGPORTDBGFWERR (0x00020000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_DBGPORTDBGFWERR_SHIFT (0x00000011u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_L3EXPDBGFWERR (0x00010000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_L3EXPDBGFWERR_SHIFT (0x00000010u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_L4FASTDBGFWERR (0x02000000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_L4FASTDBGFWERR_SHIFT (0x00000019u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_L4FWDBGFWERR (0x08000000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_L4FWDBGFWERR_SHIFT (0x0000001Bu) - -#define CONTROL_SEC_ERR_STAT_DBUG1_L4PERDBGFWERR (0x01000000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_L4PERDBGFWERR_SHIFT (0x00000018u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_L4WKUPDBGFWERR (0x04000000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_L4WKUPDBGFWERR_SHIFT (0x0000001Au) - -#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP0DBGFWERR (0x00000001u) -#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP0DBGFWERR_SHIFT (0x00000000u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP1DBGFWERR (0x00000002u) -#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP1DBGFWERR_SHIFT (0x00000001u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_MMCHS2DBGFWERR (0x00008000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_MMCHS2DBGFWERR_SHIFT (0x0000000Fu) - -#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD2 (0x00000400u) -#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD2_SHIFT (0x0000000Au) - -#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD3 (0x00006000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD3_SHIFT (0x0000000Du) - -#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD4 (0x00040000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD4_SHIFT (0x00000012u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD5 (0x00800000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD5_SHIFT (0x00000017u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD6 (0xF0000000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD6_SHIFT (0x0000001Cu) - -#define CONTROL_SEC_ERR_STAT_DBUG1_SHADBGFWERR (0x00400000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_SHADBGFWERR_SHIFT (0x00000016u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_USBDBGFWERR (0x00000800u) -#define CONTROL_SEC_ERR_STAT_DBUG1_USBDBGFWERR_SHIFT (0x0000000Bu) - - -/* CONTROL_KEK_SW_0 */ -#define CONTROL_KEK_SW_0_KEK_SW (0xFFFFFFFFu) -#define CONTROL_KEK_SW_0_KEK_SW_SHIFT (0x00000000u) - - -/* CONTROL_KEK_SW_1 */ -#define CONTROL_KEK_SW_1_KEK_SW (0xFFFFFFFFu) -#define CONTROL_KEK_SW_1_KEK_SW_SHIFT (0x00000000u) - - -/* CONTROL_KEK_SW_2 */ -#define CONTROL_KEK_SW_2_KEK_SW (0xFFFFFFFFu) -#define CONTROL_KEK_SW_2_KEK_SW_SHIFT (0x00000000u) - - -/* CONTROL_KEK_SW_3 */ -#define CONTROL_KEK_SW_3_KEK_SW (0xFFFFFFFFu) -#define CONTROL_KEK_SW_3_KEK_SW_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_BCH_0 */ -#define CONTROL_CMPK_BCH_0_CMPK_BCH (0xFFFFFFFFu) -#define CONTROL_CMPK_BCH_0_CMPK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_BCH_1 */ -#define CONTROL_CMPK_BCH_1_CMPK_BCH (0xFFFFFFFFu) -#define CONTROL_CMPK_BCH_1_CMPK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_BCH_2 */ -#define CONTROL_CMPK_BCH_2_CMPK_BCH (0xFFFFFFFFu) -#define CONTROL_CMPK_BCH_2_CMPK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_BCH_3 */ -#define CONTROL_CMPK_BCH_3_CMPK_BCH (0xFFFFFFFFu) -#define CONTROL_CMPK_BCH_3_CMPK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_BCH_4 */ -#define CONTROL_CMPK_BCH_4_CMPK_BCH (0xFFFFFFFFu) -#define CONTROL_CMPK_BCH_4_CMPK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_BCH_5 */ -#define CONTROL_CMPK_BCH_5_CMPK_BCH (0xFFFFFFFFu) -#define CONTROL_CMPK_BCH_5_CMPK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_BCH_6 */ -#define CONTROL_CMPK_BCH_6_CMPK_BCH (0xFFFFFFFFu) -#define CONTROL_CMPK_BCH_6_CMPK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_BCH_7 */ -#define CONTROL_CMPK_BCH_7_CMPK_BCH (0xFFFFFFFFu) -#define CONTROL_CMPK_BCH_7_CMPK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_BCH_8 */ -#define CONTROL_CMPK_BCH_8_CMPK_BCH (0xFFFFFFFFu) -#define CONTROL_CMPK_BCH_8_CMPK_BCH_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_0 */ -#define CONTROL_CMPK_0_CMPK (0xFFFFFFFFu) -#define CONTROL_CMPK_0_CMPK_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_1 */ -#define CONTROL_CMPK_1_CMPK (0xFFFFFFFFu) -#define CONTROL_CMPK_1_CMPK_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_2 */ -#define CONTROL_CMPK_2_CMPK (0xFFFFFFFFu) -#define CONTROL_CMPK_2_CMPK_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_3 */ -#define CONTROL_CMPK_3_CMPK (0xFFFFFFFFu) -#define CONTROL_CMPK_3_CMPK_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_4 */ -#define CONTROL_CMPK_4_CMPK (0xFFFFFFFFu) -#define CONTROL_CMPK_4_CMPK_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_5 */ -#define CONTROL_CMPK_5_CMPK (0xFFFFFFFFu) -#define CONTROL_CMPK_5_CMPK_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_6 */ -#define CONTROL_CMPK_6_CMPK (0xFFFFFFFFu) -#define CONTROL_CMPK_6_CMPK_SHIFT (0x00000000u) - - -/* CONTROL_CMPK_7 */ -#define CONTROL_CMPK_7_CMPK (0xFFFFFFFFu) -#define CONTROL_CMPK_7_CMPK_SHIFT (0x00000000u) - - -/* SSM_END_FAST_SECRAM */ -#define CONTROL_SSM_END_FAST_SECRAM_END_FAST_SECRAM (0x0000FC00u) -#define CONTROL_SSM_END_FAST_SECRAM_END_FAST_SECRAM_SHIFT (0x0000000Au) - -#define CONTROL_SSM_END_FAST_SECRAM_RSVD2 (0xFFFF0000u) -#define CONTROL_SSM_END_FAST_SECRAM_RSVD2_SHIFT (0x00000010u) - - -/* SSM_FIREWALL_CONTROLLER */ -#define CONTROL_SSM_FIREWALL_CONTROLLER_CPSR_ENFC_EN (0x00001000u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_CPSR_ENFC_EN_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_DC_ENFC_EN (0x00000800u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_DC_ENFC_EN_SHIFT (0x0000000Bu) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_IC_ENFC_EN (0x00000400u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_IC_ENFC_EN_SHIFT (0x0000000Au) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MMU_ENFC_EN (0x00000200u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MMU_ENFC_EN_SHIFT (0x00000009u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MONITOR_EN (0x00000001u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MONITOR_EN_SHIFT (0x00000000u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DATA_TRASH_EN (0x00000080u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DATA_TRASH_EN_SHIFT (0x00000007u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DETM_EN (0x00000020u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DETM_EN_SHIFT (0x00000005u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_IETM_EN (0x00000010u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_IETM_EN_SHIFT (0x00000004u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_RAMCODE_EN (0x00000100u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_RAMCODE_EN_SHIFT (0x00000008u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_STACK_EN (0x00000040u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_STACK_EN_SHIFT (0x00000006u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_SECRAM_EN (0x00000002u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_SECRAM_EN_SHIFT (0x00000001u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_SPM_STACK_EN (0x00000008u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_SPM_STACK_EN_SHIFT (0x00000003u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_SSM_FC_REG_LOCK (0x00002000u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_SSM_FC_REG_LOCK_SHIFT (0x0000000Du) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_STACKEDRAM_EN (0x00000004u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_STACKEDRAM_EN_SHIFT (0x00000002u) - - -/* SSM_START_SECURE_STACKED_RAM */ -#define CONTROL_SSM_START_SECURE_STACKED_RAM_START_STACKEDRAM (0xFFFF0000u) -#define CONTROL_SSM_START_SECURE_STACKED_RAM_START_STACKEDRAM_SHIFT (0x00000010u) - - -/* SSM_END_SECURE_STACKED_RAM */ -#define CONTROL_SSM_END_SECURE_STACKED_RAM_END_STACKEDRAM (0xFFFF0000u) -#define CONTROL_SSM_END_SECURE_STACKED_RAM_END_STACKEDRAM_SHIFT (0x00000010u) - - -/* SSM_START_SPM_STACK */ -#define CONTROL_SSM_START_SPM_STACK_START_SPM_STACK (0xFFFFFC00u) -#define CONTROL_SSM_START_SPM_STACK_START_SPM_STACK_SHIFT (0x0000000Au) - - -/* SSM_END_SPM_STACK */ -#define CONTROL_SSM_END_SPM_STACK_END_SPM_STACK (0x0000FC00u) -#define CONTROL_SSM_END_SPM_STACK_END_SPM_STACK_SHIFT (0x0000000Au) - -#define CONTROL_SSM_END_SPM_STACK_START_SPM_STACK (0xFFFF0000u) -#define CONTROL_SSM_END_SPM_STACK_START_SPM_STACK_SHIFT (0x00000010u) - - -/* SSM_START_MONITOR_RAMCODE */ -#define CONTROL_SSM_START_MONITOR_RAMCODE_START_MON_RAMCODE (0xFFFFFC00u) -#define CONTROL_SSM_START_MONITOR_RAMCODE_START_MON_RAMCODE_SHIFT (0x0000000Au) - - -/* SSM_END_MONITOR_RAMCODE */ -#define CONTROL_SSM_END_MONITOR_RAMCODE_END_MON_RAMCODE (0x0000FC00u) -#define CONTROL_SSM_END_MONITOR_RAMCODE_END_MON_RAMCODE_SHIFT (0x0000000Au) - -#define CONTROL_SSM_END_MONITOR_RAMCODE_START_MON_RAMCODE (0xFFFF0000u) -#define CONTROL_SSM_END_MONITOR_RAMCODE_START_MON_RAMCODE_SHIFT (0x00000010u) - - -/* SSM_END_MONITOR_RAMDATA */ -#define CONTROL_SSM_END_MONITOR_RAMDATA_END_MON_RAMDATA (0x0000FC00u) -#define CONTROL_SSM_END_MONITOR_RAMDATA_END_MON_RAMDATA_SHIFT (0x0000000Au) - -#define CONTROL_SSM_END_MONITOR_RAMDATA_START_MON_RAMCODE (0xFFFF0000u) -#define CONTROL_SSM_END_MONITOR_RAMDATA_START_MON_RAMCODE_SHIFT (0x00000010u) - - -/* SSM_START_MONITOR_CODE */ -#define CONTROL_SSM_START_MONITOR_CODE_START_MON_CODE (0xFFFFFC00u) -#define CONTROL_SSM_START_MONITOR_CODE_START_MON_CODE_SHIFT (0x0000000Au) - - -/* SSM_END_MONITOR_CODE */ -#define CONTROL_SSM_END_MONITOR_CODE_END_MON_CODE (0x0001FC00u) -#define CONTROL_SSM_END_MONITOR_CODE_END_MON_CODE_SHIFT (0x0000000Au) - -#define CONTROL_SSM_END_MONITOR_CODE_START_MON_CODE (0xFFFE0000u) -#define CONTROL_SSM_END_MONITOR_CODE_START_MON_CODE_SHIFT (0x00000011u) - - -/* SSM_START_MONITOR_PERIPH */ -#define CONTROL_SSM_START_MONITOR_PERIPH_START_MON_PERIPH (0xFFFFF000u) -#define CONTROL_SSM_START_MONITOR_PERIPH_START_MON_PERIPH_SHIFT (0x0000000Cu) - - -/* SSM_END_MONITOR_PERIPH */ -#define CONTROL_SSM_END_MONITOR_PERIPH_END_MON_PERIPH (0x0FFFF000u) -#define CONTROL_SSM_END_MONITOR_PERIPH_END_MON_PERIPH_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_END_MONITOR_PERIPH_START_MON_PERIPH (0xF0000000u) -#define CONTROL_SSM_END_MONITOR_PERIPH_START_MON_PERIPH_SHIFT (0x0000001Cu) - - -/* SSM_START_MONITOR_STACK */ -#define CONTROL_SSM_START_MONITOR_STACK_START_MON_STACK (0xFFFFFC00u) -#define CONTROL_SSM_START_MONITOR_STACK_START_MON_STACK_SHIFT (0x0000000Au) - - -/* SSM_END_MONITOR_STACK */ -#define CONTROL_SSM_END_MONITOR_STACK_END_MON_STACK (0x00007C00u) -#define CONTROL_SSM_END_MONITOR_STACK_END_MON_STACK_SHIFT (0x0000000Au) - -#define CONTROL_SSM_END_MONITOR_STACK_START_MON_STACK (0xFFFF8000u) -#define CONTROL_SSM_END_MONITOR_STACK_START_MON_STACK_SHIFT (0x0000000Fu) - - -/* SSM_START_MONITOR_RAMCODE_ETM */ -#define CONTROL_SSM_START_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM (0xFFFFF000u) -#define CONTROL_SSM_START_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM_SHIFT (0x0000000Cu) - - -/* SSM_END_MONITOR_RAMCODE_ETM */ -#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_END_MON_RAMCODE_ETM (0x0000F000u) -#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_END_MON_RAMCODE_ETM_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM (0xFFFF0000u) -#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM_SHIFT (0x00000010u) - - -/* SSM_END_MONITOR_RAMDATA_ETM */ -#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_END_MON_RAMDATA_ETM (0x0000F000u) -#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_END_MON_RAMDATA_ETM_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_START_MON_RAMCODE_ETM (0xFFFF0000u) -#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_START_MON_RAMCODE_ETM_SHIFT (0x00000010u) - - -/* SSM_START_MONITOR_CODE_ETM */ -#define CONTROL_SSM_START_MONITOR_CODE_ETM_START_MON_CODE_ETM (0xFFFFF000u) -#define CONTROL_SSM_START_MONITOR_CODE_ETM_START_MON_CODE_ETM_SHIFT (0x0000000Cu) - - -/* SSM_END_MONITOR_CODE_ETM */ -#define CONTROL_SSM_END_MONITOR_CODE_ETM_END_MON_CODE_ETM (0x0001F000u) -#define CONTROL_SSM_END_MONITOR_CODE_ETM_END_MON_CODE_ETM_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_END_MONITOR_CODE_ETM_START_MON_CODE_ETM (0xFFFE0000u) -#define CONTROL_SSM_END_MONITOR_CODE_ETM_START_MON_CODE_ETM_SHIFT (0x00000011u) - - -/* SSM_START_MONITOR_STACK_ETM */ -#define CONTROL_SSM_START_MONITOR_STACK_ETM_START_MON_STACK_ETM (0xFFFFF000u) -#define CONTROL_SSM_START_MONITOR_STACK_ETM_START_MON_STACK_ETM_SHIFT (0x0000000Cu) - - -/* SSM_END_MONITOR_STACK_ETM */ -#define CONTROL_SSM_END_MONITOR_STACK_ETM_END_MON_STACK_ETM (0x0000F000u) -#define CONTROL_SSM_END_MONITOR_STACK_ETM_END_MON_STACK_ETM_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_END_MONITOR_STACK_ETM_START_MON_STACK_ETM (0xFFFF0000u) -#define CONTROL_SSM_END_MONITOR_STACK_ETM_START_MON_STACK_ETM_SHIFT (0x00000010u) - - -/* SSM_START_MONITOR_SHARED_ETM */ -#define CONTROL_SSM_START_MONITOR_SHARED_ETM_START_MON_SHARED_ETM (0xFFFFF000u) -#define CONTROL_SSM_START_MONITOR_SHARED_ETM_START_MON_SHARED_ETM_SHIFT (0x0000000Cu) - - -/* SSM_END_MONITOR_SHARED_ETM */ -#define CONTROL_SSM_END_MONITOR_SHARED_ETM_END_MON_SHARED_ETM (0x0000F000u) -#define CONTROL_SSM_END_MONITOR_SHARED_ETM_END_MON_SHARED_ETM_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_END_MONITOR_SHARED_ETM_START_MON_SHARED_ETM (0xFFFF0000u) -#define CONTROL_SSM_END_MONITOR_SHARED_ETM_START_MON_SHARED_ETM_SHIFT (0x00000010u) - - -/* SSM_START_MONITOR_PERIPH_ETM */ -#define CONTROL_SSM_START_MONITOR_PERIPH_ETM_START_MON_PERIPH_ETM (0xFFFFF000u) -#define CONTROL_SSM_START_MONITOR_PERIPH_ETM_START_MON_PERIPH_ETM_SHIFT (0x0000000Cu) - - -/* SSM_END_MONITOR_PERIPH_ETM */ -#define CONTROL_SSM_END_MONITOR_PERIPH_ETM_END_MON_PERIPH_ETM (0xFFFFF000u) -#define CONTROL_SSM_END_MONITOR_PERIPH_ETM_END_MON_PERIPH_ETM_SHIFT (0x0000000Cu) - - -/* SSM_CPSR_MODE_ENFC */ -#define CONTROL_SSM_CPSR_MODE_ENFC_EA_TRAPPED_IN_MON (0x00000100u) -#define CONTROL_SSM_CPSR_MODE_ENFC_EA_TRAPPED_IN_MON_SHIFT (0x00000008u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_FIQ_TRAPPED_IN_MON (0x00000080u) -#define CONTROL_SSM_CPSR_MODE_ENFC_FIQ_TRAPPED_IN_MON_SHIFT (0x00000007u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_IRQ_TRAPPED_IN_MON (0x00000040u) -#define CONTROL_SSM_CPSR_MODE_ENFC_IRQ_TRAPPED_IN_MON_SHIFT (0x00000006u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_ABORT_ENFC (0x00000004u) -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_ABORT_ENFC_SHIFT (0x00000002u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_SYS_ENFC (0x00000010u) -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_SYS_ENFC_SHIFT (0x00000004u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_UNDEF_ENFC (0x00000008u) -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_UNDEF_ENFC_SHIFT (0x00000003u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_USER_ENFC (0x00000002u) -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_USER_ENFC_SHIFT (0x00000001u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_SYS_VS_USER_ENFC (0x00000020u) -#define CONTROL_SSM_CPSR_MODE_ENFC_SYS_VS_USER_ENFC_SHIFT (0x00000005u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_TZ_NS_BIT_ENFC (0x00000001u) -#define CONTROL_SSM_CPSR_MODE_ENFC_TZ_NS_BIT_ENFC_SHIFT (0x00000000u) - - -/* SSM_END_L3_SECRAM */ -#define CONTROL_SSM_END_L3_SECRAM_END_L3_SECRAM (0x0000FC00u) -#define CONTROL_SSM_END_L3_SECRAM_END_L3_SECRAM_SHIFT (0x0000000Au) - -#define CONTROL_SSM_END_L3_SECRAM_RSVD2 (0xFFFF0000u) -#define CONTROL_SSM_END_L3_SECRAM_RSVD2_SHIFT (0x00000010u) - - -/* CORTEX_VBBLDO_CTRL */ -#define CONTROL_CORTEX_VBBLDO_CTRL_BBSEL (0x00000004u) -#define CONTROL_CORTEX_VBBLDO_CTRL_BBSEL_SHIFT (0x00000002u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_HZ (0x00000008u) -#define CONTROL_CORTEX_VBBLDO_CTRL_HZ_SHIFT (0x00000003u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_LDOBYPASSZ (0x00000020u) -#define CONTROL_CORTEX_VBBLDO_CTRL_LDOBYPASSZ_SHIFT (0x00000005u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_LOWPWR (0x00000010u) -#define CONTROL_CORTEX_VBBLDO_CTRL_LOWPWR_SHIFT (0x00000004u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_NOCAP (0x00000002u) -#define CONTROL_CORTEX_VBBLDO_CTRL_NOCAP_SHIFT (0x00000001u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_NOVBGBYR (0x00000001u) -#define CONTROL_CORTEX_VBBLDO_CTRL_NOVBGBYR_SHIFT (0x00000000u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_RSVD2 (0xFC000000u) -#define CONTROL_CORTEX_VBBLDO_CTRL_RSVD2_SHIFT (0x0000001Au) - -#define CONTROL_CORTEX_VBBLDO_CTRL_VSETFBB (0x03E00000u) -#define CONTROL_CORTEX_VBBLDO_CTRL_VSETFBB_SHIFT (0x00000015u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_VSETRBB (0x001F0000u) -#define CONTROL_CORTEX_VBBLDO_CTRL_VSETRBB_SHIFT (0x00000010u) - - -/* CORE_SLDO_CTRL */ -#define CONTROL_CORE_SLDO_CTRL_RSVD2 (0xFC000000u) -#define CONTROL_CORE_SLDO_CTRL_RSVD2_SHIFT (0x0000001Au) - -#define CONTROL_CORE_SLDO_CTRL_VSET (0x03FF0000u) -#define CONTROL_CORE_SLDO_CTRL_VSET_SHIFT (0x00000010u) - - -/* MPU_SLDO_CTRL */ -#define CONTROL_MPU_SLDO_CTRL_RSVD2 (0xFC000000u) -#define CONTROL_MPU_SLDO_CTRL_RSVD2_SHIFT (0x0000001Au) - -#define CONTROL_MPU_SLDO_CTRL_VSET (0x03FF0000u) -#define CONTROL_MPU_SLDO_CTRL_VSET_SHIFT (0x00000010u) - - -/* REFCLK_LJCBLDO_CTRL */ -#define CONTROL_REFCLK_LJCBLDO_CTRL_ABBOFF (0x00000040u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_ABBOFF_SHIFT (0x00000006u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_AIPOFF (0x00000080u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_AIPOFF_SHIFT (0x00000007u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC1 (0x00000001u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC1_SHIFT (0x00000000u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC2 (0x00000002u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC2_SHIFT (0x00000001u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC3 (0x00000004u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC3_SHIFT (0x00000002u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC4 (0x00000008u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC4_SHIFT (0x00000003u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC5 (0x00000010u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC5_SHIFT (0x00000004u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_RSVD2 (0xFC000000u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_RSVD2_SHIFT (0x0000001Au) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_VSET (0x03FF0000u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_VSET_SHIFT (0x00000010u) - - -/* CLK32KDIVRATIO_CTRL */ -#define CONTROL_CLK32KDIVRATIO_CTRL_CLKDIVOPP50_EN (0x00000001u) -#define CONTROL_CLK32KDIVRATIO_CTRL_CLKDIVOPP50_EN_SHIFT (0x00000000u) - - -/* BANDGAP_CTRL */ -#define CONTROL_BANDGAP_CTRL_BGROFF (0x00000040u) -#define CONTROL_BANDGAP_CTRL_BGROFF_SHIFT (0x00000006u) - -#define CONTROL_BANDGAP_CTRL_CBIASSEL (0x00000080u) -#define CONTROL_BANDGAP_CTRL_CBIASSEL_SHIFT (0x00000007u) - -#define CONTROL_BANDGAP_CTRL_CLRZ (0x00000008u) -#define CONTROL_BANDGAP_CTRL_CLRZ_SHIFT (0x00000003u) - -#define CONTROL_BANDGAP_CTRL_CONTCONV (0x00000004u) -#define CONTROL_BANDGAP_CTRL_CONTCONV_SHIFT (0x00000002u) - -#define CONTROL_BANDGAP_CTRL_DTEMP (0x0000FF00u) -#define CONTROL_BANDGAP_CTRL_DTEMP_SHIFT (0x00000008u) - -#define CONTROL_BANDGAP_CTRL_ECOZ (0x00000002u) -#define CONTROL_BANDGAP_CTRL_ECOZ_SHIFT (0x00000001u) - -#define CONTROL_BANDGAP_CTRL_SOC (0x00000010u) -#define CONTROL_BANDGAP_CTRL_SOC_SHIFT (0x00000004u) - -#define CONTROL_BANDGAP_CTRL_TMPSOFF (0x00000020u) -#define CONTROL_BANDGAP_CTRL_TMPSOFF_SHIFT (0x00000005u) - -#define CONTROL_BANDGAP_CTRL_TSHUT (0x00000001u) -#define CONTROL_BANDGAP_CTRL_TSHUT_SHIFT (0x00000000u) - - -/* BANDGAP_TRIM */ -#define CONTROL_BANDGAP_TRIM_DTRBGAPC (0xFF000000u) -#define CONTROL_BANDGAP_TRIM_DTRBGAPC_SHIFT (0x00000018u) - -#define CONTROL_BANDGAP_TRIM_DTRBGAPV (0x00FF0000u) -#define CONTROL_BANDGAP_TRIM_DTRBGAPV_SHIFT (0x00000010u) - -#define CONTROL_BANDGAP_TRIM_DTRTEMPS (0x0000FF00u) -#define CONTROL_BANDGAP_TRIM_DTRTEMPS_SHIFT (0x00000008u) - -#define CONTROL_BANDGAP_TRIM_DTRTEMPSC (0x000000FFu) -#define CONTROL_BANDGAP_TRIM_DTRTEMPSC_SHIFT (0x00000000u) - - -/* PLL_CLKINPULOW_CTRL */ -#define CONTROL_PLL_CLKINPULOW_CTRL_DDR_PLL_CLKINPULOW_SEL (0x00000004u) -#define CONTROL_PLL_CLKINPULOW_CTRL_DDR_PLL_CLKINPULOW_SEL_SHIFT (0x00000002u) - -#define CONTROL_PLL_CLKINPULOW_CTRL_DISP_PLL_CLKINPULOW_SEL (0x00000002u) -#define CONTROL_PLL_CLKINPULOW_CTRL_DISP_PLL_CLKINPULOW_SEL_SHIFT (0x00000001u) - -#define CONTROL_PLL_CLKINPULOW_CTRL_MPU_DPLL_CLKINPULOW_SEL (0x00000001u) -#define CONTROL_PLL_CLKINPULOW_CTRL_MPU_DPLL_CLKINPULOW_SEL_SHIFT (0x00000000u) - - -/* MOSC_CTRL */ -#define CONTROL_MOSC_CTRL_RESSELECT (0x00000001u) -#define CONTROL_MOSC_CTRL_RESSELECT_SHIFT (0x00000000u) - - -/* RCOSC_CTRL */ -#define CONTROL_RCOSC_CTRL_STOPOSC (0x00000001u) -#define CONTROL_RCOSC_CTRL_STOPOSC_SHIFT (0x00000000u) - - -/* DEEPSLEEP_CTRL */ -#define CONTROL_DEEPSLEEP_CTRL_DSCOUNT (0x0000FFFFu) -#define CONTROL_DEEPSLEEP_CTRL_DSCOUNT_SHIFT (0x00000000u) - -#define CONTROL_DEEPSLEEP_CTRL_DSENABLE (0x00020000u) -#define CONTROL_DEEPSLEEP_CTRL_DSENABLE_SHIFT (0x00000011u) - -#define CONTROL_DEEPSLEEP_CTRL_RSVD2 (0xFFFC0000u) -#define CONTROL_DEEPSLEEP_CTRL_RSVD2_SHIFT (0x00000012u) - - -/* PE_SCRATCHPAD_0 */ -#define CONTROL_PE_SCRATCHPAD_0_PE_SCRATCHPAD_0 (0xFFFFFFFFu) -#define CONTROL_PE_SCRATCHPAD_0_PE_SCRATCHPAD_0_SHIFT (0x00000000u) - - -/* PE_SCRATCHPAD_1 */ -#define CONTROL_PE_SCRATCHPAD_1_PE_SCRATCHPAD_1 (0xFFFFFFFFu) -#define CONTROL_PE_SCRATCHPAD_1_PE_SCRATCHPAD_1_SHIFT (0x00000000u) - - -/* PE_SCRATCHPAD_2 */ -#define CONTROL_PE_SCRATCHPAD_2_PE_SCRATCHPAD_2 (0xFFFFFFFFu) -#define CONTROL_PE_SCRATCHPAD_2_PE_SCRATCHPAD_2_SHIFT (0x00000000u) - - -/* PE_SCRATCHPAD_3 */ -#define CONTROL_PE_SCRATCHPAD_3_PE_SCRATCHPAD_3 (0xFFFFFFFFu) -#define CONTROL_PE_SCRATCHPAD_3_PE_SCRATCHPAD_3_SHIFT (0x00000000u) - - -/* DEVICE_ID */ -#define CONTROL_DEVICE_ID_DEVREV (0xF0000000u) -#define CONTROL_DEVICE_ID_DEVREV_SHIFT (0x0000001Cu) - -#define CONTROL_DEVICE_ID_MFGR (0x00000FFEu) -#define CONTROL_DEVICE_ID_MFGR_SHIFT (0x00000001u) - -#define CONTROL_DEVICE_ID_PARTNUM (0x0FFFF000u) -#define CONTROL_DEVICE_ID_PARTNUM_SHIFT (0x0000000Cu) - - -/* DEV_FEATURE */ -#define CONTROL_DEV_FEATURE_CPSW (0x00000002u) -#define CONTROL_DEV_FEATURE_CPSW_SHIFT (0x00000001u) - -#define CONTROL_DEV_FEATURE_DCAN (0x00000080u) -#define CONTROL_DEV_FEATURE_DCAN_SHIFT (0x00000007u) - -#define CONTROL_DEV_FEATURE_ICSS (0x00000001u) -#define CONTROL_DEV_FEATURE_ICSS_SHIFT (0x00000000u) - -#define CONTROL_DEV_FEATURE_ICSS_FEA (0x00FF0000u) -#define CONTROL_DEV_FEATURE_ICSS_FEA_SHIFT (0x00000010u) - -#define CONTROL_DEV_FEATURE_RSVD2 (0x0000FC00u) -#define CONTROL_DEV_FEATURE_RSVD2_SHIFT (0x0000000Au) - -#define CONTROL_DEV_FEATURE_RSVD3 (0x1F000000u) -#define CONTROL_DEV_FEATURE_RSVD3_SHIFT (0x00000018u) - -#define CONTROL_DEV_FEATURE_RSVD4 (0xC0000000u) -#define CONTROL_DEV_FEATURE_RSVD4_SHIFT (0x0000001Eu) - -#define CONTROL_DEV_FEATURE_SEC_PKA_RNG_SHA (0x00000200u) -#define CONTROL_DEV_FEATURE_SEC_PKA_RNG_SHA_SHIFT (0x00000009u) - -#define CONTROL_DEV_FEATURE_SGX (0x20000000u) -#define CONTROL_DEV_FEATURE_SGX_SHIFT (0x0000001Du) - - -/* INIT_PRIORITY_0 */ -#define CONTROL_INIT_PRIORITY_0_HOST_ARM (0x00000003u) -#define CONTROL_INIT_PRIORITY_0_HOST_ARM_SHIFT (0x00000000u) - -#define CONTROL_INIT_PRIORITY_0_MMU (0x000000C0u) -#define CONTROL_INIT_PRIORITY_0_MMU_SHIFT (0x00000006u) - -#define CONTROL_INIT_PRIORITY_0_P1500 (0x0000C000u) -#define CONTROL_INIT_PRIORITY_0_P1500_SHIFT (0x0000000Eu) - -#define CONTROL_INIT_PRIORITY_0_PRUSS0 (0x0000000Cu) -#define CONTROL_INIT_PRIORITY_0_PRUSS0_SHIFT (0x00000002u) - -#define CONTROL_INIT_PRIORITY_0_PRUSS1 (0x00000030u) -#define CONTROL_INIT_PRIORITY_0_PRUSS1_SHIFT (0x00000004u) - -#define CONTROL_INIT_PRIORITY_0_RSVD2 (0xF0000000u) -#define CONTROL_INIT_PRIORITY_0_RSVD2_SHIFT (0x0000001Cu) - -#define CONTROL_INIT_PRIORITY_0_TCRD0 (0x00030000u) -#define CONTROL_INIT_PRIORITY_0_TCRD0_SHIFT (0x00000010u) - -#define CONTROL_INIT_PRIORITY_0_TCRD1 (0x00300000u) -#define CONTROL_INIT_PRIORITY_0_TCRD1_SHIFT (0x00000014u) - -#define CONTROL_INIT_PRIORITY_0_TCRD2 (0x03000000u) -#define CONTROL_INIT_PRIORITY_0_TCRD2_SHIFT (0x00000018u) - -#define CONTROL_INIT_PRIORITY_0_TCWR0 (0x000C0000u) -#define CONTROL_INIT_PRIORITY_0_TCWR0_SHIFT (0x00000012u) - -#define CONTROL_INIT_PRIORITY_0_TCWR1 (0x00C00000u) -#define CONTROL_INIT_PRIORITY_0_TCWR1_SHIFT (0x00000016u) - -#define CONTROL_INIT_PRIORITY_0_TCWR2 (0x0C000000u) -#define CONTROL_INIT_PRIORITY_0_TCWR2_SHIFT (0x0000001Au) - - -/* INIT_PRIORITY_1 */ -#define CONTROL_INIT_PRIORITY_1_CPSW (0x00000003u) -#define CONTROL_INIT_PRIORITY_1_CPSW_SHIFT (0x00000000u) - -#define CONTROL_INIT_PRIORITY_1_DEBUG (0x03000000u) -#define CONTROL_INIT_PRIORITY_1_DEBUG_SHIFT (0x00000018u) - -#define CONTROL_INIT_PRIORITY_1_LCD (0x00C00000u) -#define CONTROL_INIT_PRIORITY_1_LCD_SHIFT (0x00000016u) - -#define CONTROL_INIT_PRIORITY_1_RSVD2 (0x0000FF00u) -#define CONTROL_INIT_PRIORITY_1_RSVD2_SHIFT (0x00000008u) - -#define CONTROL_INIT_PRIORITY_1_RSVD3 (0x000C0000u) -#define CONTROL_INIT_PRIORITY_1_RSVD3_SHIFT (0x00000012u) - -#define CONTROL_INIT_PRIORITY_1_RSVD4 (0xFC000000u) -#define CONTROL_INIT_PRIORITY_1_RSVD4_SHIFT (0x0000001Au) - -#define CONTROL_INIT_PRIORITY_1_SGX (0x00300000u) -#define CONTROL_INIT_PRIORITY_1_SGX_SHIFT (0x00000014u) - -#define CONTROL_INIT_PRIORITY_1_USB_DMA (0x00000030u) -#define CONTROL_INIT_PRIORITY_1_USB_DMA_SHIFT (0x00000004u) - -#define CONTROL_INIT_PRIORITY_1_USB_QMGR (0x000000C0u) -#define CONTROL_INIT_PRIORITY_1_USB_QMGR_SHIFT (0x00000006u) - - -/* MMU_CFG */ -#define CONTROL_MMU_CFG_MMU_ABORT (0x00008000u) -#define CONTROL_MMU_CFG_MMU_ABORT_SHIFT (0x0000000Fu) - -#define CONTROL_MMU_CFG_MMU_DISABLE (0x00000080u) -#define CONTROL_MMU_CFG_MMU_DISABLE_SHIFT (0x00000007u) - -#define CONTROL_MMU_CFG_RSVD2 (0x00007F00u) -#define CONTROL_MMU_CFG_RSVD2_SHIFT (0x00000008u) - -#define CONTROL_MMU_CFG_RSVD3 (0xFFFF0000u) -#define CONTROL_MMU_CFG_RSVD3_SHIFT (0x00000010u) - - -/* TPTC_CFG */ -#define CONTROL_TPTC_CFG_TC0DBS (0x00000003u) -#define CONTROL_TPTC_CFG_TC0DBS_SHIFT (0x00000000u) - -#define CONTROL_TPTC_CFG_TC1DBS (0x0000000Cu) -#define CONTROL_TPTC_CFG_TC1DBS_SHIFT (0x00000002u) - -#define CONTROL_TPTC_CFG_TC2DBS (0x00000030u) -#define CONTROL_TPTC_CFG_TC2DBS_SHIFT (0x00000004u) - - -/* OCMC_CFG */ -#define CONTROL_OCMC_CFG_PAR_EN (0x00000001u) -#define CONTROL_OCMC_CFG_PAR_EN_SHIFT (0x00000000u) - -#define CONTROL_OCMC_CFG_PAR_INT_CLR (0x00000010u) -#define CONTROL_OCMC_CFG_PAR_INT_CLR_SHIFT (0x00000004u) - -#define CONTROL_OCMC_CFG_PAR_RESP_EN (0x00000002u) -#define CONTROL_OCMC_CFG_PAR_RESP_EN_SHIFT (0x00000001u) - -#define CONTROL_OCMC_CFG_RSVD2 (0xFFFFFFE0u) -#define CONTROL_OCMC_CFG_RSVD2_SHIFT (0x00000005u) - - -/* USB_CTRL0 */ -#define CONTROL_USB_CTRL0_CDET_EXTCTL (0x00000400u) -#define CONTROL_USB_CTRL0_CDET_EXTCTL_SHIFT (0x0000000Au) - -#define CONTROL_USB_CTRL0_CHGDET_DIS (0x00000004u) -#define CONTROL_USB_CTRL0_CHGDET_DIS_SHIFT (0x00000002u) - -#define CONTROL_USB_CTRL0_CHGDET_RSTRT (0x00000008u) -#define CONTROL_USB_CTRL0_CHGDET_RSTRT_SHIFT (0x00000003u) - -#define CONTROL_USB_CTRL0_CHGISINK_EN (0x00000040u) -#define CONTROL_USB_CTRL0_CHGISINK_EN_SHIFT (0x00000006u) - -#define CONTROL_USB_CTRL0_CHGVSRC_EN (0x00000080u) -#define CONTROL_USB_CTRL0_CHGVSRC_EN_SHIFT (0x00000007u) - -#define CONTROL_USB_CTRL0_CM_PWRDN (0x00000001u) -#define CONTROL_USB_CTRL0_CM_PWRDN_SHIFT (0x00000000u) - -#define CONTROL_USB_CTRL0_DATAPOLARITY_INV (0x00800000u) -#define CONTROL_USB_CTRL0_DATAPOLARITY_INV_SHIFT (0x00000017u) - -#define CONTROL_USB_CTRL0_DMGPIO_PD (0x00040000u) -#define CONTROL_USB_CTRL0_DMGPIO_PD_SHIFT (0x00000012u) - -#define CONTROL_USB_CTRL0_DMPULLUP (0x00000100u) -#define CONTROL_USB_CTRL0_DMPULLUP_SHIFT (0x00000008u) - -#define CONTROL_USB_CTRL0_DPGPIO_PD (0x00020000u) -#define CONTROL_USB_CTRL0_DPGPIO_PD_SHIFT (0x00000011u) - -#define CONTROL_USB_CTRL0_DPPULLUP (0x00000200u) -#define CONTROL_USB_CTRL0_DPPULLUP_SHIFT (0x00000009u) - -#define CONTROL_USB_CTRL0_GPIOMODE (0x00001000u) -#define CONTROL_USB_CTRL0_GPIOMODE_SHIFT (0x0000000Cu) - -#define CONTROL_USB_CTRL0_GPIO_SIG_CROSS (0x00004000u) -#define CONTROL_USB_CTRL0_GPIO_SIG_CROSS_SHIFT (0x0000000Eu) - -#define CONTROL_USB_CTRL0_GPIO_SIG_INV (0x00002000u) -#define CONTROL_USB_CTRL0_GPIO_SIG_INV_SHIFT (0x0000000Du) - -#define CONTROL_USB_CTRL0_OTGSESSENDEN (0x00100000u) -#define CONTROL_USB_CTRL0_OTGSESSENDEN_SHIFT (0x00000014u) - -#define CONTROL_USB_CTRL0_OTGVDET_EN (0x00080000u) -#define CONTROL_USB_CTRL0_OTGVDET_EN_SHIFT (0x00000013u) - -#define CONTROL_USB_CTRL0_OTG_PWRDN (0x00000002u) -#define CONTROL_USB_CTRL0_OTG_PWRDN_SHIFT (0x00000001u) - -#define CONTROL_USB_CTRL0_RSVD2 (0x00008000u) -#define CONTROL_USB_CTRL0_RSVD2_SHIFT (0x0000000Fu) - -#define CONTROL_USB_CTRL0_RSVD3 (0x00010000u) -#define CONTROL_USB_CTRL0_RSVD3_SHIFT (0x00000010u) - -#define CONTROL_USB_CTRL0_SINKONDP (0x00000020u) -#define CONTROL_USB_CTRL0_SINKONDP_SHIFT (0x00000005u) - -#define CONTROL_USB_CTRL0_SPAREIN (0xFF000000u) -#define CONTROL_USB_CTRL0_SPAREIN_SHIFT (0x00000018u) - -#define CONTROL_USB_CTRL0_SRCONDM (0x00000010u) -#define CONTROL_USB_CTRL0_SRCONDM_SHIFT (0x00000004u) - -#define CONTROL_USB_CTRL0_USB_PHY_SMA1 (0x00200000u) -#define CONTROL_USB_CTRL0_USB_PHY_SMA1_SHIFT (0x00000015u) - -#define CONTROL_USB_CTRL0_USB_PHY_SMA2 (0x00400000u) -#define CONTROL_USB_CTRL0_USB_PHY_SMA2_SHIFT (0x00000016u) - - -/* USB_STS0 */ -#define CONTROL_USB_STS0_CDET_DATADET (0x00000004u) -#define CONTROL_USB_STS0_CDET_DATADET_SHIFT (0x00000002u) - -#define CONTROL_USB_STS0_CDET_DMDET (0x00000010u) -#define CONTROL_USB_STS0_CDET_DMDET_SHIFT (0x00000004u) - -#define CONTROL_USB_STS0_CDET_DPDET (0x00000008u) -#define CONTROL_USB_STS0_CDET_DPDET_SHIFT (0x00000003u) - -#define CONTROL_USB_STS0_CHGDETDONE (0x00000001u) -#define CONTROL_USB_STS0_CHGDETDONE_SHIFT (0x00000000u) - -#define CONTROL_USB_STS0_CHGDETECT (0x00000002u) -#define CONTROL_USB_STS0_CHGDETECT_SHIFT (0x00000001u) - -#define CONTROL_USB_STS0_CHGDETSTS (0x000000E0u) -#define CONTROL_USB_STS0_CHGDETSTS_SHIFT (0x00000005u) - - -/* USB_CTRL1 */ -#define CONTROL_USB_CTRL1_CDET_EXTCTL (0x00000400u) -#define CONTROL_USB_CTRL1_CDET_EXTCTL_SHIFT (0x0000000Au) - -#define CONTROL_USB_CTRL1_CHGDET_DIS (0x00000004u) -#define CONTROL_USB_CTRL1_CHGDET_DIS_SHIFT (0x00000002u) - -#define CONTROL_USB_CTRL1_CHGDET_RSTRT (0x00000008u) -#define CONTROL_USB_CTRL1_CHGDET_RSTRT_SHIFT (0x00000003u) - -#define CONTROL_USB_CTRL1_CHGISINK_EN (0x00000040u) -#define CONTROL_USB_CTRL1_CHGISINK_EN_SHIFT (0x00000006u) - -#define CONTROL_USB_CTRL1_CHGVSRC_EN (0x00000080u) -#define CONTROL_USB_CTRL1_CHGVSRC_EN_SHIFT (0x00000007u) - -#define CONTROL_USB_CTRL1_CM_PWRDN (0x00000001u) -#define CONTROL_USB_CTRL1_CM_PWRDN_SHIFT (0x00000000u) - -#define CONTROL_USB_CTRL1_DATAPOLARITY_INV (0x00800000u) -#define CONTROL_USB_CTRL1_DATAPOLARITY_INV_SHIFT (0x00000017u) - -#define CONTROL_USB_CTRL1_DMGPIO_PD (0x00040000u) -#define CONTROL_USB_CTRL1_DMGPIO_PD_SHIFT (0x00000012u) - -#define CONTROL_USB_CTRL1_DMPULLUP (0x00000100u) -#define CONTROL_USB_CTRL1_DMPULLUP_SHIFT (0x00000008u) - -#define CONTROL_USB_CTRL1_DPGPIO_PD (0x00020000u) -#define CONTROL_USB_CTRL1_DPGPIO_PD_SHIFT (0x00000011u) - -#define CONTROL_USB_CTRL1_DPPULLUP (0x00000200u) -#define CONTROL_USB_CTRL1_DPPULLUP_SHIFT (0x00000009u) - -#define CONTROL_USB_CTRL1_GPIOMODE (0x00001000u) -#define CONTROL_USB_CTRL1_GPIOMODE_SHIFT (0x0000000Cu) - -#define CONTROL_USB_CTRL1_GPIO_SIG_CROSS (0x00004000u) -#define CONTROL_USB_CTRL1_GPIO_SIG_CROSS_SHIFT (0x0000000Eu) - -#define CONTROL_USB_CTRL1_GPIO_SIG_INV (0x00002000u) -#define CONTROL_USB_CTRL1_GPIO_SIG_INV_SHIFT (0x0000000Du) - -#define CONTROL_USB_CTRL1_OTGSESSENDEN (0x00100000u) -#define CONTROL_USB_CTRL1_OTGSESSENDEN_SHIFT (0x00000014u) - -#define CONTROL_USB_CTRL1_OTGVDET_EN (0x00080000u) -#define CONTROL_USB_CTRL1_OTGVDET_EN_SHIFT (0x00000013u) - -#define CONTROL_USB_CTRL1_OTG_PWRDN (0x00000002u) -#define CONTROL_USB_CTRL1_OTG_PWRDN_SHIFT (0x00000001u) - -#define CONTROL_USB_CTRL1_RSVD2 (0x00008000u) -#define CONTROL_USB_CTRL1_RSVD2_SHIFT (0x0000000Fu) - -#define CONTROL_USB_CTRL1_RSVD3 (0x00010000u) -#define CONTROL_USB_CTRL1_RSVD3_SHIFT (0x00000010u) - -#define CONTROL_USB_CTRL1_SINKONDP (0x00000020u) -#define CONTROL_USB_CTRL1_SINKONDP_SHIFT (0x00000005u) - -#define CONTROL_USB_CTRL1_SPAREIN (0xFF000000u) -#define CONTROL_USB_CTRL1_SPAREIN_SHIFT (0x00000018u) - -#define CONTROL_USB_CTRL1_SRCONDM (0x00000010u) -#define CONTROL_USB_CTRL1_SRCONDM_SHIFT (0x00000004u) - -#define CONTROL_USB_CTRL1_USB_PHY_SMA1 (0x00200000u) -#define CONTROL_USB_CTRL1_USB_PHY_SMA1_SHIFT (0x00000015u) - -#define CONTROL_USB_CTRL1_USB_PHY_SMA2 (0x00400000u) -#define CONTROL_USB_CTRL1_USB_PHY_SMA2_SHIFT (0x00000016u) - - -/* USB_STS1 */ -#define CONTROL_USB_STS1_CDET_DATADET (0x00000004u) -#define CONTROL_USB_STS1_CDET_DATADET_SHIFT (0x00000002u) - -#define CONTROL_USB_STS1_CDET_DMDET (0x00000010u) -#define CONTROL_USB_STS1_CDET_DMDET_SHIFT (0x00000004u) - -#define CONTROL_USB_STS1_CDET_DPDET (0x00000008u) -#define CONTROL_USB_STS1_CDET_DPDET_SHIFT (0x00000003u) - -#define CONTROL_USB_STS1_CHGDETDONE (0x00000001u) -#define CONTROL_USB_STS1_CHGDETDONE_SHIFT (0x00000000u) - -#define CONTROL_USB_STS1_CHGDETECT (0x00000002u) -#define CONTROL_USB_STS1_CHGDETECT_SHIFT (0x00000001u) - -#define CONTROL_USB_STS1_CHGDETSTS (0x000000E0u) -#define CONTROL_USB_STS1_CHGDETSTS_SHIFT (0x00000005u) - - -/* MAC_ID0_LO */ -#define CONTROL_MAC_ID0_LO_MACADDR_15_8 (0x000000FFu) -#define CONTROL_MAC_ID0_LO_MACADDR_15_8_SHIFT (0x00000000u) - -#define CONTROL_MAC_ID0_LO_MACADDR_7_0 (0x0000FF00u) -#define CONTROL_MAC_ID0_LO_MACADDR_7_0_SHIFT (0x00000008u) - - -/* MAC_ID0_HI */ -#define CONTROL_MAC_ID0_HI_MACADDR_23_16 (0xFF000000u) -#define CONTROL_MAC_ID0_HI_MACADDR_23_16_SHIFT (0x00000018u) - -#define CONTROL_MAC_ID0_HI_MACADDR_31_24 (0x00FF0000u) -#define CONTROL_MAC_ID0_HI_MACADDR_31_24_SHIFT (0x00000010u) - -#define CONTROL_MAC_ID0_HI_MACADDR_39_32 (0x0000FF00u) -#define CONTROL_MAC_ID0_HI_MACADDR_39_32_SHIFT (0x00000008u) - -#define CONTROL_MAC_ID0_HI_MACADDR_47_40 (0x000000FFu) -#define CONTROL_MAC_ID0_HI_MACADDR_47_40_SHIFT (0x00000000u) - - -/* MAC_ID1_LO */ -#define CONTROL_MAC_ID1_LO_MACADDR_15_8 (0x000000FFu) -#define CONTROL_MAC_ID1_LO_MACADDR_15_8_SHIFT (0x00000000u) - -#define CONTROL_MAC_ID1_LO_MACADDR_7_0 (0x0000FF00u) -#define CONTROL_MAC_ID1_LO_MACADDR_7_0_SHIFT (0x00000008u) - - -/* MAC_ID1_HI */ -#define CONTROL_MAC_ID1_HI_MACADDR_23_16 (0xFF000000u) -#define CONTROL_MAC_ID1_HI_MACADDR_23_16_SHIFT (0x00000018u) - -#define CONTROL_MAC_ID1_HI_MACADDR_31_24 (0x00FF0000u) -#define CONTROL_MAC_ID1_HI_MACADDR_31_24_SHIFT (0x00000010u) - -#define CONTROL_MAC_ID1_HI_MACADDR_39_32 (0x0000FF00u) -#define CONTROL_MAC_ID1_HI_MACADDR_39_32_SHIFT (0x00000008u) - -#define CONTROL_MAC_ID1_HI_MACADDR_47_40 (0x000000FFu) -#define CONTROL_MAC_ID1_HI_MACADDR_47_40_SHIFT (0x00000000u) - - -/* DCAN_RAMINIT */ -#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_DONE (0x00000100u) -#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_DONE_SHIFT (0x00000008u) - -#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_START (0x00000001u) -#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_START_SHIFT (0x00000000u) - -#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_DONE (0x00000200u) -#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_DONE_SHIFT (0x00000009u) - -#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_START (0x00000002u) -#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_START_SHIFT (0x00000001u) - -#define CONTROL_DCAN_RAMINIT_RSVD2 (0xFFFFFC00u) -#define CONTROL_DCAN_RAMINIT_RSVD2_SHIFT (0x0000000Au) - - -/* USB_WKUP_CTRL */ -#define CONTROL_USB_WKUP_CTRL_PHY0_WUEN (0x00000001u) -#define CONTROL_USB_WKUP_CTRL_PHY0_WUEN_SHIFT (0x00000000u) - -#define CONTROL_USB_WKUP_CTRL_PHY1_WUEN (0x00000100u) -#define CONTROL_USB_WKUP_CTRL_PHY1_WUEN_SHIFT (0x00000008u) - -#define CONTROL_USB_WKUP_CTRL_RSVD2 (0xFFFFFE00u) -#define CONTROL_USB_WKUP_CTRL_RSVD2_SHIFT (0x00000009u) - - -/* GMII_SEL */ -#define CONTROL_GMII_SEL_GMII1_SEL (0x00000003u) -#define CONTROL_GMII_SEL_GMII1_SEL_SHIFT (0x00000000u) - -#define CONTROL_GMII_SEL_GMII2_SEL (0x0000000Cu) -#define CONTROL_GMII_SEL_GMII2_SEL_SHIFT (0x00000002u) - -#define CONTROL_GMII_SEL_RGMII1_IDMODE (0x00000010u) -#define CONTROL_GMII_SEL_RGMII1_IDMODE_SHIFT (0x00000004u) - -#define CONTROL_GMII_SEL_RGMII2_IDMOE (0x00000020u) -#define CONTROL_GMII_SEL_RGMII2_IDMOE_SHIFT (0x00000005u) - -#define CONTROL_GMII_SEL_RMII1_IO_CLK_EN (0x00000040u) -#define CONTROL_GMII_SEL_RMII1_IO_CLK_EN_SHIFT (0x00000006u) - -#define CONTROL_GMII_SEL_RMII2_IO_CLK_EN (0x00000080u) -#define CONTROL_GMII_SEL_RMII2_IO_CLK_EN_SHIFT (0x00000007u) - - -/* PWMSS_CTRL */ -#define CONTROL_PWMSS_CTRL_PWMMS1_TBCLKEN (0x00000002u) -#define CONTROL_PWMSS_CTRL_PWMMS1_TBCLKEN_SHIFT (0x00000001u) - -#define CONTROL_PWMSS_CTRL_PWMSS0_TBCLKEN (0x00000001u) -#define CONTROL_PWMSS_CTRL_PWMSS0_TBCLKEN_SHIFT (0x00000000u) - -#define CONTROL_PWMSS_CTRL_PWMSS2_TBCLKEN (0x00000004u) -#define CONTROL_PWMSS_CTRL_PWMSS2_TBCLKEN_SHIFT (0x00000002u) - - -/* MREQPRIO_0 */ -#define CONTROL_MREQPRIO_0_CPSW (0x00070000u) -#define CONTROL_MREQPRIO_0_CPSW_SHIFT (0x00000010u) - -#define CONTROL_MREQPRIO_0_PRUSS1_PRU0 (0x00000700u) -#define CONTROL_MREQPRIO_0_PRUSS1_PRU0_SHIFT (0x00000008u) - -#define CONTROL_MREQPRIO_0_PRUSS1_PRU1 (0x00007000u) -#define CONTROL_MREQPRIO_0_PRUSS1_PRU1_SHIFT (0x0000000Cu) - -#define CONTROL_MREQPRIO_0_RSVD2 (0x00000080u) -#define CONTROL_MREQPRIO_0_RSVD2_SHIFT (0x00000007u) - -#define CONTROL_MREQPRIO_0_RSVD3 (0x00000800u) -#define CONTROL_MREQPRIO_0_RSVD3_SHIFT (0x0000000Bu) - -#define CONTROL_MREQPRIO_0_RSVD4 (0x00008000u) -#define CONTROL_MREQPRIO_0_RSVD4_SHIFT (0x0000000Fu) - -#define CONTROL_MREQPRIO_0_RSVD5 (0x00080000u) -#define CONTROL_MREQPRIO_0_RSVD5_SHIFT (0x00000013u) - -#define CONTROL_MREQPRIO_0_RSVD6 (0x00800000u) -#define CONTROL_MREQPRIO_0_RSVD6_SHIFT (0x00000017u) - -#define CONTROL_MREQPRIO_0_RSVD7 (0x08000000u) -#define CONTROL_MREQPRIO_0_RSVD7_SHIFT (0x0000001Bu) - -#define CONTROL_MREQPRIO_0_RSVD8 (0x80000000u) -#define CONTROL_MREQPRIO_0_RSVD8_SHIFT (0x0000001Fu) - -#define CONTROL_MREQPRIO_0_SAB_INIT0 (0x00000007u) -#define CONTROL_MREQPRIO_0_SAB_INIT0_SHIFT (0x00000000u) - -#define CONTROL_MREQPRIO_0_SAB_INIT1 (0x00000070u) -#define CONTROL_MREQPRIO_0_SAB_INIT1_SHIFT (0x00000004u) - -#define CONTROL_MREQPRIO_0_SGX (0x70000000u) -#define CONTROL_MREQPRIO_0_SGX_SHIFT (0x0000001Cu) - -#define CONTROL_MREQPRIO_0_USB0 (0x00700000u) -#define CONTROL_MREQPRIO_0_USB0_SHIFT (0x00000014u) - -#define CONTROL_MREQPRIO_0_USB1 (0x07000000u) -#define CONTROL_MREQPRIO_0_USB1_SHIFT (0x00000018u) - - -/* MREQPRIO_1 */ -#define CONTROL_MREQPRIO_1_EXP (0x00000007u) -#define CONTROL_MREQPRIO_1_EXP_SHIFT (0x00000000u) - - -/* HW_EVENT_SEL_GRP1 */ -#define CONTROL_HW_EVENT_SEL_GRP1_EVENT1 (0x000000FFu) -#define CONTROL_HW_EVENT_SEL_GRP1_EVENT1_SHIFT (0x00000000u) - -#define CONTROL_HW_EVENT_SEL_GRP1_EVENT2 (0x0000FF00u) -#define CONTROL_HW_EVENT_SEL_GRP1_EVENT2_SHIFT (0x00000008u) - -#define CONTROL_HW_EVENT_SEL_GRP1_EVENT3 (0x00FF0000u) -#define CONTROL_HW_EVENT_SEL_GRP1_EVENT3_SHIFT (0x00000010u) - -#define CONTROL_HW_EVENT_SEL_GRP1_EVENT4 (0xFF000000u) -#define CONTROL_HW_EVENT_SEL_GRP1_EVENT4_SHIFT (0x00000018u) - - -/* HW_EVENT_SEL_GRP2 */ -#define CONTROL_HW_EVENT_SEL_GRP2_EVENT5 (0x000000FFu) -#define CONTROL_HW_EVENT_SEL_GRP2_EVENT5_SHIFT (0x00000000u) - -#define CONTROL_HW_EVENT_SEL_GRP2_EVENT6 (0x0000FF00u) -#define CONTROL_HW_EVENT_SEL_GRP2_EVENT6_SHIFT (0x00000008u) - -#define CONTROL_HW_EVENT_SEL_GRP2_EVENT7 (0x00FF0000u) -#define CONTROL_HW_EVENT_SEL_GRP2_EVENT7_SHIFT (0x00000010u) - -#define CONTROL_HW_EVENT_SEL_GRP2_EVENT8 (0xFF000000u) -#define CONTROL_HW_EVENT_SEL_GRP2_EVENT8_SHIFT (0x00000018u) - - -/* HW_EVENT_SEL_GRP3 */ -#define CONTROL_HW_EVENT_SEL_GRP3_EVENT10 (0x0000FF00u) -#define CONTROL_HW_EVENT_SEL_GRP3_EVENT10_SHIFT (0x00000008u) - -#define CONTROL_HW_EVENT_SEL_GRP3_EVENT11 (0x00FF0000u) -#define CONTROL_HW_EVENT_SEL_GRP3_EVENT11_SHIFT (0x00000010u) - -#define CONTROL_HW_EVENT_SEL_GRP3_EVENT12 (0xFF000000u) -#define CONTROL_HW_EVENT_SEL_GRP3_EVENT12_SHIFT (0x00000018u) - -#define CONTROL_HW_EVENT_SEL_GRP3_EVENT9 (0x000000FFu) -#define CONTROL_HW_EVENT_SEL_GRP3_EVENT9_SHIFT (0x00000000u) - - -/* HW_EVENT_SEL_GRP4 */ -#define CONTROL_HW_EVENT_SEL_GRP4_EVENT13 (0x000000FFu) -#define CONTROL_HW_EVENT_SEL_GRP4_EVENT13_SHIFT (0x00000000u) - -#define CONTROL_HW_EVENT_SEL_GRP4_EVENT14 (0x0000FF00u) -#define CONTROL_HW_EVENT_SEL_GRP4_EVENT14_SHIFT (0x00000008u) - -#define CONTROL_HW_EVENT_SEL_GRP4_EVENT15 (0x00FF0000u) -#define CONTROL_HW_EVENT_SEL_GRP4_EVENT15_SHIFT (0x00000010u) - -#define CONTROL_HW_EVENT_SEL_GRP4_EVENT16 (0xFF000000u) -#define CONTROL_HW_EVENT_SEL_GRP4_EVENT16_SHIFT (0x00000018u) - - -/* SMRT_CTRL */ -#define CONTROL_SMRT_CTRL_SR0_SLEEP (0x00000001u) -#define CONTROL_SMRT_CTRL_SR0_SLEEP_SHIFT (0x00000000u) - -#define CONTROL_SMRT_CTRL_SR1_SLEEP (0x00000002u) -#define CONTROL_SMRT_CTRL_SR1_SLEEP_SHIFT (0x00000001u) - - -/* SABTOOTH_HW_DEBUG_SEL */ -#define CONTROL_SABTOOTH_HW_DEBUG_SEL_HW_DBG_GATE_EN (0x00000200u) -#define CONTROL_SABTOOTH_HW_DEBUG_SEL_HW_DBG_GATE_EN_SHIFT (0x00000009u) - -#define CONTROL_SABTOOTH_HW_DEBUG_SEL_HW_DBG_SEL (0x0000000Fu) -#define CONTROL_SABTOOTH_HW_DEBUG_SEL_HW_DBG_SEL_SHIFT (0x00000000u) - -#define CONTROL_SABTOOTH_HW_DEBUG_SEL_RSVD3 (0xFFFFFC00u) -#define CONTROL_SABTOOTH_HW_DEBUG_SEL_RSVD3_SHIFT (0x0000000Au) - - -/* SABTOOTH_HW_DBG_INFO */ -#define CONTROL_SABTOOTH_HW_DBG_INFO_HW_DBG_INFO (0xFFFFFFFFu) -#define CONTROL_SABTOOTH_HW_DBG_INFO_HW_DBG_INFO_SHIFT (0x00000000u) - - -/* MRGN_MODE0 */ -#define CONTROL_MRGN_MODE0_MMODE0 (0x00000003u) -#define CONTROL_MRGN_MODE0_MMODE0_SHIFT (0x00000000u) - -#define CONTROL_MRGN_MODE0_MMODE1 (0x0000000Cu) -#define CONTROL_MRGN_MODE0_MMODE1_SHIFT (0x00000002u) - -#define CONTROL_MRGN_MODE0_MMODE10 (0x00300000u) -#define CONTROL_MRGN_MODE0_MMODE10_SHIFT (0x00000014u) - -#define CONTROL_MRGN_MODE0_MMODE11 (0x00C00000u) -#define CONTROL_MRGN_MODE0_MMODE11_SHIFT (0x00000016u) - -#define CONTROL_MRGN_MODE0_MMODE12 (0x03000000u) -#define CONTROL_MRGN_MODE0_MMODE12_SHIFT (0x00000018u) - -#define CONTROL_MRGN_MODE0_MMODE13 (0x0C000000u) -#define CONTROL_MRGN_MODE0_MMODE13_SHIFT (0x0000001Au) - -#define CONTROL_MRGN_MODE0_MMODE14 (0x30000000u) -#define CONTROL_MRGN_MODE0_MMODE14_SHIFT (0x0000001Cu) - -#define CONTROL_MRGN_MODE0_MMODE15 (0xC0000000u) -#define CONTROL_MRGN_MODE0_MMODE15_SHIFT (0x0000001Eu) - -#define CONTROL_MRGN_MODE0_MMODE2 (0x00000030u) -#define CONTROL_MRGN_MODE0_MMODE2_SHIFT (0x00000004u) - -#define CONTROL_MRGN_MODE0_MMODE3 (0x000000C0u) -#define CONTROL_MRGN_MODE0_MMODE3_SHIFT (0x00000006u) - -#define CONTROL_MRGN_MODE0_MMODE4 (0x00000300u) -#define CONTROL_MRGN_MODE0_MMODE4_SHIFT (0x00000008u) - -#define CONTROL_MRGN_MODE0_MMODE5 (0x00000C00u) -#define CONTROL_MRGN_MODE0_MMODE5_SHIFT (0x0000000Au) - -#define CONTROL_MRGN_MODE0_MMODE6 (0x00003000u) -#define CONTROL_MRGN_MODE0_MMODE6_SHIFT (0x0000000Cu) - -#define CONTROL_MRGN_MODE0_MMODE7 (0x0000C000u) -#define CONTROL_MRGN_MODE0_MMODE7_SHIFT (0x0000000Eu) - -#define CONTROL_MRGN_MODE0_MMODE8 (0x00030000u) -#define CONTROL_MRGN_MODE0_MMODE8_SHIFT (0x00000010u) - -#define CONTROL_MRGN_MODE0_MMODE9 (0x000C0000u) -#define CONTROL_MRGN_MODE0_MMODE9_SHIFT (0x00000012u) - - -/* MRGN_MODE1 */ -#define CONTROL_MRGN_MODE1_MMODE16 (0x00000003u) -#define CONTROL_MRGN_MODE1_MMODE16_SHIFT (0x00000000u) - -#define CONTROL_MRGN_MODE1_MMODE17 (0x0000000Cu) -#define CONTROL_MRGN_MODE1_MMODE17_SHIFT (0x00000002u) - -#define CONTROL_MRGN_MODE1_MMODE18 (0x00000030u) -#define CONTROL_MRGN_MODE1_MMODE18_SHIFT (0x00000004u) - -#define CONTROL_MRGN_MODE1_MMODE19 (0x000000C0u) -#define CONTROL_MRGN_MODE1_MMODE19_SHIFT (0x00000006u) - - -/* VDD_MPU_OPP_050 */ -#define CONTROL_VDD_MPU_OPP_050_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_MPU_OPP_050_NTARGET_SHIFT (0x00000000u) - - -/* VDD_MPU_OPP_100 */ -#define CONTROL_VDD_MPU_OPP_100_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_MPU_OPP_100_NTARGET_SHIFT (0x00000000u) - - -/* VDD_MPU_OPP_119 */ -#define CONTROL_VDD_MPU_OPP_119_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_MPU_OPP_119_NTARGET_SHIFT (0x00000000u) - - -/* VDD_MPU_OPP_TURBO */ -#define CONTROL_VDD_MPU_OPP_TURBO_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_MPU_OPP_TURBO_NTARGET_SHIFT (0x00000000u) - - -/* VDD_CORE_OPP_050 */ -#define CONTROL_VDD_CORE_OPP_050_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_CORE_OPP_050_NTARGET_SHIFT (0x00000000u) - - -/* VDD_CORE_OPP_100 */ -#define CONTROL_VDD_CORE_OPP_100_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_CORE_OPP_100_NTARGET_SHIFT (0x00000000u) - - -/* BB_SCALE */ -#define CONTROL_BB_SCALE_BBIAS (0x00000003u) -#define CONTROL_BB_SCALE_BBIAS_SHIFT (0x00000000u) - -#define CONTROL_BB_SCALE_RSVD2 (0xFFFFF000u) -#define CONTROL_BB_SCALE_RSVD2_SHIFT (0x0000000Cu) - -#define CONTROL_BB_SCALE_SCALE (0x00000F00u) -#define CONTROL_BB_SCALE_SCALE_SHIFT (0x00000008u) - - -/* USB_VID_PID */ -#define CONTROL_USB_VID_PID_USB_PID (0x0000FFFFu) -#define CONTROL_USB_VID_PID_USB_PID_SHIFT (0x00000000u) - -#define CONTROL_USB_VID_PID_USB_VID (0xFFFF0000u) -#define CONTROL_USB_VID_PID_USB_VID_SHIFT (0x00000010u) - - -/* EFUSE_SMA */ -#define CONTROL_EFUSE_SMA_EFUSE_SMA (0xFFFFFFFFu) -#define CONTROL_EFUSE_SMA_EFUSE_SMA_SHIFT (0x00000000u) - - -/* CONF_GPMC_ADx */ -#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD0 */ -#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD1 */ -#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD2 */ -#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD3 */ -#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD4 */ -#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD5 */ -#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD6 */ -#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD7 */ -#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD8 */ -#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD9 */ -#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD10 */ -#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD11 */ -#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD12 */ -#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD13 */ -#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD14 */ -#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_AD15 */ -#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_A0 */ -#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_A1 */ -#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_A2 */ -#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_A3 */ -#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_A4 */ -#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_A5 */ -#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_A6 */ -#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_A7 */ -#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_A8 */ -#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_A9 */ -#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_A10 */ -#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_A11 */ -#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_WAIT0 */ -#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_WPN */ -#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_BE1N */ -#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_CSN0 */ -#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_CSN1 */ -#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_CSN2 */ -#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_CSN3 */ -#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_CLK */ -#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_ADVN_ALE */ -#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_OEN_REN */ -#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_WEN */ -#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_GPMC_BE0N_CLE */ -#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE (0x00000007u) -#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN (0x00000008u) -#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RSVD (0x000FFF80u) -#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE (0x00000020u) -#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA0 */ -#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA1 */ -#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA2 */ -#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA3 */ -#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA4 */ -#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA5 */ -#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA6 */ -#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA7 */ -#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA8 */ -#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA9 */ -#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA10 */ -#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA11 */ -#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA12 */ -#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA13 */ -#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA14 */ -#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA15 */ -#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA16 */ -#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA17 */ -#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA18 */ -#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_SLEWCTRL_SHIFT (0x00000006u) - -/* CONF_LCD_DATA19 */ -#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA20 */ -#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_SLEWCTRL_SHIFT (0x00000006u) - -/* CONF_LCD_DATA21 */ -#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_DATA22 */ -#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_SLEWCTRL_SHIFT (0x00000006u) - -/* CONF_LCD_DATA20 */ -#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_SLEWCTRL_SHIFT (0x00000006u) - - - - - - - - - -/* CONF_LCD_VSYNC */ -#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_HSYNC */ -#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_PCLK */ -#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_LCD_AC_BIAS_EN */ -#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_MMODE (0x00000007u) -#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUDEN (0x00000008u) -#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RSVD (0x000FFF80u) -#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MMC0_DAT3 */ -#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_MMODE (0x00000007u) -#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUDEN (0x00000008u) -#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RSVD (0x000FFF80u) -#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MMC0_DAT2 */ -#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_MMODE (0x00000007u) -#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUDEN (0x00000008u) -#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RSVD (0x000FFF80u) -#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MMC0_DAT1 */ -#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_MMODE (0x00000007u) -#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUDEN (0x00000008u) -#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RSVD (0x000FFF80u) -#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MMC0_DAT0 */ -#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_MMODE (0x00000007u) -#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUDEN (0x00000008u) -#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RSVD (0x000FFF80u) -#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MMC0_CLK */ -#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_MMODE (0x00000007u) -#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUDEN (0x00000008u) -#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RSVD (0x000FFF80u) -#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MMC0_CMD */ -#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_MMODE (0x00000007u) -#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUDEN (0x00000008u) -#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RSVD (0x000FFF80u) -#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_COL */ -#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_CRS */ -#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_RXERR */ -#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_TXEN */ -#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_RXDV */ -#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_TXD3 */ -#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_TXD2 */ -#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_TXD1 */ -#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_TXD0 */ -#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_TXCLK */ -#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_RXCLK */ -#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_RXD3 */ -#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_RXD2 */ -#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_RXD1 */ -#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MII1_RXD0 */ -#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_MMODE (0x00000007u) -#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUDEN (0x00000008u) -#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RSVD (0x000FFF80u) -#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_RMII1_REFCLK */ -#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_MMODE (0x00000007u) -#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUDEN (0x00000008u) -#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RSVD (0x000FFF80u) -#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE (0x00000020u) -#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MDIO_DATA */ -#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_MMODE (0x00000007u) -#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUDEN (0x00000008u) -#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RSVD (0x000FFF80u) -#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MDIO_CLK */ -#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_MMODE (0x00000007u) -#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUDEN (0x00000008u) -#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_RSVD (0x000FFF80u) -#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_SPI0_SCLK */ -#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_MMODE (0x00000007u) -#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUDEN (0x00000008u) -#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RSVD (0x000FFF80u) -#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE (0x00000020u) -#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_SPI0_D0 */ -#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_MMODE (0x00000007u) -#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_PUDEN (0x00000008u) -#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_RSVD (0x000FFF80u) -#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_SPI0_D1 */ -#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_MMODE (0x00000007u) -#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUDEN (0x00000008u) -#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RSVD (0x000FFF80u) -#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_SPI0_CS0 */ -#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_MMODE (0x00000007u) -#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUDEN (0x00000008u) -#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RSVD (0x000FFF80u) -#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_SPI0_CS1 */ -#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_MMODE (0x00000007u) -#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUDEN (0x00000008u) -#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RSVD (0x000FFF80u) -#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_ECAP0_IN_PWM0_OUT */ -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_MMODE (0x00000007u) -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUDEN (0x00000008u) -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RSVD (0x000FFF80u) -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RXACTIVE (0x00000020u) -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_UART0_CTSN */ -#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_MMODE (0x00000007u) -#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUDEN (0x00000008u) -#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RSVD (0x000FFF80u) -#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_UART0_RTSN */ -#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_MMODE (0x00000007u) -#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUDEN (0x00000008u) -#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RSVD (0x000FFF80u) -#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_UART0_RXD */ -#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_MMODE (0x00000007u) -#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUDEN (0x00000008u) -#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RSVD (0x000FFF80u) -#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RXACTIVE (0x00000020u) -#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_UART0_TXD */ -#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_MMODE (0x00000007u) -#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUDEN (0x00000008u) -#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RSVD (0x000FFF80u) -#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RXACTIVE (0x00000020u) -#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_UART1_CTSN */ -#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_MMODE (0x00000007u) -#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUDEN (0x00000008u) -#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RSVD (0x000FFF80u) -#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_UART1_RTSN */ -#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_MMODE (0x00000007u) -#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUDEN (0x00000008u) -#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RSVD (0x000FFF80u) -#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_UART1_RXD */ -#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_MMODE (0x00000007u) -#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUDEN (0x00000008u) -#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RSVD (0x000FFF80u) -#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RXACTIVE (0x00000020u) -#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_UART1_TXD */ -#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_MMODE (0x00000007u) -#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUDEN (0x00000008u) -#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_RSVD (0x000FFF80u) -#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_RXACTIVE (0x00000020u) -#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_I2C0_SDA */ -#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_MMODE (0x00000007u) -#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUDEN (0x00000008u) -#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RSVD (0x000FFF80u) -#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RXACTIVE (0x00000020u) -#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_I2C0_SCL */ -#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_MMODE (0x00000007u) -#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUDEN (0x00000008u) -#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RSVD (0x000FFF80u) -#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RXACTIVE (0x00000020u) -#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_I2C0_SDA */ -#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_MMODE (0x00000007u) -#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_PUDEN (0x00000008u) -#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_RSVD (0x000FFF80u) -#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_RXACTIVE (0x00000020u) -#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_I2C0_SCL */ -#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_MMODE (0x00000007u) -#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_PUDEN (0x00000008u) -#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_RSVD (0x000FFF80u) -#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_RXACTIVE (0x00000020u) -#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_SLEWCTRL_SHIFT (0x00000006u) - - - -/* CONF_MCASP0_ACLKX */ -#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_MMODE (0x00000007u) -#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUDEN (0x00000008u) -#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RSVD (0x000FFF80u) -#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MCASP0_FSX */ -#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_MMODE (0x00000007u) -#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUDEN (0x00000008u) -#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RSVD (0x000FFF80u) -#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MCASP0_AXR0 */ -#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_MMODE (0x00000007u) -#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUDEN (0x00000008u) -#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RSVD (0x000FFF80u) -#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MCASP0_AHCLKR */ -#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_MMODE (0x00000007u) -#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUDEN (0x00000008u) -#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RSVD (0x000FFF80u) -#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MCASP0_ACLKR */ -#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_MMODE (0x00000007u) -#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_PUDEN (0x00000008u) -#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RSVD (0x000FFF80u) -#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MCASP0_FSR */ -#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_MMODE (0x00000007u) -#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_PUDEN (0x00000008u) -#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RSVD (0x000FFF80u) -#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MCASP0_AXR1 */ -#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_MMODE (0x00000007u) -#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_PUDEN (0x00000008u) -#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RSVD (0x000FFF80u) -#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_MCASP0_AHCLKX */ -#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_MMODE (0x00000007u) -#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_PUDEN (0x00000008u) -#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RSVD (0x000FFF80u) -#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RXACTIVE (0x00000020u) -#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_XDMA_EVENT_INTR0 */ -#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_MMODE (0x00000007u) -#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUDEN (0x00000008u) -#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RSVD (0x000FFF80u) -#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_XDMA_EVENT_INTR1 */ -#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_MMODE (0x00000007u) -#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_PUDEN (0x00000008u) -#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_RSVD (0x000FFF80u) -#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_NRESETIN_OUT */ -#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_MMODE (0x00000007u) -#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_PUDEN (0x00000008u) -#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_RSVD (0x000FFF80u) -#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_RXACTIVE (0x00000020u) -#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_PORZ */ -#define CONTROL_CONF_PORZ_CONF_PORZ_MMODE (0x00000007u) -#define CONTROL_CONF_PORZ_CONF_PORZ_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_PORZ_CONF_PORZ_PUDEN (0x00000008u) -#define CONTROL_CONF_PORZ_CONF_PORZ_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_PORZ_CONF_PORZ_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_PORZ_CONF_PORZ_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_PORZ_CONF_PORZ_RSVD (0x000FFF80u) -#define CONTROL_CONF_PORZ_CONF_PORZ_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_PORZ_CONF_PORZ_RXACTIVE (0x00000020u) -#define CONTROL_CONF_PORZ_CONF_PORZ_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_PORZ_CONF_PORZ_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_PORZ_CONF_PORZ_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_NNMI */ -#define CONTROL_CONF_NNMI_CONF_NNMI_MMODE (0x00000007u) -#define CONTROL_CONF_NNMI_CONF_NNMI_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_NNMI_CONF_NNMI_PUDEN (0x00000008u) -#define CONTROL_CONF_NNMI_CONF_NNMI_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_NNMI_CONF_NNMI_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_NNMI_CONF_NNMI_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_NNMI_CONF_NNMI_RSVD (0x000FFF80u) -#define CONTROL_CONF_NNMI_CONF_NNMI_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_NNMI_CONF_NNMI_RXACTIVE (0x00000020u) -#define CONTROL_CONF_NNMI_CONF_NNMI_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_NNMI_CONF_NNMI_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_NNMI_CONF_NNMI_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_OSC0_IN */ -#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_MMODE (0x00000007u) -#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_PUDEN (0x00000008u) -#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_RSVD (0x000FFF80u) -#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_OSC0_OUT */ -#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_MMODE (0x00000007u) -#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_PUDEN (0x00000008u) -#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_RSVD (0x000FFF80u) -#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_RXACTIVE (0x00000020u) -#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_OSC0_VSS */ -#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_MMODE (0x00000007u) -#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_PUDEN (0x00000008u) -#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_RSVD (0x000FFF80u) -#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_RXACTIVE (0x00000020u) -#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_TMS */ -#define CONTROL_CONF_TMS_CONF_TMS_MMODE (0x00000007u) -#define CONTROL_CONF_TMS_CONF_TMS_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_TMS_CONF_TMS_PUDEN (0x00000008u) -#define CONTROL_CONF_TMS_CONF_TMS_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_TMS_CONF_TMS_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_TMS_CONF_TMS_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_TMS_CONF_TMS_RSVD (0x000FFF80u) -#define CONTROL_CONF_TMS_CONF_TMS_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_TMS_CONF_TMS_RXACTIVE (0x00000020u) -#define CONTROL_CONF_TMS_CONF_TMS_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_TMS_CONF_TMS_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_TMS_CONF_TMS_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_TDI */ -#define CONTROL_CONF_TDI_CONF_TDI_MMODE (0x00000007u) -#define CONTROL_CONF_TDI_CONF_TDI_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_TDI_CONF_TDI_PUDEN (0x00000008u) -#define CONTROL_CONF_TDI_CONF_TDI_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_TDI_CONF_TDI_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_TDI_CONF_TDI_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_TDI_CONF_TDI_RSVD (0x000FFF80u) -#define CONTROL_CONF_TDI_CONF_TDI_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_TDI_CONF_TDI_RXACTIVE (0x00000020u) -#define CONTROL_CONF_TDI_CONF_TDI_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_TDI_CONF_TDI_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_TDI_CONF_TDI_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_TDO */ -#define CONTROL_CONF_TDO_CONF_TDO_MMODE (0x00000007u) -#define CONTROL_CONF_TDO_CONF_TDO_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_TDO_CONF_TDO_PUDEN (0x00000008u) -#define CONTROL_CONF_TDO_CONF_TDO_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_TDO_CONF_TDO_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_TDO_CONF_TDO_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_TDO_CONF_TDO_RSVD (0x000FFF80u) -#define CONTROL_CONF_TDO_CONF_TDO_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_TDO_CONF_TDO_RXACTIVE (0x00000020u) -#define CONTROL_CONF_TDO_CONF_TDO_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_TDO_CONF_TDO_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_TDO_CONF_TDO_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_TCK */ -#define CONTROL_CONF_TCK_CONF_TCK_MMODE (0x00000007u) -#define CONTROL_CONF_TCK_CONF_TCK_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_TCK_CONF_TCK_PUDEN (0x00000008u) -#define CONTROL_CONF_TCK_CONF_TCK_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_TCK_CONF_TCK_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_TCK_CONF_TCK_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_TCK_CONF_TCK_RSVD (0x000FFF80u) -#define CONTROL_CONF_TCK_CONF_TCK_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_TCK_CONF_TCK_RXACTIVE (0x00000020u) -#define CONTROL_CONF_TCK_CONF_TCK_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_TCK_CONF_TCK_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_TCK_CONF_TCK_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_NTRST */ -#define CONTROL_CONF_NTRST_CONF_NTRST_MMODE (0x00000007u) -#define CONTROL_CONF_NTRST_CONF_NTRST_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_NTRST_CONF_NTRST_PUDEN (0x00000008u) -#define CONTROL_CONF_NTRST_CONF_NTRST_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_NTRST_CONF_NTRST_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_NTRST_CONF_NTRST_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_NTRST_CONF_NTRST_RSVD (0x000FFF80u) -#define CONTROL_CONF_NTRST_CONF_NTRST_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_NTRST_CONF_NTRST_RXACTIVE (0x00000020u) -#define CONTROL_CONF_NTRST_CONF_NTRST_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_NTRST_CONF_NTRST_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_NTRST_CONF_NTRST_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_EMU0 */ -#define CONTROL_CONF_EMU0_CONF_EMU0_MMODE (0x00000007u) -#define CONTROL_CONF_EMU0_CONF_EMU0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_EMU0_CONF_EMU0_PUDEN (0x00000008u) -#define CONTROL_CONF_EMU0_CONF_EMU0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_EMU0_CONF_EMU0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_EMU0_CONF_EMU0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_EMU0_CONF_EMU0_RSVD (0x000FFF80u) -#define CONTROL_CONF_EMU0_CONF_EMU0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_EMU0_CONF_EMU0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_EMU0_CONF_EMU0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_EMU0_CONF_EMU0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_EMU0_CONF_EMU0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_EMU1 */ -#define CONTROL_CONF_EMU1_CONF_EMU1_MMODE (0x00000007u) -#define CONTROL_CONF_EMU1_CONF_EMU1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_EMU1_CONF_EMU1_PUDEN (0x00000008u) -#define CONTROL_CONF_EMU1_CONF_EMU1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_EMU1_CONF_EMU1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_EMU1_CONF_EMU1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_EMU1_CONF_EMU1_RSVD (0x000FFF80u) -#define CONTROL_CONF_EMU1_CONF_EMU1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_EMU1_CONF_EMU1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_EMU1_CONF_EMU1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_EMU1_CONF_EMU1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_EMU1_CONF_EMU1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_OSC1_IN */ -#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_MMODE (0x00000007u) -#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_PUDEN (0x00000008u) -#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_RSVD (0x000FFF80u) -#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_OSC1_OUT */ -#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_MMODE (0x00000007u) -#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_PUDEN (0x00000008u) -#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_RSVD (0x000FFF80u) -#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_RXACTIVE (0x00000020u) -#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_OSC1_VSS */ -#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_MMODE (0x00000007u) -#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_PUDEN (0x00000008u) -#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_RSVD (0x000FFF80u) -#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_RXACTIVE (0x00000020u) -#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_RTC_PORZ */ -#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_MMODE (0x00000007u) -#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_PUDEN (0x00000008u) -#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_RSVD (0x000FFF80u) -#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_RXACTIVE (0x00000020u) -#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_PMIC_POWER_EN */ -#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_MMODE (0x00000007u) -#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_PUDEN (0x00000008u) -#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_RSVD (0x000FFF80u) -#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_EXT_WAKEUP */ -#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_MMODE (0x00000007u) -#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_PUDEN (0x00000008u) -#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_RSVD (0x000FFF80u) -#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_RXACTIVE (0x00000020u) -#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_ENZ_KALDO_1P8V */ -#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_MMODE (0x00000007u) -#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_PUDEN (0x00000008u) -#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_RSVD (0x000FFF80u) -#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_RXACTIVE (0x00000020u) -#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_USB0_DM */ -#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_MMODE (0x00000007u) -#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_PUDEN (0x00000008u) -#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_RSVD (0x000FFF80u) -#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_RXACTIVE (0x00000020u) -#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_USB0_DP */ -#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_MMODE (0x00000007u) -#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_PUDEN (0x00000008u) -#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_RSVD (0x000FFF80u) -#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_RXACTIVE (0x00000020u) -#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_USB0_CE */ -#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_MMODE (0x00000007u) -#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_PUDEN (0x00000008u) -#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_RSVD (0x000FFF80u) -#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_RXACTIVE (0x00000020u) -#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_USB0_ID */ -#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_MMODE (0x00000007u) -#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_PUDEN (0x00000008u) -#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_RSVD (0x000FFF80u) -#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_RXACTIVE (0x00000020u) -#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_USB0_VBUS */ -#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_MMODE (0x00000007u) -#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_PUDEN (0x00000008u) -#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_RSVD (0x000FFF80u) -#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_RXACTIVE (0x00000020u) -#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_USB0_DRVVBUS */ -#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_MMODE (0x00000007u) -#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_PUDEN (0x00000008u) -#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_RSVD (0x000FFF80u) -#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_RXACTIVE (0x00000020u) -#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_USB1_DM */ -#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_MMODE (0x00000007u) -#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_PUDEN (0x00000008u) -#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_RSVD (0x000FFF80u) -#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_RXACTIVE (0x00000020u) -#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_USB1_DP */ -#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_MMODE (0x00000007u) -#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_PUDEN (0x00000008u) -#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_RSVD (0x000FFF80u) -#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_RXACTIVE (0x00000020u) -#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_USB1_CE */ -#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_MMODE (0x00000007u) -#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_PUDEN (0x00000008u) -#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_RSVD (0x000FFF80u) -#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_RXACTIVE (0x00000020u) -#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_USB1_ID */ -#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_MMODE (0x00000007u) -#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_PUDEN (0x00000008u) -#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_RSVD (0x000FFF80u) -#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_RXACTIVE (0x00000020u) -#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_USB1_VBUS */ -#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_MMODE (0x00000007u) -#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_PUDEN (0x00000008u) -#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_RSVD (0x000FFF80u) -#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_RXACTIVE (0x00000020u) -#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_USB1_DRVVBUS */ -#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_MMODE (0x00000007u) -#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_PUDEN (0x00000008u) -#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_RSVD (0x000FFF80u) -#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_RXACTIVE (0x00000020u) -#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_RESETN */ -#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_CSN0 */ -#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_CKE */ -#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_RSVD2 (0x000FFF80u) -#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_RSVD2_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_NCK */ -#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_CASN */ -#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_RASN */ -#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_WEN */ -#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_BA0 */ -#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_BA1 */ -#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_BA2 */ -#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A0 */ -#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A1 */ -#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A2 */ -#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A3 */ -#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A4 */ -#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A5 */ -#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A6 */ -#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A7 */ -#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A8 */ -#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A9 */ -#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A10 */ -#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A11 */ -#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A12 */ -#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A13 */ -#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A14 */ -#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_A15 */ -#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_ODT */ -#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D0 */ -#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D1 */ -#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D2 */ -#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D3 */ -#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D4 */ -#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D5 */ -#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D6 */ -#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D7 */ -#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D8 */ -#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D9 */ -#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D10 */ -#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D11 */ -#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D12 */ -#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D13 */ -#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D14 */ -#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_D15 */ -#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_DQM0 */ -#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_DQM1 */ -#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_DQS0 */ -#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_DQSN0 */ -#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_DQS1 */ -#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_DQSN1 */ -#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_VREF */ -#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_VTP */ -#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_STRBEN0 */ -#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_DDR_STRBEN1 */ -#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_MMODE (0x00000007u) -#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_PUDEN (0x00000008u) -#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_RSVD (0x000FFF80u) -#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_AIN7 */ -#define CONTROL_CONF_AIN7_CONF_AIN7_MMODE (0x00000007u) -#define CONTROL_CONF_AIN7_CONF_AIN7_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_AIN7_CONF_AIN7_PUDEN (0x00000008u) -#define CONTROL_CONF_AIN7_CONF_AIN7_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_AIN7_CONF_AIN7_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_AIN7_CONF_AIN7_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_AIN7_CONF_AIN7_RSVD (0x000FFF80u) -#define CONTROL_CONF_AIN7_CONF_AIN7_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_AIN7_CONF_AIN7_RXACTIVE (0x00000020u) -#define CONTROL_CONF_AIN7_CONF_AIN7_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_AIN7_CONF_AIN7_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_AIN7_CONF_AIN7_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_AIN6 */ -#define CONTROL_CONF_AIN6_CONF_AIN6_MMODE (0x00000007u) -#define CONTROL_CONF_AIN6_CONF_AIN6_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_AIN6_CONF_AIN6_PUDEN (0x00000008u) -#define CONTROL_CONF_AIN6_CONF_AIN6_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_AIN6_CONF_AIN6_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_AIN6_CONF_AIN6_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_AIN6_CONF_AIN6_RSVD (0x000FFF80u) -#define CONTROL_CONF_AIN6_CONF_AIN6_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_AIN6_CONF_AIN6_RXACTIVE (0x00000020u) -#define CONTROL_CONF_AIN6_CONF_AIN6_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_AIN6_CONF_AIN6_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_AIN6_CONF_AIN6_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_AIN5 */ -#define CONTROL_CONF_AIN5_CONF_AIN5_MMODE (0x00000007u) -#define CONTROL_CONF_AIN5_CONF_AIN5_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_AIN5_CONF_AIN5_PUDEN (0x00000008u) -#define CONTROL_CONF_AIN5_CONF_AIN5_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_AIN5_CONF_AIN5_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_AIN5_CONF_AIN5_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_AIN5_CONF_AIN5_RSVD (0x000FFF80u) -#define CONTROL_CONF_AIN5_CONF_AIN5_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_AIN5_CONF_AIN5_RXACTIVE (0x00000020u) -#define CONTROL_CONF_AIN5_CONF_AIN5_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_AIN5_CONF_AIN5_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_AIN5_CONF_AIN5_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_AIN4 */ -#define CONTROL_CONF_AIN4_CONF_AIN4_MMODE (0x00000007u) -#define CONTROL_CONF_AIN4_CONF_AIN4_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_AIN4_CONF_AIN4_PUDEN (0x00000008u) -#define CONTROL_CONF_AIN4_CONF_AIN4_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_AIN4_CONF_AIN4_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_AIN4_CONF_AIN4_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_AIN4_CONF_AIN4_RSVD (0x000FFF80u) -#define CONTROL_CONF_AIN4_CONF_AIN4_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_AIN4_CONF_AIN4_RXACTIVE (0x00000020u) -#define CONTROL_CONF_AIN4_CONF_AIN4_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_AIN4_CONF_AIN4_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_AIN4_CONF_AIN4_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_AIN3 */ -#define CONTROL_CONF_AIN3_CONF_AIN3_MMODE (0x00000007u) -#define CONTROL_CONF_AIN3_CONF_AIN3_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_AIN3_CONF_AIN3_PUDEN (0x00000008u) -#define CONTROL_CONF_AIN3_CONF_AIN3_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_AIN3_CONF_AIN3_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_AIN3_CONF_AIN3_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_AIN3_CONF_AIN3_RSVD (0x000FFF80u) -#define CONTROL_CONF_AIN3_CONF_AIN3_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_AIN3_CONF_AIN3_RXACTIVE (0x00000020u) -#define CONTROL_CONF_AIN3_CONF_AIN3_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_AIN3_CONF_AIN3_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_AIN3_CONF_AIN3_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_AIN2 */ -#define CONTROL_CONF_AIN2_CONF_AIN2_MMODE (0x00000007u) -#define CONTROL_CONF_AIN2_CONF_AIN2_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_AIN2_CONF_AIN2_PUDEN (0x00000008u) -#define CONTROL_CONF_AIN2_CONF_AIN2_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_AIN2_CONF_AIN2_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_AIN2_CONF_AIN2_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_AIN2_CONF_AIN2_RSVD (0x000FFF80u) -#define CONTROL_CONF_AIN2_CONF_AIN2_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_AIN2_CONF_AIN2_RXACTIVE (0x00000020u) -#define CONTROL_CONF_AIN2_CONF_AIN2_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_AIN2_CONF_AIN2_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_AIN2_CONF_AIN2_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_AIN1 */ -#define CONTROL_CONF_AIN1_CONF_AIN1_MMODE (0x00000007u) -#define CONTROL_CONF_AIN1_CONF_AIN1_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_AIN1_CONF_AIN1_PUDEN (0x00000008u) -#define CONTROL_CONF_AIN1_CONF_AIN1_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_AIN1_CONF_AIN1_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_AIN1_CONF_AIN1_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_AIN1_CONF_AIN1_RSVD (0x000FFF80u) -#define CONTROL_CONF_AIN1_CONF_AIN1_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_AIN1_CONF_AIN1_RXACTIVE (0x00000020u) -#define CONTROL_CONF_AIN1_CONF_AIN1_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_AIN1_CONF_AIN1_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_AIN1_CONF_AIN1_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_AIN0 */ -#define CONTROL_CONF_AIN0_CONF_AIN0_MMODE (0x00000007u) -#define CONTROL_CONF_AIN0_CONF_AIN0_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_AIN0_CONF_AIN0_PUDEN (0x00000008u) -#define CONTROL_CONF_AIN0_CONF_AIN0_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_AIN0_CONF_AIN0_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_AIN0_CONF_AIN0_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_AIN0_CONF_AIN0_RSVD (0x000FFF80u) -#define CONTROL_CONF_AIN0_CONF_AIN0_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_AIN0_CONF_AIN0_RXACTIVE (0x00000020u) -#define CONTROL_CONF_AIN0_CONF_AIN0_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_AIN0_CONF_AIN0_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_AIN0_CONF_AIN0_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_VREFP */ -#define CONTROL_CONF_VREFP_CONF_VREFP_MMODE (0x00000007u) -#define CONTROL_CONF_VREFP_CONF_VREFP_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_VREFP_CONF_VREFP_PUDEN (0x00000008u) -#define CONTROL_CONF_VREFP_CONF_VREFP_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_VREFP_CONF_VREFP_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_VREFP_CONF_VREFP_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_VREFP_CONF_VREFP_RSVD (0x000FFF80u) -#define CONTROL_CONF_VREFP_CONF_VREFP_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_VREFP_CONF_VREFP_RXACTIVE (0x00000020u) -#define CONTROL_CONF_VREFP_CONF_VREFP_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_VREFP_CONF_VREFP_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_VREFP_CONF_VREFP_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_VREFN */ -#define CONTROL_CONF_VREFN_CONF_VREFN_MMODE (0x00000007u) -#define CONTROL_CONF_VREFN_CONF_VREFN_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_VREFN_CONF_VREFN_PUDEN (0x00000008u) -#define CONTROL_CONF_VREFN_CONF_VREFN_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_VREFN_CONF_VREFN_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_VREFN_CONF_VREFN_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_VREFN_CONF_VREFN_RSVD (0x000FFF80u) -#define CONTROL_CONF_VREFN_CONF_VREFN_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_VREFN_CONF_VREFN_RXACTIVE (0x00000020u) -#define CONTROL_CONF_VREFN_CONF_VREFN_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_VREFN_CONF_VREFN_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_VREFN_CONF_VREFN_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_AVDD */ -#define CONTROL_CONF_AVDD_CONF_AVDD_MMODE (0x00000007u) -#define CONTROL_CONF_AVDD_CONF_AVDD_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_AVDD_CONF_AVDD_PUDEN (0x00000008u) -#define CONTROL_CONF_AVDD_CONF_AVDD_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_AVDD_CONF_AVDD_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_AVDD_CONF_AVDD_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_AVDD_CONF_AVDD_RSVD (0x000FFF80u) -#define CONTROL_CONF_AVDD_CONF_AVDD_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_AVDD_CONF_AVDD_RXACTIVE (0x00000020u) -#define CONTROL_CONF_AVDD_CONF_AVDD_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_AVDD_CONF_AVDD_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_AVDD_CONF_AVDD_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_AVSS */ -#define CONTROL_CONF_AVSS_CONF_AVSS_MMODE (0x00000007u) -#define CONTROL_CONF_AVSS_CONF_AVSS_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_AVSS_CONF_AVSS_PUDEN (0x00000008u) -#define CONTROL_CONF_AVSS_CONF_AVSS_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_AVSS_CONF_AVSS_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_AVSS_CONF_AVSS_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_AVSS_CONF_AVSS_RSVD (0x000FFF80u) -#define CONTROL_CONF_AVSS_CONF_AVSS_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_AVSS_CONF_AVSS_RXACTIVE (0x00000020u) -#define CONTROL_CONF_AVSS_CONF_AVSS_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_AVSS_CONF_AVSS_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_AVSS_CONF_AVSS_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_IFORCE */ -#define CONTROL_CONF_IFORCE_CONF_IFORCE_MMODE (0x00000007u) -#define CONTROL_CONF_IFORCE_CONF_IFORCE_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_IFORCE_CONF_IFORCE_PUDEN (0x00000008u) -#define CONTROL_CONF_IFORCE_CONF_IFORCE_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_IFORCE_CONF_IFORCE_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_IFORCE_CONF_IFORCE_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_IFORCE_CONF_IFORCE_RSVD (0x000FFF80u) -#define CONTROL_CONF_IFORCE_CONF_IFORCE_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_IFORCE_CONF_IFORCE_RXACTIVE (0x00000020u) -#define CONTROL_CONF_IFORCE_CONF_IFORCE_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_IFORCE_CONF_IFORCE_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_IFORCE_CONF_IFORCE_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_VSENSE */ -#define CONTROL_CONF_VSENSE_CONF_VSENSE_MMODE (0x00000007u) -#define CONTROL_CONF_VSENSE_CONF_VSENSE_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_VSENSE_CONF_VSENSE_PUDEN (0x00000008u) -#define CONTROL_CONF_VSENSE_CONF_VSENSE_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_VSENSE_CONF_VSENSE_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_VSENSE_CONF_VSENSE_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_VSENSE_CONF_VSENSE_RSVD (0x000FFF80u) -#define CONTROL_CONF_VSENSE_CONF_VSENSE_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_VSENSE_CONF_VSENSE_RXACTIVE (0x00000020u) -#define CONTROL_CONF_VSENSE_CONF_VSENSE_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_VSENSE_CONF_VSENSE_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_VSENSE_CONF_VSENSE_SLEWCTRL_SHIFT (0x00000006u) - - -/* CONF_TESTOUT */ -#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_MMODE (0x00000007u) -#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_MMODE_SHIFT (0x00000000u) - -#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_PUDEN (0x00000008u) -#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_PUDEN_SHIFT (0x00000003u) - -#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_PUTYPESEL (0x00000010u) -#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_PUTYPESEL_SHIFT (0x00000004u) - -#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_RSVD (0x000FFF80u) -#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_RSVD_SHIFT (0x00000007u) - -#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_RXACTIVE (0x00000020u) -#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_RXACTIVE_SHIFT (0x00000005u) - -#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_SLEWCTRL (0x00000040u) -#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_SLEWCTRL_SHIFT (0x00000006u) - - -/* CQDETECT_STATUS */ -#define CONTROL_CQDETECT_STATUS_CQERR_GEMAC_A (0x00000800u) -#define CONTROL_CQDETECT_STATUS_CQERR_GEMAC_A_SHIFT (0x0000000Bu) - -#define CONTROL_CQDETECT_STATUS_CQERR_GEMAC_B (0x00001000u) -#define CONTROL_CQDETECT_STATUS_CQERR_GEMAC_B_SHIFT (0x0000000Cu) - -#define CONTROL_CQDETECT_STATUS_CQERR_GENERAL (0x00002000u) -#define CONTROL_CQDETECT_STATUS_CQERR_GENERAL_SHIFT (0x0000000Du) - -#define CONTROL_CQDETECT_STATUS_CQERR_GPMC (0x00000100u) -#define CONTROL_CQDETECT_STATUS_CQERR_GPMC_SHIFT (0x00000008u) - -#define CONTROL_CQDETECT_STATUS_CQERR_MMCSD_A (0x00000200u) -#define CONTROL_CQDETECT_STATUS_CQERR_MMCSD_A_SHIFT (0x00000009u) - -#define CONTROL_CQDETECT_STATUS_CQERR_MMCSD_B (0x00000400u) -#define CONTROL_CQDETECT_STATUS_CQERR_MMCSD_B_SHIFT (0x0000000Au) - -#define CONTROL_CQDETECT_STATUS_CQMODE_GEMAC_A (0x00080000u) -#define CONTROL_CQDETECT_STATUS_CQMODE_GEMAC_A_SHIFT (0x00000013u) - -#define CONTROL_CQDETECT_STATUS_CQMODE_GEMAC_B (0x00100000u) -#define CONTROL_CQDETECT_STATUS_CQMODE_GEMAC_B_SHIFT (0x00000014u) - -#define CONTROL_CQDETECT_STATUS_CQMODE_GENERAL (0x00200000u) -#define CONTROL_CQDETECT_STATUS_CQMODE_GENERAL_SHIFT (0x00000015u) - -#define CONTROL_CQDETECT_STATUS_CQMODE_GPMC (0x00010000u) -#define CONTROL_CQDETECT_STATUS_CQMODE_GPMC_SHIFT (0x00000010u) - -#define CONTROL_CQDETECT_STATUS_CQMODE_MMCSD_A (0x00020000u) -#define CONTROL_CQDETECT_STATUS_CQMODE_MMCSD_A_SHIFT (0x00000011u) - -#define CONTROL_CQDETECT_STATUS_CQMODE_MMCSD_B (0x00040000u) -#define CONTROL_CQDETECT_STATUS_CQMODE_MMCSD_B_SHIFT (0x00000012u) - -#define CONTROL_CQDETECT_STATUS_CQSTAT_GEMAC_A (0x00000008u) -#define CONTROL_CQDETECT_STATUS_CQSTAT_GEMAC_A_SHIFT (0x00000003u) - -#define CONTROL_CQDETECT_STATUS_CQSTAT_GEMAC_B (0x00000010u) -#define CONTROL_CQDETECT_STATUS_CQSTAT_GEMAC_B_SHIFT (0x00000004u) - -#define CONTROL_CQDETECT_STATUS_CQSTAT_GENERAL (0x00000020u) -#define CONTROL_CQDETECT_STATUS_CQSTAT_GENERAL_SHIFT (0x00000005u) - -#define CONTROL_CQDETECT_STATUS_CQSTAT_GPMC (0x00000001u) -#define CONTROL_CQDETECT_STATUS_CQSTAT_GPMC_SHIFT (0x00000000u) - -#define CONTROL_CQDETECT_STATUS_CQSTAT_MMCSD_A (0x00000002u) -#define CONTROL_CQDETECT_STATUS_CQSTAT_MMCSD_A_SHIFT (0x00000001u) - -#define CONTROL_CQDETECT_STATUS_CQSTAT_MMCSD_B (0x00000004u) -#define CONTROL_CQDETECT_STATUS_CQSTAT_MMCSD_B_SHIFT (0x00000002u) - -#define CONTROL_CQDETECT_STATUS_RSVD2 (0x0000C000u) -#define CONTROL_CQDETECT_STATUS_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_CQDETECT_STATUS_RSVD3 (0xFFC00000u) -#define CONTROL_CQDETECT_STATUS_RSVD3_SHIFT (0x00000016u) - - -/* DDR_IO_CTRL */ -#define CONTROL_DDR_IO_CTRL_DDR3_RST_DEF_VAL (0x80000000u) -#define CONTROL_DDR_IO_CTRL_DDR3_RST_DEF_VAL_SHIFT (0x0000001Fu) - -#define CONTROL_DDR_IO_CTRL_DDR_WUCLK_DISABLE (0x40000000u) -#define CONTROL_DDR_IO_CTRL_DDR_WUCLK_DISABLE_SHIFT (0x0000001Eu) - -#define CONTROL_DDR_IO_CTRL_MDDR_SEL (0x10000000u) -#define CONTROL_DDR_IO_CTRL_MDDR_SEL_SHIFT (0x0000001Cu) - -#define CONTROL_DDR_IO_CTRL_RSVD2 (0x20000000u) -#define CONTROL_DDR_IO_CTRL_RSVD2_SHIFT (0x0000001Du) - - -/* VTP_CTRL */ -#define CONTROL_VTP_CTRL_CLRZ (0x00000001u) -#define CONTROL_VTP_CTRL_CLRZ_SHIFT (0x00000000u) - -#define CONTROL_VTP_CTRL_ENABLE (0x00000040u) -#define CONTROL_VTP_CTRL_ENABLE_SHIFT (0x00000006u) - -#define CONTROL_VTP_CTRL_FILTER (0x0000000Eu) -#define CONTROL_VTP_CTRL_FILTER_SHIFT (0x00000001u) - -#define CONTROL_VTP_CTRL_LOCK (0x00000010u) -#define CONTROL_VTP_CTRL_LOCK_SHIFT (0x00000004u) - -#define CONTROL_VTP_CTRL_NCIN (0x00007F00u) -#define CONTROL_VTP_CTRL_NCIN_SHIFT (0x00000008u) - -#define CONTROL_VTP_CTRL_PCIN (0x007F0000u) -#define CONTROL_VTP_CTRL_PCIN_SHIFT (0x00000010u) - -#define CONTROL_VTP_CTRL_READY (0x00000020u) -#define CONTROL_VTP_CTRL_READY_SHIFT (0x00000005u) - -#define CONTROL_VTP_CTRL_RSVD2 (0x00008000u) -#define CONTROL_VTP_CTRL_RSVD2_SHIFT (0x0000000Fu) - -#define CONTROL_VTP_CTRL_RSVD3 (0xFF800000u) -#define CONTROL_VTP_CTRL_RSVD3_SHIFT (0x00000017u) - - -/* VREF_CTRL */ -#define CONTROL_VREF_CTRL_DDR_VREF_CCAP (0x00000018u) -#define CONTROL_VREF_CTRL_DDR_VREF_CCAP_SHIFT (0x00000003u) - -#define CONTROL_VREF_CTRL_DDR_VREF_EN (0x00000001u) -#define CONTROL_VREF_CTRL_DDR_VREF_EN_SHIFT (0x00000000u) - -#define CONTROL_VREF_CTRL_DDR_VREF_TAP (0x00000006u) -#define CONTROL_VREF_CTRL_DDR_VREF_TAP_SHIFT (0x00000001u) - - -/* SERDES_REFCLK_CTL */ -#define CONTROL_SERDES_REFCLK_CTL_PWRDN (0x00000001u) -#define CONTROL_SERDES_REFCLK_CTL_PWRDN_SHIFT (0x00000000u) - -#define CONTROL_SERDES_REFCLK_CTL_PWRDN_SE (0x00000002u) -#define CONTROL_SERDES_REFCLK_CTL_PWRDN_SE_SHIFT (0x00000001u) - - -/* TPCC_EVT_MUX_0_3 */ -#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_0 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_0_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_1 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_1_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_2 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_2_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_3 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_3_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_0_3_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_0_3_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_0_3_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_0_3_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_0_3_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_0_3_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_4_7 */ -#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_4 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_4_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_5 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_5_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_6 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_6_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_7 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_7_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_4_7_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_4_7_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_4_7_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_4_7_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_4_7_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_4_7_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_8_11 */ -#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_10 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_10_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_11 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_11_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_8 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_8_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_9 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_9_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_8_11_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_8_11_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_8_11_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_8_11_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_8_11_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_8_11_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_12_15 */ -#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_12 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_12_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_13 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_13_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_14 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_14_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_15 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_15_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_12_15_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_12_15_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_12_15_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_12_15_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_12_15_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_12_15_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_16_19 */ -#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_16 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_16_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_17 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_17_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_18 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_18_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_19 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_19_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_16_19_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_16_19_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_16_19_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_16_19_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_16_19_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_16_19_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_20_23 */ -#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_20 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_20_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_21 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_21_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_22 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_22_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_23 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_23_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_20_23_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_20_23_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_20_23_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_20_23_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_20_23_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_20_23_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_24_27 */ -#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_24 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_24_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_25 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_25_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_26 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_26_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_27 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_27_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_24_27_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_24_27_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_24_27_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_24_27_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_24_27_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_24_27_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_28_31 */ -#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_28 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_28_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_29 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_29_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_30 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_30_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_31 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_31_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_28_31_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_28_31_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_28_31_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_28_31_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_28_31_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_28_31_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_32_35 */ -#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_32 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_32_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_33 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_33_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_34 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_34_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_35 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_35_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_32_35_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_32_35_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_32_35_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_32_35_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_32_35_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_32_35_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_36_39 */ -#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_36 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_36_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_37 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_37_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_38 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_38_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_39 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_39_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_36_39_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_36_39_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_36_39_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_36_39_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_36_39_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_36_39_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_40_43 */ -#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_40 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_40_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_41 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_41_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_42 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_42_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_43 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_43_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_40_43_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_40_43_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_40_43_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_40_43_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_40_43_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_40_43_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_44_47 */ -#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_44 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_44_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_45 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_45_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_46 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_46_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_47 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_47_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_44_47_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_44_47_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_44_47_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_44_47_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_44_47_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_44_47_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_48_51 */ -#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_48 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_48_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_49 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_49_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_50 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_50_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_51 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_51_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_48_51_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_48_51_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_48_51_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_48_51_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_48_51_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_48_51_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_52_55 */ -#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_52 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_52_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_53 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_53_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_54 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_54_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_55 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_55_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_52_55_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_52_55_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_52_55_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_52_55_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_52_55_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_52_55_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_56_59 */ -#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_56 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_56_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_57 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_57_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_58 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_58_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_59 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_59_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_56_59_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_56_59_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_56_59_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_56_59_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_56_59_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_56_59_RSVD4_SHIFT (0x0000001Eu) - - -/* TPCC_EVT_MUX_60_63 */ -#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_60 (0x3F000000u) -#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_60_SHIFT (0x00000018u) - -#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_61 (0x003F0000u) -#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_61_SHIFT (0x00000010u) - -#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_62 (0x00003F00u) -#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_62_SHIFT (0x00000008u) - -#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_63 (0x0000003Fu) -#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_63_SHIFT (0x00000000u) - -#define CONTROL_TPCC_EVT_MUX_60_63_RSVD2 (0x0000C000u) -#define CONTROL_TPCC_EVT_MUX_60_63_RSVD2_SHIFT (0x0000000Eu) - -#define CONTROL_TPCC_EVT_MUX_60_63_RSVD3 (0x00C00000u) -#define CONTROL_TPCC_EVT_MUX_60_63_RSVD3_SHIFT (0x00000016u) - -#define CONTROL_TPCC_EVT_MUX_60_63_RSVD4 (0xC0000000u) -#define CONTROL_TPCC_EVT_MUX_60_63_RSVD4_SHIFT (0x0000001Eu) - - -/* TIMER_EVT_CAPT */ -#define CONTROL_TIMER_EVT_CAPT_RSVD2 (0x0000E000u) -#define CONTROL_TIMER_EVT_CAPT_RSVD2_SHIFT (0x0000000Du) - -#define CONTROL_TIMER_EVT_CAPT_RSVD3 (0xFFE00000u) -#define CONTROL_TIMER_EVT_CAPT_RSVD3_SHIFT (0x00000015u) - -#define CONTROL_TIMER_EVT_CAPT_TIMER5_EVTCAPT (0x0000001Fu) -#define CONTROL_TIMER_EVT_CAPT_TIMER5_EVTCAPT_SHIFT (0x00000000u) - -#define CONTROL_TIMER_EVT_CAPT_TIMER6_EVTCAPT (0x00001F00u) -#define CONTROL_TIMER_EVT_CAPT_TIMER6_EVTCAPT_SHIFT (0x00000008u) - -#define CONTROL_TIMER_EVT_CAPT_TIMER7_EVTCAPT (0x001F0000u) -#define CONTROL_TIMER_EVT_CAPT_TIMER7_EVTCAPT_SHIFT (0x00000010u) - - -/* ECAP_EVT_CAPT */ -#define CONTROL_ECAP_EVT_CAPT_ECAP0_EVTCAPT (0x0000001Fu) -#define CONTROL_ECAP_EVT_CAPT_ECAP0_EVTCAPT_SHIFT (0x00000000u) - -#define CONTROL_ECAP_EVT_CAPT_ECAP1_EVTCAPT (0x00001F00u) -#define CONTROL_ECAP_EVT_CAPT_ECAP1_EVTCAPT_SHIFT (0x00000008u) - -#define CONTROL_ECAP_EVT_CAPT_ECAP2_EVTCAPT (0x001F0000u) -#define CONTROL_ECAP_EVT_CAPT_ECAP2_EVTCAPT_SHIFT (0x00000010u) - -#define CONTROL_ECAP_EVT_CAPT_RSVD2 (0x0000E000u) -#define CONTROL_ECAP_EVT_CAPT_RSVD2_SHIFT (0x0000000Du) - -#define CONTROL_ECAP_EVT_CAPT_RSVD3 (0xFFE00000u) -#define CONTROL_ECAP_EVT_CAPT_RSVD3_SHIFT (0x00000015u) - - -/* ADC_EVT_CAPT */ -#define CONTROL_ADC_EVT_CAPT_ADC_EVTCAPT (0x0000000Fu) -#define CONTROL_ADC_EVT_CAPT_ADC_EVTCAPT_SHIFT (0x00000000u) - - -/* RESET_ISO */ -#define CONTROL_RESET_ISO_ISO_CONTROL (0x00000001u) -#define CONTROL_RESET_ISO_ISO_CONTROL_SHIFT (0x00000000u) - - -/* SMA0 */ -#define CONTROL_SMA0_SMA0 (0xFFFFFFFFu) -#define CONTROL_SMA0_SMA0_SHIFT (0x00000000u) - - -/* DDR_CKE_CTRL */ -#define CONTROL_DDR_CKE_CTRL_DDR_CKE_CTRL (0x00000001u) -#define CONTROL_DDR_CKE_CTRL_DDR_CKE_CTRL_SHIFT (0x00000000u) - -#define CONTROL_DDR_CKE_CTRL_SMA1 (0xFFFFFFFEu) -#define CONTROL_DDR_CKE_CTRL_SMA1_SHIFT (0x00000001u) - - -/* SMA2 */ -#define CONTROL_SMA2_SMA2 (0xFFFFFFFFu) -#define CONTROL_SMA2_SMA2_SHIFT (0x00000000u) - - -/* M3_TXEV_EOI */ -#define CONTROL_M3_TXEV_EOI_M3_TXEV_EOI (0x00000001u) -#define CONTROL_M3_TXEV_EOI_M3_TXEV_EOI_SHIFT (0x00000000u) - -#define CONTROL_M3_TXEV_EOI_SMA3 (0xFFFFFFFEu) -#define CONTROL_M3_TXEV_EOI_SMA3_SHIFT (0x00000001u) - - -/* IPC_MSG_REG0 */ -#define CONTROL_IPC_MSG_REG0_IPC_MSG_REG0 (0xFFFFFFFFu) -#define CONTROL_IPC_MSG_REG0_IPC_MSG_REG0_SHIFT (0x00000000u) - - -/* IPC_MSG_REG1 */ -#define CONTROL_IPC_MSG_REG1_IPC_MSG_REG1 (0xFFFFFFFFu) -#define CONTROL_IPC_MSG_REG1_IPC_MSG_REG1_SHIFT (0x00000000u) - - -/* IPC_MSG_REG2 */ -#define CONTROL_IPC_MSG_REG2_IPC_MSG_REG2 (0xFFFFFFFFu) -#define CONTROL_IPC_MSG_REG2_IPC_MSG_REG2_SHIFT (0x00000000u) - - -/* IPC_MSG_REG3 */ -#define CONTROL_IPC_MSG_REG3_IPC_MSG_REG3 (0xFFFFFFFFu) -#define CONTROL_IPC_MSG_REG3_IPC_MSG_REG3_SHIFT (0x00000000u) - - -/* IPC_MSG_REG4 */ -#define CONTROL_IPC_MSG_REG4_IPC_MSG_REG4 (0xFFFFFFFFu) -#define CONTROL_IPC_MSG_REG4_IPC_MSG_REG4_SHIFT (0x00000000u) - - -/* IPC_MSG_REG5 */ -#define CONTROL_IPC_MSG_REG5_IPC_MSG_REG5 (0xFFFFFFFFu) -#define CONTROL_IPC_MSG_REG5_IPC_MSG_REG5_SHIFT (0x00000000u) - - -/* IPC_MSG_REG6 */ -#define CONTROL_IPC_MSG_REG6_IPC_MSG_REG6 (0xFFFFFFFFu) -#define CONTROL_IPC_MSG_REG6_IPC_MSG_REG6_SHIFT (0x00000000u) - - -/* IPC_MSG_REG7 */ -#define CONTROL_IPC_MSG_REG7_IPC_MSG_REG7 (0xFFFFFFFFu) -#define CONTROL_IPC_MSG_REG7_IPC_MSG_REG7_SHIFT (0x00000000u) - - -/* DDR_CMD0_IOCTRL */ -#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_GP_WD0 (0x001FFC00u) -#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_GP_WD0_SHIFT (0x0000000Au) - -#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_GP_WD1 (0xFFE00000u) -#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_GP_WD1_SHIFT (0x00000015u) - -#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_I (0x00000007u) -#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_I_SHIFT (0x00000000u) - -#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_I_CLK (0x000000E0u) -#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_I_CLK_SHIFT (0x00000005u) - -#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_SR (0x00000018u) -#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_SR_SHIFT (0x00000003u) - -#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_SR_CLK (0x00000300u) -#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_SR_CLK_SHIFT (0x00000008u) - - -/* DDR_CMD1_IOCTRL */ -#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_GP_WD0 (0x001FFC00u) -#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_GP_WD0_SHIFT (0x0000000Au) - -#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_GP_WD1 (0xFFE00000u) -#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_GP_WD1_SHIFT (0x00000015u) - -#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_I (0x00000007u) -#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_I_SHIFT (0x00000000u) - -#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_I_CLK (0x000000E0u) -#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_I_CLK_SHIFT (0x00000005u) - -#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_SR (0x00000018u) -#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_SR_SHIFT (0x00000003u) - -#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_SR_CLK (0x00000300u) -#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_SR_CLK_SHIFT (0x00000008u) - - -/* DDR_CMD2_IOCTRL */ -#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_GP_WD0 (0x001FFC00u) -#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_GP_WD0_SHIFT (0x0000000Au) - -#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_GP_WD1 (0xFFE00000u) -#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_GP_WD1_SHIFT (0x00000015u) - -#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_I (0x00000007u) -#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_I_SHIFT (0x00000000u) - -#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_I_CLK (0x000000E0u) -#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_I_CLK_SHIFT (0x00000005u) - -#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_SR (0x00000018u) -#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_SR_SHIFT (0x00000003u) - -#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_SR_CLK (0x00000300u) -#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_SR_CLK_SHIFT (0x00000008u) - - -/* DDR_DATA0_IOCTRL */ -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_I (0x00000007u) -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_I_SHIFT (0x00000000u) - -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_I_CLK (0x000000E0u) -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_I_CLK_SHIFT (0x00000005u) - -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_SR (0x00000018u) -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_SR_SHIFT (0x00000003u) - -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_SR_CLK (0x00000300u) -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_SR_CLK_SHIFT (0x00000008u) - -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD0_DM (0x00040000u) -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD0_DM_SHIFT (0x00000012u) - -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD0_DQ (0x0003FC00u) -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD0_DQ_SHIFT (0x0000000Au) - -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD0_DQS (0x00080000u) -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD0_DQS_SHIFT (0x00000013u) - -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD1_DM (0x10000000u) -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD1_DM_SHIFT (0x0000001Cu) - -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD1_DQ (0x0FF00000u) -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD1_DQ_SHIFT (0x00000014u) - -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD1_DQS (0x20000000u) -#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD1_DQS_SHIFT (0x0000001Du) - - -/* DDR_DATA1_IOCTRL */ -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_I (0x00000007u) -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_I_SHIFT (0x00000000u) - -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_I_CLK (0x000000E0u) -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_I_CLK_SHIFT (0x00000005u) - -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_SR (0x00000018u) -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_SR_SHIFT (0x00000003u) - -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_SR_CLK (0x00000300u) -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_SR_CLK_SHIFT (0x00000008u) - -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD0_DM (0x00040000u) -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD0_DM_SHIFT (0x00000012u) - -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD0_DQ (0x0003FC00u) -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD0_DQ_SHIFT (0x0000000Au) - -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD0_DQS (0x00080000u) -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD0_DQS_SHIFT (0x00000013u) - -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD1_DM (0x10000000u) -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD1_DM_SHIFT (0x0000001Cu) - -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD1_DQ (0x0FF00000u) -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD1_DQ_SHIFT (0x00000014u) - -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD1_DQS (0x20000000u) -#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD1_DQS_SHIFT (0x0000001Du) - - -/* DDR_DATA2_IOCTRL */ -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_I (0x00000007u) -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_I_SHIFT (0x00000000u) - -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_I_CLK (0x000000E0u) -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_I_CLK_SHIFT (0x00000005u) - -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_SR (0x00000018u) -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_SR_SHIFT (0x00000003u) - -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_SR_CLK (0x00000300u) -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_SR_CLK_SHIFT (0x00000008u) - -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD0_DM (0x00040000u) -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD0_DM_SHIFT (0x00000012u) - -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD0_DQ (0x0003FC00u) -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD0_DQ_SHIFT (0x0000000Au) - -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD0_DQS (0x00080000u) -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD0_DQS_SHIFT (0x00000013u) - -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD1_DM (0x10000000u) -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD1_DM_SHIFT (0x0000001Cu) - -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD1_DQ (0x0FF00000u) -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD1_DQ_SHIFT (0x00000014u) - -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD1_DQS (0x20000000u) -#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD1_DQS_SHIFT (0x0000001Du) - - -/* DDR_DATA3_IOCTRL */ -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_I (0x00000007u) -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_I_SHIFT (0x00000000u) - -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_I_CLK (0x000000E0u) -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_I_CLK_SHIFT (0x00000005u) - -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_SR (0x00000018u) -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_SR_SHIFT (0x00000003u) - -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_SR_CLK (0x00000300u) -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_SR_CLK_SHIFT (0x00000008u) - -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD0_DM (0x00040000u) -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD0_DM_SHIFT (0x00000012u) - -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD0_DQ (0x0003FC00u) -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD0_DQ_SHIFT (0x0000000Au) - -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD0_DQS (0x00080000u) -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD0_DQS_SHIFT (0x00000013u) - -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD1_DM (0x10000000u) -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD1_DM_SHIFT (0x0000001Cu) - -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD1_DQ (0x0FF00000u) -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD1_DQ_SHIFT (0x00000014u) - -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD1_DQS (0x20000000u) -#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD1_DQS_SHIFT (0x0000001Du) - - -/* DDR_DATA4_IOCTRL */ -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_I (0x00000007u) -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_I_SHIFT (0x00000000u) - -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_I_CLK (0x000000E0u) -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_I_CLK_SHIFT (0x00000005u) - -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_SR (0x00000018u) -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_SR_SHIFT (0x00000003u) - -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_SR_CLK (0x00000300u) -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_SR_CLK_SHIFT (0x00000008u) - -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD0_DM (0x00040000u) -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD0_DM_SHIFT (0x00000012u) - -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD0_DQ (0x0003FC00u) -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD0_DQ_SHIFT (0x0000000Au) - -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD0_DQS (0x00080000u) -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD0_DQS_SHIFT (0x00000013u) - -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD1_DM (0x10000000u) -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD1_DM_SHIFT (0x0000001Cu) - -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD1_DQ (0x0FF00000u) -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD1_DQ_SHIFT (0x00000014u) - -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD1_DQS (0x20000000u) -#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD1_DQS_SHIFT (0x0000001Du) - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_control_C6A811x.h b/lib/tiam1808/tiam1808/hw/hw_control_C6A811x.h deleted file mode 100644 index f772db89a..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_control_C6A811x.h +++ /dev/null @@ -1,4016 +0,0 @@ -/** - * \file hw_control_C6A811x.h - * - * \brief Hardware registers and fields for CONTROL module - */ - -/* -* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _HW_CONTROL_H_ -#define _HW_CONTROL_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/*************************************************************************\ - * Registers Definition -\*************************************************************************/ - -#define CONTROL_REVISION (0x0) -#define CONTROL_HWINFO (0x4) -#define CONTROL_SYSCONFIG (0x10) -#define CONTROL_STATUS (0x40) -#define CONTROL_BOOTSTAT (0x44) -#define CONTROL_DSPBOOTADDR (0x48) -#define CONTROL_SEC_CTRL (0x100) -#define CONTROL_SEC_SW (0x104) -#define CONTROL_SEC_EMU (0x108) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG (0x110) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2 (0x114) -#define CONTROL_SW_CFG (0x118) -#define CONTROL_SW_CCFG (0x11c) -#define CONTROL_MPK(n) (0x120 + (n * 4)) -#define CONTROL_SWRV(n) (0x140 + (n * 4)) -#define CONTROL_SEC_TAP (0x180) -#define CONTROL_SEC_TAP_CMDIN (0x184) -#define CONTROL_SEC_TAP_CMDOUT (0x188) -#define CONTROL_SEC_TAP_DATIN (0x18c) -#define CONTROL_SEC_TAP_DATOUT (0x190) -#define CONTROL_MREQDOMAIN_EXP1 (0x198) -#define CONTROL_MREQDOMAIN_EXP2 (0x19c) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0 (0x1a0) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1 (0x1a4) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF (0x1a8) -#define CONTROL_SEC_LOAD_FW_EXP_VAL (0x1ac) -#define CONTROL_SEC_CTRL_RO (0x1b4) -#define CONTROL_EMIF_OBFUSCATION_KEY (0x1b8) -#define CONTROL_SEC_CLK_CTRL (0x1bc) -#define CONTROL_MREQDOMAIN_EXP3 (0x1d4) -#define CONTROL_CEK(n) (0x200 + (n * 4)) -#define CONTROL_CEK_BCH(n) (0x210 + (n * 4)) -#define CONTROL_MSV_0 (0x224) -#define CONTROL_MSV_BCH(n) (0x228 + (n * 4)) -#define CONTROL_SEC_STATUS (0x240) -#define CONTROL_SECMEM_STATUS (0x244) -#define CONTROL_SEC_ERR_STAT_FUNC(n) (0x248 + (n * 4)) -#define CONTROL_SEC_ERR_STAT_DBUG(n) (0x250 + (n * 4)) -#define CONTROL_KEK_SW(n) (0x260 + (n * 4)) -#define CONTROL_CMPK_BCH(n) (0x280 + (n * 4)) -#define CONTROL_CMPK(n) (0x2b0 + (n * 4)) -#define CONTROL_DUCATI_CLKSRC (0x2f8) -#define CONTROL_DSS_CLKSRC (0x2fc) -#define CONTROL_SSM_END_FAST_SECRAM (0x300) -#define CONTROL_SSM_FIREWALL_CONTROLLER (0x304) -#define CONTROL_SSM_START_SECURE_STACKED_RAM (0x308) -#define CONTROL_SSM_END_SECURE_STACKED_RAM (0x30c) -#define CONTROL_SSM_START_SPM_STACK (0x310) -#define CONTROL_SSM_END_SPM_STACK (0x314) -#define CONTROL_SSM_START_MONITOR_RAMCODE (0x318) -#define CONTROL_SSM_END_MONITOR_RAMCODE (0x31c) -#define CONTROL_SSM_END_MONITOR_RAMDATA (0x320) -#define CONTROL_SSM_START_MONITOR_CODE (0x324) -#define CONTROL_SSM_END_MONITOR_CODE (0x328) -#define CONTROL_SSM_START_MONITOR_PERIPH (0x32c) -#define CONTROL_SSM_END_MONITOR_PERIPH (0x330) -#define CONTROL_SSM_START_MONITOR_STACK (0x334) -#define CONTROL_SSM_END_MONITOR_STACK (0x338) -#define CONTROL_SSM_START_MONITOR_RAMCODE_ETM (0x33c) -#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM (0x340) -#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM (0x344) -#define CONTROL_SSM_START_MONITOR_CODE_ETM (0x348) -#define CONTROL_SSM_END_MONITOR_CODE_ETM (0x34c) -#define CONTROL_SSM_START_MONITOR_STACK_ETM (0x350) -#define CONTROL_SSM_END_MONITOR_STACK_ETM (0x354) -#define CONTROL_SSM_START_MONITOR_SHARED_ETM (0x358) -#define CONTROL_SSM_END_MONITOR_SHARED_ETM (0x35c) -#define CONTROL_SSM_START_MONITOR_PERIPH_ETM (0x360) -#define CONTROL_SSM_END_MONITOR_PERIPH_ETM (0x364) -#define CONTROL_SSM_CPSR_MODE_ENFC (0x368) -#define CONTROL_SSM_END_L3_SECRAM (0x36c) -#define CONTROL_SGX_VBBLDO_CTRL (0x408) -#define CONTROL_GEM_VBBLDO_CTRL (0x418) -#define CONTROL_CORTEX_VBBLDO_CTRL (0x41c) -#define CONTROL_RAMLDO_CTRL(n) (0x428 + (n * 4)) -#define CONTROL_REFCLK_LJCBLDO_CTRL (0x440) -#define CONTROL_BANDGAP_CTRL(n) (0x448 + (n * 8)) -#define CONTROL_BANDGAP_TRIM(n) (0x44c + (n * 8)) -#define CONTROL_OSC_CTRL(n) (0x468 + (n * 4)) -#define CONTROL_PCIE_CFG (0x480) -#define CONTROL_PE_SCRATCHPAD(n) (0x500 + (n * 4)) -#define CONTROL_DEVICE_ID (0x600) -#define CONTROL_INIT_PRIORITY(n) (0x608 + (n * 4)) -#define CONTROL_MMU_CFG (0x610) -#define CONTROL_TPTC_CFG (0x614) -#define CONTROL_DSP_IDLE_CFG (0x61c) -#define CONTROL_USB_CTRL(n) (0x620 + (n * 8)) -#define CONTROL_USB_STS(n) (0x624 + (n * 8)) -#define CONTROL_MAC_ID_LO(n) (0x630 + (n * 8)) -#define CONTROL_MAC_ID_HI(n) (0x634 + (n * 8)) -#define CONTROL_SW_REVISION (0x640) -#define CONTROL_DCAN_RAMINIT (0x644) -#define CONTROL_AUD_CTRL (0x64c) -#define CONTROL_GMII_SEL (0x650) -#define CONTROL_OCMEM_PWRDN (0x654) -#define CONTROL_DUCATIMEM_PWRDN (0x65c) -#define CONTROL_PWMSS_CTRL (0x664) -#define CONTROL_SD_DAC_CTRL (0x670) -#define CONTROL_SD_DAC_CAL(n) (0x674 + (n * 4)) -#define CONTROL_SD_DAC_REGCTRL(n) (0x67c + (n * 8)) -#define CONTROL_SD_DAC_REGSTATUS(n) (0x680 + (n * 8)) -#define CONTROL_EMIF_CLK_GATE (0x694) -#define CONTROL_SMRT_CTRL (0x6a0) -#define CONTROL_MODENA_HW_DEBUG_SEL (0x6a4) -#define CONTROL_MODENA_HW_DBG_INFO (0x6a8) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT (0x6b0) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS (0x6b4) -#define CONTROL_PCIE_PLLCFG(n) (0x6d8 + (n * 4)) -#define CONTROL_PCIE_PLLSTATUS (0x6ec) -#define CONTROL_PCIE_RXSTATUS (0x6f0) -#define CONTROL_PCIE_TXSTATUS (0x6f4) -#define CONTROL_PCIE_TESTCFG (0x6f8) -#define CONTROL_PCIE_MISCCFG (0x6fc) -#define CONTROL_VDD_MPU_OPP_050 (0x770) -#define CONTROL_VDD_MPU_OPP_100 (0x774) -#define CONTROL_VDD_MPU_OPP_119 (0x778) -#define CONTROL_VDD_MPU_OPP_TURBO (0x77c) -#define CONTROL_VDD_CORE_GEM_OPP_050 (0x7b8) -#define CONTROL_VDD_CORE_GEM_OPP_100 (0x7bc) -#define CONTROL_VDD_CORE_GEM_OPP_119 (0x7c0) -#define CONTROL_VDD_CORE_GEM_OPP_TURBO (0x7c4) -#define CONTROL_BB_SCALE (0x7d0) -#define CONTROL_USB_VID_PID (0x7f4) -#define CONTROL_PCIE_VID_PID (0x7f8) -#define CONTROL_EFUSE_SMA (0x7fc) -#define CONTROL_PINCTRL(n) (0x7fc + n * 4) -#define CONTROL_CQDETECT_STATUS (0xe00) -#define CONTROL_DDR_IO_CTRL (0xe04) -#define CONTROL_VTP_CTRL (0xe0c) -#define CONTROL_VREF_CTRL (0xe14) -#define CONTROL_MLBP_SIG_IO_CTRL (0xe18) -#define CONTROL_MLBP_DAT_IO_CTRL (0xe1c) -#define CONTROL_MLBP_CLK_BG_CTRL (0xe20) -#define CONTROL_SERDES_REFCLK_CTL (0xe24) -#define CONTROL_DSP_INT_MUX(n) (0xf00 + (n * 4)) -#define CONTROL_DUCATI_INT_MUX(n) (0xf54 + (n * 4)) -#define CONTROL_TPCC_EVT_MUX(n) (0xf90 + (n * 4)) -#define CONTROL_TIMER_EVT_CAPT (0xfd0) -#define CONTROL_GPIO_MUX (0xfd4) -#define CONTROL_ADC_EVT_CAPT (0xfd8) -#define CONTROL_ECAP_EVT_CAPT (0xfdc) -#define CONTROL_RESET_ISO (0x1000) -#define CONTROL_DAC_TRIM(n) (0x1310 + (n * 4)) -#define CONTROL_SMA(n) (0x1318 + (n * 4)) -#define CONTROL_RTC_IDLE (0x1348) -#define CONTROL_ARM_INT_MUX(n) (0x1600 + (n * 4)) -#define CONTROL_INITIATOR_PRIO(n) (0x16c0 + (n * 4)) -#define CONTROL_DMAOBS (0x16f0) -#define CONTROL_INTOBS (0x16f4) -#define CONTROL_DTC_CTRL(n) (0x1700 + (n * 4)) -#define CONTROL_DTC0_LOAD(n) (0x1708 + (n * 4)) -#define CONTROL_DTC1_LOAD(n) (0x1718 + (n * 4)) -#define CONTROL_ICSS_INT_MUX(n) (0x1750 + (n * 4)) -#define CONTROL_CHIP_HW_DBG_SEL (0x1780) - - -/**************************************************************************\ - * Field Definition Macros -\**************************************************************************/ - -/** @brief CONTROL_REVISION register fields */ -#define CONTROL_REVISION_IP_REV_CUSTOM (0x000000C0u) -#define CONTROL_REVISION_IP_REV_CUSTOM_SHIFT (0x00000006u) - -#define CONTROL_REVISION_IP_REV_FUNC (0x0FFF0000u) -#define CONTROL_REVISION_IP_REV_FUNC_SHIFT (0x00000010u) - -#define CONTROL_REVISION_IP_REV_MAJOR (0x00000700u) -#define CONTROL_REVISION_IP_REV_MAJOR_SHIFT (0x00000008u) - -#define CONTROL_REVISION_IP_REV_MINOR (0x0000003Fu) -#define CONTROL_REVISION_IP_REV_MINOR_SHIFT (0x00000000u) - -#define CONTROL_REVISION_IP_REV_RTL (0x0000F800u) -#define CONTROL_REVISION_IP_REV_RTL_SHIFT (0x0000000Bu) - -#define CONTROL_REVISION_IP_REV_SCHEME (0xC0000000u) -#define CONTROL_REVISION_IP_REV_SCHEME_SHIFT (0x0000001Eu) - -/** @brief CONTROL_HWINFO register fields */ -#define CONTROL_HWINFO_IP_HWINFO (0xFFFFFFFFu) -#define CONTROL_HWINFO_IP_HWINFO_SHIFT (0x00000000u) - -/** @brief CONTROL_SYSCONFIG register fields */ -#define CONTROL_SYSCONFIG_FREEEMU (0x00000002u) -#define CONTROL_SYSCONFIG_FREEEMU_SHIFT (0x00000001u) - -#define CONTROL_SYSCONFIG_IDLEMODE (0x0000000Cu) -#define CONTROL_SYSCONFIG_IDLEMODE_SHIFT (0x00000002u) - -#define CONTROL_SYSCONFIG_STANDBY (0x00000030u) -#define CONTROL_SYSCONFIG_STANDBY_SHIFT (0x00000004u) - -/** @brief CONTROL_STATUS register fields */ -#define CONTROL_STATUS_ADMUX (0x000C0000u) -#define CONTROL_STATUS_ADMUX_SHIFT (0x00000012u) - -#define CONTROL_STATUS_BW (0x00010000u) -#define CONTROL_STATUS_BW_SHIFT (0x00000010u) - -#define CONTROL_STATUS_DEVTYPE (0x00000700u) -#define CONTROL_STATUS_DEVTYPE_SHIFT (0x00000008u) - -#define CONTROL_STATUS_SYSBOOT0 (0x000000FFu) -#define CONTROL_STATUS_SYSBOOT0_SHIFT (0x00000000u) - -#define CONTROL_STATUS_SYSBOOT1 (0x00C00000u) -#define CONTROL_STATUS_SYSBOOT1_SHIFT (0x00000016u) - -#define CONTROL_STATUS_TESTMD (0x00300000u) -#define CONTROL_STATUS_TESTMD_SHIFT (0x00000014u) - -#define CONTROL_STATUS_WAITEN (0x00020000u) -#define CONTROL_STATUS_WAITEN_SHIFT (0x00000011u) - -/** @brief BOOTSTAT register fields */ -#define CONTROL_BOOTSTAT_BC (0x00000001u) -#define CONTROL_BOOTSTAT_BC_SHIFT (0x00000000u) - -#define CONTROL_BOOTSTAT_BOOTERR (0x000F0000u) -#define CONTROL_BOOTSTAT_BOOTERR_SHIFT (0x00000010u) - -/** @brief CONTROL_DSPBOOTADDR register fields */ -#define CONTROL_DSPBOOTADDR_BOOTADDR (0xFFFFFC00u) -#define CONTROL_DSPBOOTADDR_BOOTADDR_SHIFT (0xAu) - -#define CONTROL_DSPBOOTADDR_RSTDONE (0x00000001u) -#define CONTROL_DSPBOOTADDR_RSTDONE_SHIFT (0x0u) - -/** @brief CONTROL_SEC_CTRL register fields */ -#define CONTROL_SEC_CTRL_BSCENABLE (0x00000200u) -#define CONTROL_SEC_CTRL_BSCENABLE_SHIFT (0x00000009u) - -#define CONTROL_SEC_CTRL_CATSCANEN (0x00000100u) -#define CONTROL_SEC_CTRL_CATSCANEN_SHIFT (0x00000008u) - -#define CONTROL_SEC_CTRL_CMPKEFUSENOTDEC (0x00002000u) -#define CONTROL_SEC_CTRL_CMPKEFUSENOTDEC_SHIFT (0x0000000Du) - -#define CONTROL_SEC_CTRL_CPEFUSELDDONE (0x00000400u) -#define CONTROL_SEC_CTRL_CPEFUSELDDONE_SHIFT (0x0000000Au) - -#define CONTROL_SEC_CTRL_CPEFUSENOTDEC (0x00001000u) -#define CONTROL_SEC_CTRL_CPEFUSENOTDEC_SHIFT (0x0000000Cu) - -#define CONTROL_SEC_CTRL_CPEFUSEWRDIS (0x00000800u) -#define CONTROL_SEC_CTRL_CPEFUSEWRDIS_SHIFT (0x0000000Bu) - -#define CONTROL_SEC_CTRL_DMLEDCOREEN (0x00000080u) -#define CONTROL_SEC_CTRL_DMLEDCOREEN_SHIFT (0x00000007u) - -#define CONTROL_SEC_CTRL_FASTOCMSECSAVE (0x30000000u) -#define CONTROL_SEC_CTRL_FASTOCMSECSAVE_SHIFT (0x0000001Cu) - -#define CONTROL_SEC_CTRL_KEKSWENABLE0 (0x00000004u) -#define CONTROL_SEC_CTRL_KEKSWENABLE0_SHIFT (0x00000002u) - -#define CONTROL_SEC_CTRL_KEKSWENABLE1 (0x00000010u) -#define CONTROL_SEC_CTRL_KEKSWENABLE1_SHIFT (0x00000004u) - -#define CONTROL_SEC_CTRL_L3OCMSECSAVE (0x0C000000u) -#define CONTROL_SEC_CTRL_L3OCMSECSAVE_SHIFT (0x0000001Au) - -#define CONTROL_SEC_CTRL_SECCTRLWRDISABLE (0x80000000u) -#define CONTROL_SEC_CTRL_SECCTRLWRDISABLE_SHIFT (0x0000001Fu) - -#define CONTROL_SEC_CTRL_SECUREMODEINITDONE (0x40000000u) -#define CONTROL_SEC_CTRL_SECUREMODEINITDONE_SHIFT (0x0000001Eu) - -#define CONTROL_SEC_CTRL_WDOPDISABLE (0x00000001u) -#define CONTROL_SEC_CTRL_WDOPDISABLE_SHIFT (0x00000000u) - -#define CONTROL_SEC_CTRL_WDREGENABLE (0x00000002u) -#define CONTROL_SEC_CTRL_WDREGENABLE_SHIFT (0x00000001u) - -/** @brief CONTROL_SEC_SW register fields */ -#define CONTROL_SEC_SW_SW_HW_PARAMETERS (0xFFFFFFFFu) -#define CONTROL_SEC_SW_SW_HW_PARAMETERS_SHIFT (0x00000000u) - -/** @brief CONTROL_SEC_EMU register fields */ -#define CONTROL_SEC_EMU_ETMSECPRIVDBGEN (0x00001000u) -#define CONTROL_SEC_EMU_ETMSECPRIVDBGEN_SHIFT (0x0000000Cu) - -#define CONTROL_SEC_EMU_GENDBGEN (0x00000FFFu) -#define CONTROL_SEC_EMU_GENDBGEN_SHIFT (0x00000000u) - -#define CONTROL_SEC_EMU_GENDBGEN_M3 (0x0000C000u) -#define CONTROL_SEC_EMU_GENDBGEN_M3_SHIFT (0x0000000Eu) - -#define CONTROL_SEC_EMU_ICESECPRIVDBGEN (0x00002000u) -#define CONTROL_SEC_EMU_ICESECPRIVDBGEN_SHIFT (0x0000000Du) - -#define CONTROL_SEC_EMU_SECEMUWRDIS (0x80000000u) -#define CONTROL_SEC_EMU_SECEMUWRDIS_SHIFT (0x0000001Fu) - -/** @brief SECURE_EMIF_SDRAM_CONFIG register fields */ -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CL (0x00003C00u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CL_SHIFT (0x0000000Au) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CWL (0x00030000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CWL_SHIFT (0x00000010u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DDR_TERM (0x07000000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DDR_TERM_SHIFT (0x00000018u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DYN_ODT (0x00600000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DYN_ODT_SHIFT (0x00000015u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_EBANK (0x00000008u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_EBANK_SHIFT (0x00000003u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK (0x00000070u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK_SHIFT (0x00000004u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK_POS (0x18000000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK_POS_SHIFT (0x0000001Bu) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_NARROW_MODE (0x0000C000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_NARROW_MODE_SHIFT (0x0000000Eu) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_PAGESIZE (0x00000007u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_PAGESIZE_SHIFT (0x00000000u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_ROWSIZE (0x00000380u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_ROWSIZE_SHIFT (0x00000007u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_DRIVE (0x000C0000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_DRIVE_SHIFT (0x00000012u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_TYPE (0xE0000000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_TYPE_SHIFT (0x0000001Du) - -/** @brief SECURE_EMIF_SDRAM_CONFIG_2 register fields */ -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_CS1_NVMEN (0x40000000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_CS1_NVMEN_SHIFT (0x0000001Eu) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_EBANK_POS (0x08000000u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_EBANK_POS_SHIFT (0x0000001Bu) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBNUM (0x00000030u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBNUM_SHIFT (0x00000004u) - -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBSIZE (0x00000007u) -#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBSIZE_SHIFT (0x00000000u) - -/** @brief CONTROL_SW_CFG register fields */ -#define CONTROL_SW_CFG_SW_CFG (0xFFFFFFFFu) -#define CONTROL_SW_CFG_SW_CFG_SHIFT (0x00000000u) - -/** @brief CONTROL_SW_CCFG register fields */ -#define CONTROL_SW_CCFG_SW_CCFG (0x0000FFFFu) -#define CONTROL_SW_CCFG_SW_CCFG_SHIFT (0x00000000u) - -#define CONTROL_SW_CCFG_SW_CCFG_RED (0xFFFF0000u) -#define CONTROL_SW_CCFG_SW_CCFG_RED_SHIFT (0x00000010u) - -/** @brief CONTROL_MPK(n) register fields */ -#define CONTROL_MPK_MPK (0xFFFFFFFFu) -#define CONTROL_MPK_MPK_SHIFT (0x00000000u) - -/** @brief CONTROL_SWRV(n) register fields */ -#define CONTROL_SWRV_SWRV (0x0000FFFFu) -#define CONTROL_SWRV_SWRV_SHIFT (0x00000000u) - -#define CONTROL_SWRV_SWRV_RED (0xFFFF0000u) -#define CONTROL_SWRV_SWRV_RED_SHIFT (0x00000010u) - -/** @brief CONTROL_SEC_TAP register fields */ -#define CONTROL_SEC_TAP_1500EN (0x00000008u) -#define CONTROL_SEC_TAP_1500EN_SHIFT (0x00000003u) - -#define CONTROL_SEC_TAP_DAPTAPEN (0x00000001u) -#define CONTROL_SEC_TAP_DAPTAPEN_SHIFT (0x00000000u) - -#define CONTROL_SEC_TAP_PART1500DIS (0x00000010u) -#define CONTROL_SEC_TAP_PART1500DIS_SHIFT (0x00000004u) - -#define CONTROL_SEC_TAP_SABERMPUTAPEN (0x00000200u) -#define CONTROL_SEC_TAP_SABERMPUTAPEN_SHIFT (0x00000009u) - -#define CONTROL_SEC_TAP_SECTAPWRDISABLE (0x80000000u) -#define CONTROL_SEC_TAP_SECTAPWRDISABLE_SHIFT (0x0000001Fu) - -#define CONTROL_SEC_TAP_WAKEUPTAPEN (0x00000004u) -#define CONTROL_SEC_TAP_WAKEUPTAPEN_SHIFT (0x00000002u) - -/** @brief CONTROL_SEC_TAP_CMDIN register fields */ -#define CONTROL_SEC_TAP_CMDIN_CMDIN (0x000000FFu) -#define CONTROL_SEC_TAP_CMDIN_CMDIN_SHIFT (0x00000000u) - -/** @brief CONTROL_SEC_TAP_CMDOUT register fields */ -#define CONTROL_SEC_TAP_CMDOUT_CMDOUT (0x000000FFu) -#define CONTROL_SEC_TAP_CMDOUT_CMDOUT_SHIFT (0x00000000u) - -/** @brief CONTROL_SEC_TAP_DATIN register fields */ -#define CONTROL_SEC_TAP_DATIN_DATAIN (0x000000FFu) -#define CONTROL_SEC_TAP_DATIN_DATAIN_SHIFT (0x00000000u) - -/** @brief CONTROL_SEC_TAP_DATOUT register fields */ -#define CONTROL_SEC_TAP_DATOUT_DATAOUT (0x000000FFu) -#define CONTROL_SEC_TAP_DATOUT_DATAOUT_SHIFT (0x00000000u) - -/** @brief CONTROL_MREQDOMAIN_EXP1 register fields */ -#define CONTROL_MREQDOMAIN_EXP1_2DBITBLT_DOM (0x001C0000u) -#define CONTROL_MREQDOMAIN_EXP1_2DBITBLT_DOM_SHIFT (0x00000012u) - -#define CONTROL_MREQDOMAIN_EXP1_L3_EXP_DOM (0x00000007u) -#define CONTROL_MREQDOMAIN_EXP1_L3_EXP_DOM_SHIFT (0x00000000u) - -#define CONTROL_MREQDOMAIN_EXP1_LCD_CTRL_DOM (0x00038000u) -#define CONTROL_MREQDOMAIN_EXP1_LCD_CTRL_DOM_SHIFT (0x0000000Fu) - -#define CONTROL_MREQDOMAIN_EXP1_LCK (0x80000000u) -#define CONTROL_MREQDOMAIN_EXP1_LCK_SHIFT (0x0000001Fu) - -#define CONTROL_MREQDOMAIN_EXP1_MLB_DOM (0x00007000u) -#define CONTROL_MREQDOMAIN_EXP1_MLB_DOM_SHIFT (0x0000000Cu) - -#define CONTROL_MREQDOMAIN_EXP1_SGX_DOM (0x07000000u) -#define CONTROL_MREQDOMAIN_EXP1_SGX_DOM_SHIFT (0x00000018u) - -#define CONTROL_MREQDOMAIN_EXP1_WAKE_DOM (0x00E00000u) -#define CONTROL_MREQDOMAIN_EXP1_WAKE_DOM_SHIFT (0x00000015u) - -/** @brief CONTROL_MREQDOMAIN_EXP2 register fields */ -#define CONTROL_MREQDOMAIN_EXP2_GEMAC_DOM (0x001C0000u) -#define CONTROL_MREQDOMAIN_EXP2_GEMAC_DOM_SHIFT (0x00000012u) - -#define CONTROL_MREQDOMAIN_EXP2_LCK (0x80000000u) -#define CONTROL_MREQDOMAIN_EXP2_LCK_SHIFT (0x0000001Fu) - -#define CONTROL_MREQDOMAIN_EXP2_P1500_DOM (0x00038000u) -#define CONTROL_MREQDOMAIN_EXP2_P1500_DOM_SHIFT (0x0000000Fu) - -#define CONTROL_MREQDOMAIN_EXP2_USB0_DOM (0x00000E00u) -#define CONTROL_MREQDOMAIN_EXP2_USB0_DOM_SHIFT (0x00000009u) - -#define CONTROL_MREQDOMAIN_EXP2_USB1_DOM (0x00007000u) -#define CONTROL_MREQDOMAIN_EXP2_USB1_DOM_SHIFT (0x0000000Cu) - -/** @brief L3_HW_FW_EXP_VAL_CONF0 register fields */ -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECDBG_EN (0x00040000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECDBG_EN_SHIFT (0x00000012u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECLOCK_EN (0x00000004u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECLOCK_EN_SHIFT (0x00000002u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECDBG_EN (0x01000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECDBG_EN_SHIFT (0x00000018u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECLOCK_EN (0x00000100u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECLOCK_EN_SHIFT (0x00000008u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECDBG_EN (0x00800000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECDBG_EN_SHIFT (0x00000017u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECLOCK_EN (0x00000080u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECLOCK_EN_SHIFT (0x00000007u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECDBG_EN (0x00100000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECDBG_EN_SHIFT (0x00000014u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECLOCK_EN (0x00000010u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECLOCK_EN_SHIFT (0x00000004u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECDBG_EN (0x00080000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECDBG_EN_SHIFT (0x00000013u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECLOCK_EN (0x00000008u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECLOCK_EN_SHIFT (0x00000003u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECDBG_EN (0x04000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECDBG_EN_SHIFT (0x0000001Au) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECLOCK_EN (0x00000400u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECLOCK_EN_SHIFT (0x0000000Au) - -/** @brief L3_HW_FW_EXP_VAL_CONF1 register fields */ -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECDBG_EN (0x08000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECDBG_EN_SHIFT (0x0000001Bu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECLOCK_EN (0x00000800u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECLOCK_EN_SHIFT (0x0000000Bu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECDBG_EN (0x10000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECDBG_EN_SHIFT (0x0000001Cu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECLOCK_EN (0x00001000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECLOCK_EN_SHIFT (0x0000000Cu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECDBG_EN (0x02000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECDBG_EN_SHIFT (0x00000019u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECLOCK_EN (0x00000200u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECLOCK_EN_SHIFT (0x00000009u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECDBG_EN (0x01000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECDBG_EN_SHIFT (0x00000018u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECLOCK_EN (0x00000100u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECLOCK_EN_SHIFT (0x00000008u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECDBG_EN (0x00080000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECDBG_EN_SHIFT (0x00000013u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECLOCK_EN (0x00000008u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECLOCK_EN_SHIFT (0x00000003u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECDBG_EN (0x00100000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECDBG_EN_SHIFT (0x00000014u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECLOCK_EN (0x00000010u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECLOCK_EN_SHIFT (0x00000004u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECDBG_EN (0x00200000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECDBG_EN_SHIFT (0x00000015u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECLOCK_EN (0x00000020u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECLOCK_EN_SHIFT (0x00000005u) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECDBG_EN (0x04000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECDBG_EN_SHIFT (0x0000001Au) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECLOCK_EN (0x00000400u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECLOCK_EN_SHIFT (0x0000000Au) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECDBG_EN (0x40000000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECDBG_EN_SHIFT (0x0000001Eu) - -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECLOCK_EN (0x00004000u) -#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECLOCK_EN_SHIFT (0x0000000Eu) - -/** @brief L4_HW_FW_EXP_VAL_CONF register fields */ -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECDBG_EN (0x01000000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECDBG_EN_SHIFT (0x00000018u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECLOCK_EN (0x00000100u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECLOCK_EN_SHIFT (0x00000008u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECDBG_EN (0x00100000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECDBG_EN_SHIFT (0x00000014u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECLOCK_EN (0x00000010u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECLOCK_EN_SHIFT (0x00000004u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECDBG_EN (0x00200000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECDBG_EN_SHIFT (0x00000015u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECLOCK_EN (0x00000020u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECLOCK_EN_SHIFT (0x00000005u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECDBG_EN (0x00010000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECDBG_EN_SHIFT (0x00000010u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECLOCK_EN (0x00000001u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECLOCK_EN_SHIFT (0x00000000u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECDBG_EN (0x00020000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECDBG_EN_SHIFT (0x00000011u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECLOCK_EN (0x00000002u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECLOCK_EN_SHIFT (0x00000001u) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECDBG_EN (0x10000000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECDBG_EN_SHIFT (0x0000001Cu) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECLOCK_EN (0x00001000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECLOCK_EN_SHIFT (0x0000000Cu) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECDBG_EN (0x20000000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECDBG_EN_SHIFT (0x0000001Du) - -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECLOCK_EN (0x00002000u) -#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECLOCK_EN_SHIFT (0x0000000Du) - -/** @brief CONTROL_SEC_LOAD_FW_EXP_VAL register fields */ -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FAST_LD_EXPVAL_REQN (0x00000010u) -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FAST_LD_EXPVAL_REQN_SHIFT (0x00000004u) - -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FW_LD_EXPVAL_REQN (0x00000004u) -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FW_LD_EXPVAL_REQN_SHIFT (0x00000002u) - -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4PER_LD_EXPVAL_REQN (0x00000008u) -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4PER_LD_EXPVAL_REQN_SHIFT (0x00000003u) - -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4WKUP_LD_EXPVAL_REQN (0x00000020u) -#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4WKUP_LD_EXPVAL_REQN_SHIFT (0x00000005u) - -/** @brief CONTROL_SEC_CTRL_RO register fields */ -#define CONTROL_SEC_CTRL_RO_CUSTMPK (0x00000010u) -#define CONTROL_SEC_CTRL_RO_CUSTMPK_SHIFT (0x00000004u) - -#define CONTROL_SEC_CTRL_RO_EMIF_CFG_RO_EN (0x00000002u) -#define CONTROL_SEC_CTRL_RO_EMIF_CFG_RO_EN_SHIFT (0x00000001u) - -#define CONTROL_SEC_CTRL_RO_EMIF_OBFS_EN (0x00000004u) -#define CONTROL_SEC_CTRL_RO_EMIF_OBFS_EN_SHIFT (0x00000002u) - -#define CONTROL_SEC_CTRL_RO_SECKEYACCEN (0x00000008u) -#define CONTROL_SEC_CTRL_RO_SECKEYACCEN_SHIFT (0x00000003u) - -/** @brief EMIF_OBFUSCATION_KEY register fields */ -#define CONTROL_EMIF_OBFUSCATION_KEY_OBFUSCATIONKEY (0x0000FFFFu) -#define CONTROL_EMIF_OBFUSCATION_KEY_OBFUSCATIONKEY_SHIFT (0x00000000u) - -/** @brief SEC_CLK_CTRL register fields */ -#define CONTROL_SEC_CLK_CTRL_SECCLKLCK (0x80000000u) -#define CONTROL_SEC_CLK_CTRL_SECCLKLCK_SHIFT (0x0000001Fu) - -#define CONTROL_SEC_CLK_CTRL_SECTIMERCLKSEL (0x00000030u) -#define CONTROL_SEC_CLK_CTRL_SECTIMERCLKSEL_SHIFT (0x00000004u) - -#define CONTROL_SEC_CLK_CTRL_SECWDCLKSEL (0x00000001u) -#define CONTROL_SEC_CLK_CTRL_SECWDCLKSEL_SHIFT (0x00000000u) - -/** @brief CONTROL_MREQDOMAIN_EXP3 register fields */ -#define CONTROL_MREQDOMAIN_EXP3_LCK (0x80000000u) -#define CONTROL_MREQDOMAIN_EXP3_LCK_SHIFT (0x0000001Fu) - -#define CONTROL_MREQDOMAIN_EXP3_PRU0_DOM (0x00000007u) -#define CONTROL_MREQDOMAIN_EXP3_PRU0_DOM_SHIFT (0x00000000u) - -#define CONTROL_MREQDOMAIN_EXP3_PRU1_DOM (0x00000038u) -#define CONTROL_MREQDOMAIN_EXP3_PRU1_DOM_SHIFT (0x00000003u) - -#define CONTROL_MREQDOMAIN_EXP3_PRU2_DOM (0x000001C0u) -#define CONTROL_MREQDOMAIN_EXP3_PRU2_DOM_SHIFT (0x00000006u) - -#define CONTROL_MREQDOMAIN_EXP3_PRU3_DOM (0x00000E00u) -#define CONTROL_MREQDOMAIN_EXP3_PRU3_DOM_SHIFT (0x00000009u) - -/** @brief CONTROL_CEK(n) register fields */ -#define CONTROL_CEK_CEK (0xFFFFFFFFu) -#define CONTROL_CEK_CEK_SHIFT (0x00000000u) - -/** @brief CONTROL_CEK_BCH(n) register fields */ -#define CONTROL_CEK_BCH_CEK_BCH (0xFFFFFFFFu) -#define CONTROL_CEK_BCH_CEK_BCH_SHIFT (0x00000000u) - -/** @brief CONTROL_MSV_0 register fields */ -#define CONTROL_MSV_0_MSV (0xFFFFFFFFu) -#define CONTROL_MSV_0_MSV_SHIFT (0x00000000u) - -/** @brief CONTROL_MSV_BCH(n) register fields */ -#define CONTROL_MSV_BCH_MSV_BCH (0xFFFFFFFFu) -#define CONTROL_MSV_BCH_MSV_BCH_SHIFT (0x00000000u) - -/** @brief CONTROL_SEC_STATUS register fields */ -#define CONTROL_SEC_STATUS_EMURST (0x00000020u) -#define CONTROL_SEC_STATUS_EMURST_SHIFT (0x00000005u) - -#define CONTROL_SEC_STATUS_GFXDOMAINRST (0x00000200u) -#define CONTROL_SEC_STATUS_GFXDOMAINRST_SHIFT (0x00000009u) - -#define CONTROL_SEC_STATUS_GLOBALCOLDRST (0x00000001u) -#define CONTROL_SEC_STATUS_GLOBALCOLDRST_SHIFT (0x00000000u) - -#define CONTROL_SEC_STATUS_GLOBALWARMRST (0x00000002u) -#define CONTROL_SEC_STATUS_GLOBALWARMRST_SHIFT (0x00000001u) - -#define CONTROL_SEC_STATUS_ICSS0RST (0x00040000u) -#define CONTROL_SEC_STATUS_ICSS0RST_SHIFT (0x00000012u) - -#define CONTROL_SEC_STATUS_ICSS1RST (0x00080000u) -#define CONTROL_SEC_STATUS_ICSS1RST_SHIFT (0x00000013u) - -#define CONTROL_SEC_STATUS_MPUDOMAINRST (0x00000040u) -#define CONTROL_SEC_STATUS_MPUDOMAINRST_SHIFT (0x00000006u) - -#define CONTROL_SEC_STATUS_MPURST (0x00020000u) -#define CONTROL_SEC_STATUS_MPURST_SHIFT (0x00000011u) - -#define CONTROL_SEC_STATUS_PERDOMAINRST (0x00000080u) -#define CONTROL_SEC_STATUS_PERDOMAINRST_SHIFT (0x00000007u) - -#define CONTROL_SEC_STATUS_PUBWDRST (0x00000004u) -#define CONTROL_SEC_STATUS_PUBWDRST_SHIFT (0x00000002u) - -#define CONTROL_SEC_STATUS_SECWDRST (0x00000008u) -#define CONTROL_SEC_STATUS_SECWDRST_SHIFT (0x00000003u) - -#define CONTROL_SEC_STATUS_SSMVIOLATIONRST (0x00000010u) -#define CONTROL_SEC_STATUS_SSMVIOLATIONRST_SHIFT (0x00000004u) - -#define CONTROL_SEC_STATUS_WKUPDOMAINRST (0x00000100u) -#define CONTROL_SEC_STATUS_WKUPDOMAINRST_SHIFT (0x00000008u) - -/** @brief CONTROL_SECMEM_STATUS register fields */ -#define CONTROL_SECMEM_STATUS_A8L1DEST (0x00000001u) -#define CONTROL_SECMEM_STATUS_A8L1DEST_SHIFT (0x00000000u) - -#define CONTROL_SECMEM_STATUS_A8L1NOTACC (0x00010000u) -#define CONTROL_SECMEM_STATUS_A8L1NOTACC_SHIFT (0x00000010u) - -#define CONTROL_SECMEM_STATUS_A8L2DEST (0x00000002u) -#define CONTROL_SECMEM_STATUS_A8L2DEST_SHIFT (0x00000001u) - -#define CONTROL_SECMEM_STATUS_A8L2NOTACC (0x00020000u) -#define CONTROL_SECMEM_STATUS_A8L2NOTACC_SHIFT (0x00000011u) - -#define CONTROL_SECMEM_STATUS_FASTSECRAMDEST (0x00000004u) -#define CONTROL_SECMEM_STATUS_FASTSECRAMDEST_SHIFT (0x00000002u) - -#define CONTROL_SECMEM_STATUS_FASTSECRAMNOTACC (0x00040000u) -#define CONTROL_SECMEM_STATUS_FASTSECRAMNOTACC_SHIFT (0x00000012u) - -#define CONTROL_SECMEM_STATUS_L3SECRAMDEST (0x00000008u) -#define CONTROL_SECMEM_STATUS_L3SECRAMDEST_SHIFT (0x00000003u) - -#define CONTROL_SECMEM_STATUS_L3SECRAMNOTACC (0x00080000u) -#define CONTROL_SECMEM_STATUS_L3SECRAMNOTACC_SHIFT (0x00000013u) - -/** @brief CONTROL_SEC_ERR_STAT_FUNC0 register fields */ -#define CONTROL_SEC_ERR_STAT_FUNC0_EMIFFWERR (0x00000010u) -#define CONTROL_SEC_ERR_STAT_FUNC0_EMIFFWERR_SHIFT (0x00000004u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_GPMCFWERR (0x00000004u) -#define CONTROL_SEC_ERR_STAT_FUNC0_GPMCFWERR_SHIFT (0x00000002u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_L3RAMFWERR (0x00000001u) -#define CONTROL_SEC_ERR_STAT_FUNC0_L3RAMFWERR_SHIFT (0x00000000u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_SGXFWERR (0x00020000u) -#define CONTROL_SEC_ERR_STAT_FUNC0_SGXFWERR_SHIFT (0x00000011u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC0FWERR (0x01000000u) -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC0FWERR_SHIFT (0x00000018u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC1FWERR (0x02000000u) -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC1FWERR_SHIFT (0x00000019u) - -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC2FWERR (0x04000000u) -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC2FWERR_SHIFT (0x0000001Au) - -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTCCFWERR (0x00800000u) -#define CONTROL_SEC_ERR_STAT_FUNC0_TPTCCFWERR_SHIFT (0x00000017u) - -/** @brief CONTROL_SEC_ERR_STAT_FUNC1 register fields */ -#define CONTROL_SEC_ERR_STAT_FUNC1_ADCFWERR (0x00000200u) -#define CONTROL_SEC_ERR_STAT_FUNC1_ADCFWERR_SHIFT (0x00000009u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_AES0FWERR (0x00100000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_AES0FWERR_SHIFT (0x00000014u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_CRYPTODMAFWERR (0x00080000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_CRYPTODMAFWERR_SHIFT (0x00000013u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_DBGPORTFWERR (0x00020000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_DBGPORTFWERR_SHIFT (0x00000011u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_L3EXPFWERR (0x00010000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_L3EXPFWERR_SHIFT (0x00000010u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_L4FASTFWERR (0x02000000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_L4FASTFWERR_SHIFT (0x00000019u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_L4FWFWERR (0x08000000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_L4FWFWERR_SHIFT (0x0000001Bu) - -#define CONTROL_SEC_ERR_STAT_FUNC1_L4PERFWERR (0x01000000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_L4PERFWERR_SHIFT (0x00000018u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_L4WKUPFWERR (0x04000000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_L4WKUPFWERR_SHIFT (0x0000001Au) - -#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP0FWERR (0x00000001u) -#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP0FWERR_SHIFT (0x00000000u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP1FWERR (0x00000002u) -#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP1FWERR_SHIFT (0x00000001u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_MMCHS2FWERR (0x00008000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_MMCHS2FWERR_SHIFT (0x0000000Fu) - -#define CONTROL_SEC_ERR_STAT_FUNC1_SECMODFWERR (0x00040000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_SECMODFWERR_SHIFT (0x00000012u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_SHAFWERR (0x00400000u) -#define CONTROL_SEC_ERR_STAT_FUNC1_SHAFWERR_SHIFT (0x00000016u) - -#define CONTROL_SEC_ERR_STAT_FUNC1_USBFWERR (0x00000800u) -#define CONTROL_SEC_ERR_STAT_FUNC1_USBFWERR_SHIFT (0x0000000Bu) - -/** @brief CONTROL_SEC_ERR_STAT_DBUG0 register fields */ -#define CONTROL_SEC_ERR_STAT_DBUG0_EMIFDBGFWERR (0x00000010u) -#define CONTROL_SEC_ERR_STAT_DBUG0_EMIFDBGFWERR_SHIFT (0x00000004u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_GPMCDBGFWERR (0x00000004u) -#define CONTROL_SEC_ERR_STAT_DBUG0_GPMCDBGFWERR_SHIFT (0x00000002u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_L3RAMDBGFWERR (0x00000001u) -#define CONTROL_SEC_ERR_STAT_DBUG0_L3RAMDBGFWERR_SHIFT (0x00000000u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_SGXDBGFWERR (0x00020000u) -#define CONTROL_SEC_ERR_STAT_DBUG0_SGXDBGFWERR_SHIFT (0x00000011u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC0DBGFWERR (0x01000000u) -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC0DBGFWERR_SHIFT (0x00000018u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC1DBGFWERR (0x02000000u) -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC1DBGFWERR_SHIFT (0x00000019u) - -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC2DBGFWERR (0x04000000u) -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC2DBGFWERR_SHIFT (0x0000001Au) - -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTCCDBGFWERR (0x00800000u) -#define CONTROL_SEC_ERR_STAT_DBUG0_TPTCCDBGFWERR_SHIFT (0x00000017u) - -/** @brief CONTROL_SEC_ERR_STAT_DBUG1 register fields */ -#define CONTROL_SEC_ERR_STAT_DBUG1_ADCDBGFWERR (0x00000200u) -#define CONTROL_SEC_ERR_STAT_DBUG1_ADCDBGFWERR_SHIFT (0x00000009u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_AES0DBGFWERR (0x00100000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_AES0DBGFWERR_SHIFT (0x00000014u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_CRYPTODMADBGFWERR (0x00080000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_CRYPTODMADBGFWERR_SHIFT (0x00000013u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_DBGPORTDBGFWERR (0x00020000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_DBGPORTDBGFWERR_SHIFT (0x00000011u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_L3EXPDBGFWERR (0x00010000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_L3EXPDBGFWERR_SHIFT (0x00000010u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_L4FASTDBGFWERR (0x02000000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_L4FASTDBGFWERR_SHIFT (0x00000019u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_L4FWDBGFWERR (0x08000000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_L4FWDBGFWERR_SHIFT (0x0000001Bu) - -#define CONTROL_SEC_ERR_STAT_DBUG1_L4PERDBGFWERR (0x01000000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_L4PERDBGFWERR_SHIFT (0x00000018u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_L4WKUPDBGFWERR (0x04000000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_L4WKUPDBGFWERR_SHIFT (0x0000001Au) - -#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP0DBGFWERR (0x00000001u) -#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP0DBGFWERR_SHIFT (0x00000000u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP1DBGFWERR (0x00000002u) -#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP1DBGFWERR_SHIFT (0x00000001u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_MMCHS2DBGFWERR (0x00008000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_MMCHS2DBGFWERR_SHIFT (0x0000000Fu) - -#define CONTROL_SEC_ERR_STAT_DBUG1_SHADBGFWERR (0x00400000u) -#define CONTROL_SEC_ERR_STAT_DBUG1_SHADBGFWERR_SHIFT (0x00000016u) - -#define CONTROL_SEC_ERR_STAT_DBUG1_USBDBGFWERR (0x00000800u) -#define CONTROL_SEC_ERR_STAT_DBUG1_USBDBGFWERR_SHIFT (0x0000000Bu) - -/** @brief CONTROL_KEK_SW(n) register fields */ -#define CONTROL_KEK_SW_KEK_SW (0xFFFFFFFFu) -#define CONTROL_KEK_SW_KEK_SW_SHIFT (0x00000000u) - -/** @brief CONTROL_CMPK_BCH(n) register fields */ -#define CONTROL_CMPK_BCH_CMPK_BCH (0xFFFFFFFFu) -#define CONTROL_CMPK_BCH_CMPK_BCH_SHIFT (0x00000000u) - -/** @brief CONTROL_CMPK(n) register fields */ -#define CONTROL_CMPK_CMPK (0xFFFFFFFFu) -#define CONTROL_CMPK_CMPK_SHIFT (0x00000000u) - -/** @brief CONTROL_DUCATI_CLKSRC register fields */ -#define CONTROL_DUCATI_CLKSRC_DUCATI_MUX_SRC (0x00000003u) -#define CONTROL_DUCATI_CLKSRC_DUCATI_MUX_SRC_SHIFT (0x0u) - -/** @brief CONTROL_DSS_CLKSRC register fields */ -#define CONTROL_DSS_CLKSRC_DSS_MUX_SRC (0x00000003u) -#define CONTROL_DSS_CLKSRC_DSS_MUX_SRC_SHIFT (0x0u) - -/** @brief SSM_END_FAST_SECRAM register fields */ -#define CONTROL_SSM_END_FAST_SECRAM_END_FAST_SECRAM (0x0000FC00u) -#define CONTROL_SSM_END_FAST_SECRAM_END_FAST_SECRAM_SHIFT (0x0000000Au) - -/** @brief SSM_FIREWALL_CONTROLLER register fields */ -#define CONTROL_SSM_FIREWALL_CONTROLLER_CPSR_ENFC_EN (0x00001000u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_CPSR_ENFC_EN_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_DC_ENFC_EN (0x00000800u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_DC_ENFC_EN_SHIFT (0x0000000Bu) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_IC_ENFC_EN (0x00000400u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_IC_ENFC_EN_SHIFT (0x0000000Au) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MMU_ENFC_EN (0x00000200u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MMU_ENFC_EN_SHIFT (0x00000009u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MONITOR_EN (0x00000001u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MONITOR_EN_SHIFT (0x00000000u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DATA_TRASH_EN (0x00000080u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DATA_TRASH_EN_SHIFT (0x00000007u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DETM_EN (0x00000020u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DETM_EN_SHIFT (0x00000005u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_IETM_EN (0x00000010u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_IETM_EN_SHIFT (0x00000004u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_RAMCODE_EN (0x00000100u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_RAMCODE_EN_SHIFT (0x00000008u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_STACK_EN (0x00000040u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_STACK_EN_SHIFT (0x00000006u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_SECRAM_EN (0x00000002u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_SECRAM_EN_SHIFT (0x00000001u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_SPM_STACK_EN (0x00000008u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_SPM_STACK_EN_SHIFT (0x00000003u) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_SSM_FC_REG_LOCK (0x00002000u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_SSM_FC_REG_LOCK_SHIFT (0x0000000Du) - -#define CONTROL_SSM_FIREWALL_CONTROLLER_STACKEDRAM_EN (0x00000004u) -#define CONTROL_SSM_FIREWALL_CONTROLLER_STACKEDRAM_EN_SHIFT (0x00000002u) - -/** @brief SSM_START_SECURE_STACKED_RAM register fields */ -#define CONTROL_SSM_START_SECURE_STACKED_RAM_START_STACKEDRAM (0xFFFF0000u) -#define CONTROL_SSM_START_SECURE_STACKED_RAM_START_STACKEDRAM_SHIFT (0x00000010u) - -/** @brief SSM_END_SECURE_STACKED_RAM register fields */ -#define CONTROL_SSM_END_SECURE_STACKED_RAM_END_STACKEDRAM (0xFFFF0000u) -#define CONTROL_SSM_END_SECURE_STACKED_RAM_END_STACKEDRAM_SHIFT (0x00000010u) - -/** @brief SSM_START_SPM_STACK register fields */ -#define CONTROL_SSM_START_SPM_STACK_START_SPM_STACK (0xFFFFFC00u) -#define CONTROL_SSM_START_SPM_STACK_START_SPM_STACK_SHIFT (0x0000000Au) - -/** @brief SSM_END_SPM_STACK register fields */ -#define CONTROL_SSM_END_SPM_STACK_END_SPM_STACK (0x0000FC00u) -#define CONTROL_SSM_END_SPM_STACK_END_SPM_STACK_SHIFT (0x0000000Au) - -#define CONTROL_SSM_END_SPM_STACK_START_SPM_STACK (0xFFFF0000u) -#define CONTROL_SSM_END_SPM_STACK_START_SPM_STACK_SHIFT (0x00000010u) - -/** @brief SSM_START_MONITOR_RAMCODE register fields */ -#define CONTROL_SSM_START_MONITOR_RAMCODE_START_MON_RAMCODE (0xFFFFFC00u) -#define CONTROL_SSM_START_MONITOR_RAMCODE_START_MON_RAMCODE_SHIFT (0x0000000Au) - -/** @brief SSM_END_MONITOR_RAMCODE register fields */ -#define CONTROL_SSM_END_MONITOR_RAMCODE_END_MON_RAMCODE (0x0000FC00u) -#define CONTROL_SSM_END_MONITOR_RAMCODE_END_MON_RAMCODE_SHIFT (0x0000000Au) - -#define CONTROL_SSM_END_MONITOR_RAMCODE_START_MON_RAMCODE (0xFFFF0000u) -#define CONTROL_SSM_END_MONITOR_RAMCODE_START_MON_RAMCODE_SHIFT (0x00000010u) - -/** @brief SSM_END_MONITOR_RAMDATA register fields */ -#define CONTROL_SSM_END_MONITOR_RAMDATA_END_MON_RAMDATA (0x0000FC00u) -#define CONTROL_SSM_END_MONITOR_RAMDATA_END_MON_RAMDATA_SHIFT (0x0000000Au) - -#define CONTROL_SSM_END_MONITOR_RAMDATA_START_MON_RAMCODE (0xFFFF0000u) -#define CONTROL_SSM_END_MONITOR_RAMDATA_START_MON_RAMCODE_SHIFT (0x00000010u) - -/** @brief SSM_START_MONITOR_CODE register fields */ -#define CONTROL_SSM_START_MONITOR_CODE_START_MON_CODE (0xFFFFFC00u) -#define CONTROL_SSM_START_MONITOR_CODE_START_MON_CODE_SHIFT (0x0000000Au) - -/** @brief SSM_END_MONITOR_CODE register fields */ -#define CONTROL_SSM_END_MONITOR_CODE_END_MON_CODE (0x0001FC00u) -#define CONTROL_SSM_END_MONITOR_CODE_END_MON_CODE_SHIFT (0x0000000Au) - -#define CONTROL_SSM_END_MONITOR_CODE_START_MON_CODE (0xFFFE0000u) -#define CONTROL_SSM_END_MONITOR_CODE_START_MON_CODE_SHIFT (0x00000011u) - -/** @brief SSM_START_MONITOR_PERIPH register fields */ -#define CONTROL_SSM_START_MONITOR_PERIPH_START_MON_PERIPH (0xFFFFF000u) -#define CONTROL_SSM_START_MONITOR_PERIPH_START_MON_PERIPH_SHIFT (0x0000000Cu) - -/** @brief SSM_END_MONITOR_PERIPH register fields */ -#define CONTROL_SSM_END_MONITOR_PERIPH_END_MON_PERIPH (0x0FFFF000u) -#define CONTROL_SSM_END_MONITOR_PERIPH_END_MON_PERIPH_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_END_MONITOR_PERIPH_START_MON_PERIPH (0xF0000000u) -#define CONTROL_SSM_END_MONITOR_PERIPH_START_MON_PERIPH_SHIFT (0x0000001Cu) - -/** @brief SSM_START_MONITOR_STACK register fields */ -#define CONTROL_SSM_START_MONITOR_STACK_START_MON_STACK (0xFFFFFC00u) -#define CONTROL_SSM_START_MONITOR_STACK_START_MON_STACK_SHIFT (0x0000000Au) - -/** @brief SSM_END_MONITOR_STACK register fields */ -#define CONTROL_SSM_END_MONITOR_STACK_END_MON_STACK (0x00007C00u) -#define CONTROL_SSM_END_MONITOR_STACK_END_MON_STACK_SHIFT (0x0000000Au) - -#define CONTROL_SSM_END_MONITOR_STACK_START_MON_STACK (0xFFFF8000u) -#define CONTROL_SSM_END_MONITOR_STACK_START_MON_STACK_SHIFT (0x0000000Fu) - -/** @brief SSM_START_MONITOR_RAMCODE_ETM register fields */ -#define CONTROL_SSM_START_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM (0xFFFFF000u) -#define CONTROL_SSM_START_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM_SHIFT (0x0000000Cu) - -/** @brief SSM_END_MONITOR_RAMCODE_ETM register fields */ -#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_END_MON_RAMCODE_ETM (0x0000F000u) -#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_END_MON_RAMCODE_ETM_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM (0xFFFF0000u) -#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM_SHIFT (0x00000010u) - -/** @brief SSM_END_MONITOR_RAMDATA_ETM register fields */ -#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_END_MON_RAMDATA_ETM (0x0000F000u) -#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_END_MON_RAMDATA_ETM_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_START_MON_RAMCODE_ETM (0xFFFF0000u) -#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_START_MON_RAMCODE_ETM_SHIFT (0x00000010u) - -/** @brief SSM_START_MONITOR_CODE_ETM register fields */ -#define CONTROL_SSM_START_MONITOR_CODE_ETM_START_MON_CODE_ETM (0xFFFFF000u) -#define CONTROL_SSM_START_MONITOR_CODE_ETM_START_MON_CODE_ETM_SHIFT (0x0000000Cu) - -/** @brief SSM_END_MONITOR_CODE_ETM register fields */ -#define CONTROL_SSM_END_MONITOR_CODE_ETM_END_MON_CODE_ETM (0x0001F000u) -#define CONTROL_SSM_END_MONITOR_CODE_ETM_END_MON_CODE_ETM_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_END_MONITOR_CODE_ETM_START_MON_CODE_ETM (0xFFFE0000u) -#define CONTROL_SSM_END_MONITOR_CODE_ETM_START_MON_CODE_ETM_SHIFT (0x00000011u) - -/** @brief SSM_START_MONITOR_STACK_ETM register fields */ -#define CONTROL_SSM_START_MONITOR_STACK_ETM_START_MON_STACK_ETM (0xFFFFF000u) -#define CONTROL_SSM_START_MONITOR_STACK_ETM_START_MON_STACK_ETM_SHIFT (0x0000000Cu) - -/** @brief SSM_END_MONITOR_STACK_ETM register fields */ -#define CONTROL_SSM_END_MONITOR_STACK_ETM_END_MON_STACK_ETM (0x0000F000u) -#define CONTROL_SSM_END_MONITOR_STACK_ETM_END_MON_STACK_ETM_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_END_MONITOR_STACK_ETM_START_MON_STACK_ETM (0xFFFF0000u) -#define CONTROL_SSM_END_MONITOR_STACK_ETM_START_MON_STACK_ETM_SHIFT (0x00000010u) - -/** @brief SSM_START_MONITOR_SHARED_ETM register fields */ -#define CONTROL_SSM_START_MONITOR_SHARED_ETM_START_MON_SHARED_ETM (0xFFFFF000u) -#define CONTROL_SSM_START_MONITOR_SHARED_ETM_START_MON_SHARED_ETM_SHIFT (0x0000000Cu) - -/** @brief SSM_END_MONITOR_SHARED_ETM register fields */ -#define CONTROL_SSM_END_MONITOR_SHARED_ETM_END_MON_SHARED_ETM (0x0000F000u) -#define CONTROL_SSM_END_MONITOR_SHARED_ETM_END_MON_SHARED_ETM_SHIFT (0x0000000Cu) - -#define CONTROL_SSM_END_MONITOR_SHARED_ETM_START_MON_SHARED_ETM (0xFFFF0000u) -#define CONTROL_SSM_END_MONITOR_SHARED_ETM_START_MON_SHARED_ETM_SHIFT (0x00000010u) - -/** @brief SSM_START_MONITOR_PERIPH_ETM register fields */ -#define CONTROL_SSM_START_MONITOR_PERIPH_ETM_START_MON_PERIPH_ETM (0xFFFFF000u) -#define CONTROL_SSM_START_MONITOR_PERIPH_ETM_START_MON_PERIPH_ETM_SHIFT (0x0000000Cu) - -/** @brief SSM_END_MONITOR_PERIPH_ETM register fields */ -#define CONTROL_SSM_END_MONITOR_PERIPH_ETM_END_MON_PERIPH_ETM (0xFFFFF000u) -#define CONTROL_SSM_END_MONITOR_PERIPH_ETM_END_MON_PERIPH_ETM_SHIFT (0x0000000Cu) - -/** @brief SSM_CPSR_MODE_ENFC register fields */ -#define CONTROL_SSM_CPSR_MODE_ENFC_EA_TRAPPED_IN_MON (0x00000100u) -#define CONTROL_SSM_CPSR_MODE_ENFC_EA_TRAPPED_IN_MON_SHIFT (0x00000008u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_FIQ_TRAPPED_IN_MON (0x00000080u) -#define CONTROL_SSM_CPSR_MODE_ENFC_FIQ_TRAPPED_IN_MON_SHIFT (0x00000007u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_IRQ_TRAPPED_IN_MON (0x00000040u) -#define CONTROL_SSM_CPSR_MODE_ENFC_IRQ_TRAPPED_IN_MON_SHIFT (0x00000006u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_ABORT_ENFC (0x00000004u) -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_ABORT_ENFC_SHIFT (0x00000002u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_SYS_ENFC (0x00000010u) -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_SYS_ENFC_SHIFT (0x00000004u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_UNDEF_ENFC (0x00000008u) -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_UNDEF_ENFC_SHIFT (0x00000003u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_USER_ENFC (0x00000002u) -#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_USER_ENFC_SHIFT (0x00000001u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_SYS_VS_USER_ENFC (0x00000020u) -#define CONTROL_SSM_CPSR_MODE_ENFC_SYS_VS_USER_ENFC_SHIFT (0x00000005u) - -#define CONTROL_SSM_CPSR_MODE_ENFC_TZ_NS_BIT_ENFC (0x00000001u) -#define CONTROL_SSM_CPSR_MODE_ENFC_TZ_NS_BIT_ENFC_SHIFT (0x00000000u) - -/** @brief SSM_END_L3_SECRAM register fields */ -#define CONTROL_SSM_END_L3_SECRAM_END_L3_SECRAM (0x0000FC00u) -#define CONTROL_SSM_END_L3_SECRAM_END_L3_SECRAM_SHIFT (0x0000000Au) - -/** @brief CONTROL_SGX_VBBLDO_CTRL register fields */ -#define CONTROL_SGX_VBBLDO_CTRL_VSETFBB (0x03E00000u) -#define CONTROL_SGX_VBBLDO_CTRL_VSETFBB_SHIFT (0x15u) - -#define CONTROL_SGX_VBBLDO_CTRL_VSETRBB (0x001F0000u) -#define CONTROL_SGX_VBBLDO_CTRL_VSETRBB_SHIFT (0x10u) - -#define CONTROL_SGX_VBBLDO_CTRL_LDOBYPASSZ (0x00000020u) -#define CONTROL_SGX_VBBLDO_CTRL_LDOBYPASSZ_SHIFT (0x5u) - -#define CONTROL_SGX_VBBLDO_CTRL_LOWPWR (0x00000010u) -#define CONTROL_SGX_VBBLDO_CTRL_LOWPWR_SHIFT (0x4u) - -#define CONTROL_SGX_VBBLDO_CTRL_HZ (0x00000008u) -#define CONTROL_SGX_VBBLDO_CTRL_HZ_SHIFT (0x3u) - -#define CONTROL_SGX_VBBLDO_CTRL_BBSEL (0x00000004u) -#define CONTROL_SGX_VBBLDO_CTRL_BBSEL_SHIFT (0x2u) - -#define CONTROL_SGX_VBBLDO_CTRL_NOCAP (0x00000002u) -#define CONTROL_SGX_VBBLDO_CTRL_NOCAP_SHIFT (0x1u) - -#define CONTROL_SGX_VBBLDO_CTRL_NOVBGBYR (0x00000001u) -#define CONTROL_SGX_VBBLDO_CTRL_NOVBGBYR_SHIFT (0x0u) - -/** @brief CONTROL_GEM_VBBLDO_CTRL register fields */ -#define CONTROL_GEM_VBBLDO_CTRL_VSETFBB (0x03E00000u) -#define CONTROL_GEM_VBBLDO_CTRL_VSETFBB_SHIFT (0x15u) - -#define CONTROL_GEM_VBBLDO_CTRL_VSETRBB (0x001F0000u) -#define CONTROL_GEM_VBBLDO_CTRL_VSETRBB_SHIFT (0x10u) - -#define CONTROL_GEM_VBBLDO_CTRL_LDOBYPASSZ (0x00000020u) -#define CONTROL_GEM_VBBLDO_CTRL_LDOBYPASSZ_SHIFT (0x5u) - -#define CONTROL_GEM_VBBLDO_CTRL_LOWPWR (0x00000010u) -#define CONTROL_GEM_VBBLDO_CTRL_LOWPWR_SHIFT (0x4u) - -#define CONTROL_GEM_VBBLDO_CTRL_HZ (0x00000008u) -#define CONTROL_GEM_VBBLDO_CTRL_HZ_SHIFT (0x3u) - -#define CONTROL_GEM_VBBLDO_CTRL_BBSEL (0x00000004u) -#define CONTROL_GEM_VBBLDO_CTRL_BBSEL_SHIFT (0x2u) - -#define CONTROL_GEM_VBBLDO_CTRL_NOCAP (0x00000002u) -#define CONTROL_GEM_VBBLDO_CTRL_NOCAP_SHIFT (0x1u) - -#define CONTROL_GEM_VBBLDO_CTRL_NOVBGBYR (0x00000001u) -#define CONTROL_GEM_VBBLDO_CTRL_NOVBGBYR_SHIFT (0x0u) - -/** @brief CORTEX_VBBLDO_CTRL register fields */ -#define CONTROL_CORTEX_VBBLDO_CTRL_BBSEL (0x00000004u) -#define CONTROL_CORTEX_VBBLDO_CTRL_BBSEL_SHIFT (0x00000002u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_HZ (0x00000008u) -#define CONTROL_CORTEX_VBBLDO_CTRL_HZ_SHIFT (0x00000003u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_LDOBYPASSZ (0x00000020u) -#define CONTROL_CORTEX_VBBLDO_CTRL_LDOBYPASSZ_SHIFT (0x00000005u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_LOWPWR (0x00000010u) -#define CONTROL_CORTEX_VBBLDO_CTRL_LOWPWR_SHIFT (0x00000004u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_NOCAP (0x00000002u) -#define CONTROL_CORTEX_VBBLDO_CTRL_NOCAP_SHIFT (0x00000001u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_NOVBGBYR (0x00000001u) -#define CONTROL_CORTEX_VBBLDO_CTRL_NOVBGBYR_SHIFT (0x00000000u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_VSETFBB (0x03E00000u) -#define CONTROL_CORTEX_VBBLDO_CTRL_VSETFBB_SHIFT (0x00000015u) - -#define CONTROL_CORTEX_VBBLDO_CTRL_VSETRBB (0x001F0000u) -#define CONTROL_CORTEX_VBBLDO_CTRL_VSETRBB_SHIFT (0x00000010u) - -/** @brief CONTROL_RAMLDO_CTRL register fields */ -#define CONTROL_RAMLDO_CTRL_VSET (0x03FF0000u) -#define CONTROL_RAMLDO_CTRL_VSET_SHIFT (0x10u) - -#define CONTROL_RAMLDO_CTRL_AIPOFF (0x00000080u) -#define CONTROL_RAMLDO_CTRL_AIPOFF_SHIFT (0x7u) - -#define CONTROL_RAMLDO_CTRL_SRAMALLRET (0x00000040u) -#define CONTROL_RAMLDO_CTRL_SRAMALLRET_SHIFT (0x6u) - -#define CONTROL_RAMLDO_CTRL_ABBOFF (0x00000020u) -#define CONTROL_RAMLDO_CTRL_ABBOFF_SHIFT (0x5u) - -#define CONTROL_RAMLDO_CTRL_ENFUNC5 (0x00000010u) -#define CONTROL_RAMLDO_CTRL_ENFUNC5_SHIFT (0x4u) - -#define CONTROL_RAMLDO_CTRL_ENFUNC4 (0x00000008u) -#define CONTROL_RAMLDO_CTRL_ENFUNC4_SHIFT (0x3u) - -#define CONTROL_RAMLDO_CTRL_ENFUNC3 (0x00000004u) -#define CONTROL_RAMLDO_CTRL_ENFUNC3_SHIFT (0x2u) - -#define CONTROL_RAMLDO_CTRL_ENFUNC2 (0x00000002u) -#define CONTROL_RAMLDO_CTRL_ENFUNC2_SHIFT (0x1u) - -#define CONTROL_RAMLDO_CTRL_ENFUNC1 (0x00000001u) -#define CONTROL_RAMLDO_CTRL_ENFUNC1_SHIFT (0x0u) - -/** @brief REFCLK_LJCBLDO_CTRL register fields */ -#define CONTROL_REFCLK_LJCBLDO_CTRL_ABBOFF (0x00000040u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_ABBOFF_SHIFT (0x00000006u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_AIPOFF (0x00000080u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_AIPOFF_SHIFT (0x00000007u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC1 (0x00000001u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC1_SHIFT (0x00000000u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC2 (0x00000002u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC2_SHIFT (0x00000001u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC3 (0x00000004u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC3_SHIFT (0x00000002u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC4 (0x00000008u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC4_SHIFT (0x00000003u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC5 (0x00000010u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC5_SHIFT (0x00000004u) - -#define CONTROL_REFCLK_LJCBLDO_CTRL_VSET (0x03FF0000u) -#define CONTROL_REFCLK_LJCBLDO_CTRL_VSET_SHIFT (0x00000010u) - -/** @brief BANDGAP_CTRL register fields */ -#define CONTROL_BANDGAP_CTRL_BGROFF (0x00000040u) -#define CONTROL_BANDGAP_CTRL_BGROFF_SHIFT (0x00000006u) - -#define CONTROL_BANDGAP_CTRL_CBIASSEL (0x00000080u) -#define CONTROL_BANDGAP_CTRL_CBIASSEL_SHIFT (0x00000007u) - -#define CONTROL_BANDGAP_CTRL_CLRZ (0x00000008u) -#define CONTROL_BANDGAP_CTRL_CLRZ_SHIFT (0x00000003u) - -#define CONTROL_BANDGAP_CTRL_CONTCONV (0x00000004u) -#define CONTROL_BANDGAP_CTRL_CONTCONV_SHIFT (0x00000002u) - -#define CONTROL_BANDGAP_CTRL_DTEMP (0x0000FF00u) -#define CONTROL_BANDGAP_CTRL_DTEMP_SHIFT (0x00000008u) - -#define CONTROL_BANDGAP_CTRL_ECOZ (0x00000002u) -#define CONTROL_BANDGAP_CTRL_ECOZ_SHIFT (0x00000001u) - -#define CONTROL_BANDGAP_CTRL_SOC (0x00000010u) -#define CONTROL_BANDGAP_CTRL_SOC_SHIFT (0x00000004u) - -#define CONTROL_BANDGAP_CTRL_TMPSOFF (0x00000020u) -#define CONTROL_BANDGAP_CTRL_TMPSOFF_SHIFT (0x00000005u) - -#define CONTROL_BANDGAP_CTRL_TSHUT (0x00000001u) -#define CONTROL_BANDGAP_CTRL_TSHUT_SHIFT (0x00000000u) - -/** @brief BANDGAP_TRIM register fields */ -#define CONTROL_BANDGAP_TRIM_DTRBGAPC (0xFF000000u) -#define CONTROL_BANDGAP_TRIM_DTRBGAPC_SHIFT (0x00000018u) - -#define CONTROL_BANDGAP_TRIM_DTRBGAPV (0x00FF0000u) -#define CONTROL_BANDGAP_TRIM_DTRBGAPV_SHIFT (0x00000010u) - -#define CONTROL_BANDGAP_TRIM_DTRTEMPS (0x0000FF00u) -#define CONTROL_BANDGAP_TRIM_DTRTEMPS_SHIFT (0x00000008u) - -#define CONTROL_BANDGAP_TRIM_DTRTEMPSC (0x000000FFu) -#define CONTROL_BANDGAP_TRIM_DTRTEMPSC_SHIFT (0x00000000u) - -/** @brief CONTROL_OSC_CTRL(n) register fields */ -#define CONTROL_OSC0_CTRL_RESELECT (0x00000001u) -#define CONTROL_OSC0_CTRL_RESELECT_SHIFT (0x0u) - -#define CONTROL_OSC1_CTRL_GZ (0x00000008u) -#define CONTROL_OSC1_CTRL_GZ_SHIFT (0x3u) - -#define CONTROL_OSC1_CTRL_SW2 (0x00000004u) -#define CONTROL_OSC1_CTRL_SW2_SHIFT (0x2u) - -#define CONTROL_OSC1_CTRL_SW1 (0x00000002u) -#define CONTROL_OSC1_CTRL_SW1_SHIFT (0x1u) - -#define CONTROL_OSC1_CTRL_RESELECT (0x00000001u) -#define CONTROL_OSC1_CTRL_RESELECT_SHIFT (0x0u) - -/** @brief CONTROL_PCIE_CFG register fields */ -#define CONTROL_PCIE_CFG_PCIE_TERM_ENABLE (0x80000000u) -#define CONTROL_PCIE_CFG_PCIE_TERM_ENABLE_SHIFT (0x1Fu) - -#define CONTROL_PCIE_CFG_PCIE_TERM_VALUE (0x70000000u) -#define CONTROL_PCIE_CFG_PCIE_TERM_VALUE_SHIFT (0x1Cu) - -#define CONTROL_PCIE_CFG_PCIDEVTYPE (0x00000003u) -#define CONTROL_PCIE_CFG_PCIDEVTYPE_SHIFT (0x0u) - -/** @brief PE_SCRATCHPAD(n) register fields */ -#define CONTROL_PE_SCRATCHPAD_PE_SCRATCHPAD_0 (0xFFFFFFFFu) -#define CONTROL_PE_SCRATCHPAD_PE_SCRATCHPAD_0_SHIFT (0x00000000u) - -/** @brief DEVICE_ID register fields */ -#define CONTROL_DEVICE_ID_DEVREV (0xF0000000u) -#define CONTROL_DEVICE_ID_DEVREV_SHIFT (0x0000001Cu) - -#define CONTROL_DEVICE_ID_MFGR (0x00000FFEu) -#define CONTROL_DEVICE_ID_MFGR_SHIFT (0x00000001u) - -#define CONTROL_DEVICE_ID_PARTNUM (0x0FFFF000u) -#define CONTROL_DEVICE_ID_PARTNUM_SHIFT (0x0000000Cu) - -/** @brief INIT_PRIORITY_0 register fields */ -#define CONTROL_INIT_PRIORITY_0_HOST_ARM (0x00000003u) -#define CONTROL_INIT_PRIORITY_0_HOST_ARM_SHIFT (0x00000000u) - -#define CONTROL_INIT_PRIORITY_0_MMU (0x000000C0u) -#define CONTROL_INIT_PRIORITY_0_MMU_SHIFT (0x00000006u) - -#define CONTROL_INIT_PRIORITY_0_P1500 (0x0000C000u) -#define CONTROL_INIT_PRIORITY_0_P1500_SHIFT (0x0000000Eu) - -#define CONTROL_INIT_PRIORITY_0_PRUSS0 (0x0000000Cu) -#define CONTROL_INIT_PRIORITY_0_PRUSS0_SHIFT (0x00000002u) - -#define CONTROL_INIT_PRIORITY_0_PRUSS1 (0x00000030u) -#define CONTROL_INIT_PRIORITY_0_PRUSS1_SHIFT (0x00000004u) - -#define CONTROL_INIT_PRIORITY_0_TCRD0 (0x00030000u) -#define CONTROL_INIT_PRIORITY_0_TCRD0_SHIFT (0x00000010u) - -#define CONTROL_INIT_PRIORITY_0_TCRD1 (0x00300000u) -#define CONTROL_INIT_PRIORITY_0_TCRD1_SHIFT (0x00000014u) - -#define CONTROL_INIT_PRIORITY_0_TCRD2 (0x03000000u) -#define CONTROL_INIT_PRIORITY_0_TCRD2_SHIFT (0x00000018u) - -#define CONTROL_INIT_PRIORITY_0_TCWR0 (0x000C0000u) -#define CONTROL_INIT_PRIORITY_0_TCWR0_SHIFT (0x00000012u) - -#define CONTROL_INIT_PRIORITY_0_TCWR1 (0x00C00000u) -#define CONTROL_INIT_PRIORITY_0_TCWR1_SHIFT (0x00000016u) - -#define CONTROL_INIT_PRIORITY_0_TCWR2 (0x0C000000u) -#define CONTROL_INIT_PRIORITY_0_TCWR2_SHIFT (0x0000001Au) - -/** @brief INIT_PRIORITY_1 register fields */ -#define CONTROL_INIT_PRIORITY_1_CPSW (0x00000003u) -#define CONTROL_INIT_PRIORITY_1_CPSW_SHIFT (0x00000000u) - -#define CONTROL_INIT_PRIORITY_1_DEBUG (0x03000000u) -#define CONTROL_INIT_PRIORITY_1_DEBUG_SHIFT (0x00000018u) - -#define CONTROL_INIT_PRIORITY_1_LCD (0x00C00000u) -#define CONTROL_INIT_PRIORITY_1_LCD_SHIFT (0x00000016u) - -#define CONTROL_INIT_PRIORITY_1_SGX (0x00300000u) -#define CONTROL_INIT_PRIORITY_1_SGX_SHIFT (0x00000014u) - -#define CONTROL_INIT_PRIORITY_1_USB_DMA (0x00000030u) -#define CONTROL_INIT_PRIORITY_1_USB_DMA_SHIFT (0x00000004u) - -#define CONTROL_INIT_PRIORITY_1_USB_QMGR (0x000000C0u) -#define CONTROL_INIT_PRIORITY_1_USB_QMGR_SHIFT (0x00000006u) - -/** @brief MMU_CFG register fields */ -#define CONTROL_MMU_CFG_MMU_ABORT (0x00008000u) -#define CONTROL_MMU_CFG_MMU_ABORT_SHIFT (0x0000000Fu) - -#define CONTROL_MMU_CFG_MMU_DISABLE (0x00000080u) -#define CONTROL_MMU_CFG_MMU_DISABLE_SHIFT (0x00000007u) - -/** @brief TPTC_CFG register fields */ -#define CONTROL_TPTC_CFG_TC0DBS (0x00000003u) -#define CONTROL_TPTC_CFG_TC0DBS_SHIFT (0x00000000u) - -#define CONTROL_TPTC_CFG_TC1DBS (0x0000000Cu) -#define CONTROL_TPTC_CFG_TC1DBS_SHIFT (0x00000002u) - -#define CONTROL_TPTC_CFG_TC2DBS (0x00000030u) -#define CONTROL_TPTC_CFG_TC2DBS_SHIFT (0x00000004u) - -/** @brief CONTROL_DSP_IDLE_CFG register fields */ -#define CONTROL_DSP_IDLE_CFG_DSPSTBY (0x00008000u) -#define CONTROL_DSP_IDLE_CFG_DSPSTBY_SHIFT (0xFu) - -#define CONTROL_DSP_IDLE_CFG_STBYMODE (0x00000030u) -#define CONTROL_DSP_IDLE_CFG_STBYMODE_SHIFT (0x4u) - -#define CONTROL_DSP_IDLE_CFG_IDLEMODE (0x0000000Cu) -#define CONTROL_DSP_IDLE_CFG_IDLEMODE_SHIFT (0x2u) - -/** @brief USB_CTRL0 register fields */ -#define CONTROL_USB_CTRL0_CDET_EXTCTL (0x00000400u) -#define CONTROL_USB_CTRL0_CDET_EXTCTL_SHIFT (0x0000000Au) - -#define CONTROL_USB_CTRL0_CHGDET_DIS (0x00000004u) -#define CONTROL_USB_CTRL0_CHGDET_DIS_SHIFT (0x00000002u) - -#define CONTROL_USB_CTRL0_CHGDET_RSTRT (0x00000008u) -#define CONTROL_USB_CTRL0_CHGDET_RSTRT_SHIFT (0x00000003u) - -#define CONTROL_USB_CTRL0_CHGISINK_EN (0x00000040u) -#define CONTROL_USB_CTRL0_CHGISINK_EN_SHIFT (0x00000006u) - -#define CONTROL_USB_CTRL0_CHGVSRC_EN (0x00000080u) -#define CONTROL_USB_CTRL0_CHGVSRC_EN_SHIFT (0x00000007u) - -#define CONTROL_USB_CTRL0_CM_PWRDN (0x00000001u) -#define CONTROL_USB_CTRL0_CM_PWRDN_SHIFT (0x00000000u) - -#define CONTROL_USB_CTRL0_DATAPOLARITY_INV (0x00800000u) -#define CONTROL_USB_CTRL0_DATAPOLARITY_INV_SHIFT (0x00000017u) - -#define CONTROL_USB_CTRL0_DMGPIO_PD (0x00040000u) -#define CONTROL_USB_CTRL0_DMGPIO_PD_SHIFT (0x00000012u) - -#define CONTROL_USB_CTRL0_DMPULLUP (0x00000100u) -#define CONTROL_USB_CTRL0_DMPULLUP_SHIFT (0x00000008u) - -#define CONTROL_USB_CTRL0_DPGPIO_PD (0x00020000u) -#define CONTROL_USB_CTRL0_DPGPIO_PD_SHIFT (0x00000011u) - -#define CONTROL_USB_CTRL0_DPPULLUP (0x00000200u) -#define CONTROL_USB_CTRL0_DPPULLUP_SHIFT (0x00000009u) - -#define CONTROL_USB_CTRL0_GPIOMODE (0x00001000u) -#define CONTROL_USB_CTRL0_GPIOMODE_SHIFT (0x0000000Cu) - -#define CONTROL_USB_CTRL0_GPIO_SIG_CROSS (0x00004000u) -#define CONTROL_USB_CTRL0_GPIO_SIG_CROSS_SHIFT (0x0000000Eu) - -#define CONTROL_USB_CTRL0_GPIO_SIG_INV (0x00002000u) -#define CONTROL_USB_CTRL0_GPIO_SIG_INV_SHIFT (0x0000000Du) - -#define CONTROL_USB_CTRL0_OTGSESSENDEN (0x00100000u) -#define CONTROL_USB_CTRL0_OTGSESSENDEN_SHIFT (0x00000014u) - -#define CONTROL_USB_CTRL0_OTGVDET_EN (0x00080000u) -#define CONTROL_USB_CTRL0_OTGVDET_EN_SHIFT (0x00000013u) - -#define CONTROL_USB_CTRL0_OTG_PWRDN (0x00000002u) -#define CONTROL_USB_CTRL0_OTG_PWRDN_SHIFT (0x00000001u) - -#define CONTROL_USB_CTRL0_SINKONDP (0x00000020u) -#define CONTROL_USB_CTRL0_SINKONDP_SHIFT (0x00000005u) - -#define CONTROL_USB_CTRL0_SPAREIN (0xFF000000u) -#define CONTROL_USB_CTRL0_SPAREIN_SHIFT (0x00000018u) - -#define CONTROL_USB_CTRL0_SRCONDM (0x00000010u) -#define CONTROL_USB_CTRL0_SRCONDM_SHIFT (0x00000004u) - -#define CONTROL_USB_CTRL0_USB_PHY_SMA1 (0x00200000u) -#define CONTROL_USB_CTRL0_USB_PHY_SMA1_SHIFT (0x00000015u) - -#define CONTROL_USB_CTRL0_USB_PHY_SMA2 (0x00400000u) -#define CONTROL_USB_CTRL0_USB_PHY_SMA2_SHIFT (0x00000016u) - -/** @brief USB_STS0 register fields */ -#define CONTROL_USB_STS0_CDET_DATADET (0x00000004u) -#define CONTROL_USB_STS0_CDET_DATADET_SHIFT (0x00000002u) - -#define CONTROL_USB_STS0_CDET_DMDET (0x00000010u) -#define CONTROL_USB_STS0_CDET_DMDET_SHIFT (0x00000004u) - -#define CONTROL_USB_STS0_CDET_DPDET (0x00000008u) -#define CONTROL_USB_STS0_CDET_DPDET_SHIFT (0x00000003u) - -#define CONTROL_USB_STS0_CHGDETDONE (0x00000001u) -#define CONTROL_USB_STS0_CHGDETDONE_SHIFT (0x00000000u) - -#define CONTROL_USB_STS0_CHGDETECT (0x00000002u) -#define CONTROL_USB_STS0_CHGDETECT_SHIFT (0x00000001u) - -#define CONTROL_USB_STS0_CHGDETSTS (0x000000E0u) -#define CONTROL_USB_STS0_CHGDETSTS_SHIFT (0x00000005u) - -/** @brief USB_CTRL1 register fields */ -#define CONTROL_USB_CTRL1_CDET_EXTCTL (0x00000400u) -#define CONTROL_USB_CTRL1_CDET_EXTCTL_SHIFT (0x0000000Au) - -#define CONTROL_USB_CTRL1_CHGDET_DIS (0x00000004u) -#define CONTROL_USB_CTRL1_CHGDET_DIS_SHIFT (0x00000002u) - -#define CONTROL_USB_CTRL1_CHGDET_RSTRT (0x00000008u) -#define CONTROL_USB_CTRL1_CHGDET_RSTRT_SHIFT (0x00000003u) - -#define CONTROL_USB_CTRL1_CHGISINK_EN (0x00000040u) -#define CONTROL_USB_CTRL1_CHGISINK_EN_SHIFT (0x00000006u) - -#define CONTROL_USB_CTRL1_CHGVSRC_EN (0x00000080u) -#define CONTROL_USB_CTRL1_CHGVSRC_EN_SHIFT (0x00000007u) - -#define CONTROL_USB_CTRL1_CM_PWRDN (0x00000001u) -#define CONTROL_USB_CTRL1_CM_PWRDN_SHIFT (0x00000000u) - -#define CONTROL_USB_CTRL1_DATAPOLARITY_INV (0x00800000u) -#define CONTROL_USB_CTRL1_DATAPOLARITY_INV_SHIFT (0x00000017u) - -#define CONTROL_USB_CTRL1_DMGPIO_PD (0x00040000u) -#define CONTROL_USB_CTRL1_DMGPIO_PD_SHIFT (0x00000012u) - -#define CONTROL_USB_CTRL1_DMPULLUP (0x00000100u) -#define CONTROL_USB_CTRL1_DMPULLUP_SHIFT (0x00000008u) - -#define CONTROL_USB_CTRL1_DPGPIO_PD (0x00020000u) -#define CONTROL_USB_CTRL1_DPGPIO_PD_SHIFT (0x00000011u) - -#define CONTROL_USB_CTRL1_DPPULLUP (0x00000200u) -#define CONTROL_USB_CTRL1_DPPULLUP_SHIFT (0x00000009u) - -#define CONTROL_USB_CTRL1_GPIOMODE (0x00001000u) -#define CONTROL_USB_CTRL1_GPIOMODE_SHIFT (0x0000000Cu) - -#define CONTROL_USB_CTRL1_GPIO_SIG_CROSS (0x00004000u) -#define CONTROL_USB_CTRL1_GPIO_SIG_CROSS_SHIFT (0x0000000Eu) - -#define CONTROL_USB_CTRL1_GPIO_SIG_INV (0x00002000u) -#define CONTROL_USB_CTRL1_GPIO_SIG_INV_SHIFT (0x0000000Du) - -#define CONTROL_USB_CTRL1_OTGSESSENDEN (0x00100000u) -#define CONTROL_USB_CTRL1_OTGSESSENDEN_SHIFT (0x00000014u) - -#define CONTROL_USB_CTRL1_OTGVDET_EN (0x00080000u) -#define CONTROL_USB_CTRL1_OTGVDET_EN_SHIFT (0x00000013u) - -#define CONTROL_USB_CTRL1_OTG_PWRDN (0x00000002u) -#define CONTROL_USB_CTRL1_OTG_PWRDN_SHIFT (0x00000001u) - -#define CONTROL_USB_CTRL1_SINKONDP (0x00000020u) -#define CONTROL_USB_CTRL1_SINKONDP_SHIFT (0x00000005u) - -#define CONTROL_USB_CTRL1_SPAREIN (0xFF000000u) -#define CONTROL_USB_CTRL1_SPAREIN_SHIFT (0x00000018u) - -#define CONTROL_USB_CTRL1_SRCONDM (0x00000010u) -#define CONTROL_USB_CTRL1_SRCONDM_SHIFT (0x00000004u) - -#define CONTROL_USB_CTRL1_USB_PHY_SMA1 (0x00200000u) -#define CONTROL_USB_CTRL1_USB_PHY_SMA1_SHIFT (0x00000015u) - -#define CONTROL_USB_CTRL1_USB_PHY_SMA2 (0x00400000u) -#define CONTROL_USB_CTRL1_USB_PHY_SMA2_SHIFT (0x00000016u) - -/** @brief USB_STS1 register fields */ -#define CONTROL_USB_STS1_CDET_DATADET (0x00000004u) -#define CONTROL_USB_STS1_CDET_DATADET_SHIFT (0x00000002u) - -#define CONTROL_USB_STS1_CDET_DMDET (0x00000010u) -#define CONTROL_USB_STS1_CDET_DMDET_SHIFT (0x00000004u) - -#define CONTROL_USB_STS1_CDET_DPDET (0x00000008u) -#define CONTROL_USB_STS1_CDET_DPDET_SHIFT (0x00000003u) - -#define CONTROL_USB_STS1_CHGDETDONE (0x00000001u) -#define CONTROL_USB_STS1_CHGDETDONE_SHIFT (0x00000000u) - -#define CONTROL_USB_STS1_CHGDETECT (0x00000002u) -#define CONTROL_USB_STS1_CHGDETECT_SHIFT (0x00000001u) - -#define CONTROL_USB_STS1_CHGDETSTS (0x000000E0u) -#define CONTROL_USB_STS1_CHGDETSTS_SHIFT (0x00000005u) - -/** @brief MAC_ID0_LO register fields */ -#define CONTROL_MAC_ID0_LO_MACADDR_15_8 (0x000000FFu) -#define CONTROL_MAC_ID0_LO_MACADDR_15_8_SHIFT (0x00000000u) - -#define CONTROL_MAC_ID0_LO_MACADDR_7_0 (0x0000FF00u) -#define CONTROL_MAC_ID0_LO_MACADDR_7_0_SHIFT (0x00000008u) - -/** @brief MAC_ID0_HI register fields */ -#define CONTROL_MAC_ID0_HI_MACADDR_23_16 (0xFF000000u) -#define CONTROL_MAC_ID0_HI_MACADDR_23_16_SHIFT (0x00000018u) - -#define CONTROL_MAC_ID0_HI_MACADDR_31_24 (0x00FF0000u) -#define CONTROL_MAC_ID0_HI_MACADDR_31_24_SHIFT (0x00000010u) - -#define CONTROL_MAC_ID0_HI_MACADDR_39_32 (0x0000FF00u) -#define CONTROL_MAC_ID0_HI_MACADDR_39_32_SHIFT (0x00000008u) - -#define CONTROL_MAC_ID0_HI_MACADDR_47_40 (0x000000FFu) -#define CONTROL_MAC_ID0_HI_MACADDR_47_40_SHIFT (0x00000000u) - -/** @brief MAC_ID1_LO register fields */ -#define CONTROL_MAC_ID1_LO_MACADDR_15_8 (0x000000FFu) -#define CONTROL_MAC_ID1_LO_MACADDR_15_8_SHIFT (0x00000000u) - -#define CONTROL_MAC_ID1_LO_MACADDR_7_0 (0x0000FF00u) -#define CONTROL_MAC_ID1_LO_MACADDR_7_0_SHIFT (0x00000008u) - -/** @brief MAC_ID1_HI register fields */ -#define CONTROL_MAC_ID1_HI_MACADDR_23_16 (0xFF000000u) -#define CONTROL_MAC_ID1_HI_MACADDR_23_16_SHIFT (0x00000018u) - -#define CONTROL_MAC_ID1_HI_MACADDR_31_24 (0x00FF0000u) -#define CONTROL_MAC_ID1_HI_MACADDR_31_24_SHIFT (0x00000010u) - -#define CONTROL_MAC_ID1_HI_MACADDR_39_32 (0x0000FF00u) -#define CONTROL_MAC_ID1_HI_MACADDR_39_32_SHIFT (0x00000008u) - -#define CONTROL_MAC_ID1_HI_MACADDR_47_40 (0x000000FFu) -#define CONTROL_MAC_ID1_HI_MACADDR_47_40_SHIFT (0x00000000u) - -/** @brief CONTROL_SW_REVISION register fields */ -#define CONTROL_SW_REVISION_REV (0xFFFFFFFFu) -#define CONTROL_SW_REVISION_REV_SHIFT (0x0u) - -/** @brief DCAN_RAMINIT register fields */ -#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_DONE (0x00000100u) -#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_DONE_SHIFT (0x00000008u) - -#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_START (0x00000001u) -#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_START_SHIFT (0x00000000u) - -#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_DONE (0x00000200u) -#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_DONE_SHIFT (0x00000009u) - -#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_START (0x00000002u) -#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_START_SHIFT (0x00000001u) - -/** @brief CONTROL_AUD_CTRL register fields */ -#define CONTROL_AUD_CTRL_MCB_LBFSX (0x00000002u) -#define CONTROL_AUD_CTRL_MCB_LBFSX_SHIFT (0x1u) - -#define CONTROL_AUD_CTRL_MCB_LBCLKX (0x00000001u) -#define CONTROL_AUD_CTRL_MCB_LBCLKX_SHIFT (0x0u) - -/** @brief GMII_SEL register fields */ -#define CONTROL_GMII_SEL_GMII1_SEL (0x00000003u) -#define CONTROL_GMII_SEL_GMII1_SEL_SHIFT (0x00000000u) - -#define CONTROL_GMII_SEL_GMII2_SEL (0x0000000Cu) -#define CONTROL_GMII_SEL_GMII2_SEL_SHIFT (0x00000002u) - -#define CONTROL_GMII_SEL_RGMII1_IDMODE (0x00000010u) -#define CONTROL_GMII_SEL_RGMII1_IDMODE_SHIFT (0x00000004u) - -#define CONTROL_GMII_SEL_RGMII2_IDMOE (0x00000020u) -#define CONTROL_GMII_SEL_RGMII2_IDMOE_SHIFT (0x00000005u) - -#define CONTROL_GMII_SEL_RMII1_IO_CLK_EN (0x00000040u) -#define CONTROL_GMII_SEL_RMII1_IO_CLK_EN_SHIFT (0x00000006u) - -#define CONTROL_GMII_SEL_RMII2_IO_CLK_EN (0x00000080u) -#define CONTROL_GMII_SEL_RMII2_IO_CLK_EN_SHIFT (0x00000007u) - -/** @brief CONTROL_OCMEM_PWRDN register fields */ -#define CONTROL_OCMEM_PWRDN_MEM_PWRDN_STATUS (0x00000002u) -#define CONTROL_OCMEM_PWRDN_MEM_PWRDN_STATUS_SHIFT (0x1u) - -#define CONTROL_OCMEM_PWRDN_MEM_PWRDN (0x00000001u) -#define CONTROL_OCMEM_PWRDN_MEM_PWRDN_SHIFT (0x0u) - -/** @brief CONTROL_DUCATIMEM_PWRDN register fields */ -#define CONTROL_DUCATIMEM_PWRDN_MEM_PWRDN_STATUS (0x00000002u) -#define CONTROL_DUCATIMEM_PWRDN_MEM_PWRDN_STATUS_SHIFT (0x1u) - -#define CONTROL_DUCATIMEM_PWRDN_MEM_PWRDN (0x00000001u) -#define CONTROL_DUCATIMEM_PWRDN_MEM_PWRDN_SHIFT (0x0u) - -/** @brief PWMSS_CTRL register fields */ -#define CONTROL_PWMSS_CTRL_PWMMS1_TBCLKEN (0x00000002u) -#define CONTROL_PWMSS_CTRL_PWMMS1_TBCLKEN_SHIFT (0x00000001u) - -#define CONTROL_PWMSS_CTRL_PWMSS0_TBCLKEN (0x00000001u) -#define CONTROL_PWMSS_CTRL_PWMSS0_TBCLKEN_SHIFT (0x00000000u) - -#define CONTROL_PWMSS_CTRL_PWMSS2_TBCLKEN (0x00000004u) -#define CONTROL_PWMSS_CTRL_PWMSS2_TBCLKEN_SHIFT (0x00000002u) - -/** @brief CONTROL_SD_DAC_CTRL register fields */ -#define CONTROL_SD_DAC_CTRL_DAC1_cm4 (0x02000000u) -#define CONTROL_SD_DAC_CTRL_DAC1_cm4_SHIFT (0x19u) - -#define CONTROL_SD_DAC_CTRL_DAC1_cm (0x01000000u) -#define CONTROL_SD_DAC_CTRL_DAC1_cm_SHIFT (0x18u) - -#define CONTROL_SD_DAC_CTRL_DAC1_cm2 (0x00800000u) -#define CONTROL_SD_DAC_CTRL_DAC1_cm2_SHIFT (0x17u) - -#define CONTROL_SD_DAC_CTRL_DAC1_cm1 (0x00400000u) -#define CONTROL_SD_DAC_CTRL_DAC1_cm1_SHIFT (0x16u) - -#define CONTROL_SD_DAC_CTRL_DAC1_cm0 (0x00200000u) -#define CONTROL_SD_DAC_CTRL_DAC1_cm0_SHIFT (0x15u) - -#define CONTROL_SD_DAC_CTRL_DAC0_cm4 (0x00100000u) -#define CONTROL_SD_DAC_CTRL_DAC0_cm4_SHIFT (0x14u) - -#define CONTROL_SD_DAC_CTRL_DAC0_cm (0x00080000u) -#define CONTROL_SD_DAC_CTRL_DAC0_cm_SHIFT (0x13u) - -#define CONTROL_SD_DAC_CTRL_DAC0_cm2 (0x00040000u) -#define CONTROL_SD_DAC_CTRL_DAC0_cm2_SHIFT (0x12u) - -#define CONTROL_SD_DAC_CTRL_DAC0_cm1 (0x00020000u) -#define CONTROL_SD_DAC_CTRL_DAC0_cm1_SHIFT (0x11u) - -#define CONTROL_SD_DAC_CTRL_DAC0_cm0 (0x00010000u) -#define CONTROL_SD_DAC_CTRL_DAC0_cm0_SHIFT (0x10u) - -#define CONTROL_SD_DAC_CTRL_TVOUTBYPASS (0x00000100u) -#define CONTROL_SD_DAC_CTRL_TVOUTBYPASS_SHIFT (0x8u) - -#define CONTROL_SD_DAC_CTRL_ACEN (0x00000080u) -#define CONTROL_SD_DAC_CTRL_ACEN_SHIFT (0x7u) - -#define CONTROL_SD_DAC_CTRL_INPUTINV (0x00000040u) -#define CONTROL_SD_DAC_CTRL_INPUTINV_SHIFT (0x6u) - -#define CONTROL_SD_DAC_CTRL_DEMEN (0x00000020u) -#define CONTROL_SD_DAC_CTRL_DEMEN_SHIFT (0x5u) - -#define CONTROL_SD_DAC_CTRL_PBNDACz (0x00000010u) -#define CONTROL_SD_DAC_CTRL_PBNDACz_SHIFT (0x4u) - -#define CONTROL_SD_DAC_CTRL_PBNBGz (0x00000008u) -#define CONTROL_SD_DAC_CTRL_PBNBGz_SHIFT (0x3u) - -#define CONTROL_SD_DAC_CTRL_OFFMODE (0x00000004u) -#define CONTROL_SD_DAC_CTRL_OFFMODE_SHIFT (0x2u) - -#define CONTROL_SD_DAC_CTRL_SD_CALSEL (0x00000002u) -#define CONTROL_SD_DAC_CTRL_SD_CALSEL_SHIFT (0x1u) - -#define CONTROL_SD_DAC_CTRL_RESETz (0x00000001u) -#define CONTROL_SD_DAC_CTRL_RESETz_SHIFT (0x0u) - -/** @brief CONTROL_SD_DAC_CAL register fields */ -#define CONTROL_SD_DAC_CAL_SDDAC_CAL (0x000003FFu) -#define CONTROL_SD_DAC_CAL_SDDAC_CAL_SHIFT (0x0u) - -/** @brief CONTROL_SD_DAC_REGCTRL register fields */ -#define CONTROL_SD_DAC_REGCTRL_SDDAC_CTL (0x0000FFFFu) -#define CONTROL_SD_DAC_REGCTRL_SDDAC_CTL_SHIFT (0x0u) - -/** @brief CONTROL_SD_DAC_REGSTATUS register fields */ -#define CONTROL_SD_DAC_REGSTATUS_STATUS (0x00000001u) -#define CONTROL_SD_DAC_REGSTATUS_STATUS_SHIFT (0x0u) - -/** @brief CONTROL_EMIF_CLK_GATE register fields */ -#define CONTROL_EMIF_CLK_GATE_DDR0_CKE_STATUS (0x00000004u) -#define CONTROL_EMIF_CLK_GATE_DDR0_CKE_STATUS_SHIFT (0x2u) - -#define CONTROL_EMIF_CLK_GATE_DDRPHY0_CLK_GATE (0x00000001u) -#define CONTROL_EMIF_CLK_GATE_DDRPHY0_CLK_GATE_SHIFT (0x0u) - -/** @brief SMRT_CTRL register fields */ -#define CONTROL_SMRT_CTRL_SR0_SLEEP (0x00000001u) -#define CONTROL_SMRT_CTRL_SR0_SLEEP_SHIFT (0x00000000u) - -#define CONTROL_SMRT_CTRL_SR1_SLEEP (0x00000002u) -#define CONTROL_SMRT_CTRL_SR1_SLEEP_SHIFT (0x00000001u) - -/** @brief MODENA_HW_DEBUG_SEL register fields */ -#define CONTROL_MODENA_HW_DEBUG_SEL_HW_DBG_GATE_EN (0x00000200u) -#define CONTROL_MODENA_HW_DEBUG_SEL_HW_DBG_GATE_EN_SHIFT (0x00000009u) - -#define CONTROL_MODENA_HW_DEBUG_SEL_HW_DBG_SEL (0x0000000Fu) -#define CONTROL_MODENA_HW_DEBUG_SEL_HW_DBG_SEL_SHIFT (0x00000000u) - -/** @brief MODENA_HW_DBG_INFO register fields */ -#define CONTROL_MODENA_HW_DBG_INFO_HW_DBG_INFO (0xFFFFFFFFu) -#define CONTROL_MODENA_HW_DBG_INFO_HW_DBG_INFO_SHIFT (0x00000000u) - -/** @brief CONTROL_PRCM_DEBUG_ALWON_DEFAULT register fields */ -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_USB_CLK_OFF (0x20000000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_USB_CLK_OFF_SHIFT (0x1Du) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_PCI_CLK_OFF (0x08000000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_PCI_CLK_OFF_SHIFT (0x1Bu) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_DMM_EMIF_CLK_OFF (0x02000000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_DMM_EMIF_CLK_OFF_SHIFT (0x19u) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_DUCATI_CLK_OFF (0x01000000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_DUCATI_CLK_OFF_SHIFT (0x18u) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_RTC_CLK_OFF (0x00400000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_RTC_CLK_OFF_SHIFT (0x16u) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_VCP_CLK_OFF (0x00200000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_VCP_CLK_OFF_SHIFT (0x15u) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_OCMC_RAM_CLK_OFF (0x00100000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_OCMC_RAM_CLK_OFF_SHIFT (0x14u) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_MPU_CLK_OFF (0x00080000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_MPU_CLK_OFF_SHIFT (0x13u) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_MMU_CFG_CLK_OFF (0x00040000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_MMU_CFG_CLK_OFF_SHIFT (0x12u) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_MMU_CLK_OFF (0x00020000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_MMU_CLK_OFF_SHIFT (0x11u) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_ETHERNET_CLK_OFF (0x00010000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_ETHERNET_CLK_OFF_SHIFT (0x10u) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_L3_SLOW_CLK_OFF (0x00004000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_L3_SLOW_CLK_OFF_SHIFT (0xEu) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_L3_MED_CLK_OFF (0x00002000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_L3_MED_CLK_OFF_SHIFT (0xDu) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_L3_FAST_CLK_OFF (0x00001000u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_L3_FAST_CLK_OFF_SHIFT (0xCu) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_SYSCLK6_CLK_OFF (0x00000400u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_SYSCLK6_CLK_OFF_SHIFT (0xAu) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_SYSCLK5_CLK_OFF (0x00000200u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_SYSCLK5_CLK_OFF_SHIFT (0x9u) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_SYSCLK4_CLK_OFF (0x00000100u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_SYSCLK4_CLK_OFF_SHIFT (0x8u) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_DEF_PWR_ON (0x00000010u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_DEF_PWR_ON_SHIFT (0x4u) - -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_HW_DBG_READ_EN (0x00000008u) -#define CONTROL_PRCM_DEBUG_ALWON_DEFAULT_HW_DBG_READ_EN_SHIFT (0x3u) - -/** @brief CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS register fields */ -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_SGX_PD_DSS_CLK_STATUS_GLUE (0x80000000u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_SGX_PD_DSS_CLK_STATUS_GLUE_SHIFT (0x1Fu) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_SGX_PD_CLK_STATUS_PRCM (0x40000000u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_SGX_PD_CLK_STATUS_PRCM_SHIFT (0x1Eu) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_SGX_PD_MEM_ON_GLUE (0x20000000u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_SGX_PD_MEM_ON_GLUE_SHIFT (0x1Du) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_SGX_PD_SWITCH_ON_GLUE (0x10000000u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_SGX_PD_SWITCH_ON_GLUE_SHIFT (0x1Cu) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_SGX_PD_ON_PRCM (0x08000000u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_SGX_PD_ON_PRCM_SHIFT (0x1Bu) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_DSS_PD_DSS_CLK_STATUS_GLUE (0x02000000u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_DSS_PD_DSS_CLK_STATUS_GLUE_SHIFT (0x19u) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_DSS_PD_CLK_STATUS_PRCM (0x01000000u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_DSS_PD_CLK_STATUS_PRCM_SHIFT (0x18u) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_DSS_PD_MEM_ON_GLUE (0x00800000u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_DSS_PD_MEM_ON_GLUE_SHIFT (0x17u) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_DSS_PD_SWITCH_ON_GLUE (0x00400000u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_DSS_PD_SWITCH_ON_GLUE_SHIFT (0x16u) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_DSS_PD_ON_PRCM (0x00200000u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_DSS_PD_ON_PRCM_SHIFT (0x15u) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_ACTIVE_PD_GEM_CLK_STATUS_GLUE (0x00000100u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_ACTIVE_PD_GEM_CLK_STATUS_GLUE_SHIFT (0x8u) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_ACTIVE_PD_GEM_CLK_STATUS_PRCM (0x00000080u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_ACTIVE_PD_GEM_CLK_STATUS_PRCM_SHIFT (0x7u) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_ACTIVE_PD_MEM_ON_GLUE (0x00000040u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_ACTIVE_PD_MEM_ON_GLUE_SHIFT (0x6u) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_ACTIVE_PD_SWITCH_ON_GLUE (0x00000020u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_ACTIVE_PD_SWITCH_ON_GLUE_SHIFT (0x5u) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_ACTIVE_PD_ON_PRCM (0x00000010u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_ACTIVE_PD_ON_PRCM_SHIFT (0x4u) - -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_HW_DBG_READ_EN (0x00000008u) -#define CONTROL_PRCM_DEBUG_PD_DOMAIN_STATUS_HW_DBG_READ_EN_SHIFT (0x3u) - -/** @brief CONTROL_PCIE_PLLCFG(n) register fields */ -#define CONTROL_PCIE_PLLCFG0_SEL_IN_FREQ (0x80000000u) -#define CONTROL_PCIE_PLLCFG0_SEL_IN_FREQ_SHIFT (0x1Fu) - -#define CONTROL_PCIE_PLLCFG0_DIGCLRZ (0x40000000u) -#define CONTROL_PCIE_PLLCFG0_DIGCLRZ_SHIFT (0x1Eu) - -#define CONTROL_PCIE_PLLCFG0_AMUXSEL (0x08000000u) -#define CONTROL_PCIE_PLLCFG0_AMUXSEL_SHIFT (0x1Bu) - -#define CONTROL_PCIE_PLLCFG0_TESTCLKMUXSEL (0x04000000u) -#define CONTROL_PCIE_PLLCFG0_TESTCLKMUXSEL_SHIFT (0x1Au) - -#define CONTROL_PCIE_PLLCFG0_APLL_MISC_CTRL (0x03F00000u) -#define CONTROL_PCIE_PLLCFG0_APLL_MISC_CTRL_SHIFT (0x14u) - -#define CONTROL_PCIE_PLLCFG0_DIS_REFCLK (0x00080000u) -#define CONTROL_PCIE_PLLCFG0_DIS_REFCLK_SHIFT (0x13u) - -#define CONTROL_PCIE_PLLCFG0_EN_3P (0x00040000u) -#define CONTROL_PCIE_PLLCFG0_EN_3P_SHIFT (0x12u) - -#define CONTROL_PCIE_PLLCFG0_PFD_CLR (0x00020000u) -#define CONTROL_PCIE_PLLCFG0_PFD_CLR_SHIFT (0x11u) - -#define CONTROL_PCIE_PLLCFG0_CLK_FLIP (0x00010000u) -#define CONTROL_PCIE_PLLCFG0_CLK_FLIP_SHIFT (0x10u) - -#define CONTROL_PCIE_PLLCFG0_EN_RTRIM (0x00008000u) -#define CONTROL_PCIE_PLLCFG0_EN_RTRIM_SHIFT (0xFu) - -#define CONTROL_PCIE_PLLCFG0_EN_MEAS (0x00004000u) -#define CONTROL_PCIE_PLLCFG0_EN_MEAS_SHIFT (0xEu) - -#define CONTROL_PCIE_PLLCFG0_EN_LATCH (0x00003000u) -#define CONTROL_PCIE_PLLCFG0_EN_LATCH_SHIFT (0xCu) - -#define CONTROL_PCIE_PLLCFG0_CP_CTRL (0x00000F00u) -#define CONTROL_PCIE_PLLCFG0_CP_CTRL_SHIFT (0x8u) - -#define CONTROL_PCIE_PLLCFG0_RESVALUE (0x000000C0u) -#define CONTROL_PCIE_PLLCFG0_RESVALUE_SHIFT (0x6u) - -#define CONTROL_PCIE_PLLCFG0_C1_2X (0x00000020u) -#define CONTROL_PCIE_PLLCFG0_C1_2X_SHIFT (0x5u) - -#define CONTROL_PCIE_PLLCFG0_ENDIGLDO (0x00000010u) -#define CONTROL_PCIE_PLLCFG0_ENDIGLDO_SHIFT (0x4u) - -#define CONTROL_PCIE_PLLCFG0_APLL_CP_CURR (0x00000008u) -#define CONTROL_PCIE_PLLCFG0_APLL_CP_CURR_SHIFT (0x3u) - -#define CONTROL_PCIE_PLLCFG0_ENBGSC_REF (0x00000004u) -#define CONTROL_PCIE_PLLCFG0_ENBGSC_REF_SHIFT (0x2u) - -#define CONTROL_PCIE_PLLCFG0_ENPLLLDO (0x00000002u) -#define CONTROL_PCIE_PLLCFG0_ENPLLLDO_SHIFT (0x1u) - -#define CONTROL_PCIE_PLLCFG0_ENPLL (0x00000001u) -#define CONTROL_PCIE_PLLCFG0_ENPLL_SHIFT (0x0u) - -#define CONTROL_PCIE_PLLCFG1_ENSATAMODE (0x80000000u) -#define CONTROL_PCIE_PLLCFG1_ENSATAMODE_SHIFT (0x1Fu) - -#define CONTROL_PCIE_PLLCFG1_PLLREFSEL (0x40000000u) -#define CONTROL_PCIE_PLLCFG1_PLLREFSEL_SHIFT (0x1Eu) - -#define CONTROL_PCIE_PLLCFG1_NP1_DIV_INT (0x3C000000u) -#define CONTROL_PCIE_PLLCFG1_NP1_DIV_INT_SHIFT (0x1Au) - -#define CONTROL_PCIE_PLLCFG1_MDIVINT (0x03FC0000u) -#define CONTROL_PCIE_PLLCFG1_MDIVINT_SHIFT (0x12u) - -#define CONTROL_PCIE_PLLCFG1_MDIVFRAC (0x0003FFC0u) -#define CONTROL_PCIE_PLLCFG1_MDIVFRAC_SHIFT (0x6u) - -#define CONTROL_PCIE_PLLCFG1_EN_CLKAUX (0x00000020u) -#define CONTROL_PCIE_PLLCFG1_EN_CLKAUX_SHIFT (0x5u) - -#define CONTROL_PCIE_PLLCFG1_EN_CLK125M (0x00000010u) -#define CONTROL_PCIE_PLLCFG1_EN_CLK125M_SHIFT (0x4u) - -#define CONTROL_PCIE_PLLCFG1_EN_CLK100M (0x00000008u) -#define CONTROL_PCIE_PLLCFG1_EN_CLK100M_SHIFT (0x3u) - -#define CONTROL_PCIE_PLLCFG1_EN_CLK50M (0x00000004u) -#define CONTROL_PCIE_PLLCFG1_EN_CLK50M_SHIFT (0x2u) - -#define CONTROL_PCIE_PLLCFG1_ENSSC (0x00000002u) -#define CONTROL_PCIE_PLLCFG1_ENSSC_SHIFT (0x1u) - -#define CONTROL_PCIE_PLLCFG1_MDIVPULSE (0x00000001u) -#define CONTROL_PCIE_PLLCFG1_MDIVPULSE_SHIFT (0x0u) - -#define CONTROL_PCIE_PLLCFG2_SSCDNSPREAD (0x80000000u) -#define CONTROL_PCIE_PLLCFG2_SSCDNSPREAD_SHIFT (0x1Fu) - -#define CONTROL_PCIE_PLLCFG2_SSCMANT (0x7F000000u) -#define CONTROL_PCIE_PLLCFG2_SSCMANT_SHIFT (0x18u) - -#define CONTROL_PCIE_PLLCFG2_SSCEXPO (0x00E00000u) -#define CONTROL_PCIE_PLLCFG2_SSCEXPO_SHIFT (0x15u) - -#define CONTROL_PCIE_PLLCFG2_SSCFRSPREAD (0x001FFFFFu) -#define CONTROL_PCIE_PLLCFG2_SSCFRSPREAD_SHIFT (0x0u) - -#define CONTROL_PCIE_PLLCFG3_DIGLDO_PULLDOWNZ (0x04000000u) -#define CONTROL_PCIE_PLLCFG3_DIGLDO_PULLDOWNZ_SHIFT (0x1Au) - -#define CONTROL_PCIE_PLLCFG3_DIGLDO_DIS_SC_PROT (0x02000000u) -#define CONTROL_PCIE_PLLCFG3_DIGLDO_DIS_SC_PROT_SHIFT (0x19u) - -#define CONTROL_PCIE_PLLCFG3_DIGLDO_EN_SUB_REGULATION (0x01000000u) -#define CONTROL_PCIE_PLLCFG3_DIGLDO_EN_SUB_REGULATION_SHIFT (0x18u) - -#define CONTROL_PCIE_PLLCFG3_DIGLDO_EN_HP_CAPLESSMODE (0x00800000u) -#define CONTROL_PCIE_PLLCFG3_DIGLDO_EN_HP_CAPLESSMODE_SHIFT (0x17u) - -#define CONTROL_PCIE_PLLCFG3_DIGLDO_EN_CAPLESSMODE (0x00400000u) -#define CONTROL_PCIE_PLLCFG3_DIGLDO_EN_CAPLESSMODE_SHIFT (0x16u) - -#define CONTROL_PCIE_PLLCFG3_DIGLDO_EN_LP_CAPLESSMODE (0x00200000u) -#define CONTROL_PCIE_PLLCFG3_DIGLDO_EN_LP_CAPLESSMODE_SHIFT (0x15u) - -#define CONTROL_PCIE_PLLCFG3_DIGLDO_VSET (0x001F0000u) -#define CONTROL_PCIE_PLLCFG3_DIGLDO_VSET_SHIFT (0x10u) - -#define CONTROL_PCIE_PLLCFG3_PLLLDO_CTRL_15_14_13 (0x0000E000u) -#define CONTROL_PCIE_PLLCFG3_PLLLDO_CTRL_15_14_13_SHIFT (0xDu) - -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_RETENTION (0x00001000u) -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_RETENTION_SHIFT (0xCu) - -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_LDO_STABLE (0x00000800u) -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_LDO_STABLE_SHIFT (0xBu) - -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_BYPASS (0x00000400u) -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_BYPASS_SHIFT (0xAu) - -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_SC_PROT (0x00000200u) -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_SC_PROT_SHIFT (0x9u) - -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_EXT_CAP (0x00000100u) -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_EXT_CAP_SHIFT (0x8u) - -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_BUF_CUR (0x00000080u) -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_BUF_CUR_SHIFT (0x7u) - -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_LP (0x00000040u) -#define CONTROL_PCIE_PLLCFG3_PLLLDO_EN_LP_SHIFT (0x6u) - -#define CONTROL_PCIE_PLLCFG3_PLLLDO_CTRL_TRIM (0x0000003Eu) -#define CONTROL_PCIE_PLLCFG3_PLLLDO_CTRL_TRIM_SHIFT (0x1u) - -#define CONTROL_PCIE_PLLCFG3_PLLLDO_CTRL (0x00000001u) -#define CONTROL_PCIE_PLLCFG3_PLLLDO_CTRL_SHIFT (0x0u) - -#define CONTROL_PCIE_PLLCFG4_AUX_CLK_SEL (0x01000000u) -#define CONTROL_PCIE_PLLCFG4_AUX_CLK_SEL_SHIFT (0x18u) - -#define CONTROL_PCIE_PLLCFG4_AUX_DIV (0x00F00000u) -#define CONTROL_PCIE_PLLCFG4_AUX_DIV_SHIFT (0x14u) - -#define CONTROL_PCIE_PLLCFG4_RTRIM_RANGE (0x000C0000u) -#define CONTROL_PCIE_PLLCFG4_RTRIM_RANGE_SHIFT (0x12u) - -#define CONTROL_PCIE_PLLCFG4_RTRIM_EXT_EN (0x00020000u) -#define CONTROL_PCIE_PLLCFG4_RTRIM_EXT_EN_SHIFT (0x11u) - -#define CONTROL_PCIE_PLLCFG4_RTRIM_SPEED (0x00010000u) -#define CONTROL_PCIE_PLLCFG4_RTRIM_SPEED_SHIFT (0x10u) - -#define CONTROL_PCIE_PLLCFG4_RTRIM_MODE (0x0000C000u) -#define CONTROL_PCIE_PLLCFG4_RTRIM_MODE_SHIFT (0xEu) - -#define CONTROL_PCIE_PLLCFG4_RTRIM_EXT_VAL (0x00003C00u) -#define CONTROL_PCIE_PLLCFG4_RTRIM_EXT_VAL_SHIFT (0xAu) - -#define CONTROL_PCIE_PLLCFG4_VTUNE_RANGE (0x00000300u) -#define CONTROL_PCIE_PLLCFG4_VTUNE_RANGE_SHIFT (0x8u) - -#define CONTROL_PCIE_PLLCFG4_VTUNE_EXT_EN (0x00000080u) -#define CONTROL_PCIE_PLLCFG4_VTUNE_EXT_EN_SHIFT (0x7u) - -#define CONTROL_PCIE_PLLCFG4_VTUNE_SPEED (0x00000040u) -#define CONTROL_PCIE_PLLCFG4_VTUNE_SPEED_SHIFT (0x6u) - -#define CONTROL_PCIE_PLLCFG4_VTUNE_MODE (0x00000030u) -#define CONTROL_PCIE_PLLCFG4_VTUNE_MODE_SHIFT (0x4u) - -#define CONTROL_PCIE_PLLCFG4_VTUNE_EXT_VAL (0x0000000Fu) -#define CONTROL_PCIE_PLLCFG4_VTUNE_EXT_VAL_SHIFT (0x0u) - -/** @brief CONTROL_PCIE_PLLSTATUS register fields */ -#define CONTROL_PCIE_PLLSTATUS_RTRIMSTS (0x00000F00u) -#define CONTROL_PCIE_PLLSTATUS_RTRIMSTS_SHIFT (0x8u) - -#define CONTROL_PCIE_PLLSTATUS_VTUNESTS (0x000000F0u) -#define CONTROL_PCIE_PLLSTATUS_VTUNESTS_SHIFT (0x4u) - -#define CONTROL_PCIE_PLLSTATUS_APLLDIGSTS5 (0x00000008u) -#define CONTROL_PCIE_PLLSTATUS_APLLDIGSTS5_SHIFT (0x3u) - -#define CONTROL_PCIE_PLLSTATUS_APLLDIGSTS4 (0x00000004u) -#define CONTROL_PCIE_PLLSTATUS_APLLDIGSTS4_SHIFT (0x2u) - -#define CONTROL_PCIE_PLLSTATUS_APLLDIGSTS1 (0x00000002u) -#define CONTROL_PCIE_PLLSTATUS_APLLDIGSTS1_SHIFT (0x1u) - -#define CONTROL_PCIE_PLLSTATUS_APLLDIGSTS0 (0x00000001u) -#define CONTROL_PCIE_PLLSTATUS_APLLDIGSTS0_SHIFT (0x0u) - -/** @brief CONTROL_PCIE_RXSTATUS register fields */ -#define CONTROL_PCIE_RXSTATUS_TESTFAIL (0x00000001u) -#define CONTROL_PCIE_RXSTATUS_TESTFAIL_SHIFT (0x0u) - -/** @brief CONTROL_PCIE_TXSTATUS register fields */ -#define CONTROL_PCIE_TXSTATUS_TESTFAIL (0x00000001u) -#define CONTROL_PCIE_TXSTATUS_TESTFAIL_SHIFT (0x0u) - -/** @brief CONTROL_PCIE_TESTCFG register fields */ -#define CONTROL_PCIE_TESTCFG_TX_TESTPATT (0x00000380u) -#define CONTROL_PCIE_TESTCFG_TX_TESTPATT_SHIFT (0x7u) - -#define CONTROL_PCIE_TESTCFG_RX_TESTPATT (0x00000007u) -#define CONTROL_PCIE_TESTCFG_RX_TESTPATT_SHIFT (0x0u) - -/** @brief CONTROL_PCIE_MISCCFG register fields */ -/* TBD */ - -/** @brief VDD_MPU_OPP_050 register fields */ -#define CONTROL_VDD_MPU_OPP_050_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_MPU_OPP_050_NTARGET_SHIFT (0x00000000u) - -/** @brief VDD_MPU_OPP_100 register fields */ -#define CONTROL_VDD_MPU_OPP_100_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_MPU_OPP_100_NTARGET_SHIFT (0x00000000u) - -/** @brief VDD_MPU_OPP_119 register fields */ -#define CONTROL_VDD_MPU_OPP_119_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_MPU_OPP_119_NTARGET_SHIFT (0x00000000u) - -/** @brief VDD_MPU_OPP_TURBO register fields */ -#define CONTROL_VDD_MPU_OPP_TURBO_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_MPU_OPP_TURBO_NTARGET_SHIFT (0x00000000u) - -/** @brief VDD_CORE_GEM_OPP_050 register fields */ -#define CONTROL_VDD_CORE_GEM_OPP_050_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_CORE_GEM_OPP_050_NTARGET_SHIFT (0x00000000u) - -/** @brief VDD_CORE_GEM_OPP_100 register fields */ -#define CONTROL_VDD_CORE_GEM_OPP_100_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_CORE_GEM_OPP_100_NTARGET_SHIFT (0x00000000u) - -/** @brief VDD_CORE_GEM_OPP_119 register fields */ -#define CONTROL_VDD_CORE_GEM_OPP_119_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_CORE_GEM_OPP_119_NTARGET_SHIFT (0x00000000u) - -/** @brief VDD_CORE_GEM_OPP_TURBO register fields */ -#define CONTROL_VDD_CORE_GEM_OPP_TURBO_NTARGET (0x00FFFFFFu) -#define CONTROL_VDD_CORE_GEM_OPP_TURBO_NTARGET_SHIFT (0x00000000u) - -/** @brief BB_SCALE register fields */ -#define CONTROL_BB_SCALE_BBIAS (0x00000003u) -#define CONTROL_BB_SCALE_BBIAS_SHIFT (0x00000000u) - -#define CONTROL_BB_SCALE_SCALE (0x00000F00u) -#define CONTROL_BB_SCALE_SCALE_SHIFT (0x00000008u) - -/** @brief USB_VID_PID register fields */ -#define CONTROL_USB_VID_PID_USB_PID (0x0000FFFFu) -#define CONTROL_USB_VID_PID_USB_PID_SHIFT (0x00000000u) - -#define CONTROL_USB_VID_PID_USB_VID (0xFFFF0000u) -#define CONTROL_USB_VID_PID_USB_VID_SHIFT (0x00000010u) - -/** @brief CONTROL_PCIE_VID_PID register fields */ -#define CONTROL_PCIE_VID_PID_PCIE_VID (0xFFFF0000u) -#define CONTROL_PCIE_VID_PID_PCIE_VID_SHIFT (0x10u) - -#define CONTROL_PCIE_VID_PID_PCIE_PID (0x0000FFFFu) -#define CONTROL_PCIE_VID_PID_PCIE_PID_SHIFT (0x0u) - -/** @brief EFUSE_SMA register fields */ -#define CONTROL_EFUSE_SMA_EFUSE_SMA (0xFFFFFFFFu) -#define CONTROL_EFUSE_SMA_EFUSE_SMA_SHIFT (0x00000000u) - -/** @brief PINCTRL(n) register fields */ -#define CONTROL_PINCTRL_MUXMODE (0x000007ffu) -#define CONTROL_PINCTRL_MUXMODE_SHIFT (0x00000000u) - -#define CONTROL_PINCTRL_PULLUDEN (0x00010000u) -#define CONTROL_PINCTRL_PULLUDEN_SHIFT (0x00000010u) - -#define CONTROL_PINCTRL_PULLTYPESEL (0x00020000u) -#define CONTROL_PINCTRL_PULLTYPESEL_SHIFT (0x00000011u) - -#define CONTROL_PINCTRL_RXACTIVE (0x00040000u) -#define CONTROL_PINCTRL_RXACTIVE_SHIFT (0x00000012u) - -#define CONTROL_PINCTRL_SLEWCTRL (0x00080000u) -#define CONTROL_PINCTRL_SLEWCTRL_SHIFT (0x00000013u) - -/* PINCTRL MUXMODE tokens */ -#define CONTROL_PINCTRL1_MUXMODE_SD1_CLK (0x1u) -#define CONTROL_PINCTRL1_MUXMODE_PR1_MII_MT1_CLK (0x4u) -#define CONTROL_PINCTRL1_MUXMODE_GP411 (0x80u) - -#define CONTROL_PINCTRL2_MUXMODE_SD1_CMD (0x1u) -#define CONTROL_PINCTRL2_MUXMODE_PR1_MII1_TXD3 (0x4u) -#define CONTROL_PINCTRL2_MUXMODE_EHRPWM1_TRIPZONE_INPUT (0x20u) -#define CONTROL_PINCTRL2_MUXMODE_GP00 (0x80u) - -#define CONTROL_PINCTRL3_MUXMODE_SD1_DAT0 (0x1u) -#define CONTROL_PINCTRL3_MUXMODE_PR1_MII1_TXD2 (0x4u) -#define CONTROL_PINCTRL3_MUXMODE_GP412 (0x80u) - -#define CONTROL_PINCTRL4_MUXMODE_SD1_DAT1_SDIRQ (0x1u) -#define CONTROL_PINCTRL4_MUXMODE_PR1_MII1_TXD1 (0x4u) -#define CONTROL_PINCTRL4_MUXMODE_EHRPWM1A (0x20u) -#define CONTROL_PINCTRL4_MUXMODE_GP413 (0x80u) - -#define CONTROL_PINCTRL5_MUXMODE_SD1_DAT2_SDRW (0x1u) -#define CONTROL_PINCTRL5_MUXMODE_PR1_MII1_TXD0 (0x4u) -#define CONTROL_PINCTRL5_MUXMODE_EHRPWM1B (0x20u) -#define CONTROL_PINCTRL5_MUXMODE_GP414 (0x80u) - -#define CONTROL_PINCTRL6_MUXMODE_SD1_DAT3 (0x1u) -#define CONTROL_PINCTRL6_MUXMODE_PR1_MII1_CRS (0x4u) -#define CONTROL_PINCTRL6_MUXMODE_PR1_PRU0_R3016 (0x8u) -#define CONTROL_PINCTRL6_MUXMODE_PR1_PRU0_R3116 (0x10u) -#define CONTROL_PINCTRL6_MUXMODE_EQEP2_INDEX (0x20u) -#define CONTROL_PINCTRL6_MUXMODE_GP415 (0x80u) - -#define CONTROL_PINCTRL7_MUXMODE_DEVOSC_WAKE (0x1u) -#define CONTROL_PINCTRL7_MUXMODE_SPI1_SCS1n (0x2u) -#define CONTROL_PINCTRL7_MUXMODE_PR1_MII1_CRS (0x4u) -#define CONTROL_PINCTRL7_MUXMODE_PR1_PRU0_R3016 (0x8u) -#define CONTROL_PINCTRL7_MUXMODE_PR1_PRU0_R3116 (0x10u) -#define CONTROL_PINCTRL7_MUXMODE_TIM5_IO (0x40u) -#define CONTROL_PINCTRL7_MUXMODE_GP17 (0x80u) - -#define CONTROL_PINCTRL8_MUXMODE_SD0_CLK (0x1u) -#define CONTROL_PINCTRL8_MUXMODE_EHRPWM2A (0x20u) -#define CONTROL_PINCTRL8_MUXMODE_GP01 (0x80u) - -#define CONTROL_PINCTRL9_MUXMODE_SD0_CMD (0x1u) -#define CONTROL_PINCTRL9_MUXMODE_SD1_CMD (0x2u) -#define CONTROL_PINCTRL9_MUXMODE_EHRPWM2B (0x20u) -#define CONTROL_PINCTRL9_MUXMODE_GP02 (0x80u) - -#define CONTROL_PINCTRL10_MUXMODE_SD0_DAT0 (0x1u) -#define CONTROL_PINCTRL10_MUXMODE_SD1_DAT4 (0x2u) -#define CONTROL_PINCTRL10_MUXMODE_EHRPWM2_TRIPZONE_INPUT (0x20u) -#define CONTROL_PINCTRL10_MUXMODE_GP03 (0x80u) - -#define CONTROL_PINCTRL11_MUXMODE_SD0_DAT1_SDIRQn (0x1u) -#define CONTROL_PINCTRL11_MUXMODE_SD1_DAT5 (0x2u) -#define CONTROL_PINCTRL11_MUXMODE_GP04 (0x80u) - -#define CONTROL_PINCTRL12_MUXMODE_SD0_DAT2_SDRWn (0x1u) -#define CONTROL_PINCTRL12_MUXMODE_SD1_DAT6 (0x2u) -#define CONTROL_PINCTRL12_MUXMODE_GP05 (0x80u) - -#define CONTROL_PINCTRL13_MUXMODE_SD0_DAT3 (0x1u) -#define CONTROL_PINCTRL13_MUXMODE_SD1_DAT7 (0x2u) -#define CONTROL_PINCTRL13_MUXMODE_GP06 (0x80u) - -#define CONTROL_PINCTRL14_MUXMODE_AUD_CLKIN0 (0x1u) -#define CONTROL_PINCTRL14_MUXMODE_MCA0_AXR7 (0x2u) -#define CONTROL_PINCTRL14_MUXMODE_MCA0_AHCLKX (0x4u) -#define CONTROL_PINCTRL14_MUXMODE_MCA3_AHCLKX (0x8u) -#define CONTROL_PINCTRL14_MUXMODE_ATL_CLKOUT1 (0x10u) -#define CONTROL_PINCTRL14_MUXMODE_ATL_CLKOUT0 (0x20u) -#define CONTROL_PINCTRL14_MUXMODE_USB1_DRVVBUS (0x80u) -#define CONTROL_PINCTRL14_MUXMODE_PR1_PRU0_R3116 (0x100u) - -#define CONTROL_PINCTRL15_MUXMODE_AUD_CLKIN1 (0x1u) -#define CONTROL_PINCTRL15_MUXMODE_MCA0_AXR8 (0x2u) -#define CONTROL_PINCTRL15_MUXMODE_MCA1_AHCLKX (0x4u) -#define CONTROL_PINCTRL15_MUXMODE_MCA4_AHCLKX (0x8u) -#define CONTROL_PINCTRL15_MUXMODE_ATL_CLKOUT2 (0x10u) -#define CONTROL_PINCTRL15_MUXMODE_EDMA_EVT3 (0x20u) -#define CONTROL_PINCTRL15_MUXMODE_TIM2_IO (0x40u) -#define CONTROL_PINCTRL15_MUXMODE_GP08 (0x80u) - -#define CONTROL_PINCTRL16_MUXMODE_AUD_CLKIN2 (0x1u) -#define CONTROL_PINCTRL16_MUXMODE_MCA0_AXR9 (0x2u) -#define CONTROL_PINCTRL16_MUXMODE_MCA2_AHCLKX (0x4u) -#define CONTROL_PINCTRL16_MUXMODE_MCA5_AHCLKX (0x8u) -#define CONTROL_PINCTRL16_MUXMODE_ATL_CLKOUT3 (0x10u) -#define CONTROL_PINCTRL16_MUXMODE_EDMA_EVT2 (0x20u) -#define CONTROL_PINCTRL16_MUXMODE_TIM3_IO (0x40u) -#define CONTROL_PINCTRL16_MUXMODE_GP09 (0x80u) - -#define CONTROL_PINCTRL17_MUXMODE_MCA0_ACLKX (0x1u) -#define CONTROL_PINCTRL17_MUXMODE_PR1_MII1_RXD3 (0x4u) -#define CONTROL_PINCTRL17_MUXMODE_PR1_PRU0_R310 (0x8u) -#define CONTROL_PINCTRL17_MUXMODE_PR1_PRU0_R300 (0x10u) -#define CONTROL_PINCTRL17_MUXMODE_EQEP1A_IN (0x40u) - -#define CONTROL_PINCTRL18_MUXMODE_MCA0_AFSX (0x1u) -#define CONTROL_PINCTRL18_MUXMODE_PR1_MII1_RXD2 (0x4u) -#define CONTROL_PINCTRL18_MUXMODE_PR1_PRU0_R311 (0x8u) -#define CONTROL_PINCTRL18_MUXMODE_PR1_PRU0_R301 (0x10u) -#define CONTROL_PINCTRL18_MUXMODE_EQEP1B_IN (0x40u) - -#define CONTROL_PINCTRL19_MUXMODE_MCA0_ACLKR (0x1u) -#define CONTROL_PINCTRL19_MUXMODE_MCA5_AXR2 (0x2u) -#define CONTROL_PINCTRL19_MUXMODE_PR1_MII1_RXD1 (0x4u) -#define CONTROL_PINCTRL19_MUXMODE_PR1_PRU0_R312 (0x8u) -#define CONTROL_PINCTRL19_MUXMODE_PR1_PRU0_R302 (0x10u) -#define CONTROL_PINCTRL19_MUXMODE_EQEP1_INDEX (0x40u) - -#define CONTROL_PINCTRL20_MUXMODE_MCA0_AFSR (0x1u) -#define CONTROL_PINCTRL20_MUXMODE_MCA5_AXR3 (0x2u) -#define CONTROL_PINCTRL20_MUXMODE_PR1_MII1_RXD0 (0x4u) -#define CONTROL_PINCTRL20_MUXMODE_PR1_PRU0_R313 (0x8u) -#define CONTROL_PINCTRL20_MUXMODE_PR1_PRU0_R303 (0x10u) -#define CONTROL_PINCTRL20_MUXMODE_EQEP1_STROBE (0x40u) - -#define CONTROL_PINCTRL21_MUXMODE_MCA0_AXR0 (0x1u) -#define CONTROL_PINCTRL21_MUXMODE_PR1_MII_MR1_CLK (0x4u) -#define CONTROL_PINCTRL21_MUXMODE_PR1_PRU0_R314 (0x8u) -#define CONTROL_PINCTRL21_MUXMODE_PR1_PRU0_R304 (0x10u) -#define CONTROL_PINCTRL21_MUXMODE_EHRPWM1A (0x40u) - -#define CONTROL_PINCTRL22_MUXMODE_MCA0_AXR1 (0x1u) -#define CONTROL_PINCTRL22_MUXMODE_PR1_MII_MT0_CLK (0x4u) -#define CONTROL_PINCTRL22_MUXMODE_PR1_PRU0_R315 (0x8u) -#define CONTROL_PINCTRL22_MUXMODE_PR1_PRU0_R305 (0x10u) -#define CONTROL_PINCTRL22_MUXMODE_I2C3_SCL (0x20u) -#define CONTROL_PINCTRL22_MUXMODE_EHRPWM1B (0x40u) -#define CONTROL_PINCTRL22_MUXMODE_MMC1_SDWP (0x100u) - -#define CONTROL_PINCTRL23_MUXMODE_MCA0_AXR2 (0x1u) -#define CONTROL_PINCTRL23_MUXMODE_PR1_MII0_RXLINK (0x4u) -#define CONTROL_PINCTRL23_MUXMODE_PR1_PRU0_R316 (0x8u) -#define CONTROL_PINCTRL23_MUXMODE_PR1_PRU0_R306 (0x10u) -#define CONTROL_PINCTRL23_MUXMODE_I2C3_SDA (0x20u) -#define CONTROL_PINCTRL23_MUXMODE_EHRPWM1_TRIPZONE_INPUT (0x40u) -#define CONTROL_PINCTRL23_MUXMODE_MMC1_SDCD (0x100u) - -#define CONTROL_PINCTRL24_MUXMODE_MCA0_AXR3 (0x1u) -#define CONTROL_PINCTRL24_MUXMODE_PR1_MII1_COL (0x4u) -#define CONTROL_PINCTRL24_MUXMODE_PR1_PRU0_R307 (0x10u) -#define CONTROL_PINCTRL24_MUXMODE_PR1_PRU0_R317 (0x20u) - -#define CONTROL_PINCTRL25_MUXMODE_MCA0_AXR4 (0x1u) -#define CONTROL_PINCTRL25_MUXMODE_MCA1_AXR8 (0x2u) -#define CONTROL_PINCTRL25_MUXMODE_PR1_MII0_COL (0x4u) -#define CONTROL_PINCTRL25_MUXMODE_PR1_PRU0_R318 (0x8u) -#define CONTROL_PINCTRL25_MUXMODE_PR1_PRU0_R308 (0x10u) -#define CONTROL_PINCTRL25_MUXMODE_EQEP2A_IN (0x40u) - -#define CONTROL_PINCTRL26_MUXMODE_MCA0_AXR5 (0x1u) -#define CONTROL_PINCTRL26_MUXMODE_MCA1_AXR9 (0x2u) -#define CONTROL_PINCTRL26_MUXMODE_PR1_MII0_RXER (0x4u) -#define CONTROL_PINCTRL26_MUXMODE_PR1_PRU0_R319 (0x8u) -#define CONTROL_PINCTRL26_MUXMODE_PR1_PRU0_R309 (0x10u) -#define CONTROL_PINCTRL26_MUXMODE_EQEP2B_IN (0x40u) - -#define CONTROL_PINCTRL27_MUXMODE_MCA0_AXR6 (0x1u) -#define CONTROL_PINCTRL27_MUXMODE_MCB_DR (0x2u) -#define CONTROL_PINCTRL27_MUXMODE_PR1_PRU0_R3110 (0x8u) -#define CONTROL_PINCTRL27_MUXMODE_PR1_PRU0_R3010 (0x10u) - -#define CONTROL_PINCTRL28_MUXMODE_MCA0_AXR7 (0x1u) -#define CONTROL_PINCTRL28_MUXMODE_MCB_DX (0x2u) -#define CONTROL_PINCTRL28_MUXMODE_PR1_PRU0_R3111 (0x8u) -#define CONTROL_PINCTRL28_MUXMODE_PR1_PRU0_R3011 (0x10u) - -#define CONTROL_PINCTRL29_MUXMODE_MCA0_AXR8 (0x1u) -#define CONTROL_PINCTRL29_MUXMODE_MCB_FSX (0x2u) -#define CONTROL_PINCTRL29_MUXMODE_MCB_FSR (0x4u) -#define CONTROL_PINCTRL29_MUXMODE_PR1_PRU0_R3112 (0x8u) -#define CONTROL_PINCTRL29_MUXMODE_PR1_PRU0_R3012 (0x10u) -#define CONTROL_PINCTRL29_MUXMODE_MMC0_SDWP (0x100u) - -#define CONTROL_PINCTRL30_MUXMODE_MCA0_AXR9 (0x1u) -#define CONTROL_PINCTRL30_MUXMODE_MCB_CLKX (0x2u) -#define CONTROL_PINCTRL30_MUXMODE_MCB_CLKR (0x4u) -#define CONTROL_PINCTRL30_MUXMODE_MMC0_SDCD (0x100u) - -#define CONTROL_PINCTRL31_MUXMODE_MCA1_ACLKX (0x1u) -#define CONTROL_PINCTRL31_MUXMODE_PR1_MII0_TXEN (0x4u) - -#define CONTROL_PINCTRL32_MUXMODE_MCA1_AFSX (0x1u) -#define CONTROL_PINCTRL32_MUXMODE_PR1_MII0_TXD3 (0x4u) - -#define CONTROL_PINCTRL33_MUXMODE_MCA1_ACLKR (0x1u) -#define CONTROL_PINCTRL33_MUXMODE_MCA1_AXR4 (0x2u) -#define CONTROL_PINCTRL33_MUXMODE_PR1_MII0_TXD2 (0x4u) - -#define CONTROL_PINCTRL34_MUXMODE_MCA1_AFSR (0x1u) -#define CONTROL_PINCTRL34_MUXMODE_MCA1_AXR5 (0x2u) -#define CONTROL_PINCTRL34_MUXMODE_PR1_MII1_RXER (0x4u) -#define CONTROL_PINCTRL34_MUXMODE_EHRPWM0A (0x40u) - -#define CONTROL_PINCTRL35_MUXMODE_MCA1_AXR0 (0x1u) -#define CONTROL_PINCTRL35_MUXMODE_SD0_DAT4 (0x2u) -#define CONTROL_PINCTRL35_MUXMODE_PR1_MII1_RXDV (0x4u) -#define CONTROL_PINCTRL35_MUXMODE_EHRPWM0B (0x40u) - -#define CONTROL_PINCTRL36_MUXMODE_MCA1_AXR1 (0x1u) -#define CONTROL_PINCTRL36_MUXMODE_SD0_DAT5 (0x2u) -#define CONTROL_PINCTRL36_MUXMODE_PR1_MII1_TXEN (0x4u) -#define CONTROL_PINCTRL36_MUXMODE_EHRPWM0_TRIPZONE_INPUT (0x40u) - -#define CONTROL_PINCTRL37_MUXMODE_MCA1_AXR2 (0x1u) -#define CONTROL_PINCTRL37_MUXMODE_MCB_FSR (0x2u) -#define CONTROL_PINCTRL37_MUXMODE_ECAP2_IN_PWM2_OUT (0x4u) -#define CONTROL_PINCTRL37_MUXMODE_EHRPWM0_SYNCI (0x20u) -#define CONTROL_PINCTRL37_MUXMODE_EHRPWM0_SYNCO (0x40u) - -#define CONTROL_PINCTRL38_MUXMODE_MCA1_AXR3 (0x1u) -#define CONTROL_PINCTRL38_MUXMODE_MCB_CLKR (0x2u) -#define CONTROL_PINCTRL38_MUXMODE_PR1_MII1_RXLINK (0x4u) -#define CONTROL_PINCTRL38_MUXMODE_EQEP0A_IN (0x40u) - -#define CONTROL_PINCTRL39_MUXMODE_MCA2_ACLKX (0x1u) -#define CONTROL_PINCTRL39_MUXMODE_PR1_MII0_TXD1 (0x2u) -#define CONTROL_PINCTRL39_MUXMODE_GP010 (0x80u) - -#define CONTROL_PINCTRL40_MUXMODE_MCA2_AFSX (0x1u) -#define CONTROL_PINCTRL40_MUXMODE_PR1_MII0_TXD0 (0x2u) -#define CONTROL_PINCTRL40_MUXMODE_GP011 (0x80u) - -#define CONTROL_PINCTRL41_MUXMODE_MCA2_AXR0 (0x1u) -#define CONTROL_PINCTRL41_MUXMODE_SD0_DAT6 (0x2u) -#define CONTROL_PINCTRL41_MUXMODE_EQEP0B_IN (0x10u) -#define CONTROL_PINCTRL41_MUXMODE_UART5_RXD (0x20u) -#define CONTROL_PINCTRL41_MUXMODE_GP012 (0x80u) - -#define CONTROL_PINCTRL42_MUXMODE_MCA2_AXR1 (0x1u) -#define CONTROL_PINCTRL42_MUXMODE_SD0_DAT7 (0x2u) -#define CONTROL_PINCTRL42_MUXMODE_EQEP0_INDEX (0x10u) -#define CONTROL_PINCTRL42_MUXMODE_UART5_TXD (0x20u) -#define CONTROL_PINCTRL42_MUXMODE_GP013 (0x80u) - -#define CONTROL_PINCTRL43_MUXMODE_MCA2_AXR2 (0x1u) -#define CONTROL_PINCTRL43_MUXMODE_MCA1_AXR6 (0x2u) -#define CONTROL_PINCTRL43_MUXMODE_PR1_MII_MR0_CLK (0x4u) -#define CONTROL_PINCTRL43_MUXMODE_EQEP0_STROBE (0x10u) -#define CONTROL_PINCTRL43_MUXMODE_TIM2_IO (0x40u) -#define CONTROL_PINCTRL43_MUXMODE_GP014 (0x80u) - -#define CONTROL_PINCTRL44_MUXMODE_MCA2_AXR3 (0x1u) -#define CONTROL_PINCTRL44_MUXMODE_MCA1_AXR7 (0x2u) -#define CONTROL_PINCTRL44_MUXMODE_PR1_MII0_RXDV (0x4u) -#define CONTROL_PINCTRL44_MUXMODE_TIM3_IO (0x40u) -#define CONTROL_PINCTRL44_MUXMODE_GP015 (0x80u) - -#define CONTROL_PINCTRL45_MUXMODE_MCA3_ACLKX (0x1u) -#define CONTROL_PINCTRL45_MUXMODE_PR1_PRU0_R3120 (0x10u) -#define CONTROL_PINCTRL45_MUXMODE_PR1_PRU0_R3020 (0x20u) -#define CONTROL_PINCTRL45_MUXMODE_GP016 (0x80u) - -#define CONTROL_PINCTRL46_MUXMODE_MCA3_AFSX (0x1u) -#define CONTROL_PINCTRL46_MUXMODE_PR1_PRU0_R3119 (0x10u) -#define CONTROL_PINCTRL46_MUXMODE_PR1_PRU0_R3019 (0x20u) -#define CONTROL_PINCTRL46_MUXMODE_GP017 (0x80u) - -#define CONTROL_PINCTRL47_MUXMODE_MCA3_AXR0 (0x1u) -#define CONTROL_PINCTRL47_MUXMODE_PR1_PRU0_R3118 (0x10u) -#define CONTROL_PINCTRL47_MUXMODE_PR1_PRU0_R3018 (0x20u) -#define CONTROL_PINCTRL47_MUXMODE_TIM4_IO (0x40u) -#define CONTROL_PINCTRL47_MUXMODE_GP018 (0x80u) - -#define CONTROL_PINCTRL48_MUXMODE_MCA3_AXR1 (0x1u) -#define CONTROL_PINCTRL48_MUXMODE_PR1_PRU0_R3117 (0x10u) -#define CONTROL_PINCTRL48_MUXMODE_PR1_PRU0_R3017 (0x20u) -#define CONTROL_PINCTRL48_MUXMODE_TIM5_IO (0x40u) -#define CONTROL_PINCTRL48_MUXMODE_GP019 (0x80u) - -#define CONTROL_PINCTRL49_MUXMODE_MCA3_AXR2 (0x1u) -#define CONTROL_PINCTRL49_MUXMODE_MCA1_AXR8 (0x2u) -#define CONTROL_PINCTRL49_MUXMODE_PR1_MII0_RXD3 (0x4u) -#define CONTROL_PINCTRL49_MUXMODE_EQEP2_INDEX (0x10u) -#define CONTROL_PINCTRL49_MUXMODE_GP020 (0x80u) - -#define CONTROL_PINCTRL50_MUXMODE_MCA3_AXR3 (0x1u) -#define CONTROL_PINCTRL50_MUXMODE_MCA1_AXR9 (0x2u) -#define CONTROL_PINCTRL50_MUXMODE_PR1_MII0_RXD2 (0x4u) -#define CONTROL_PINCTRL50_MUXMODE_EQEP2_STROBE (0x10u) - -#define CONTROL_PINCTRL51_MUXMODE_MCA4_ACLKX (0x1u) -#define CONTROL_PINCTRL51_MUXMODE_PR1_PRU0_R3114 (0x10u) -#define CONTROL_PINCTRL51_MUXMODE_PR1_PRU0_R3014 (0x20u) -#define CONTROL_PINCTRL51_MUXMODE_GP021 (0x80u) - -#define CONTROL_PINCTRL52_MUXMODE_MCA4_AFSX (0x1u) -#define CONTROL_PINCTRL52_MUXMODE_PR1_MII0_RXD1 (0x2u) -#define CONTROL_PINCTRL52_MUXMODE_PR1_PRU0_R3115 (0x10u) -#define CONTROL_PINCTRL52_MUXMODE_PR1_PRU0_R3015 (0x20u) -#define CONTROL_PINCTRL52_MUXMODE_GP022 (0x80u) - -#define CONTROL_PINCTRL53_MUXMODE_MCA4_AXR0 (0x1u) -#define CONTROL_PINCTRL53_MUXMODE_PR1_MII0_RXD0 (0x2u) -#define CONTROL_PINCTRL53_MUXMODE_PR1_PRU0_R3113 (0x10u) -#define CONTROL_PINCTRL53_MUXMODE_PR1_PRU0_R3013 (0x20u) -#define CONTROL_PINCTRL53_MUXMODE_GP023 (0x80u) - -#define CONTROL_PINCTRL54_MUXMODE_MCA4_AXR1 (0x1u) -#define CONTROL_PINCTRL54_MUXMODE_PR1_MII0_CRS (0x2u) -#define CONTROL_PINCTRL54_MUXMODE_TIM6_IO (0x40u) -#define CONTROL_PINCTRL54_MUXMODE_GP024 (0x80u) - -#define CONTROL_PINCTRL55_MUXMODE_MCA5_ACLKX (0x1u) -#define CONTROL_PINCTRL55_MUXMODE_GP025 (0x80u) - -#define CONTROL_PINCTRL56_MUXMODE_MCA5_AFSX (0x1u) -#define CONTROL_PINCTRL56_MUXMODE_GP026 (0x80u) - -#define CONTROL_PINCTRL57_MUXMODE_MCA5_AXR0 (0x1u) -#define CONTROL_PINCTRL57_MUXMODE_MCA4_AXR2 (0x2u) -#define CONTROL_PINCTRL57_MUXMODE_PR1_ECAP0_CAPIN_APWM_O (0x20u) -#define CONTROL_PINCTRL57_MUXMODE_GP027 (0x80u) - -#define CONTROL_PINCTRL58_MUXMODE_MCA5_AXR1 (0x1u) -#define CONTROL_PINCTRL58_MUXMODE_MCA4_AXR3 (0x2u) -#define CONTROL_PINCTRL58_MUXMODE_TIM7_IO (0x40u) -#define CONTROL_PINCTRL58_MUXMODE_GP028 (0x80u) - -#define CONTROL_PINCTRL59_MUXMODE_MLB_SIG (0x1u) -#define CONTROL_PINCTRL59_MUXMODE_UART2_RXD (0x8u) -#define CONTROL_PINCTRL59_MUXMODE_GP029 (0x80u) - -#define CONTROL_PINCTRL60_MUXMODE_MLB_DAT (0x1u) -#define CONTROL_PINCTRL60_MUXMODE_TCLKIN (0x8u) -#define CONTROL_PINCTRL60_MUXMODE_GP030 (0x80u) - -#define CONTROL_PINCTRL61_MUXMODE_MLB_CLK (0x1u) -#define CONTROL_PINCTRL61_MUXMODE_UART2_TXD (0x8u) -#define CONTROL_PINCTRL61_MUXMODE_GP031 (0x80u) - -#define CONTROL_PINCTRL62_MUXMODE_MLBP_SIGP (0x1u) -#define CONTROL_PINCTRL62_MUXMODE_GP17 (0x80u) - -#define CONTROL_PINCTRL63_MUXMODE_MLBP_SIGN (0x1u) -#define CONTROL_PINCTRL63_MUXMODE_GP18 (0x80u) - -#define CONTROL_PINCTRL64_MUXMODE_MLBP_DATP (0x1u) -#define CONTROL_PINCTRL64_MUXMODE_GP19 (0x80u) - -#define CONTROL_PINCTRL65_MUXMODE_MLBP_DATN (0x1u) -#define CONTROL_PINCTRL65_MUXMODE_GP110 (0x80u) - -#define CONTROL_PINCTRL66_MUXMODE_MLBP_CLKP (0x1u) - -#define CONTROL_PINCTRL67_MUXMODE_MLBP_CLKN (0x1u) - -#define CONTROL_PINCTRL68_MUXMODE_DCAN0_TX (0x1u) -#define CONTROL_PINCTRL68_MUXMODE_UART2_TXD (0x2u) -#define CONTROL_PINCTRL68_MUXMODE_I2C3_SDA (0x20u) -#define CONTROL_PINCTRL68_MUXMODE_GP10 (0x80u) - -#define CONTROL_PINCTRL69_MUXMODE_DCAN0_RX (0x1u) -#define CONTROL_PINCTRL69_MUXMODE_UART2_RXD (0x2u) -#define CONTROL_PINCTRL69_MUXMODE_I2C3_SCL (0x20u) -#define CONTROL_PINCTRL69_MUXMODE_GP11 (0x80u) - -#define CONTROL_PINCTRL70_MUXMODE_UART0_RXD (0x1u) - -#define CONTROL_PINCTRL71_MUXMODE_UART0_TXD (0x1u) - -#define CONTROL_PINCTRL72_MUXMODE_UART0_CTSn (0x1u) -#define CONTROL_PINCTRL72_MUXMODE_UART4_RXD (0x2u) -#define CONTROL_PINCTRL72_MUXMODE_DCAN1_TX (0x8u) -#define CONTROL_PINCTRL72_MUXMODE_SPI1_SCS3n (0x10u) -#define CONTROL_PINCTRL72_MUXMODE_SD0_SDCD (0x40u) -#define CONTROL_PINCTRL72_MUXMODE_GP416 (0x80u) - -#define CONTROL_PINCTRL73_MUXMODE_UART0_RTSn (0x1u) -#define CONTROL_PINCTRL73_MUXMODE_UART4_TXD (0x2u) -#define CONTROL_PINCTRL73_MUXMODE_DCAN1_RX (0x8u) -#define CONTROL_PINCTRL73_MUXMODE_SPI1_SCS2n (0x10u) -#define CONTROL_PINCTRL73_MUXMODE_SD2_SDCD (0x40u) -#define CONTROL_PINCTRL73_MUXMODE_GP417 (0x80u) - -#define CONTROL_PINCTRL74_MUXMODE_UART0_DCDn (0x1u) -#define CONTROL_PINCTRL74_MUXMODE_UART3_RXD (0x2u) -#define CONTROL_PINCTRL74_MUXMODE_SPI0_SCS3n (0x10u) -#define CONTROL_PINCTRL74_MUXMODE_I2C2_SCL (0x20u) -#define CONTROL_PINCTRL74_MUXMODE_SD1_POW (0x40u) -#define CONTROL_PINCTRL74_MUXMODE_GP12 (0x80u) - -#define CONTROL_PINCTRL75_MUXMODE_UART0_DSRn (0x1u) -#define CONTROL_PINCTRL75_MUXMODE_UART3_TXD (0x2u) -#define CONTROL_PINCTRL75_MUXMODE_SPI0_SCS2n (0x10u) -#define CONTROL_PINCTRL75_MUXMODE_I2C2_SDA (0x20u) -#define CONTROL_PINCTRL75_MUXMODE_SD1_SDWP (0x40u) -#define CONTROL_PINCTRL75_MUXMODE_GP13 (0x80u) - -#define CONTROL_PINCTRL76_MUXMODE_UART0_DTRn (0x1u) -#define CONTROL_PINCTRL76_MUXMODE_UART3_CTSn (0x2u) -#define CONTROL_PINCTRL76_MUXMODE_UART1_TXD (0x4u) -#define CONTROL_PINCTRL76_MUXMODE_PR1_PRU1_R3014 (0x8u) -#define CONTROL_PINCTRL76_MUXMODE_PR1_PRU1_R3114 (0x10u) -#define CONTROL_PINCTRL76_MUXMODE_ECAP2_IN_PWM2_OUT (0x20u) -#define CONTROL_PINCTRL76_MUXMODE_GP14 (0x80u) - -#define CONTROL_PINCTRL77_MUXMODE_UART0_RIN (0x1u) -#define CONTROL_PINCTRL77_MUXMODE_UART3_RTSn (0x2u) -#define CONTROL_PINCTRL77_MUXMODE_UART1_RXD (0x4u) -#define CONTROL_PINCTRL77_MUXMODE_PR1_PRU1_R3015 (0x8u) -#define CONTROL_PINCTRL77_MUXMODE_PR1_PRU1_R3115 (0x10u) -#define CONTROL_PINCTRL77_MUXMODE_ECAP1_IN_PWM1_OUT (0x20u) -#define CONTROL_PINCTRL77_MUXMODE_GP15 (0x80u) - -#define CONTROL_PINCTRL78_MUXMODE_I2C1_SCL (0x1u) - -#define CONTROL_PINCTRL79_MUXMODE_I2C1_SDA (0x1u) - -#define CONTROL_PINCTRL80_MUXMODE_SPI0_SCS1n (0x1u) -#define CONTROL_PINCTRL80_MUXMODE_SD1_SDCD (0x2u) -#define CONTROL_PINCTRL80_MUXMODE_EHRPWM0A (0x8u) -#define CONTROL_PINCTRL80_MUXMODE_PR1_ECAP0_CAPIN_APWM_O (0x10u) -#define CONTROL_PINCTRL80_MUXMODE_EDMA_EVT1 (0x20u) -#define CONTROL_PINCTRL80_MUXMODE_TIM4_IO (0x40u) -#define CONTROL_PINCTRL80_MUXMODE_GP16 (0x80u) -#define CONTROL_PINCTRL80_MUXMODE_ECAP0_IN_PWM0_OUT (0x100u) - -#define CONTROL_PINCTRL81_MUXMODE_SPI0_SCS0n (0x1u) -#define CONTROL_PINCTRL81_MUXMODE_GP418 (0x80u) - -#define CONTROL_PINCTRL82_MUXMODE_SPI0_SCLK (0x1u) -#define CONTROL_PINCTRL82_MUXMODE_EHRPWM0_TRIPZONE_INPUT (0x8u) - -#define CONTROL_PINCTRL83_MUXMODE_SPI0_D1 (0x1u) -#define CONTROL_PINCTRL83_MUXMODE_EHRPWM0_SYNCI (0x4u) -#define CONTROL_PINCTRL83_MUXMODE_EHRPWM0_SYNCO (0x8u) - -#define CONTROL_PINCTRL84_MUXMODE_SPI0_D0 (0x1u) -#define CONTROL_PINCTRL84_MUXMODE_EHRPWM0B (0x8u) - -#define CONTROL_PINCTRL85_MUXMODE_SPI1_SCS0n (0x1u) -#define CONTROL_PINCTRL85_MUXMODE_GP116 (0x80u) - -#define CONTROL_PINCTRL86_MUXMODE_SPI1_SCLK (0x1u) -#define CONTROL_PINCTRL86_MUXMODE_GP117 (0x80u) - -#define CONTROL_PINCTRL87_MUXMODE_SPI1_D1 (0x1u) -#define CONTROL_PINCTRL87_MUXMODE_ECAP2_IN_PWM2_OUT (0x8u) -#define CONTROL_PINCTRL87_MUXMODE_GP118 (0x80u) - -#define CONTROL_PINCTRL88_MUXMODE_SPI1_D0 (0x1u) -#define CONTROL_PINCTRL88_MUXMODE_ECAP1_IN_PWM1_OUT (0x8u) -#define CONTROL_PINCTRL88_MUXMODE_GP126 (0x80u) - -#define CONTROL_PINCTRL89_MUXMODE_GPMC_D0 (0x1u) -#define CONTROL_PINCTRL89_MUXMODE_SPI2_D1 (0x4u) -#define CONTROL_PINCTRL89_MUXMODE_BTMODE0 (0x80u) - -#define CONTROL_PINCTRL90_MUXMODE_GPMC_D1 (0x1u) -#define CONTROL_PINCTRL90_MUXMODE_SPI2_D0 (0x4u) -#define CONTROL_PINCTRL90_MUXMODE_BTMODE1 (0x80u) - -#define CONTROL_PINCTRL91_MUXMODE_GPMC_D2 (0x1u) -#define CONTROL_PINCTRL91_MUXMODE_BTMODE2 (0x80u) - -#define CONTROL_PINCTRL92_MUXMODE_GPMC_D3 (0x1u) -#define CONTROL_PINCTRL92_MUXMODE_BTMODE3 (0x80u) - -#define CONTROL_PINCTRL93_MUXMODE_GPMC_D4 (0x1u) -#define CONTROL_PINCTRL93_MUXMODE_GP56 (0x40u) -#define CONTROL_PINCTRL93_MUXMODE_BTMODE4 (0x80u) - -#define CONTROL_PINCTRL94_MUXMODE_GPMC_D5 (0x1u) -#define CONTROL_PINCTRL94_MUXMODE_GP57 (0x40u) -#define CONTROL_PINCTRL94_MUXMODE_BTMODE5 (0x80u) - -#define CONTROL_PINCTRL95_MUXMODE_GPMC_D6 (0x1u) -#define CONTROL_PINCTRL95_MUXMODE_EHRPWM2_TRIPZONE_INPUT (0x10u) -#define CONTROL_PINCTRL95_MUXMODE_GP58 (0x40u) -#define CONTROL_PINCTRL95_MUXMODE_BTMODE6 (0x80u) - -#define CONTROL_PINCTRL96_MUXMODE_GPMC_D7 (0x1u) -#define CONTROL_PINCTRL96_MUXMODE_GP59 (0x40u) -#define CONTROL_PINCTRL96_MUXMODE_BTMODE7 (0x80u) - -#define CONTROL_PINCTRL97_MUXMODE_GPMC_D8 (0x1u) -#define CONTROL_PINCTRL97_MUXMODE_UART7_TXD (0x8u) -#define CONTROL_PINCTRL97_MUXMODE_GP40 (0x40u) -#define CONTROL_PINCTRL97_MUXMODE_BTMODE8 (0x80u) - -#define CONTROL_PINCTRL98_MUXMODE_GPMC_D9 (0x1u) -#define CONTROL_PINCTRL98_MUXMODE_UART7_RXD (0x8u) -#define CONTROL_PINCTRL98_MUXMODE_GP41 (0x40u) -#define CONTROL_PINCTRL98_MUXMODE_BTMODE9 (0x80u) - -#define CONTROL_PINCTRL99_MUXMODE_GPMC_D10 (0x1u) -#define CONTROL_PINCTRL99_MUXMODE_UART7_RTSn (0x8u) -#define CONTROL_PINCTRL99_MUXMODE_GP42 (0x40u) -#define CONTROL_PINCTRL99_MUXMODE_BTMODE10 (0x80u) - -#define CONTROL_PINCTRL100_MUXMODE_GPMC_D11 (0x1u) -#define CONTROL_PINCTRL100_MUXMODE_UART7_CTSn (0x8u) -#define CONTROL_PINCTRL100_MUXMODE_GP43 (0x40u) -#define CONTROL_PINCTRL100_MUXMODE_BTMODE11 (0x80u) - -#define CONTROL_PINCTRL101_MUXMODE_GPMC_D12 (0x1u) -#define CONTROL_PINCTRL101_MUXMODE_EHRPWM2A (0x10u) -#define CONTROL_PINCTRL101_MUXMODE_GP44 (0x40u) -#define CONTROL_PINCTRL101_MUXMODE_BTMODE12 (0x80u) - -#define CONTROL_PINCTRL102_MUXMODE_GPMC_D13 (0x1u) -#define CONTROL_PINCTRL102_MUXMODE_EHRPWM2B (0x10u) -#define CONTROL_PINCTRL102_MUXMODE_GP45 (0x40u) -#define CONTROL_PINCTRL102_MUXMODE_BTMODE13 (0x80u) - -#define CONTROL_PINCTRL103_MUXMODE_GPMC_D14 (0x1u) -#define CONTROL_PINCTRL103_MUXMODE_GP46 (0x40u) -#define CONTROL_PINCTRL103_MUXMODE_BTMODE14 (0x80u) - -#define CONTROL_PINCTRL104_MUXMODE_GPMC_D15 (0x1u) -#define CONTROL_PINCTRL104_MUXMODE_GP47 (0x40u) -#define CONTROL_PINCTRL104_MUXMODE_BTMODE15 (0x80u) - -#define CONTROL_PINCTRL105_MUXMODE_GPMC_A16 (0x1u) -#define CONTROL_PINCTRL105_MUXMODE_I2C2_SCL (0x8u) -#define CONTROL_PINCTRL105_MUXMODE_GP25 (0x80u) - -#define CONTROL_PINCTRL106_MUXMODE_GPMC_A17 (0x1u) -#define CONTROL_PINCTRL106_MUXMODE_I2C2_SDA (0x8u) -#define CONTROL_PINCTRL106_MUXMODE_GP26 (0x80u) - -#define CONTROL_PINCTRL107_MUXMODE_GPMC_A18 (0x1u) -#define CONTROL_PINCTRL107_MUXMODE_I2C3_SCL (0x8u) -#define CONTROL_PINCTRL107_MUXMODE_TIM2_IO (0x40u) -#define CONTROL_PINCTRL107_MUXMODE_GP113 (0x80u) - -#define CONTROL_PINCTRL108_MUXMODE_GPMC_A19 (0x1u) -#define CONTROL_PINCTRL108_MUXMODE_I2C3_SDA (0x8u) -#define CONTROL_PINCTRL108_MUXMODE_TIM3_IO (0x40u) -#define CONTROL_PINCTRL108_MUXMODE_GP114 (0x80u) - -#define CONTROL_PINCTRL109_MUXMODE_GPMC_A20 (0x1u) -#define CONTROL_PINCTRL109_MUXMODE_GPMC_INVA26 (0x2u) -#define CONTROL_PINCTRL109_MUXMODE_SPI2_SCS1n (0x4u) -#define CONTROL_PINCTRL109_MUXMODE_GP48 (0x40u) -#define CONTROL_PINCTRL109_MUXMODE_GP115 (0x80u) - -#define CONTROL_PINCTRL110_MUXMODE_GPMC_A21 (0x1u) -#define CONTROL_PINCTRL110_MUXMODE_GPMC_INVA27 (0x2u) -#define CONTROL_PINCTRL110_MUXMODE_SPI2_D0 (0x4u) -#define CONTROL_PINCTRL110_MUXMODE_GP116 (0x80u) - -#define CONTROL_PINCTRL111_MUXMODE_GPMC_A22 (0x1u) -#define CONTROL_PINCTRL111_MUXMODE_SPI2_D1 (0x4u) -#define CONTROL_PINCTRL111_MUXMODE_TIM4_IO (0x40u) -#define CONTROL_PINCTRL111_MUXMODE_GP117 (0x80u) - -#define CONTROL_PINCTRL112_MUXMODE_GPMC_A23 (0x1u) -#define CONTROL_PINCTRL112_MUXMODE_SPI2_SCLK (0x4u) -#define CONTROL_PINCTRL112_MUXMODE_TIM5_IO (0x40u) -#define CONTROL_PINCTRL112_MUXMODE_GP118 (0x80u) - -#define CONTROL_PINCTRL113_MUXMODE_SD2_DAT7 (0x1u) -#define CONTROL_PINCTRL113_MUXMODE_GPMC_A24 (0x2u) -#define CONTROL_PINCTRL113_MUXMODE_GPMC_A20 (0x4u) -#define CONTROL_PINCTRL113_MUXMODE_VIN1B_HSYNC (0x10u) -#define CONTROL_PINCTRL113_MUXMODE_UART2_RXD (0x20u) -#define CONTROL_PINCTRL113_MUXMODE_GP119 (0x80u) - -#define CONTROL_PINCTRL114_MUXMODE_SD2_DAT6 (0x1u) -#define CONTROL_PINCTRL114_MUXMODE_GPMC_A25 (0x2u) -#define CONTROL_PINCTRL114_MUXMODE_GPMC_A21 (0x4u) -#define CONTROL_PINCTRL114_MUXMODE_VIN1B_VSYNC (0x10u) -#define CONTROL_PINCTRL114_MUXMODE_UART2_TXD (0x20u) -#define CONTROL_PINCTRL114_MUXMODE_GP120 (0x80u) - -#define CONTROL_PINCTRL115_MUXMODE_SD2_DAT5 (0x1u) -#define CONTROL_PINCTRL115_MUXMODE_GPMC_A26 (0x2u) -#define CONTROL_PINCTRL115_MUXMODE_GPMC_A22 (0x4u) -#define CONTROL_PINCTRL115_MUXMODE_TIM6_IO (0x40u) -#define CONTROL_PINCTRL115_MUXMODE_GP121 (0x80u) - -#define CONTROL_PINCTRL116_MUXMODE_SD2_DAT4 (0x1u) -#define CONTROL_PINCTRL116_MUXMODE_GPMC_A27 (0x2u) -#define CONTROL_PINCTRL116_MUXMODE_GPMC_A23 (0x4u) -#define CONTROL_PINCTRL116_MUXMODE_GPMC_CS7n (0x8u) -#define CONTROL_PINCTRL116_MUXMODE_EDMA_EVT0 (0x20u) -#define CONTROL_PINCTRL116_MUXMODE_TIM7_IO (0x40u) -#define CONTROL_PINCTRL116_MUXMODE_GP122 (0x80u) - -#define CONTROL_PINCTRL117_MUXMODE_SD2_DAT3 (0x1u) -#define CONTROL_PINCTRL117_MUXMODE_GPMC_A1 (0x2u) -#define CONTROL_PINCTRL117_MUXMODE_GP25 (0x80u) - -#define CONTROL_PINCTRL118_MUXMODE_SD2_DAT2_SDRWn (0x1u) -#define CONTROL_PINCTRL118_MUXMODE_GPMC_A2 (0x2u) -#define CONTROL_PINCTRL118_MUXMODE_GP26 (0x80u) - -#define CONTROL_PINCTRL119_MUXMODE_SD2_DAT1_SDIRQn (0x1u) -#define CONTROL_PINCTRL119_MUXMODE_GPMC_A3 (0x2u) -#define CONTROL_PINCTRL119_MUXMODE_GP113 (0x80u) - -#define CONTROL_PINCTRL120_MUXMODE_SD2_DAT0 (0x1u) -#define CONTROL_PINCTRL120_MUXMODE_GPMC_A4 (0x2u) -#define CONTROL_PINCTRL120_MUXMODE_GP114 (0x80u) - -#define CONTROL_PINCTRL121_MUXMODE_SD2_CLK (0x1u) -#define CONTROL_PINCTRL121_MUXMODE_GP115 (0x80u) - -#define CONTROL_PINCTRL122_MUXMODE_GPMC_CS0n (0x1u) -#define CONTROL_PINCTRL122_MUXMODE_GP123 (0x80u) - -#define CONTROL_PINCTRL123_MUXMODE_GPMC_CS1n (0x1u) -#define CONTROL_PINCTRL123_MUXMODE_GPMC_A25 (0x2u) -#define CONTROL_PINCTRL123_MUXMODE_GP124 (0x80u) - -#define CONTROL_PINCTRL124_MUXMODE_GPMC_CS2n (0x1u) -#define CONTROL_PINCTRL124_MUXMODE_GPMC_A24 (0x2u) -#define CONTROL_PINCTRL124_MUXMODE_GP125 (0x80u) - -#define CONTROL_PINCTRL125_MUXMODE_GPMC_CS3n (0x1u) -#define CONTROL_PINCTRL125_MUXMODE_VIN1B_CLK (0x2u) -#define CONTROL_PINCTRL125_MUXMODE_SPI2_SCS0n (0x4u) -#define CONTROL_PINCTRL125_MUXMODE_GP126 (0x80u) - -#define CONTROL_PINCTRL126_MUXMODE_GPMC_CS4n (0x1u) -#define CONTROL_PINCTRL126_MUXMODE_SD2_CMD (0x2u) -#define CONTROL_PINCTRL126_MUXMODE_GP18 (0x80u) - -#define CONTROL_PINCTRL127_MUXMODE_GPMC_CLK (0x1u) -#define CONTROL_PINCTRL127_MUXMODE_GPMC_CS5n (0x2u) -#define CONTROL_PINCTRL127_MUXMODE_SPI2_SCLK (0x4u) -#define CONTROL_PINCTRL127_MUXMODE_GPMC_WAIT1 (0x8u) -#define CONTROL_PINCTRL127_MUXMODE_CLKOUT1 (0x10u) -#define CONTROL_PINCTRL127_MUXMODE_EDMA_EVT3 (0x20u) -#define CONTROL_PINCTRL127_MUXMODE_TIM4_IO (0x40u) -#define CONTROL_PINCTRL127_MUXMODE_GP127 (0x80u) - -#define CONTROL_PINCTRL128_MUXMODE_GPMC_ADVn_ALE (0x1u) -#define CONTROL_PINCTRL128_MUXMODE_GPMC_CS6n (0x2u) -#define CONTROL_PINCTRL128_MUXMODE_TIM5_IO (0x40u) -#define CONTROL_PINCTRL128_MUXMODE_GP128 (0x80u) - -#define CONTROL_PINCTRL129_MUXMODE_GPMC_OEn_Ren (0x1u) -#define CONTROL_PINCTRL129_MUXMODE_GP49 (0x80u) - -#define CONTROL_PINCTRL130_MUXMODE_GPMC_WEn (0x1u) -#define CONTROL_PINCTRL130_MUXMODE_GP410 (0x80u) - -#define CONTROL_PINCTRL131_MUXMODE_GPMC_BE0n_CLE (0x1u) -#define CONTROL_PINCTRL131_MUXMODE_GPMC_A25 (0x2u) -#define CONTROL_PINCTRL131_MUXMODE_EDMA_EVT2 (0x20u) -#define CONTROL_PINCTRL131_MUXMODE_TIM6_IO (0x40u) -#define CONTROL_PINCTRL131_MUXMODE_GP129 (0x80u) - -#define CONTROL_PINCTRL132_MUXMODE_GPMC_BE1n (0x1u) -#define CONTROL_PINCTRL132_MUXMODE_GPMC_A24 (0x2u) -#define CONTROL_PINCTRL132_MUXMODE_EDMA_EVT1 (0x20u) -#define CONTROL_PINCTRL132_MUXMODE_TIM7_IO (0x40u) -#define CONTROL_PINCTRL132_MUXMODE_GP130 (0x80u) - -#define CONTROL_PINCTRL133_MUXMODE_GPMC_WAIT0 (0x1u) -#define CONTROL_PINCTRL133_MUXMODE_GPMC_A26 (0x2u) -#define CONTROL_PINCTRL133_MUXMODE_EDMA_EVT0 (0x20u) -#define CONTROL_PINCTRL133_MUXMODE_GP131 (0x80u) - -#define CONTROL_PINCTRL134_MUXMODE_VIN0B_CLK (0x1u) -#define CONTROL_PINCTRL134_MUXMODE_CLKOUT0 (0x20u) -#define CONTROL_PINCTRL134_MUXMODE_GP19 (0x80u) - -#define CONTROL_PINCTRL135_MUXMODE_VIN0A_DE (0x1u) -#define CONTROL_PINCTRL135_MUXMODE_VIN0B_HSYNC (0x10u) -#define CONTROL_PINCTRL135_MUXMODE_UART5_TXD (0x20u) -#define CONTROL_PINCTRL135_MUXMODE_I2C2_SDA (0x40u) -#define CONTROL_PINCTRL135_MUXMODE_GP20 (0x80u) - -#define CONTROL_PINCTRL136_MUXMODE_VIN0A_FLD (0x1u) -#define CONTROL_PINCTRL136_MUXMODE_VIN0B_VSYNC (0x10u) -#define CONTROL_PINCTRL136_MUXMODE_UART5_RXD (0x20u) -#define CONTROL_PINCTRL136_MUXMODE_I2C2_SCL (0x40u) -#define CONTROL_PINCTRL136_MUXMODE_GP21 (0x80u) - -#define CONTROL_PINCTRL137_MUXMODE_VIN0A_CLK (0x1u) -#define CONTROL_PINCTRL137_MUXMODE_GP22 (0x80u) - -#define CONTROL_PINCTRL138_MUXMODE_VIN0A_HSYNC (0x1u) -#define CONTROL_PINCTRL138_MUXMODE_UART5_RTSn (0x20u) -#define CONTROL_PINCTRL138_MUXMODE_GP23 (0x80u) - -#define CONTROL_PINCTRL139_MUXMODE_VIN0A_VSYNC (0x1u) -#define CONTROL_PINCTRL139_MUXMODE_UART5_CTSn (0x20u) -#define CONTROL_PINCTRL139_MUXMODE_GP24 (0x80u) - -#define CONTROL_PINCTRL140_MUXMODE_VIN0A_D0 (0x1u) -#define CONTROL_PINCTRL140_MUXMODE_PR1_EDC_LATCH0_IN (0x4u) -#define CONTROL_PINCTRL140_MUXMODE_GP111 (0x80u) - -#define CONTROL_PINCTRL141_MUXMODE_VIN0A_D1 (0x1u) -#define CONTROL_PINCTRL141_MUXMODE_PR1_EDC_LATCH1_IN (0x4u) -#define CONTROL_PINCTRL141_MUXMODE_GP112 (0x80u) - -#define CONTROL_PINCTRL142_MUXMODE_VIN0A_D2 (0x1u) -#define CONTROL_PINCTRL142_MUXMODE_GP27 (0x80u) - -#define CONTROL_PINCTRL143_MUXMODE_VIN0A_D3 (0x1u) -#define CONTROL_PINCTRL143_MUXMODE_PR1_EDC_SYNC0_OUT (0x4u) -#define CONTROL_PINCTRL143_MUXMODE_GP28 (0x80u) - -#define CONTROL_PINCTRL144_MUXMODE_VIN0A_D4 (0x1u) -#define CONTROL_PINCTRL144_MUXMODE_PR1_EDC_SYNC1_OUT (0x4u) -#define CONTROL_PINCTRL144_MUXMODE_GP29 (0x80u) - -#define CONTROL_PINCTRL145_MUXMODE_VIN0A_D5 (0x1u) -#define CONTROL_PINCTRL145_MUXMODE_PR1_EDIO_SOF (0x4u) -#define CONTROL_PINCTRL145_MUXMODE_GP210 (0x80u) - -#define CONTROL_PINCTRL146_MUXMODE_VIN0A_D6 (0x1u) -#define CONTROL_PINCTRL146_MUXMODE_PR1_MDIO_MDCLK (0x4u) -#define CONTROL_PINCTRL146_MUXMODE_GP211 (0x80u) - -#define CONTROL_PINCTRL147_MUXMODE_VIN0A_D7 (0x1u) -#define CONTROL_PINCTRL147_MUXMODE_PR1_MDIO_DATA (0x4u) -#define CONTROL_PINCTRL147_MUXMODE_GP212 (0x80u) - -#define CONTROL_PINCTRL148_MUXMODE_VIN0A_D8_BD0 (0x1u) -#define CONTROL_PINCTRL148_MUXMODE_PR1_MII_MT1_CLK (0x4u) -#define CONTROL_PINCTRL148_MUXMODE_GP213 (0x80u) - -#define CONTROL_PINCTRL149_MUXMODE_VIN0A_D9_BD1 (0x1u) -#define CONTROL_PINCTRL149_MUXMODE_PR1_MII1_TXD3 (0x4u) -#define CONTROL_PINCTRL149_MUXMODE_GP214 (0x80u) - -#define CONTROL_PINCTRL150_MUXMODE_VIN0A_D10_BD2 (0x1u) -#define CONTROL_PINCTRL150_MUXMODE_PR1_MII1_TXD2 (0x4u) -#define CONTROL_PINCTRL150_MUXMODE_GP215 (0x80u) - -#define CONTROL_PINCTRL151_MUXMODE_VIN0A_D11_BD3 (0x1u) -#define CONTROL_PINCTRL151_MUXMODE_PR1_MII1_TXD1 (0x4u) -#define CONTROL_PINCTRL151_MUXMODE_GP216 (0x80u) - -#define CONTROL_PINCTRL152_MUXMODE_VIN0A_D12_BD4 (0x1u) -#define CONTROL_PINCTRL152_MUXMODE_PR1_MII1_TXD0 (0x4u) -#define CONTROL_PINCTRL152_MUXMODE_PR1_PRU1_R3116 (0x8u) -#define CONTROL_PINCTRL152_MUXMODE_UART7_RTSn (0x10u) -#define CONTROL_PINCTRL152_MUXMODE_CLKOUT1 (0x20u) -#define CONTROL_PINCTRL152_MUXMODE_PR1_PRU1_R3016 (0x40u) -#define CONTROL_PINCTRL152_MUXMODE_GP217 (0x80u) - -#define CONTROL_PINCTRL153_MUXMODE_VIN0A_D13_BD5 (0x1u) -#define CONTROL_PINCTRL153_MUXMODE_PR1_MII1_RXD3 (0x4u) -#define CONTROL_PINCTRL153_MUXMODE_PR1_PRU1_R3120 (0x8u) -#define CONTROL_PINCTRL153_MUXMODE_UART7_CTSn (0x10u) -#define CONTROL_PINCTRL153_MUXMODE_PR1_PRU1_R3020 (0x40u) -#define CONTROL_PINCTRL153_MUXMODE_GP218 (0x80u) - -#define CONTROL_PINCTRL154_MUXMODE_VIN0A_D14_BD6 (0x1u) -#define CONTROL_PINCTRL154_MUXMODE_PR1_MII1_RXD2 (0x4u) -#define CONTROL_PINCTRL154_MUXMODE_PR1_PRU1_R3119 (0x8u) -#define CONTROL_PINCTRL154_MUXMODE_UART7_RXD (0x10u) -#define CONTROL_PINCTRL154_MUXMODE_PR1_PRU1_R3019 (0x40u) -#define CONTROL_PINCTRL154_MUXMODE_GP219 (0x80u) - -#define CONTROL_PINCTRL155_MUXMODE_VIN0A_D15_BD7 (0x1u) -#define CONTROL_PINCTRL155_MUXMODE_PR1_MII1_RXD1 (0x4u) -#define CONTROL_PINCTRL155_MUXMODE_PR1_PRU1_R3118 (0x8u) -#define CONTROL_PINCTRL155_MUXMODE_UART7_TXD (0x10u) -#define CONTROL_PINCTRL155_MUXMODE_PR1_PRU1_R3018 (0x40u) -#define CONTROL_PINCTRL155_MUXMODE_GP220 (0x80u) - -#define CONTROL_PINCTRL156_MUXMODE_VIN0A_D16 (0x1u) -#define CONTROL_PINCTRL156_MUXMODE_PR1_MII1_RXD0 (0x4u) -#define CONTROL_PINCTRL156_MUXMODE_PR1_PRU1_R3117 (0x8u) -#define CONTROL_PINCTRL156_MUXMODE_I2C2_SCL (0x20u) -#define CONTROL_PINCTRL156_MUXMODE_PR1_PRU1_R3017 (0x40u) -#define CONTROL_PINCTRL156_MUXMODE_GP010 (0x80u) - -#define CONTROL_PINCTRL157_MUXMODE_VIN0A_D17 (0x1u) -#define CONTROL_PINCTRL157_MUXMODE_PR1_MII_MR1_CLK (0x4u) -#define CONTROL_PINCTRL157_MUXMODE_EMAC1_RMRXER (0x8u) -#define CONTROL_PINCTRL157_MUXMODE_GP011 (0x80u) - -#define CONTROL_PINCTRL158_MUXMODE_VIN0A_D18 (0x1u) -#define CONTROL_PINCTRL158_MUXMODE_PR1_MII1_COL (0x4u) -#define CONTROL_PINCTRL158_MUXMODE_EMAC1_RMRXD1 (0x8u) -#define CONTROL_PINCTRL158_MUXMODE_I2C3_SCL (0x20u) -#define CONTROL_PINCTRL158_MUXMODE_GP012 (0x80u) - -#define CONTROL_PINCTRL159_MUXMODE_VIN0A_D19 (0x1u) -#define CONTROL_PINCTRL159_MUXMODE_PR1_MII1_RXER (0x4u) -#define CONTROL_PINCTRL159_MUXMODE_EMAC1_RMRXD0 (0x8u) -#define CONTROL_PINCTRL159_MUXMODE_I2C3_SDA (0x20u) -#define CONTROL_PINCTRL159_MUXMODE_GP013 (0x80u) - -#define CONTROL_PINCTRL160_MUXMODE_VIN0A_D20 (0x1u) -#define CONTROL_PINCTRL160_MUXMODE_PR1_MII1_RXDV (0x4u) -#define CONTROL_PINCTRL160_MUXMODE_EMAC1_RMCRSDV (0x8u) -#define CONTROL_PINCTRL160_MUXMODE_SPI3_SCS0n (0x20u) -#define CONTROL_PINCTRL160_MUXMODE_GP014 (0x80u) - -#define CONTROL_PINCTRL161_MUXMODE_VIN0A_D21 (0x1u) -#define CONTROL_PINCTRL161_MUXMODE_PR1_MII1_TXEN (0x4u) -#define CONTROL_PINCTRL161_MUXMODE_EMAC1_RMTXD0 (0x8u) -#define CONTROL_PINCTRL161_MUXMODE_SPI3_SCLK (0x20u) -#define CONTROL_PINCTRL161_MUXMODE_GP015 (0x80u) - -#define CONTROL_PINCTRL162_MUXMODE_VIN0A_D22 (0x1u) -#define CONTROL_PINCTRL162_MUXMODE_PR1_MII1_RXLINK (0x4u) -#define CONTROL_PINCTRL162_MUXMODE_EMAC1_RMTXD1 (0x8u) -#define CONTROL_PINCTRL162_MUXMODE_SPI3_D1 (0x20u) -#define CONTROL_PINCTRL162_MUXMODE_GP016 (0x80u) - -#define CONTROL_PINCTRL163_MUXMODE_VIN0A_D23 (0x1u) -#define CONTROL_PINCTRL163_MUXMODE_PR1_MII1_CRS (0x4u) -#define CONTROL_PINCTRL163_MUXMODE_EMAC1_RMTXEN (0x8u) -#define CONTROL_PINCTRL163_MUXMODE_SPI3_D0 (0x20u) -#define CONTROL_PINCTRL163_MUXMODE_GP017 (0x80u) - -#define CONTROL_PINCTRL164_MUXMODE_VIN0A_DE (0x1u) -#define CONTROL_PINCTRL164_MUXMODE_VOUT0_VCOM (0x4u) -#define CONTROL_PINCTRL164_MUXMODE_UART6_RXD (0x10u) -#define CONTROL_PINCTRL164_MUXMODE_GP018 (0x80u) - -#define CONTROL_PINCTRL166_MUXMODE_VIN0A_FLD (0x1u) -#define CONTROL_PINCTRL166_MUXMODE_VOUT0_LOAD1 (0x4u) -#define CONTROL_PINCTRL166_MUXMODE_UART6_TXD (0x10u) -#define CONTROL_PINCTRL166_MUXMODE_GP020 (0x80u) - -#define CONTROL_PINCTRL168_MUXMODE_VOUT0_LOAD0 (0x4u) -#define CONTROL_PINCTRL168_MUXMODE_GPMC_A5 (0x10u) -#define CONTROL_PINCTRL168_MUXMODE_UART4_RXD (0x20u) -#define CONTROL_PINCTRL168_MUXMODE_GP022 (0x80u) - -#define CONTROL_PINCTRL169_MUXMODE_VOUT0_LOAD2 (0x4u) -#define CONTROL_PINCTRL169_MUXMODE_GPMC_A6 (0x10u) -#define CONTROL_PINCTRL169_MUXMODE_UART4_TXD (0x20u) -#define CONTROL_PINCTRL169_MUXMODE_GP023 (0x80u) - -#define CONTROL_PINCTRL176_MUXMODE_VOUT0_CLK (0x1u) - -#define CONTROL_PINCTRL177_MUXMODE_VOUT0_HSYNC (0x1u) -#define CONTROL_PINCTRL177_MUXMODE_GP419 (0x80u) - -#define CONTROL_PINCTRL178_MUXMODE_VOUT0_VSYNC (0x1u) -#define CONTROL_PINCTRL178_MUXMODE_VOUT0_LOAD3 (0x4u) -#define CONTROL_PINCTRL178_MUXMODE_GP420 (0x80u) - -#define CONTROL_PINCTRL179_MUXMODE_VOUT0_AVID (0x1u) -#define CONTROL_PINCTRL179_MUXMODE_VOUT0_FLD (0x2u) -#define CONTROL_PINCTRL179_MUXMODE_SPI3_SCLK (0x10u) -#define CONTROL_PINCTRL179_MUXMODE_TIM7_IO (0x40u) -#define CONTROL_PINCTRL179_MUXMODE_GP221 (0x80u) - -#define CONTROL_PINCTRL180_MUXMODE_VOUT0_B_CB_C2 (0x1u) -#define CONTROL_PINCTRL180_MUXMODE_EMU2 (0x2u) -#define CONTROL_PINCTRL180_MUXMODE_PR1_PRU1_R300 (0x8u) -#define CONTROL_PINCTRL180_MUXMODE_PR1_PRU1_R310 (0x10u) -#define CONTROL_PINCTRL180_MUXMODE_EHRPWM1A (0x20u) -#define CONTROL_PINCTRL180_MUXMODE_GP222 (0x80u) -#define CONTROL_PINCTRL180_MUXMODE_HW_DBG0 (0x400u) - -#define CONTROL_PINCTRL181_MUXMODE_VOUT0_B_CB_C3 (0x1u) -#define CONTROL_PINCTRL181_MUXMODE_CLKOUT0 (0x2u) -#define CONTROL_PINCTRL181_MUXMODE_PR1_PRU1_R301 (0x8u) -#define CONTROL_PINCTRL181_MUXMODE_PR1_PRU1_R311 (0x10u) -#define CONTROL_PINCTRL181_MUXMODE_UART6_TXD (0x40u) -#define CONTROL_PINCTRL181_MUXMODE_GP223 (0x80u) -#define CONTROL_PINCTRL181_MUXMODE_HW_DBG1 (0x400u) - -#define CONTROL_PINCTRL182_MUXMODE_VOUT0_B_CB_C4 (0x1u) -#define CONTROL_PINCTRL182_MUXMODE_PR1_PRU1_R306 (0x8u) -#define CONTROL_PINCTRL182_MUXMODE_PR1_PRU1_R316 (0x10u) -#define CONTROL_PINCTRL182_MUXMODE_EQEP2_INDEX (0x20u) -#define CONTROL_PINCTRL182_MUXMODE_GP421 (0x80u) -#define CONTROL_PINCTRL182_MUXMODE_OBS_IRQ0 (0x200u) -#define CONTROL_PINCTRL182_MUXMODE_HW_DBG2 (0x400u) - -#define CONTROL_PINCTRL183_MUXMODE_VOUT0_B_CB_C5 (0x1u) -#define CONTROL_PINCTRL183_MUXMODE_GP422 (0x80u) -#define CONTROL_PINCTRL183_MUXMODE_OBS_DMA0 (0x200u) -#define CONTROL_PINCTRL183_MUXMODE_HW_DBG3 (0x400u) - -#define CONTROL_PINCTRL184_MUXMODE_VOUT0_B_CB_C6 (0x1u) -#define CONTROL_PINCTRL184_MUXMODE_GP423 (0x80u) -#define CONTROL_PINCTRL184_MUXMODE_OBS_IRQ1 (0x200u) -#define CONTROL_PINCTRL184_MUXMODE_HW_DBG4 (0x400u) - -#define CONTROL_PINCTRL185_MUXMODE_VOUT0_B_CB_C7 (0x1u) -#define CONTROL_PINCTRL185_MUXMODE_GP424 (0x80u) -#define CONTROL_PINCTRL185_MUXMODE_OBS_DMA1 (0x200u) -#define CONTROL_PINCTRL185_MUXMODE_HW_DBG5 (0x400u) - -#define CONTROL_PINCTRL186_MUXMODE_VOUT0_B_CB_C8 (0x1u) -#define CONTROL_PINCTRL186_MUXMODE_PR1_MII_MT0_CLK (0x4u) -#define CONTROL_PINCTRL186_MUXMODE_GP425 (0x80u) -#define CONTROL_PINCTRL186_MUXMODE_HW_DBG6 (0x400u) - -#define CONTROL_PINCTRL187_MUXMODE_VOUT0_B_CB_C9 (0x1u) -#define CONTROL_PINCTRL187_MUXMODE_PR1_MII0_RXLINK (0x4u) -#define CONTROL_PINCTRL187_MUXMODE_GP426 (0x80u) -#define CONTROL_PINCTRL187_MUXMODE_HW_DBG7 (0x400u) - -#define CONTROL_PINCTRL188_MUXMODE_VOUT0_G_Y_YC2 (0x1u) -#define CONTROL_PINCTRL188_MUXMODE_EMU3 (0x2u) -#define CONTROL_PINCTRL188_MUXMODE_PR1_MII0_COL (0x4u) -#define CONTROL_PINCTRL188_MUXMODE_PR1_PRU1_R302 (0x8u) -#define CONTROL_PINCTRL188_MUXMODE_PR1_PRU1_R312 (0x10u) -#define CONTROL_PINCTRL188_MUXMODE_EHRPWM1B (0x20u) -#define CONTROL_PINCTRL188_MUXMODE_GP224 (0x80u) -#define CONTROL_PINCTRL188_MUXMODE_HW_DBG8 (0x400u) - -#define CONTROL_PINCTRL189_MUXMODE_VOUT0_G_Y_YC3 (0x1u) -#define CONTROL_PINCTRL189_MUXMODE_EQEP1_STROBE (0x2u) -#define CONTROL_PINCTRL189_MUXMODE_PR1_MII0_RXER (0x4u) -#define CONTROL_PINCTRL189_MUXMODE_PR1_PRU1_R303 (0x8u) -#define CONTROL_PINCTRL189_MUXMODE_PR1_PRU1_R313 (0x10u) -#define CONTROL_PINCTRL189_MUXMODE_EHRPWM1_TRIPZONE_INPUT (0x20u) -#define CONTROL_PINCTRL189_MUXMODE_UART6_RXD (0x40u) -#define CONTROL_PINCTRL189_MUXMODE_GP225 (0x80u) -#define CONTROL_PINCTRL189_MUXMODE_HW_DBG9 (0x400u) - -#define CONTROL_PINCTRL190_MUXMODE_VOUT0_G_Y_YC4 (0x1u) -#define CONTROL_PINCTRL190_MUXMODE_PR1_MII0_TXEN (0x4u) -#define CONTROL_PINCTRL190_MUXMODE_GP510 (0x80u) -#define CONTROL_PINCTRL190_MUXMODE_HW_DBG10 (0x400u) - -#define CONTROL_PINCTRL191_MUXMODE_VOUT0_G_Y_YC5 (0x1u) -#define CONTROL_PINCTRL191_MUXMODE_PR1_MII0_TXD3 (0x4u) -#define CONTROL_PINCTRL191_MUXMODE_GP511 (0x80u) -#define CONTROL_PINCTRL191_MUXMODE_HW_DBG11 (0x400u) - -#define CONTROL_PINCTRL192_MUXMODE_VOUT0_G_Y_YC6 (0x1u) -#define CONTROL_PINCTRL192_MUXMODE_PR1_MII0_TXD2 (0x4u) -#define CONTROL_PINCTRL192_MUXMODE_GP512 (0x80u) -#define CONTROL_PINCTRL192_MUXMODE_HW_DBG12 (0x400u) - -#define CONTROL_PINCTRL193_MUXMODE_VOUT0_G_Y_YC7 (0x1u) -#define CONTROL_PINCTRL193_MUXMODE_PR1_MII0_TXD1 (0x4u) -#define CONTROL_PINCTRL193_MUXMODE_GP513 (0x80u) -#define CONTROL_PINCTRL193_MUXMODE_HW_DBG13 (0x400u) - -#define CONTROL_PINCTRL194_MUXMODE_VOUT0_G_Y_YC8 (0x1u) -#define CONTROL_PINCTRL194_MUXMODE_PR1_MII0_TXD0 (0x4u) -#define CONTROL_PINCTRL194_MUXMODE_GP514 (0x80u) -#define CONTROL_PINCTRL194_MUXMODE_HW_DBG14 (0x400u) - -#define CONTROL_PINCTRL195_MUXMODE_VOUT0_G_Y_YC9 (0x1u) -#define CONTROL_PINCTRL195_MUXMODE_PR1_MII_MR0_CLK (0x4u) -#define CONTROL_PINCTRL195_MUXMODE_GP515 (0x80u) -#define CONTROL_PINCTRL195_MUXMODE_HW_DBG15 (0x400u) - -#define CONTROL_PINCTRL196_MUXMODE_VOUT0_R_CR2 (0x1u) -#define CONTROL_PINCTRL196_MUXMODE_EMU4 (0x2u) -#define CONTROL_PINCTRL196_MUXMODE_PR1_MII0_RXDV (0x4u) -#define CONTROL_PINCTRL196_MUXMODE_PR1_PRU1_R304 (0x8u) -#define CONTROL_PINCTRL196_MUXMODE_PR1_PRU1_R314 (0x10u) -#define CONTROL_PINCTRL196_MUXMODE_EQEP2A_IN (0x20u) -#define CONTROL_PINCTRL196_MUXMODE_UART6_CTSn (0x40u) -#define CONTROL_PINCTRL196_MUXMODE_GP226 (0x80u) -#define CONTROL_PINCTRL196_MUXMODE_HW_DBG16 (0x400u) - -#define CONTROL_PINCTRL197_MUXMODE_VOUT0_R_CR3 (0x1u) -#define CONTROL_PINCTRL197_MUXMODE_CLKOUT1 (0x2u) -#define CONTROL_PINCTRL197_MUXMODE_PR1_MII0_RXD3 (0x4u) -#define CONTROL_PINCTRL197_MUXMODE_PR1_PRU1_R305 (0x8u) -#define CONTROL_PINCTRL197_MUXMODE_PR1_PRU1_R315 (0x10u) -#define CONTROL_PINCTRL197_MUXMODE_EQEP2B_IN (0x20u) -#define CONTROL_PINCTRL197_MUXMODE_UART6_RTSn (0x40u) -#define CONTROL_PINCTRL197_MUXMODE_GP227 (0x80u) -#define CONTROL_PINCTRL197_MUXMODE_HW_DBG17 (0x400u) - -#define CONTROL_PINCTRL198_MUXMODE_VOUT0_R_CR4 (0x1u) -#define CONTROL_PINCTRL198_MUXMODE_PR1_MII0_RXD2 (0x4u) -#define CONTROL_PINCTRL198_MUXMODE_PR1_PRU1_R307 (0x8u) -#define CONTROL_PINCTRL198_MUXMODE_PR1_PRU1_R317 (0x10u) -#define CONTROL_PINCTRL198_MUXMODE_EQEP2_STROBE (0x20u) -#define CONTROL_PINCTRL198_MUXMODE_GP427 (0x80u) -#define CONTROL_PINCTRL198_MUXMODE_HW_DBG18 (0x400u) - -#define CONTROL_PINCTRL199_MUXMODE_VOUT0_R_CR5 (0x1u) -#define CONTROL_PINCTRL199_MUXMODE_PR1_MII0_RXD1 (0x4u) -#define CONTROL_PINCTRL199_MUXMODE_GP428 (0x80u) -#define CONTROL_PINCTRL199_MUXMODE_HW_DBG19 (0x400u) - -#define CONTROL_PINCTRL200_MUXMODE_VOUT0_R_CR6 (0x1u) -#define CONTROL_PINCTRL200_MUXMODE_PR1_MII0_RXD0 (0x4u) -#define CONTROL_PINCTRL200_MUXMODE_GP429 (0x80u) -#define CONTROL_PINCTRL200_MUXMODE_HW_DBG20 (0x400u) - -#define CONTROL_PINCTRL201_MUXMODE_VOUT0_R_CR7 (0x1u) -#define CONTROL_PINCTRL201_MUXMODE_PR1_MII0_CRS (0x4u) -#define CONTROL_PINCTRL201_MUXMODE_GP430 (0x80u) -#define CONTROL_PINCTRL201_MUXMODE_HW_DBG21 (0x400u) - -#define CONTROL_PINCTRL202_MUXMODE_VOUT0_R_CR8 (0x1u) -#define CONTROL_PINCTRL202_MUXMODE_PR1_MDIO_MDCLK (0x40u) -#define CONTROL_PINCTRL202_MUXMODE_GP431 (0x80u) -#define CONTROL_PINCTRL202_MUXMODE_HW_DBG22 (0x400u) - -#define CONTROL_PINCTRL203_MUXMODE_VOUT0_R_CR9 (0x1u) -#define CONTROL_PINCTRL203_MUXMODE_PR1_MDIO_DATA (0x40u) -#define CONTROL_PINCTRL203_MUXMODE_GP55 (0x80u) -#define CONTROL_PINCTRL203_MUXMODE_HW_DBG23 (0x400u) - -#define CONTROL_PINCTRL204_MUXMODE_VOUT1_CLK (0x1u) -#define CONTROL_PINCTRL204_MUXMODE_EMAC1_MTCLK (0x2u) -#define CONTROL_PINCTRL204_MUXMODE_VIN1A_HSYNC (0x4u) -#define CONTROL_PINCTRL204_MUXMODE_GP228 (0x80u) - -#define CONTROL_PINCTRL205_MUXMODE_VOUT1_HSYNC (0x1u) -#define CONTROL_PINCTRL205_MUXMODE_EMAC1_MCOL (0x2u) -#define CONTROL_PINCTRL205_MUXMODE_VIN1A_VSYNC (0x4u) -#define CONTROL_PINCTRL205_MUXMODE_SPI3_D1 (0x10u) -#define CONTROL_PINCTRL205_MUXMODE_UART3_RTSn (0x20u) -#define CONTROL_PINCTRL205_MUXMODE_VOUT1_LOAD0 (0x40u) -#define CONTROL_PINCTRL205_MUXMODE_GP229 (0x80u) - -#define CONTROL_PINCTRL206_MUXMODE_VOUT1_VSYNC (0x1u) -#define CONTROL_PINCTRL206_MUXMODE_EMAC1_MCRS (0x2u) -#define CONTROL_PINCTRL206_MUXMODE_VIN1A_FLD (0x4u) -#define CONTROL_PINCTRL206_MUXMODE_VIN1A_DE (0x8u) -#define CONTROL_PINCTRL206_MUXMODE_SPI3_D0 (0x10u) -#define CONTROL_PINCTRL206_MUXMODE_UART3_CTSn (0x20u) -#define CONTROL_PINCTRL206_MUXMODE_VOUT1_LOAD3 (0x40u) -#define CONTROL_PINCTRL206_MUXMODE_GP230 (0x80u) - -#define CONTROL_PINCTRL207_MUXMODE_VOUT1_AVID (0x1u) -#define CONTROL_PINCTRL207_MUXMODE_EMAC1_MRXER (0x2u) -#define CONTROL_PINCTRL207_MUXMODE_VIN1A_CLK (0x4u) -#define CONTROL_PINCTRL207_MUXMODE_VOUT1_VCOM (0x10u) -#define CONTROL_PINCTRL207_MUXMODE_UART4_RTSn (0x20u) -#define CONTROL_PINCTRL207_MUXMODE_TIM6_IO (0x40u) -#define CONTROL_PINCTRL207_MUXMODE_GP231 (0x80u) - -#define CONTROL_PINCTRL208_MUXMODE_VOUT1_B_CB_C3 (0x1u) -#define CONTROL_PINCTRL208_MUXMODE_EMAC1_MRCLK (0x2u) -#define CONTROL_PINCTRL208_MUXMODE_VIN1A_D0 (0x4u) -#define CONTROL_PINCTRL208_MUXMODE_PR1_UART0_CTS_N (0x8u) -#define CONTROL_PINCTRL208_MUXMODE_UART4_CTSn (0x20u) -#define CONTROL_PINCTRL208_MUXMODE_VOUT1_LOAD1 (0x40u) -#define CONTROL_PINCTRL208_MUXMODE_GP30 (0x80u) - -#define CONTROL_PINCTRL209_MUXMODE_VOUT1_B_CB_C4 (0x1u) -#define CONTROL_PINCTRL209_MUXMODE_EMAC1_MRXD0 (0x2u) -#define CONTROL_PINCTRL209_MUXMODE_VIN1A_D1 (0x4u) -#define CONTROL_PINCTRL209_MUXMODE_UART4_RXD (0x20u) -#define CONTROL_PINCTRL209_MUXMODE_GP31 (0x80u) - -#define CONTROL_PINCTRL210_MUXMODE_VOUT1_B_CB_C5 (0x1u) -#define CONTROL_PINCTRL210_MUXMODE_EMAC1_MRXD1 (0x2u) -#define CONTROL_PINCTRL210_MUXMODE_VIN1A_D2 (0x4u) -#define CONTROL_PINCTRL210_MUXMODE_UART4_TXD (0x20u) -#define CONTROL_PINCTRL210_MUXMODE_GP32 (0x80u) - -#define CONTROL_PINCTRL211_MUXMODE_VOUT1_B_CB_C6 (0x1u) -#define CONTROL_PINCTRL211_MUXMODE_EMAC1_MRXD2 (0x2u) -#define CONTROL_PINCTRL211_MUXMODE_VIN1A_D3 (0x4u) -#define CONTROL_PINCTRL211_MUXMODE_UART3_RXD (0x20u) -#define CONTROL_PINCTRL211_MUXMODE_GP33 (0x80u) - -#define CONTROL_PINCTRL212_MUXMODE_VOUT1_B_CB_C7 (0x1u) -#define CONTROL_PINCTRL212_MUXMODE_EMAC1_MRXD3 (0x2u) -#define CONTROL_PINCTRL212_MUXMODE_VIN1A_D4 (0x4u) -#define CONTROL_PINCTRL212_MUXMODE_UART3_TXD (0x20u) -#define CONTROL_PINCTRL212_MUXMODE_GP34 (0x80u) - -#define CONTROL_PINCTRL213_MUXMODE_VOUT1_B_CB_C8 (0x1u) -#define CONTROL_PINCTRL213_MUXMODE_EMAC1_MRXD4 (0x2u) -#define CONTROL_PINCTRL213_MUXMODE_VIN1A_D5 (0x4u) -#define CONTROL_PINCTRL213_MUXMODE_PR1_EDIO_DATA_OUT0 (0x10u) -#define CONTROL_PINCTRL213_MUXMODE_I2C3_SCL (0x20u) -#define CONTROL_PINCTRL213_MUXMODE_GP35 (0x80u) -#define CONTROL_PINCTRL213_MUXMODE_PR1_EDIO_DATA_IN0 (0x200u) - -#define CONTROL_PINCTRL214_MUXMODE_VOUT1_B_CB_C9 (0x1u) -#define CONTROL_PINCTRL214_MUXMODE_EMAC1_MRXD5 (0x2u) -#define CONTROL_PINCTRL214_MUXMODE_VIN1A_D6 (0x4u) -#define CONTROL_PINCTRL214_MUXMODE_PR1_EDIO_DATA_OUT1 (0x10u) -#define CONTROL_PINCTRL214_MUXMODE_I2C3_SDA (0x20u) -#define CONTROL_PINCTRL214_MUXMODE_GP36 (0x80u) -#define CONTROL_PINCTRL214_MUXMODE_PR1_EDIO_DATA_IN1 (0x200u) - -#define CONTROL_PINCTRL215_MUXMODE_VOUT1_G_Y_YC3 (0x1u) -#define CONTROL_PINCTRL215_MUXMODE_EMAC1_MRXD6 (0x2u) -#define CONTROL_PINCTRL215_MUXMODE_VIN1A_D8 (0x4u) -#define CONTROL_PINCTRL215_MUXMODE_PR1_EDIO_DATA_OUT2 (0x10u) -#define CONTROL_PINCTRL215_MUXMODE_PR1_PRU1_R308 (0x20u) -#define CONTROL_PINCTRL215_MUXMODE_PR1_PRU1_R318 (0x40u) -#define CONTROL_PINCTRL215_MUXMODE_GP37 (0x80u) -#define CONTROL_PINCTRL215_MUXMODE_PR1_EDIO_DATA_IN2 (0x200u) - -#define CONTROL_PINCTRL216_MUXMODE_VOUT1_G_Y_YC4 (0x1u) -#define CONTROL_PINCTRL216_MUXMODE_EMAC1_MRXD7 (0x2u) -#define CONTROL_PINCTRL216_MUXMODE_VIN1A_D9 (0x4u) -#define CONTROL_PINCTRL216_MUXMODE_PR1_EDIO_DATA_OUT3 (0x10u) -#define CONTROL_PINCTRL216_MUXMODE_PR1_PRU1_R309 (0x20u) -#define CONTROL_PINCTRL216_MUXMODE_PR1_PRU1_R319 (0x40u) -#define CONTROL_PINCTRL216_MUXMODE_GP38 (0x80u) -#define CONTROL_PINCTRL216_MUXMODE_PR1_EDIO_DATA_IN3 (0x200u) -#define CONTROL_PINCTRL216_MUXMODE_UART2_RXD (0x400u) - -#define CONTROL_PINCTRL217_MUXMODE_VOUT1_G_Y_YC5 (0x1u) -#define CONTROL_PINCTRL217_MUXMODE_EMAC1_MRXDV (0x2u) -#define CONTROL_PINCTRL217_MUXMODE_VIN1A_D10 (0x4u) -#define CONTROL_PINCTRL217_MUXMODE_PR1_EDIO_DATA_OUT4 (0x10u) -#define CONTROL_PINCTRL217_MUXMODE_PR1_PRU1_R3010 (0x20u) -#define CONTROL_PINCTRL217_MUXMODE_PR1_PRU1_R3110 (0x40u) -#define CONTROL_PINCTRL217_MUXMODE_GP39 (0x80u) -#define CONTROL_PINCTRL217_MUXMODE_PR1_EDIO_DATA_IN4 (0x200u) -#define CONTROL_PINCTRL217_MUXMODE_UART2_TXD (0x400u) - -#define CONTROL_PINCTRL218_MUXMODE_VOUT1_G_Y_YC6 (0x1u) -#define CONTROL_PINCTRL218_MUXMODE_EMAC1_GMTCLK (0x2u) -#define CONTROL_PINCTRL218_MUXMODE_VIN1A_D11 (0x4u) -#define CONTROL_PINCTRL218_MUXMODE_PR1_EDIO_DATA_OUT5 (0x10u) -#define CONTROL_PINCTRL218_MUXMODE_PR1_PRU1_R3011 (0x20u) -#define CONTROL_PINCTRL218_MUXMODE_PR1_PRU1_R3111 (0x40u) -#define CONTROL_PINCTRL218_MUXMODE_GP310 (0x80u) -#define CONTROL_PINCTRL218_MUXMODE_PR1_EDIO_DATA_IN5 (0x200u) -#define CONTROL_PINCTRL218_MUXMODE_UART7_RTSn (0x400u) - -#define CONTROL_PINCTRL219_MUXMODE_VOUT1_G_Y_YC7 (0x1u) -#define CONTROL_PINCTRL219_MUXMODE_EMAC1_MTXD0 (0x2u) -#define CONTROL_PINCTRL219_MUXMODE_VIN1A_D12 (0x4u) -#define CONTROL_PINCTRL219_MUXMODE_PR1_EDIO_DATA_OUT6 (0x10u) -#define CONTROL_PINCTRL219_MUXMODE_PR1_PRU1_R3012 (0x20u) -#define CONTROL_PINCTRL219_MUXMODE_PR1_PRU1_R3112 (0x40u) -#define CONTROL_PINCTRL219_MUXMODE_GP311 (0x80u) -#define CONTROL_PINCTRL219_MUXMODE_PR1_EDIO_DATA_IN6 (0x200u) -#define CONTROL_PINCTRL219_MUXMODE_UART7_CTSn (0x400u) - -#define CONTROL_PINCTRL220_MUXMODE_VOUT1_G_Y_YC8 (0x1u) -#define CONTROL_PINCTRL220_MUXMODE_EMAC1_MTXD1 (0x2u) -#define CONTROL_PINCTRL220_MUXMODE_VIN1A_D13 (0x4u) -#define CONTROL_PINCTRL220_MUXMODE_PR1_EDIO_DATA_OUT7 (0x10u) -#define CONTROL_PINCTRL220_MUXMODE_PR1_PRU1_R3013 (0x20u) -#define CONTROL_PINCTRL220_MUXMODE_PR1_PRU1_R3113 (0x40u) -#define CONTROL_PINCTRL220_MUXMODE_GP312 (0x80u) -#define CONTROL_PINCTRL220_MUXMODE_PR1_EDIO_DATA_IN7 (0x200u) -#define CONTROL_PINCTRL220_MUXMODE_UART7_RXD (0x400u) - -#define CONTROL_PINCTRL221_MUXMODE_VOUT1_G_Y_YC9 (0x1u) -#define CONTROL_PINCTRL221_MUXMODE_EMAC1_MTXD2 (0x2u) -#define CONTROL_PINCTRL221_MUXMODE_VIN1A_D14 (0x4u) -#define CONTROL_PINCTRL221_MUXMODE_PR1_EDIO_SOF (0x10u) -#define CONTROL_PINCTRL221_MUXMODE_GP313 (0x80u) -#define CONTROL_PINCTRL221_MUXMODE_PR1_UART0_CTS_N (0x200u) -#define CONTROL_PINCTRL221_MUXMODE_UART7_TXD (0x400u) - -#define CONTROL_PINCTRL222_MUXMODE_VOUT1_R_CR4 (0x1u) -#define CONTROL_PINCTRL222_MUXMODE_EMAC1_MTXD3 (0x2u) -#define CONTROL_PINCTRL222_MUXMODE_VIN1A_D15 (0x4u) -#define CONTROL_PINCTRL222_MUXMODE_PR1_EDIO_LATCH_IN (0x10u) -#define CONTROL_PINCTRL222_MUXMODE_SPI3_SCS1n (0x20u) -#define CONTROL_PINCTRL222_MUXMODE_GP314 (0x80u) -#define CONTROL_PINCTRL222_MUXMODE_PR1_UART0_RTS_N (0x200u) - -#define CONTROL_PINCTRL223_MUXMODE_VOUT1_R_CR5 (0x1u) -#define CONTROL_PINCTRL223_MUXMODE_EMAC1_MTXD4 (0x2u) -#define CONTROL_PINCTRL223_MUXMODE_VIN1A_D16 (0x4u) -#define CONTROL_PINCTRL223_MUXMODE_SPI3_SCLK (0x20u) -#define CONTROL_PINCTRL223_MUXMODE_GP315 (0x80u) -#define CONTROL_PINCTRL223_MUXMODE_PR1_UART0_RXD (0x200u) - -#define CONTROL_PINCTRL224_MUXMODE_VOUT1_R_CR6 (0x1u) -#define CONTROL_PINCTRL224_MUXMODE_EMAC1_MTXD5 (0x2u) -#define CONTROL_PINCTRL224_MUXMODE_VIN1A_D17 (0x4u) -#define CONTROL_PINCTRL224_MUXMODE_SPI3_D1 (0x20u) -#define CONTROL_PINCTRL224_MUXMODE_GP316 (0x80u) -#define CONTROL_PINCTRL224_MUXMODE_PR1_UART0_TXD (0x200u) - -#define CONTROL_PINCTRL225_MUXMODE_VOUT1_R_CR7 (0x1u) -#define CONTROL_PINCTRL225_MUXMODE_EMAC1_MTXD6 (0x2u) -#define CONTROL_PINCTRL225_MUXMODE_VIN1A_D18 (0x4u) -#define CONTROL_PINCTRL225_MUXMODE_SPI3_D0 (0x20u) -#define CONTROL_PINCTRL225_MUXMODE_GP317 (0x80u) -#define CONTROL_PINCTRL225_MUXMODE_PR1_EDC_LATCH0_IN (0x100u) -#define CONTROL_PINCTRL225_MUXMODE_TIMER4_IO (0x400u) - -#define CONTROL_PINCTRL226_MUXMODE_VOUT1_R_CR8 (0x1u) -#define CONTROL_PINCTRL226_MUXMODE_EMAC1_MTXD7 (0x2u) -#define CONTROL_PINCTRL226_MUXMODE_VIN1A_D19 (0x4u) -#define CONTROL_PINCTRL226_MUXMODE_UART5_RXD (0x20u) -#define CONTROL_PINCTRL226_MUXMODE_GP318 (0x80u) -#define CONTROL_PINCTRL226_MUXMODE_PR1_EDC_LATCH1_IN (0x100u) -#define CONTROL_PINCTRL226_MUXMODE_PR1_UART0_RTS_N (0x200u) -#define CONTROL_PINCTRL226_MUXMODE_TIMER5_IO (0x400u) - -#define CONTROL_PINCTRL227_MUXMODE_VOUT1_R_CR9 (0x1u) -#define CONTROL_PINCTRL227_MUXMODE_EMAC1_MTXEN (0x2u) -#define CONTROL_PINCTRL227_MUXMODE_VIN1A_D20 (0x4u) -#define CONTROL_PINCTRL227_MUXMODE_UART5_TXD (0x20u) -#define CONTROL_PINCTRL227_MUXMODE_GP319 (0x80u) - -#define CONTROL_PINCTRL228_MUXMODE_VOUT1_G_Y_YC2 (0x1u) -#define CONTROL_PINCTRL228_MUXMODE_GPMC_A13 (0x2u) -#define CONTROL_PINCTRL228_MUXMODE_VIN1A_D21 (0x4u) -#define CONTROL_PINCTRL228_MUXMODE_SPI2_SCS2n (0x20u) -#define CONTROL_PINCTRL228_MUXMODE_I2C2_SCL (0x40u) -#define CONTROL_PINCTRL228_MUXMODE_GP320 (0x80u) -#define CONTROL_PINCTRL228_MUXMODE_PR1_EDC_SYNC0_OUT (0x100u) -#define CONTROL_PINCTRL228_MUXMODE_PR1_UART0_RXD (0x200u) - -#define CONTROL_PINCTRL229_MUXMODE_VOUT1_R_CR3 (0x1u) -#define CONTROL_PINCTRL229_MUXMODE_GPMC_A14 (0x2u) -#define CONTROL_PINCTRL229_MUXMODE_VIN1A_D22 (0x4u) -#define CONTROL_PINCTRL229_MUXMODE_SPI2_SCLK (0x20u) -#define CONTROL_PINCTRL229_MUXMODE_I2C2_SDA (0x40u) -#define CONTROL_PINCTRL229_MUXMODE_GP321 (0x80u) -#define CONTROL_PINCTRL229_MUXMODE_PR1_EDC_SYNC1_OUT (0x100u) -#define CONTROL_PINCTRL229_MUXMODE_PR1_UART0_TXD (0x200u) - -#define CONTROL_PINCTRL230_MUXMODE_VOUT1_R_CR2 (0x1u) -#define CONTROL_PINCTRL230_MUXMODE_GPMC_A15 (0x2u) -#define CONTROL_PINCTRL230_MUXMODE_VIN1A_D23 (0x4u) -#define CONTROL_PINCTRL230_MUXMODE_SPI2_D1 (0x20u) -#define CONTROL_PINCTRL230_MUXMODE_VOUT1_LOAD2 (0x40u) -#define CONTROL_PINCTRL230_MUXMODE_GP322 (0x80u) - -#define CONTROL_PINCTRL231_MUXMODE_VOUT1_B_CB_C2 (0x1u) -#define CONTROL_PINCTRL231_MUXMODE_GPMC_A0 (0x2u) -#define CONTROL_PINCTRL231_MUXMODE_VIN1A_D7 (0x4u) -#define CONTROL_PINCTRL231_MUXMODE_SPI2_D0 (0x20u) -#define CONTROL_PINCTRL231_MUXMODE_GP330 (0x80u) - -#define CONTROL_PINCTRL232_MUXMODE_EMAC_RMREFCLK (0x1u) -#define CONTROL_PINCTRL232_MUXMODE_TIM2_IO (0x40u) -#define CONTROL_PINCTRL232_MUXMODE_GP110 (0x80u) - -#define CONTROL_PINCTRL233_MUXMODE_MDCLK (0x1u) -#define CONTROL_PINCTRL233_MUXMODE_GP111 (0x80u) - -#define CONTROL_PINCTRL234_MUXMODE_MDIO (0x1u) -#define CONTROL_PINCTRL234_MUXMODE_GP112 (0x80u) - -#define CONTROL_PINCTRL235_MUXMODE_EMAC0_MTCLK (0x1u) -#define CONTROL_PINCTRL235_MUXMODE_VIN1B_D0 (0x2u) -#define CONTROL_PINCTRL235_MUXMODE_SPI3_SCS3n (0x20u) -#define CONTROL_PINCTRL235_MUXMODE_I2C2_SDA (0x40u) -#define CONTROL_PINCTRL235_MUXMODE_GP323 (0x80u) - -#define CONTROL_PINCTRL236_MUXMODE_EMAC0_MCOL (0x1u) -#define CONTROL_PINCTRL236_MUXMODE_VIN1B_D1 (0x2u) -#define CONTROL_PINCTRL236_MUXMODE_EMAC0_RMRXD0 (0x4u) -#define CONTROL_PINCTRL236_MUXMODE_GP324 (0x80u) - -#define CONTROL_PINCTRL237_MUXMODE_EMAC0_MCRS (0x1u) -#define CONTROL_PINCTRL237_MUXMODE_VIN1B_D2 (0x2u) -#define CONTROL_PINCTRL237_MUXMODE_EMAC0_RMRXD1 (0x4u) -#define CONTROL_PINCTRL237_MUXMODE_GP325 (0x80u) - -#define CONTROL_PINCTRL238_MUXMODE_EMAC0_MRXER (0x1u) -#define CONTROL_PINCTRL238_MUXMODE_VIN1B_D3 (0x2u) -#define CONTROL_PINCTRL238_MUXMODE_EMAC0_RMRXER (0x4u) -#define CONTROL_PINCTRL238_MUXMODE_GP326 (0x80u) - -#define CONTROL_PINCTRL239_MUXMODE_EMAC0_MRCLK (0x1u) -#define CONTROL_PINCTRL239_MUXMODE_VIN1B_D4 (0x2u) -#define CONTROL_PINCTRL239_MUXMODE_EMAC0_RMCRSDV (0x4u) -#define CONTROL_PINCTRL239_MUXMODE_SPI3_SCS2n (0x20u) -#define CONTROL_PINCTRL239_MUXMODE_GP327 (0x80u) - -#define CONTROL_PINCTRL240_MUXMODE_EMAC0_MRXD0 (0x1u) -#define CONTROL_PINCTRL240_MUXMODE_VIN1B_D5 (0x2u) -#define CONTROL_PINCTRL240_MUXMODE_EMAC0_RMTXD0 (0x4u) -#define CONTROL_PINCTRL240_MUXMODE_GP328 (0x80u) - -#define CONTROL_PINCTRL241_MUXMODE_EMAC0_MRXD1 (0x1u) -#define CONTROL_PINCTRL241_MUXMODE_VIN1B_D6 (0x2u) -#define CONTROL_PINCTRL241_MUXMODE_EMAC0_RMTXD1 (0x4u) -#define CONTROL_PINCTRL241_MUXMODE_GP329 (0x80u) - -#define CONTROL_PINCTRL242_MUXMODE_EMAC0_MRXD2 (0x1u) -#define CONTROL_PINCTRL242_MUXMODE_VIN1B_D7 (0x2u) -#define CONTROL_PINCTRL242_MUXMODE_EMAC0_RMTXEN (0x4u) -#define CONTROL_PINCTRL242_MUXMODE_GP330 (0x80u) - -#define CONTROL_PINCTRL243_MUXMODE_EMAC0_MRXD3 (0x1u) -#define CONTROL_PINCTRL243_MUXMODE_GPMC_A27 (0x4u) -#define CONTROL_PINCTRL243_MUXMODE_GPMC_A26 (0x8u) -#define CONTROL_PINCTRL243_MUXMODE_GPMC_A0 (0x10u) -#define CONTROL_PINCTRL243_MUXMODE_UART5_RXD (0x20u) -#define CONTROL_PINCTRL243_MUXMODE_GP516 (0x80u) - -#define CONTROL_PINCTRL244_MUXMODE_EMAC0_MRXD4 (0x1u) -#define CONTROL_PINCTRL244_MUXMODE_GPMC_A1 (0x10u) -#define CONTROL_PINCTRL244_MUXMODE_UART5_TXD (0x20u) -#define CONTROL_PINCTRL244_MUXMODE_GP517 (0x80u) - -#define CONTROL_PINCTRL245_MUXMODE_EMAC0_MRXD5 (0x1u) -#define CONTROL_PINCTRL245_MUXMODE_GPMC_A2 (0x10u) -#define CONTROL_PINCTRL245_MUXMODE_UART5_CTSn (0x20u) -#define CONTROL_PINCTRL245_MUXMODE_GP518 (0x80u) - -#define CONTROL_PINCTRL246_MUXMODE_EMAC0_MRXD6 (0x1u) -#define CONTROL_PINCTRL246_MUXMODE_GPMC_A3 (0x10u) -#define CONTROL_PINCTRL246_MUXMODE_UART5_RTSn (0x20u) -#define CONTROL_PINCTRL246_MUXMODE_GP519 (0x80u) - -#define CONTROL_PINCTRL247_MUXMODE_EMAC0_MRXD7 (0x1u) -#define CONTROL_PINCTRL247_MUXMODE_GPMC_A4 (0x10u) -#define CONTROL_PINCTRL247_MUXMODE_SPI2_SCS3n (0x20u) -#define CONTROL_PINCTRL247_MUXMODE_GP520 (0x80u) - -#define CONTROL_PINCTRL248_MUXMODE_EMAC0_MRXDV (0x1u) -#define CONTROL_PINCTRL248_MUXMODE_GPMC_A5 (0x10u) -#define CONTROL_PINCTRL248_MUXMODE_SPI2_SCLK (0x20u) -#define CONTROL_PINCTRL248_MUXMODE_GP521 (0x80u) - -#define CONTROL_PINCTRL249_MUXMODE_EMAC0_GMTCLK (0x1u) -#define CONTROL_PINCTRL249_MUXMODE_GPMC_A6 (0x10u) -#define CONTROL_PINCTRL249_MUXMODE_SPI2_D1 (0x20u) -#define CONTROL_PINCTRL249_MUXMODE_GP522 (0x80u) - -#define CONTROL_PINCTRL250_MUXMODE_EMAC0_MTXD0 (0x1u) -#define CONTROL_PINCTRL250_MUXMODE_GPMC_A7 (0x10u) -#define CONTROL_PINCTRL250_MUXMODE_SPI2_D0 (0x20u) -#define CONTROL_PINCTRL250_MUXMODE_GP523 (0x80u) - -#define CONTROL_PINCTRL251_MUXMODE_EMAC0_MTXD1 (0x1u) -#define CONTROL_PINCTRL251_MUXMODE_GPMC_A8 (0x10u) -#define CONTROL_PINCTRL251_MUXMODE_UART4_RXD (0x20u) -#define CONTROL_PINCTRL251_MUXMODE_GP524 (0x80u) - -#define CONTROL_PINCTRL252_MUXMODE_EMAC0_MTXD2 (0x1u) -#define CONTROL_PINCTRL252_MUXMODE_EMAC1_RMRXD0 (0x2u) -#define CONTROL_PINCTRL252_MUXMODE_GPMC_A9 (0x10u) -#define CONTROL_PINCTRL252_MUXMODE_UART4_TXD (0x20u) -#define CONTROL_PINCTRL252_MUXMODE_EHRPWM2A (0x40u) -#define CONTROL_PINCTRL252_MUXMODE_GP525 (0x80u) - -#define CONTROL_PINCTRL253_MUXMODE_EMAC0_MTXD3 (0x1u) -#define CONTROL_PINCTRL253_MUXMODE_EMAC1_RMRXD1 (0x2u) -#define CONTROL_PINCTRL253_MUXMODE_GPMC_A10 (0x10u) -#define CONTROL_PINCTRL253_MUXMODE_UART4_CTSn (0x20u) -#define CONTROL_PINCTRL253_MUXMODE_EHRPWM2B (0x40u) -#define CONTROL_PINCTRL253_MUXMODE_GP526 (0x80u) - -#define CONTROL_PINCTRL254_MUXMODE_EMAC0_MTXD4 (0x1u) -#define CONTROL_PINCTRL254_MUXMODE_EMAC1_RMRXER (0x2u) -#define CONTROL_PINCTRL254_MUXMODE_GPMC_A11 (0x10u) -#define CONTROL_PINCTRL254_MUXMODE_UART4_RTSn (0x20u) -#define CONTROL_PINCTRL254_MUXMODE_EHRPWM2_TRIPZONE_INPUT (0x40u) -#define CONTROL_PINCTRL254_MUXMODE_GP527 (0x80u) - -#define CONTROL_PINCTRL255_MUXMODE_EMAC0_MTXD5 (0x1u) -#define CONTROL_PINCTRL255_MUXMODE_EMAC1_RMCRSDV (0x2u) -#define CONTROL_PINCTRL255_MUXMODE_GPMC_A12 (0x10u) -#define CONTROL_PINCTRL255_MUXMODE_UART1_RXD (0x20u) -#define CONTROL_PINCTRL255_MUXMODE_GP528 (0x80u) - -#define CONTROL_PINCTRL256_MUXMODE_EMAC0_MTXD6 (0x1u) -#define CONTROL_PINCTRL256_MUXMODE_EMAC1_RMTXD0 (0x2u) -#define CONTROL_PINCTRL256_MUXMODE_GPMC_A13 (0x10u) -#define CONTROL_PINCTRL256_MUXMODE_UART1_TXD (0x20u) -#define CONTROL_PINCTRL256_MUXMODE_EQEP1A_IN (0x40u) -#define CONTROL_PINCTRL256_MUXMODE_GP529 (0x80u) - -#define CONTROL_PINCTRL257_MUXMODE_EMAC0_MTXD7 (0x1u) -#define CONTROL_PINCTRL257_MUXMODE_EMAC1_RMTXD1 (0x2u) -#define CONTROL_PINCTRL257_MUXMODE_GPMC_A14 (0x10u) -#define CONTROL_PINCTRL257_MUXMODE_UART1_CTSn (0x20u) -#define CONTROL_PINCTRL257_MUXMODE_EQEP1B_IN (0x40u) -#define CONTROL_PINCTRL257_MUXMODE_GP530 (0x80u) - -#define CONTROL_PINCTRL258_MUXMODE_EMAC0_MTXEN (0x1u) -#define CONTROL_PINCTRL258_MUXMODE_EMAC1_RMTXEN (0x2u) -#define CONTROL_PINCTRL258_MUXMODE_GPMC_A15 (0x10u) -#define CONTROL_PINCTRL258_MUXMODE_UART1_RTSn (0x20u) -#define CONTROL_PINCTRL258_MUXMODE_EQEP1_INDEX (0x40u) -#define CONTROL_PINCTRL258_MUXMODE_GP531 (0x80u) - -#define CONTROL_PINCTRL260_MUXMODE_RESETn (0x1u) - -#define CONTROL_PINCTRL261_MUXMODE_NMIn (0x1u) - -#define CONTROL_PINCTRL262_MUXMODE_RSTOUT_WD_OUTn (0x1u) - -#define CONTROL_PINCTRL263_MUXMODE_I2C0_SCL (0x1u) - -#define CONTROL_PINCTRL264_MUXMODE_I2C0_SDA (0x1u) - -#define CONTROL_PINCTRL270_MUXMODE_USB0_DRVVBUS (0x1u) -#define CONTROL_PINCTRL270_MUXMODE_GP07 (0x2u) - -/** @brief CQDETECT_STATUS register fields */ -#define CONTROL_CQDETECT_STATUS_CQERR_GEMAC_A (0x00000800u) -#define CONTROL_CQDETECT_STATUS_CQERR_GEMAC_A_SHIFT (0x0000000Bu) - -#define CONTROL_CQDETECT_STATUS_CQERR_GEMAC_B (0x00001000u) -#define CONTROL_CQDETECT_STATUS_CQERR_GEMAC_B_SHIFT (0x0000000Cu) - -#define CONTROL_CQDETECT_STATUS_CQERR_GENERAL (0x00002000u) -#define CONTROL_CQDETECT_STATUS_CQERR_GENERAL_SHIFT (0x0000000Du) - -#define CONTROL_CQDETECT_STATUS_CQERR_GPMC (0x00000100u) -#define CONTROL_CQDETECT_STATUS_CQERR_GPMC_SHIFT (0x00000008u) - -#define CONTROL_CQDETECT_STATUS_CQERR_MMCSD_A (0x00000200u) -#define CONTROL_CQDETECT_STATUS_CQERR_MMCSD_A_SHIFT (0x00000009u) - -#define CONTROL_CQDETECT_STATUS_CQERR_MMCSD_B (0x00000400u) -#define CONTROL_CQDETECT_STATUS_CQERR_MMCSD_B_SHIFT (0x0000000Au) - -#define CONTROL_CQDETECT_STATUS_CQMODE_GEMAC_A (0x00080000u) -#define CONTROL_CQDETECT_STATUS_CQMODE_GEMAC_A_SHIFT (0x00000013u) - -#define CONTROL_CQDETECT_STATUS_CQMODE_GEMAC_B (0x00100000u) -#define CONTROL_CQDETECT_STATUS_CQMODE_GEMAC_B_SHIFT (0x00000014u) - -#define CONTROL_CQDETECT_STATUS_CQMODE_GENERAL (0x00200000u) -#define CONTROL_CQDETECT_STATUS_CQMODE_GENERAL_SHIFT (0x00000015u) - -#define CONTROL_CQDETECT_STATUS_CQMODE_GPMC (0x00010000u) -#define CONTROL_CQDETECT_STATUS_CQMODE_GPMC_SHIFT (0x00000010u) - -#define CONTROL_CQDETECT_STATUS_CQMODE_MMCSD_A (0x00020000u) -#define CONTROL_CQDETECT_STATUS_CQMODE_MMCSD_A_SHIFT (0x00000011u) - -#define CONTROL_CQDETECT_STATUS_CQMODE_MMCSD_B (0x00040000u) -#define CONTROL_CQDETECT_STATUS_CQMODE_MMCSD_B_SHIFT (0x00000012u) - -#define CONTROL_CQDETECT_STATUS_CQSTAT_GEMAC_A (0x00000008u) -#define CONTROL_CQDETECT_STATUS_CQSTAT_GEMAC_A_SHIFT (0x00000003u) - -#define CONTROL_CQDETECT_STATUS_CQSTAT_GEMAC_B (0x00000010u) -#define CONTROL_CQDETECT_STATUS_CQSTAT_GEMAC_B_SHIFT (0x00000004u) - -#define CONTROL_CQDETECT_STATUS_CQSTAT_GENERAL (0x00000020u) -#define CONTROL_CQDETECT_STATUS_CQSTAT_GENERAL_SHIFT (0x00000005u) - -#define CONTROL_CQDETECT_STATUS_CQSTAT_GPMC (0x00000001u) -#define CONTROL_CQDETECT_STATUS_CQSTAT_GPMC_SHIFT (0x00000000u) - -#define CONTROL_CQDETECT_STATUS_CQSTAT_MMCSD_A (0x00000002u) -#define CONTROL_CQDETECT_STATUS_CQSTAT_MMCSD_A_SHIFT (0x00000001u) - -#define CONTROL_CQDETECT_STATUS_CQSTAT_MMCSD_B (0x00000004u) -#define CONTROL_CQDETECT_STATUS_CQSTAT_MMCSD_B_SHIFT (0x00000002u) - -/** @brief DDR_IO_CTRL register fields */ -#define CONTROL_DDR_IO_CTRL_DDR3_RST_DEF_VAL (0x80000000u) -#define CONTROL_DDR_IO_CTRL_DDR3_RST_DEF_VAL_SHIFT (0x0000001Fu) - -#define CONTROL_DDR_IO_CTRL_DDR_WUCLK_DISABLE (0x40000000u) -#define CONTROL_DDR_IO_CTRL_DDR_WUCLK_DISABLE_SHIFT (0x0000001Eu) - -#define CONTROL_DDR_IO_CTRL_MDDR_SEL (0x10000000u) -#define CONTROL_DDR_IO_CTRL_MDDR_SEL_SHIFT (0x0000001Cu) - -/** @brief VTP_CTRL register fields */ -#define CONTROL_VTP_CTRL_CLRZ (0x00000001u) -#define CONTROL_VTP_CTRL_CLRZ_SHIFT (0x00000000u) - -#define CONTROL_VTP_CTRL_ENABLE (0x00000040u) -#define CONTROL_VTP_CTRL_ENABLE_SHIFT (0x00000006u) - -#define CONTROL_VTP_CTRL_FILTER (0x0000000Eu) -#define CONTROL_VTP_CTRL_FILTER_SHIFT (0x00000001u) - -#define CONTROL_VTP_CTRL_LOCK (0x00000010u) -#define CONTROL_VTP_CTRL_LOCK_SHIFT (0x00000004u) - -#define CONTROL_VTP_CTRL_NCIN (0x00007F00u) -#define CONTROL_VTP_CTRL_NCIN_SHIFT (0x00000008u) - -#define CONTROL_VTP_CTRL_PCIN (0x007F0000u) -#define CONTROL_VTP_CTRL_PCIN_SHIFT (0x00000010u) - -#define CONTROL_VTP_CTRL_READY (0x00000020u) -#define CONTROL_VTP_CTRL_READY_SHIFT (0x00000005u) - -/** @brief VREF_CTRL register fields */ -#define CONTROL_VREF_CTRL_DDR_VREF_CCAP (0x00000018u) -#define CONTROL_VREF_CTRL_DDR_VREF_CCAP_SHIFT (0x00000003u) - -#define CONTROL_VREF_CTRL_DDR_VREF_EN (0x00000001u) -#define CONTROL_VREF_CTRL_DDR_VREF_EN_SHIFT (0x00000000u) - -#define CONTROL_VREF_CTRL_DDR_VREF_TAP (0x00000006u) -#define CONTROL_VREF_CTRL_DDR_VREF_TAP_SHIFT (0x00000001u) - -/** @brief CONTROL_MLBP_SIG_IO_CTRL register fields */ -#define CONTROL_MLBP_SIG_IO_CTRL_NC_IN (0x003F0000u) -#define CONTROL_MLBP_SIG_IO_CTRL_NC_IN_SHIFT (0x10u) - -#define CONTROL_MLBP_SIG_IO_CTRL_PC_IN (0x00003F00u) -#define CONTROL_MLBP_SIG_IO_CTRL_PC_IN_SHIFT (0x8u) - -#define CONTROL_MLBP_SIG_IO_CTRL_PWRDNRX (0x00000020u) -#define CONTROL_MLBP_SIG_IO_CTRL_PWRDNRX_SHIFT (0x5u) - -#define CONTROL_MLBP_SIG_IO_CTRL_PWRDNTX (0x00000010u) -#define CONTROL_MLBP_SIG_IO_CTRL_PWRDNTX_SHIFT (0x4u) - -#define CONTROL_MLBP_SIG_IO_CTRL_EN_EXT_RES (0x00000008u) -#define CONTROL_MLBP_SIG_IO_CTRL_EN_EXT_RES_SHIFT (0x3u) - -#define CONTROL_MLBP_SIG_IO_CTRL_ENLVCMOS (0x00000004u) -#define CONTROL_MLBP_SIG_IO_CTRL_ENLVCMOS_SHIFT (0x2u) - -#define CONTROL_MLBP_SIG_IO_CTRL_ENN (0x00000002u) -#define CONTROL_MLBP_SIG_IO_CTRL_ENN_SHIFT (0x1u) - -#define CONTROL_MLBP_SIG_IO_CTRL_ENP (0x00000001u) -#define CONTROL_MLBP_SIG_IO_CTRL_ENP_SHIFT (0x0u) - -/** @brief CONTROL_MLBP_DAT_IO_CTRL register fields */ -#define CONTROL_MLBP_DAT_IO_CTRL_NC_IN (0x003F0000u) -#define CONTROL_MLBP_DAT_IO_CTRL_NC_IN_SHIFT (0x10u) - -#define CONTROL_MLBP_DAT_IO_CTRL_PC_IN (0x00003F00u) -#define CONTROL_MLBP_DAT_IO_CTRL_PC_IN_SHIFT (0x8u) - -#define CONTROL_MLBP_DAT_IO_CTRL_PWRDNRX (0x00000020u) -#define CONTROL_MLBP_DAT_IO_CTRL_PWRDNRX_SHIFT (0x5u) - -#define CONTROL_MLBP_DAT_IO_CTRL_PWRDNTX (0x00000010u) -#define CONTROL_MLBP_DAT_IO_CTRL_PWRDNTX_SHIFT (0x4u) - -#define CONTROL_MLBP_DAT_IO_CTRL_EN_EXT_RES (0x00000008u) -#define CONTROL_MLBP_DAT_IO_CTRL_EN_EXT_RES_SHIFT (0x3u) - -#define CONTROL_MLBP_DAT_IO_CTRL_ENLVCMOS (0x00000004u) -#define CONTROL_MLBP_DAT_IO_CTRL_ENLVCMOS_SHIFT (0x2u) - -#define CONTROL_MLBP_DAT_IO_CTRL_ENN (0x00000002u) -#define CONTROL_MLBP_DAT_IO_CTRL_ENN_SHIFT (0x1u) - -#define CONTROL_MLBP_DAT_IO_CTRL_ENP (0x00000001u) -#define CONTROL_MLBP_DAT_IO_CTRL_ENP_SHIFT (0x0u) - -/** @brief CONTROL_MLBP_CLK_BG_CTRL register fields */ -#define CONTROL_MLBP_CLK_BG_CTRL_BG_TRIM (0x000000FCu) -#define CONTROL_MLBP_CLK_BG_CTRL_BG_TRIM_SHIFT (0x2u) - -#define CONTROL_MLBP_CLK_BG_CTRL_BG_PWRDN (0x00000002u) -#define CONTROL_MLBP_CLK_BG_CTRL_BG_PWRDN_SHIFT (0x1u) - -#define CONTROL_MLBP_CLK_BG_CTRL_CLK_PWRDN (0x00000001u) -#define CONTROL_MLBP_CLK_BG_CTRL_CLK_PWRDN_SHIFT (0x0u) - -/** @brief SERDES_REFCLK_CTL register fields */ -#define CONTROL_SERDES_REFCLK_CTL_PWRDN (0x00000001u) -#define CONTROL_SERDES_REFCLK_CTL_PWRDN_SHIFT (0x00000000u) - -#define CONTROL_SERDES_REFCLK_CTL_PWRDN_SE (0x00000002u) -#define CONTROL_SERDES_REFCLK_CTL_PWRDN_SE_SHIFT (0x00000001u) - -/** @brief CONTROL_DSP_INT_MUX(n) register fields */ -/* TBD */ - -/** @brief CONTROL_DUCATI_INT_MUX(n) register fields */ -/* TBD */ - -/** @brief CONTROL_TPCC_EVT_MUX(n) register fields */ -/* TBD */ - -/** @brief TIMER_EVT_CAPT register fields */ -#define CONTROL_TIMER_EVT_CAPT_TIMER5_EVTCAPT (0x0000001Fu) -#define CONTROL_TIMER_EVT_CAPT_TIMER5_EVTCAPT_SHIFT (0x00000000u) - -#define CONTROL_TIMER_EVT_CAPT_TIMER6_EVTCAPT (0x00001F00u) -#define CONTROL_TIMER_EVT_CAPT_TIMER6_EVTCAPT_SHIFT (0x00000008u) - -#define CONTROL_TIMER_EVT_CAPT_TIMER7_EVTCAPT (0x001F0000u) -#define CONTROL_TIMER_EVT_CAPT_TIMER7_EVTCAPT_SHIFT (0x00000010u) - -/** @brief CONTROL_GPIO_MUX register fields */ -#define CONTROL_GPIO_MUX_GPIO1_5_MUX (0x00000020u) -#define CONTROL_GPIO_MUX_GPIO1_5_MUX_SHIFT (0x5u) - -#define CONTROL_GPIO_MUX_GPIO1_4_MUX (0x00000010u) -#define CONTROL_GPIO_MUX_GPIO1_4_MUX_SHIFT (0x4u) - -#define CONTROL_GPIO_MUX_GPIO1_3_MUX (0x00000008u) -#define CONTROL_GPIO_MUX_GPIO1_3_MUX_SHIFT (0x3u) - -#define CONTROL_GPIO_MUX_GPIO1_2_MUX (0x00000004u) -#define CONTROL_GPIO_MUX_GPIO1_2_MUX_SHIFT (0x2u) - -#define CONTROL_GPIO_MUX_GPIO1_1_MUX (0x00000002u) -#define CONTROL_GPIO_MUX_GPIO1_1_MUX_SHIFT (0x1u) - -#define CONTROL_GPIO_MUX_GPIO1_0_MUX (0x00000001u) -#define CONTROL_GPIO_MUX_GPIO1_0_MUX_SHIFT (0x0u) - -/** @brief ECAP_EVT_CAPT register fields */ -#define CONTROL_ECAP_EVT_CAPT_ECAP0_EVTCAPT (0x0000001Fu) -#define CONTROL_ECAP_EVT_CAPT_ECAP0_EVTCAPT_SHIFT (0x00000000u) - -#define CONTROL_ECAP_EVT_CAPT_ECAP1_EVTCAPT (0x00001F00u) -#define CONTROL_ECAP_EVT_CAPT_ECAP1_EVTCAPT_SHIFT (0x00000008u) - -#define CONTROL_ECAP_EVT_CAPT_ECAP2_EVTCAPT (0x001F0000u) -#define CONTROL_ECAP_EVT_CAPT_ECAP2_EVTCAPT_SHIFT (0x00000010u) - -/** @brief ADC_EVT_CAPT register fields */ -#define CONTROL_ADC_EVT_CAPT_ADC_EVTCAPT (0x0000000Fu) -#define CONTROL_ADC_EVT_CAPT_ADC_EVTCAPT_SHIFT (0x00000000u) - -/** @brief RESET_ISO register fields */ -#define CONTROL_RESET_ISO_ISO_CONTROL (0x00000001u) -#define CONTROL_RESET_ISO_ISO_CONTROL_SHIFT (0x00000000u) - -/** @brief CONTROL_DAC_TRIM(n) register fields */ -#define CONTROL_DAC_TRIM_TRIM (0xFFFFFFFFu) -#define CONTROL_DAC_TRIM_TRIM_SHIFT (0x0u) - -/** @brief SMA0 register fields */ -#define CONTROL_SMA0_SMA0 (0xFFFFFFFFu) -#define CONTROL_SMA0_SMA0_SHIFT (0x00000000u) - -/** @brief SMA2 register fields */ -#define CONTROL_SMA2_SMA2 (0xFFFFFFFFu) -#define CONTROL_SMA2_SMA2_SHIFT (0x00000000u) - -/** @brief CONTROL_RTC_IDLE register fields */ -#define CONTROL_RTC_IDLE_SIDLE_ACK (0x00000006u) -#define CONTROL_RTC_IDLE_SIDLE_ACK_SHIFT (0x1u) - -#define CONTROL_RTC_IDLE_SIDLE_REQ (0x00000001u) -#define CONTROL_RTC_IDLE_SIDLE_REQ_SHIFT (0x0u) - -/** @brief CONTROL_ARM_INT_MUX(n) register fields */ -/* TBD */ - -/** @brief CONTROL_INITIATOR_PRIO(n) register fields */ -#define CONTROL_INITIATOR_PRIO0_GEM_MDMA (0x07000000u) -#define CONTROL_INITIATOR_PRIO0_GEM_MDMA_SHIFT (0x18u) - -#define CONTROL_INITIATOR_PRIO0_GEM_CFG (0x00700000u) -#define CONTROL_INITIATOR_PRIO0_GEM_CFG_SHIFT (0x14u) - -#define CONTROL_INITIATOR_PRIO0_SYS_MMU (0x00070000u) -#define CONTROL_INITIATOR_PRIO0_SYS_MMU_SHIFT (0x10u) - -#define CONTROL_INITIATOR_PRIO0_SGX530 (0x00007000u) -#define CONTROL_INITIATOR_PRIO0_SGX530_SHIFT (0xCu) - -#define CONTROL_INITIATOR_PRIO0_BitBlt_MMU (0x00000700u) -#define CONTROL_INITIATOR_PRIO0_BitBlt_MMU_SHIFT (0x8u) - -#define CONTROL_INITIATOR_PRIO0_HOST_ARM1 (0x00000070u) -#define CONTROL_INITIATOR_PRIO0_HOST_ARM1_SHIFT (0x4u) - -#define CONTROL_INITIATOR_PRIO0_HOST_ARM0 (0x00000007u) -#define CONTROL_INITIATOR_PRIO0_HOST_ARM0_SHIFT (0x0u) - -#define CONTROL_INITIATOR_PRIO1_TCWR3 (0x70000000u) -#define CONTROL_INITIATOR_PRIO1_TCWR3_SHIFT (0x1Cu) - -#define CONTROL_INITIATOR_PRIO1_TCRD3 (0x07000000u) -#define CONTROL_INITIATOR_PRIO1_TCRD3_SHIFT (0x18u) - -#define CONTROL_INITIATOR_PRIO1_TCWR2 (0x00700000u) -#define CONTROL_INITIATOR_PRIO1_TCWR2_SHIFT (0x14u) - -#define CONTROL_INITIATOR_PRIO1_TCRD2 (0x00070000u) -#define CONTROL_INITIATOR_PRIO1_TCRD2_SHIFT (0x10u) - -#define CONTROL_INITIATOR_PRIO1_TCWR1 (0x00007000u) -#define CONTROL_INITIATOR_PRIO1_TCWR1_SHIFT (0xCu) - -#define CONTROL_INITIATOR_PRIO1_TCRD1 (0x00000700u) -#define CONTROL_INITIATOR_PRIO1_TCRD1_SHIFT (0x8u) - -#define CONTROL_INITIATOR_PRIO1_TCWR0 (0x00000070u) -#define CONTROL_INITIATOR_PRIO1_TCWR0_SHIFT (0x4u) - -#define CONTROL_INITIATOR_PRIO1_TCRD0 (0x00000007u) -#define CONTROL_INITIATOR_PRIO1_TCRD0_SHIFT (0x0u) - -#define CONTROL_INITIATOR_PRIO2_DEBUG (0x07000000u) -#define CONTROL_INITIATOR_PRIO2_DEBUG_SHIFT (0x18u) - -#define CONTROL_INITIATOR_PRIO2_3PGSW (0x00700000u) -#define CONTROL_INITIATOR_PRIO2_3PGSW_SHIFT (0x14u) - -#define CONTROL_INITIATOR_PRIO2_SECSS (0x00070000u) -#define CONTROL_INITIATOR_PRIO2_SECSS_SHIFT (0x10u) - -#define CONTROL_INITIATOR_PRIO2_PCIe (0x00007000u) -#define CONTROL_INITIATOR_PRIO2_PCIe_SHIFT (0xCu) - -#define CONTROL_INITIATOR_PRIO2_ISS (0x00000700u) -#define CONTROL_INITIATOR_PRIO2_ISS_SHIFT (0x8u) - -#define CONTROL_INITIATOR_PRIO3_PRUSS1 (0x00000070u) -#define CONTROL_INITIATOR_PRIO3_PRUSS1_SHIFT (0x4u) - -#define CONTROL_INITIATOR_PRIO3_PRUSS0 (0x00000007u) -#define CONTROL_INITIATOR_PRIO3_PRUSS0_SHIFT (0x0u) - -#define CONTROL_INITIATOR_PRIO4_P1500 (0x00007000u) -#define CONTROL_INITIATOR_PRIO4_P1500_SHIFT (0xCu) - -#define CONTROL_INITIATOR_PRIO4_MLB (0x00000700u) -#define CONTROL_INITIATOR_PRIO4_MLB_SHIFT (0x8u) - -#define CONTROL_INITIATOR_PRIO4_USB1 (0x00000070u) -#define CONTROL_INITIATOR_PRIO4_USB1_SHIFT (0x4u) - -#define CONTROL_INITIATOR_PRIO4_USB0 (0x00000007u) -#define CONTROL_INITIATOR_PRIO4_USB0_SHIFT (0x0u) - -/** @brief CONTROL_DMAOBS register fields */ -#define CONTROL_DMAOBS_DMAOBS2_EN (0x80000000u) -#define CONTROL_DMAOBS_DMAOBS2_EN_SHIFT (0x1Fu) - -#define CONTROL_DMAOBS_DMAOBS2_SEL (0x00FF0000u) -#define CONTROL_DMAOBS_DMAOBS2_SEL_SHIFT (0x10u) - -#define CONTROL_DMAOBS_DMAOBS1_EN (0x00008000u) -#define CONTROL_DMAOBS_DMAOBS1_EN_SHIFT (0xFu) - -#define CONTROL_DMAOBS_DMAOBS1_SEL (0x000000FFu) -#define CONTROL_DMAOBS_DMAOBS1_SEL_SHIFT (0x0u) - -/** @brief CONTROL_INTOBS register fields */ -#define CONTROL_INTOBS_INTOBS2_EN (0x80000000u) -#define CONTROL_INTOBS_INTOBS2_EN_SHIFT (0x1Fu) - -#define CONTROL_INTOBS_INTOBS2_SEL (0x00FF0000u) -#define CONTROL_INTOBS_INTOBS2_SEL_SHIFT (0x10u) - -#define CONTROL_INTOBS_INTOBS1_EN (0x00008000u) -#define CONTROL_INTOBS_INTOBS1_EN_SHIFT (0xFu) - -#define CONTROL_INTOBS_INTOBS1_SEL (0x000000FFu) -#define CONTROL_INTOBS_INTOBS1_SEL_SHIFT (0x0u) - -/** @brief CONTROL_DTC_CTRL(n) register fields */ -#define CONTROL_DTC_CTRL_DTC_RESET (0x40000000u) -#define CONTROL_DTC_CTRL_DTC_RESET_SHIFT (0x1Eu) - -#define CONTROL_DTC_CTRL_PCLK_INV (0x00010000u) -#define CONTROL_DTC_CTRL_PCLK_INV_SHIFT (0x10u) - -#define CONTROL_DTC_CTRL_TCON_LOAD3_POL (0x00008000u) -#define CONTROL_DTC_CTRL_TCON_LOAD3_POL_SHIFT (0xFu) - -#define CONTROL_DTC_CTRL_TCON_LOAD2_POL (0x00004000u) -#define CONTROL_DTC_CTRL_TCON_LOAD2_POL_SHIFT (0xEu) - -#define CONTROL_DTC_CTRL_TCON_LOAD1_POL (0x00002000u) -#define CONTROL_DTC_CTRL_TCON_LOAD1_POL_SHIFT (0xDu) - -#define CONTROL_DTC_CTRL_TCON_LOAD0_POL (0x00001000u) -#define CONTROL_DTC_CTRL_TCON_LOAD0_POL_SHIFT (0xCu) - -#define CONTROL_DTC_CTRL_TCON_VCOM_ALT (0x00000400u) -#define CONTROL_DTC_CTRL_TCON_VCOM_ALT_SHIFT (0xAu) - -#define CONTROL_DTC_CTRL_TCON_VCOM_POL (0x00000200u) -#define CONTROL_DTC_CTRL_TCON_VCOM_POL_SHIFT (0x9u) - -#define CONTROL_DTC_CTRL_TCON_VCOM_EN (0x00000100u) -#define CONTROL_DTC_CTRL_TCON_VCOM_EN_SHIFT (0x8u) - -#define CONTROL_DTC_CTRL_DITHER_MODE (0x0000000Cu) -#define CONTROL_DTC_CTRL_DITHER_MODE_SHIFT (0x2u) - -#define CONTROL_DTC_CTRL_DITHER_ACTVID_POL (0x00000002u) -#define CONTROL_DTC_CTRL_DITHER_ACTVID_POL_SHIFT (0x1u) - -#define CONTROL_DTC_CTRL_DITHER_ENABLE (0x00000001u) -#define CONTROL_DTC_CTRL_DITHER_ENABLE_SHIFT (0x0u) - -/** @brief CONTROL_DTC0_LOAD(n) register fields */ -#define CONTROL_DTC0_LOAD012_TCON_LOAD_WIDTH (0x07FF0000u) -#define CONTROL_DTC0_LOAD012_TCON_LOAD_WIDTH_SHIFT (0x10u) - -#define CONTROL_DTC0_LOAD012_TCON_LOAD_ON (0x000007FFu) -#define CONTROL_DTC0_LOAD012_TCON_LOAD_ON_SHIFT (0x0u) - -#define CONTROL_DTC0_LOAD3_LOAD3_VSMOD (0x80000000u) -#define CONTROL_DTC0_LOAD3_LOAD3_VSMOD_SHIFT (0x1Fu) - -#define CONTROL_DTC0_LOAD3_LOAD3_VSCNT (0x78000000u) -#define CONTROL_DTC0_LOAD3_LOAD3_VSCNT_SHIFT (0x1Bu) - -#define CONTROL_DTC0_LOAD3_TCON_LOAD_WIDTH (0x07FF0000u) -#define CONTROL_DTC0_LOAD3_TCON_LOAD_WIDTH_SHIFT (0x10u) - -#define CONTROL_DTC0_LOAD3_TCON_LOAD_ON (0x000007FFu) -#define CONTROL_DTC0_LOAD3_TCON_LOAD_ON_SHIFT (0x0u) - -/** @brief CONTROL_DTC1_LOAD(n) register fields */ -#define CONTROL_DTC1_LOAD012_TCON_LOAD_WIDTH (0x07FF0000u) -#define CONTROL_DTC1_LOAD012_TCON_LOAD_WIDTH_SHIFT (0x10u) - -#define CONTROL_DTC1_LOAD012_TCON_LOAD_ON (0x000007FFu) -#define CONTROL_DTC1_LOAD012_TCON_LOAD_ON_SHIFT (0x0u) - -#define CONTROL_DTC1_LOAD3_LOAD3_VSMOD (0x80000000u) -#define CONTROL_DTC1_LOAD3_LOAD3_VSMOD_SHIFT (0x1Fu) - -#define CONTROL_DTC1_LOAD3_LOAD3_VSCNT (0x78000000u) -#define CONTROL_DTC1_LOAD3_LOAD3_VSCNT_SHIFT (0x1Bu) - -#define CONTROL_DTC1_LOAD3_TCON_LOAD_WIDTH (0x07FF0000u) -#define CONTROL_DTC1_LOAD3_TCON_LOAD_WIDTH_SHIFT (0x10u) - -#define CONTROL_DTC1_LOAD3_TCON_LOAD_ON (0x000007FFu) -#define CONTROL_DTC1_LOAD3_TCON_LOAD_ON_SHIFT (0x0u) - -/** @brief CONTROL_ICSS_INT_MUX(n) register fields */ -/* TBD */ - -/** @brief CONTROL_CHIP_HW_DBG_SEL register fields */ -#define CONTROL_CHIP_HW_DBG_SEL_CHIP_DBG_SEL (0x00000007u) -#define CONTROL_CHIP_HW_DBG_SEL_CHIP_DBG_SEL_SHIFT (0x0u) - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_dcan.h b/lib/tiam1808/tiam1808/hw/hw_dcan.h deleted file mode 100644 index 24a8b7aed..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_dcan.h +++ /dev/null @@ -1,1289 +0,0 @@ - - -/** - * @Component: DCAN - * - * @Filename: ../../CredDataBase/dcan_cred.h - * - ============================================================================ */ -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - - -#ifndef _HW_DCAN_H_ -#define _HW_DCAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***********************************************************************\ - * Register arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundle arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundles Definition -\***********************************************************************/ - - - -/*************************************************************************\ - * Registers Definition -\*************************************************************************/ - -#define DCAN_CTL (0x0) -#define DCAN_PARITYERR_EOI (0x04) -#define DCAN_ES (0x4) -#define DCAN_ERRC (0x8) -#define DCAN_BTR (0xc) -#define DCAN_INT (0x10) -#define DCAN_TEST (0x14) -#define DCAN_PERR (0x1c) -#define DCAN_ABOTR (0x80) -#define DCAN_TXRQ_X (0x84) -#define DCAN_TXRQ(n) (0x88 + (n * 4)) -#define DCAN_NWDAT_X (0x98) -#define DCAN_NWDAT(n) (0x9c + (n * 4)) -#define DCAN_INTPND_X (0xac) -#define DCAN_INTPND(n) (0xB0 + (n * 4)) -#define DCAN_MSGVAL_X (0xc0) -#define DCAN_MSGVAL(n) (0xC4 + (n * 4)) -#define DCAN_INTMUX(n) (0xD8 + (n * 4)) -#define DCAN_IFCMD(n) (0x100 + (((n) - 1) * 0x20)) -#define DCAN_IFMSK(n) (0x104 + (((n) - 1) * 0x20)) -#define DCAN_IFARB(n) (0x108 + (((n) - 1) * 0x20)) -#define DCAN_IFMCTL(n) (0x10c + (((n) - 1) * 0x20)) -#define DCAN_IFDATA(n) (0x110 + (((n) - 1) * 0x20)) -#define DCAN_IFDATB(n) (0x114 + (((n) - 1) * 0x20)) -#define DCAN_IF3OBS (0x140) -#define DCAN_IF3UPD(n) (0x160 + (n * 4)) -#define DCAN_TIOC (0x1e0) -#define DCAN_RIOC (0x1e4) - -/**************************************************************************\ - * Field Definition Macros -\**************************************************************************/ - -/* CTL */ -#define DCAN_CTL_ABO (0x00000200u) -#define DCAN_CTL_ABO_SHIFT (0x00000009u) -#define DCAN_CTL_ABO_DISABLED (0x0u) -#define DCAN_CTL_ABO_ENABLED (0x1u) - -#define DCAN_CTL_CCE (0x00000040u) -#define DCAN_CTL_CCE_SHIFT (0x00000006u) -#define DCAN_CTL_CCE_ACCESS (0x1u) -#define DCAN_CTL_CCE_NOACCESS (0x0u) - -#define DCAN_CTL_DAR (0x00000020u) -#define DCAN_CTL_DAR_SHIFT (0x00000005u) -#define DCAN_CTL_DAR_DISABLED (0x1u) -#define DCAN_CTL_DAR_ENABLED (0x0u) - -#define DCAN_CTL_DE1 (0x00040000u) -#define DCAN_CTL_DE1_SHIFT (0x00000012u) -#define DCAN_CTL_DE1_DISABLED (0x0u) -#define DCAN_CTL_DE1_ENABLED (0x1u) - -#define DCAN_CTL_DE2 (0x00080000u) -#define DCAN_CTL_DE2_SHIFT (0x00000013u) -#define DCAN_CTL_DE2_DISABLED (0x0u) -#define DCAN_CTL_DE2_ENABLED (0x1u) - -#define DCAN_CTL_DE3 (0x00100000u) -#define DCAN_CTL_DE3_SHIFT (0x00000014u) -#define DCAN_CTL_DE3_DISABLED (0x0u) -#define DCAN_CTL_DE3_ENABLED (0x1u) - -#define DCAN_CTL_EIE (0x00000008u) -#define DCAN_CTL_EIE_SHIFT (0x00000003u) -#define DCAN_CTL_EIE_DISABLED (0x0u) -#define DCAN_CTL_EIE_ENABLED (0x1u) - -#define DCAN_CTL_IDS (0x00000100u) -#define DCAN_CTL_IDS_SHIFT (0x00000008u) -#define DCAN_CTL_IDS_INTERRUPT (0x1u) -#define DCAN_CTL_IDS_WAIT (0x0u) - -#define DCAN_CTL_IE0 (0x00000002u) -#define DCAN_CTL_IE0_SHIFT (0x00000001u) -#define DCAN_CTL_IE0_DISABLED (0x0u) -#define DCAN_CTL_IE0_ENABLED (0x1u) - -#define DCAN_CTL_IE1 (0x00020000u) -#define DCAN_CTL_IE1_SHIFT (0x00000011u) -#define DCAN_CTL_IE1_DISABLED (0x0u) -#define DCAN_CTL_IE1_ENABLED (0x1u) - -#define DCAN_CTL_INIT (0x00000001u) -#define DCAN_CTL_INIT_SHIFT (0x00000000u) -#define DCAN_CTL_INIT_INITMODE (0x1u) -#define DCAN_CTL_INIT_NORMAL (0x0u) - -#define DCAN_CTL_INITDBG (0x00010000u) -#define DCAN_CTL_INITDBG_SHIFT (0x00000010u) -#define DCAN_CTL_INITDBG_DISABLED (0x0u) -#define DCAN_CTL_INITDBG_ENABLED (0x1u) - -#define DCAN_CTL_PDR (0x01000000u) -#define DCAN_CTL_PDR_SHIFT (0x00000018u) -#define DCAN_CTL_PDR_NOTPOWERDOWN (0x0u) -#define DCAN_CTL_PDR_POWERDOWN (0x1u) - -#define DCAN_CTL_PMD (0x00003C00u) -#define DCAN_CTL_PMD_SHIFT (0x0000000Au) -#define DCAN_CTL_PMD_DISABLED (0x5u) -#define DCAN_CTL_PMD_ENABLED (0x1u) - -#define DCAN_CTL_SIE (0x00000004u) -#define DCAN_CTL_SIE_SHIFT (0x00000002u) -#define DCAN_CTL_SIE_DISABLED (0x0u) -#define DCAN_CTL_SIE_ENABLED (0x1u) - -#define DCAN_CTL_SWR (0x00008000u) -#define DCAN_CTL_SWR_SHIFT (0x0000000Fu) -#define DCAN_CTL_SWR_NORMAL (0x0u) -#define DCAN_CTL_SWR_RESET (0x1u) - -#define DCAN_CTL_TEST (0x00000080u) -#define DCAN_CTL_TEST_SHIFT (0x00000007u) -#define DCAN_CTL_TEST_NORMALMODE (0x0u) -#define DCAN_CTL_TEST_TESTMODE (0x1u) - -#define DCAN_CTL_WUBA (0x02000000u) -#define DCAN_CTL_WUBA_SHIFT (0x00000019u) -#define DCAN_CTL_WUBA_DETECTION (0x1u) -#define DCAN_CTL_WUBA_NODETECTION (0x0u) - - -/* PARITYERR_EOI */ -#define DCAN_PARITYERR_EOI_PARITYERR_EOI (0x00000100u) -#define DCAN_PARITYERR_EOI_PARITYERR_EOI_SHIFT (0x00000008u) -#define DCAN_PARITYERR_EOI_PARITYERR_EOI_ENDOFINTERRUPT (0x1u) -#define DCAN_PARITYERR_EOI_PARITYERR_EOI_NOEFFECT (0x0u) - - -/* ES */ -#define DCAN_ES_BOFF (0x00000080u) -#define DCAN_ES_BOFF_SHIFT (0x00000007u) -#define DCAN_ES_BOFF_ERROR (0x1u) -#define DCAN_ES_BOFF_NOERROR (0x0u) - -#define DCAN_ES_EPASS (0x00000020u) -#define DCAN_ES_EPASS_SHIFT (0x00000005u) -#define DCAN_ES_EPASS_NOPASSIVE (0x0u) -#define DCAN_ES_EPASS_PASSIVEERROR (0x1u) - -#define DCAN_ES_EWARN (0x00000040u) -#define DCAN_ES_EWARN_SHIFT (0x00000006u) -#define DCAN_ES_EWARN_ATLEAST1ERRORABOVE_96 (0x1u) -#define DCAN_ES_EWARN_ERRENCOUNTERBELOW_96 (0x0u) - -#define DCAN_ES_LEC (0x00000007u) -#define DCAN_ES_LEC_SHIFT (0x00000000u) -#define DCAN_ES_LEC_ACKERROR (0x3u) -#define DCAN_ES_LEC_BIT0ERROR (0x5u) -#define DCAN_ES_LEC_BIT1ERROR (0x4u) -#define DCAN_ES_LEC_CRCERROR (0x6u) -#define DCAN_ES_LEC_FORMERROR (0x2u) -#define DCAN_ES_LEC_NOERROR (0x0u) -#define DCAN_ES_LEC_NOEVENT (0x7u) -#define DCAN_ES_LEC_STUFFERROR (0x1u) - -#define DCAN_ES_PDA (0x00000400u) -#define DCAN_ES_PDA_SHIFT (0x0000000Au) -#define DCAN_ES_PDA_NOTPOWERDOWN (0x0u) -#define DCAN_ES_PDA_POWERDOWN (0x1u) - -#define DCAN_ES_PER (0x00000100u) -#define DCAN_ES_PER_SHIFT (0x00000008u) -#define DCAN_ES_PER_ERROR (0x1u) -#define DCAN_ES_PER_NOERROR (0x0u) - -#define DCAN_ES_RXOK (0x00000010u) -#define DCAN_ES_RXOK_SHIFT (0x00000004u) -#define DCAN_ES_RXOK_MESSAGERECIEVED (0x1u) -#define DCAN_ES_RXOK_NOMESSAGE (0x0u) - -#define DCAN_ES_TXOK (0x00000008u) -#define DCAN_ES_TXOK_SHIFT (0x00000003u) -#define DCAN_ES_TXOK_MESSAGETRANSMITTED (0x1u) -#define DCAN_ES_TXOK_NOMESSAGE (0x0u) - -#define DCAN_ES_WAKEUPPND (0x00000200u) -#define DCAN_ES_WAKEUPPND_SHIFT (0x00000009u) -#define DCAN_ES_WAKEUPPND_INITWAKEUP (0x1u) -#define DCAN_ES_WAKEUPPND_NOWAKEUP (0x0u) - - -/* ERRC */ -#define DCAN_ERRC_REC (0x00007F00u) -#define DCAN_ERRC_REC_SHIFT (0x00000008u) - -#define DCAN_ERRC_RP (0x00008000u) -#define DCAN_ERRC_RP_SHIFT (0x0000000Fu) -#define DCAN_ERRC_RP_BELOWERRORPASSIVELEVEL (0x0u) -#define DCAN_ERRC_RP_REACHEDERRORPASSIVELEVEL (0x1u) - -#define DCAN_ERRC_TEC (0x000000FFu) -#define DCAN_ERRC_TEC_SHIFT (0x00000000u) - - -/* BTR */ -#define DCAN_BTR_BRP (0x0000003Fu) -#define DCAN_BTR_BRP_SHIFT (0x00000000u) - -#define DCAN_BTR_BRPE (0x000F0000u) -#define DCAN_BTR_BRPE_SHIFT (0x00000010u) - -#define DCAN_BTR_DCAN_BTR (0xFFFFFFFFu) -#define DCAN_BTR_DCAN_BTR_SHIFT (0x00000000u) - -#define DCAN_BTR_SJW (0x000000C0u) -#define DCAN_BTR_SJW_SHIFT (0x00000006u) - -#define DCAN_BTR_TSEG1 (0x00000F00u) -#define DCAN_BTR_TSEG1_SHIFT (0x00000008u) - -#define DCAN_BTR_TSEG2 (0x00007000u) -#define DCAN_BTR_TSEG2_SHIFT (0x0000000Cu) - - -/* INT */ -#define DCAN_INT_INT0ID (0x0000FFFFu) -#define DCAN_INT_INT0ID_SHIFT (0x00000000u) - -#define DCAN_INT_INT1ID (0x00FF0000u) -#define DCAN_INT_INT1ID_SHIFT (0x00000010u) - - -/* TEST */ -#define DCAN_TEST_EXL (0x00000100u) -#define DCAN_TEST_EXL_SHIFT (0x00000008u) -#define DCAN_TEST_EXL_DISABLED (0x0u) -#define DCAN_TEST_EXL_ENABLED (0x1u) - -#define DCAN_TEST_LBACK (0x00000010u) -#define DCAN_TEST_LBACK_SHIFT (0x00000004u) -#define DCAN_TEST_LBACK_DISABLED (0x0u) -#define DCAN_TEST_LBACK_ENABLED (0x1u) - -#define DCAN_TEST_RDA (0x00000200u) -#define DCAN_TEST_RDA_SHIFT (0x00000009u) -#define DCAN_TEST_RDA_ACCESS (0x1u) -#define DCAN_TEST_RDA_NORMAL (0x0u) - -#define DCAN_TEST_RX (0x00000080u) -#define DCAN_TEST_RX_SHIFT (0x00000007u) -#define DCAN_TEST_RX_DOMINANT (0x0u) -#define DCAN_TEST_RX_RECESSIVE (0x1u) - -#define DCAN_TEST_TX (0x00000060u) -#define DCAN_TEST_TX_SHIFT (0x00000005u) -#define DCAN_TEST_TX_DOMINANT (0x2u) -#define DCAN_TEST_TX_NORMAL (0x0u) -#define DCAN_TEST_TX_RECESSIVE (0x3u) -#define DCAN_TEST_TX_SAMPLEPOINT (0x1u) - -#define DCAN_TEST_SILENT (0x00000008u) -#define DCAN_TEST_SILENT_SHIFT (0x00000003u) -#define DCAN_TEST_SILENT_DISABLED (0x0u) -#define DCAN_TEST_SILENT_ENABLED (0x1u) - - -/* PERR */ -#define DCAN_PERR_MESSAGE_NUMBER (0x000000FFu) -#define DCAN_PERR_MESSAGE_NUMBER_SHIFT (0x00000000u) - -#define DCAN_PERR_WORD_NUMBER (0x00000700u) -#define DCAN_PERR_WORD_NUMBER_SHIFT (0x00000008u) - - -/* ABOTR */ -#define DCAN_ABOTR_ABOTIME (0xFFFFFFFFu) -#define DCAN_ABOTR_ABOTIME_SHIFT (0x00000000u) - - -/* TXRQ_X */ -#define DCAN_TXRQ_X_TXRQSTREG1 (0x00000003u) -#define DCAN_TXRQ_X_TXRQSTREG1_SHIFT (0x00000000u) - -#define DCAN_TXRQ_X_TXRQSTREG2 (0x0000000Cu) -#define DCAN_TXRQ_X_TXRQSTREG2_SHIFT (0x00000002u) - -#define DCAN_TXRQ_X_TXRQSTREG3 (0x00000030u) -#define DCAN_TXRQ_X_TXRQSTREG3_SHIFT (0x00000004u) - -#define DCAN_TXRQ_X_TXRQSTREG4 (0x000000C0u) -#define DCAN_TXRQ_X_TXRQSTREG4_SHIFT (0x00000006u) - -#define DCAN_TXRQ_X_TXRQSTREG5 (0x00000300u) -#define DCAN_TXRQ_X_TXRQSTREG5_SHIFT (0x00000008u) - -#define DCAN_TXRQ_X_TXRQSTREG6 (0x00000C00u) -#define DCAN_TXRQ_X_TXRQSTREG6_SHIFT (0x0000000Au) - -#define DCAN_TXRQ_X_TXRQSTREG7 (0x00003000u) -#define DCAN_TXRQ_X_TXRQSTREG7_SHIFT (0x0000000Cu) - -#define DCAN_TXRQ_X_TXRQSTREG8 (0x0000C000u) -#define DCAN_TXRQ_X_TXRQSTREG8_SHIFT (0x0000000Eu) - - -/* TXRQ12 */ -#define DCAN_TXRQ12_TXRQST_16_1 (0x0000FFFFu) -#define DCAN_TXRQ12_TXRQST_16_1_SHIFT (0x00000000u) - -#define DCAN_TXRQ12_TXRQST_32_17 (0xFFFF0000u) -#define DCAN_TXRQ12_TXRQST_32_17_SHIFT (0x00000010u) - - -/* TXRQ34 */ -#define DCAN_TXRQ34_TXRQST_48_33 (0x0000FFFFu) -#define DCAN_TXRQ34_TXRQST_48_33_SHIFT (0x00000000u) - -#define DCAN_TXRQ34_TXRQST_64_49 (0xFFFF0000u) -#define DCAN_TXRQ34_TXRQST_64_49_SHIFT (0x00000010u) - - -/* TXRQ56 */ -#define DCAN_TXRQ56_TXRQST_80_65 (0x0000FFFFu) -#define DCAN_TXRQ56_TXRQST_80_65_SHIFT (0x00000000u) - -#define DCAN_TXRQ56_TXRQST_96_81 (0xFFFF0000u) -#define DCAN_TXRQ56_TXRQST_96_81_SHIFT (0x00000010u) - - -/* TXRQ78 */ -#define DCAN_TXRQ78_TXRQST_112_97 (0x0000FFFFu) -#define DCAN_TXRQ78_TXRQST_112_97_SHIFT (0x00000000u) - -#define DCAN_TXRQ78_TXRQST_128_113 (0xFFFF0000u) -#define DCAN_TXRQ78_TXRQST_128_113_SHIFT (0x00000010u) - - -/* NWDAT_X */ -#define DCAN_NWDAT_X_NEWDATREG1 (0x00000003u) -#define DCAN_NWDAT_X_NEWDATREG1_SHIFT (0x00000000u) - -#define DCAN_NWDAT_X_NEWDATREG2 (0x0000000Cu) -#define DCAN_NWDAT_X_NEWDATREG2_SHIFT (0x00000002u) - -#define DCAN_NWDAT_X_NEWDATREG3 (0x00000030u) -#define DCAN_NWDAT_X_NEWDATREG3_SHIFT (0x00000004u) - -#define DCAN_NWDAT_X_NEWDATREG4 (0x000000C0u) -#define DCAN_NWDAT_X_NEWDATREG4_SHIFT (0x00000006u) - -#define DCAN_NWDAT_X_NEWDATREG5 (0x00000300u) -#define DCAN_NWDAT_X_NEWDATREG5_SHIFT (0x00000008u) - -#define DCAN_NWDAT_X_NEWDATREG6 (0x00000C00u) -#define DCAN_NWDAT_X_NEWDATREG6_SHIFT (0x0000000Au) - -#define DCAN_NWDAT_X_NEWDATREG7 (0x00003000u) -#define DCAN_NWDAT_X_NEWDATREG7_SHIFT (0x0000000Cu) - -#define DCAN_NWDAT_X_NEWDATREG8 (0x0000C000u) -#define DCAN_NWDAT_X_NEWDATREG8_SHIFT (0x0000000Eu) - - -/* NWDAT12 */ -#define DCAN_NWDAT12_NEWDAT_16_1 (0x0000FFFFu) -#define DCAN_NWDAT12_NEWDAT_16_1_SHIFT (0x00000000u) - -#define DCAN_NWDAT12_NEWDAT_32_17 (0xFFFF0000u) -#define DCAN_NWDAT12_NEWDAT_32_17_SHIFT (0x00000010u) - -#define DCAN_NWDAT12_NEWDAT_80_65 (0x0000FFFFu) -#define DCAN_NWDAT12_NEWDAT_80_65_SHIFT (0x00000000u) - - -/* NWDAT34 */ -#define DCAN_NWDAT34_NEWDAT_48_33 (0x0000FFFFu) -#define DCAN_NWDAT34_NEWDAT_48_33_SHIFT (0x00000000u) - -#define DCAN_NWDAT34_NEWDAT_64_49 (0xFFFF0000u) -#define DCAN_NWDAT34_NEWDAT_64_49_SHIFT (0x00000010u) - - -/* NWDAT56 */ - -#define DCAN_NWDAT56_NEWDAT_96_81 (0xFFFF0000u) -#define DCAN_NWDAT56_NEWDAT_96_81_SHIFT (0x00000000u) - - -/* NWDAT78 */ -#define DCAN_NWDAT78_NEWDAT_112_97 (0x0000FFFFu) -#define DCAN_NWDAT78_NEWDAT_112_97_SHIFT (0x00000000u) - -#define DCAN_NWDAT78_NEWDAT_128_113 (0xFFFF0000u) -#define DCAN_NWDAT78_NEWDAT_128_113_SHIFT (0x00000010u) - - -/* INTPND_X */ -#define DCAN_INTPND_X_INTPNDREG1 (0x00000003u) -#define DCAN_INTPND_X_INTPNDREG1_SHIFT (0x00000000u) - -#define DCAN_INTPND_X_INTPNDREG2 (0x0000000Cu) -#define DCAN_INTPND_X_INTPNDREG2_SHIFT (0x00000002u) - -#define DCAN_INTPND_X_INTPNDREG3 (0x00000030u) -#define DCAN_INTPND_X_INTPNDREG3_SHIFT (0x00000004u) - -#define DCAN_INTPND_X_INTPNDREG4 (0x000000C0u) -#define DCAN_INTPND_X_INTPNDREG4_SHIFT (0x00000006u) - -#define DCAN_INTPND_X_INTPNDREG5 (0x00000300u) -#define DCAN_INTPND_X_INTPNDREG5_SHIFT (0x00000008u) - -#define DCAN_INTPND_X_INTPNDREG6 (0x00000C00u) -#define DCAN_INTPND_X_INTPNDREG6_SHIFT (0x0000000Au) - -#define DCAN_INTPND_X_INTPNDREG7 (0x00003000u) -#define DCAN_INTPND_X_INTPNDREG7_SHIFT (0x0000000Cu) - -#define DCAN_INTPND_X_INTPNDREG8 (0x0000C000u) -#define DCAN_INTPND_X_INTPNDREG8_SHIFT (0x0000000Eu) - - -/* INTPND12 */ -#define DCAN_INTPND12_INTPND_16_1 (0x0000FFFFu) -#define DCAN_INTPND12_INTPND_16_1_SHIFT (0x00000001u) - -#define DCAN_INTPND12_INTPND_32_17 (0xFFFF0000u) -#define DCAN_INTPND12_INTPND_32_17_SHIFT (0x00000010u) - - -/* INTPND34 */ -#define DCAN_INTPND34_INTPND_48_33 (0x0000FFFFu) -#define DCAN_INTPND34_INTPND_48_33_SHIFT (0x00000001u) - -#define DCAN_INTPND34_INTPND_64_49 (0xFFFF0000u) -#define DCAN_INTPND34_INTPND_64_49_SHIFT (0x00000010u) - - -/* INTPND56 */ -#define DCAN_INTPND56_INTPND_80_65 (0x0000FFFFu) -#define DCAN_INTPND56_INTPND_80_65_SHIFT (0x00000001u) - -#define DCAN_INTPND56_INTPND_96_81 (0xFFFF0000u) -#define DCAN_INTPND56_INTPND_96_81_SHIFT (0x00000000u) - - - -/* INTPND78 */ - -#define DCAN_INTPND78_INTPND_128_113 (0xFFFF0000u) -#define DCAN_INTPND78_INTPND_128_113_SHIFT (0x00000010u) - - -/* MSGVAL_X */ -#define DCAN_MSGVAL_X_MSGVALREG1 (0x00000003u) -#define DCAN_MSGVAL_X_MSGVALREG1_SHIFT (0x00000000u) - -#define DCAN_MSGVAL_X_MSGVALREG2 (0x0000000Cu) -#define DCAN_MSGVAL_X_MSGVALREG2_SHIFT (0x00000002u) - -#define DCAN_MSGVAL_X_MSGVALREG3 (0x00000030u) -#define DCAN_MSGVAL_X_MSGVALREG3_SHIFT (0x00000004u) - -#define DCAN_MSGVAL_X_MSGVALREG4 (0x000000C0u) -#define DCAN_MSGVAL_X_MSGVALREG4_SHIFT (0x00000006u) - -#define DCAN_MSGVAL_X_MSGVALREG5 (0x00000300u) -#define DCAN_MSGVAL_X_MSGVALREG5_SHIFT (0x00000008u) - -#define DCAN_MSGVAL_X_MSGVALREG6 (0x00000C00u) -#define DCAN_MSGVAL_X_MSGVALREG6_SHIFT (0x0000000Au) - -#define DCAN_MSGVAL_X_MSGVALREG7 (0x00003000u) -#define DCAN_MSGVAL_X_MSGVALREG7_SHIFT (0x0000000Cu) - -#define DCAN_MSGVAL_X_MSGVALREG8 (0x0000C000u) -#define DCAN_MSGVAL_X_MSGVALREG8_SHIFT (0x00000000u) - - -/* MSGVAL12 */ -#define DCAN_MSGVAL12_MSGVAL_16_1 (0x0000FFFFu) -#define DCAN_MSGVAL12_MSGVAL_16_1_SHIFT (0x00000001u) - -#define DCAN_MSGVAL12_MSGVAL_32_17 (0xFFFF0000u) -#define DCAN_MSGVAL12_MSGVAL_32_17_SHIFT (0x00000010u) - - -/* MSGVAL34 */ -#define DCAN_MSGVAL34_MSGVAL_48_33 (0x0000FFFFu) -#define DCAN_MSGVAL34_MSGVAL_48_33_SHIFT (0x00000001u) - -#define DCAN_MSGVAL34_MSGVAL_64_49 (0xFFFF0000u) -#define DCAN_MSGVAL34_MSGVAL_64_49_SHIFT (0x00000010u) - - -/* MSGVAL56 */ -#define DCAN_MSGVAL56_MSGVAL_80_65 (0x0000FFFFu) -#define DCAN_MSGVAL56_MSGVAL_80_65_SHIFT (0x00000001u) - -#define DCAN_MSGVAL56_MSGVAL_96_81 (0xFFFF0000u) -#define DCAN_MSGVAL56_MSGVAL_96_81_SHIFT (0x00000010u) - - -/* MSGVAL78 */ -#define DCAN_MSGVAL78_MSGVAL_112_97 (0x0000FFFFu) -#define DCAN_MSGVAL78_MSGVAL_112_97_SHIFT (0x00000001u) - -#define DCAN_MSGVAL78_MSGVAL_128_113 (0xFFFF0000u) -#define DCAN_MSGVAL78_MSGVAL_128_113_SHIFT (0x00000010u) - - -/* INTMUX12 */ -#define DCAN_INTMUX12_INTMUX_16_1 (0x0000FFFFu) -#define DCAN_INTMUX12_INTMUX_16_1_SHIFT (0x00000001u) - -#define DCAN_INTMUX12_INTMUX_32_17 (0xFFFF0000u) -#define DCAN_INTMUX12_INTMUX_32_17_SHIFT (0x00000010u) - - -/* INTMUX34 */ -#define DCAN_INTMUX34_INTMUX_48_33 (0x0000FFFFu) -#define DCAN_INTMUX34_INTMUX_48_33_SHIFT (0x00000001u) - -#define DCAN_INTMUX34_INTMUX_64_49 (0xFFFF0000u) -#define DCAN_INTMUX34_INTMUX_64_49_SHIFT (0x00000010u) - - -/* INTMUX56 */ -#define DCAN_INTMUX56_INTMUX_80_65 (0x0000FFFFu) -#define DCAN_INTMUX56_INTMUX_80_65_SHIFT (0x00000001u) - -#define DCAN_INTMUX56_INTMUX_96_81 (0xFFFF0000u) -#define DCAN_INTMUX56_INTMUX_96_81_SHIFT (0x00000010u) - - -/* INTMUX78 */ -#define DCAN_INTMUX78_INTMUX_112_95 (0x0000FFFFu) -#define DCAN_INTMUX78_INTMUX_112_95_SHIFT (0x00000001u) - -#define DCAN_INTMUX78_INTMUX_128_113 (0xFFFF0000u) -#define DCAN_INTMUX78_INTMUX_128_113_SHIFT (0x00000010u) - -/* IFxCMD mu */ -#define DCAN_IFCMD_ARB (0x00200000u) -#define DCAN_IFCMD_ARB_SHIFT (0x00000015u) -#define DCAN_IFCMD_ARB_NOCHANGE (0x0u) -#define DCAN_IFCMD_ARB_OBJTOREG (0x1u) -#define DCAN_IFCMD_ARB_REGTOOBJ (0x1u) - -#define DCAN_IFCMD_BUSY (0x00008000u) -#define DCAN_IFCMD_BUSY_SHIFT (0x0000000Fu) -#define DCAN_IFCMD_BUSY_NOTRANSFER (0x0u) -#define DCAN_IFCMD_BUSY_TRANSFER (0x1u) - -#define DCAN_IFCMD_CLRINTPND (0x00080000u) -#define DCAN_IFCMD_CLRINTPND_SHIFT (0x00000013u) -#define DCAN_IFCMD_CLRINTPND_CHANGE (0x1u) -#define DCAN_IFCMD_CLRINTPND_NOCHANGE (0x0u) - -#define DCAN_IFCMD_CONTROL (0x00100000u) -#define DCAN_IFCMD_CONTROL_SHIFT (0x00000014u) - -#define DCAN_IFCMD_DATAA (0x00020000u) -#define DCAN_IFCMD_DATAA_SHIFT (0x00000011u) - -#define DCAN_IFCMD_DATAB (0x00010000u) -#define DCAN_IFCMD_DATAB_SHIFT (0x00000010u) - -#define DCAN_IFCMD_DMAACTIVE (0x00004000u) -#define DCAN_IFCMD_DMAACTIVE_SHIFT (0x0000000Eu) -#define DCAN_IFCMD_DMAACTIVE_ACTIVE (0x1u) -#define DCAN_IFCMD_DMAACTIVE_INACTIVE (0x0u) - -#define DCAN_IFCMD_MASK (0x00400000u) -#define DCAN_IFCMD_MASK_SHIFT (0x00000016u) - -#define DCAN_IFCMD_MESSAGENUMBER (0x000000FFu) -#define DCAN_IFCMD_MESSAGENUMBER_SHIFT (0x00000000u) - -#define DCAN_IFCMD_TXRQST_NEWDAT (0x00040000u) -#define DCAN_IFCMD_TXRQST_NEWDAT_SHIFT (0x00000012u) - -#define DCAN_IFCMD_WR_RD (0x00800000u) -#define DCAN_IFCMD_WR_RD_SHIFT (0x00000017u) - - -/* IFxMSK mu */ -#define DCAN_IFMSK_MDIR (0x40000000u) -#define DCAN_IFMSK_MDIR_SHIFT (0x00000001Eu) -#define DCAN_IFMSK_MDIR_NOTUSED (0x0u) -#define DCAN_IFMSK_MDIR_USED (0x1u) - -#define DCAN_IFMSK_MSK (0x1FFFFFFFu) -#define DCAN_IFMSK_MSK_SHIFT (0x00000000u) -#define DCAN_IFMSK_MSK_NOTUSED (0x0u) -#define DCAN_IFMSK_MSK_USED (0x1u) - -#define DCAN_IFMSK_MXTD (0x80000000u) -#define DCAN_IFMSK_MXTD_SHIFT (0x00000001Fu) -#define DCAN_IFMSK_MXTD_NOTUSED (0x0u) -#define DCAN_IFMSK_MXTD_USED (0x1u) - - -/* IFxARB mu */ -#define DCAN_IFARB_DIR (0x20000000u) -#define DCAN_IFARB_DIR_SHIFT (0x0000001Du) -#define DCAN_IFARB_DIR_RECEIVE (0x0u) -#define DCAN_IFARB_DIR_TRANSMIT (0x1u) - -#define DCAN_IFARB_MSGVAL (0x80000000u) -#define DCAN_IFARB_MSGVAL_SHIFT (0x0000001Fu) -#define DCAN_IFARB_MSGVAL_IGNORED (0x0u) -#define DCAN_IFARB_MSGVAL_USED (0x1u) - -#define DCAN_IFARB_MSK (0x1FFFFFFFu) -#define DCAN_IFARB_MSK_SHIFT (0x000000000u) -#define DCAN_IFARB_MSK_RECEIVE (0x0u) -#define DCAN_IFARB_MSK_TRANSMIT (0x1u) - -#define DCAN_IFARB_XTD (0x40000000u) -#define DCAN_IFARB_XTD_SHIFT (0x0000001Eu) -#define DCAN_IFARB_XTD_11_BIT (0x0u) -#define DCAN_IFARB_XTD_29_BIT (0x1u) - -/* IFxMCTL mu */ -#define DCAN_IFMCTL_DATALENGTHCODE (0x0000000Fu) -#define DCAN_IFMCTL_DATALENGTHCODE_SHIFT (0x00000000u) - -#define DCAN_IFMCTL_EOB (0x00000080u) -#define DCAN_IFMCTL_EOB_SHIFT (0x00000007u) - -#define DCAN_IFMCTL_INTPND (0x00002000u) -#define DCAN_IFMCTL_INTPND_SHIFT (0x0000000Du) -#define DCAN_IFMCTL_INTPND_INTERRUPT (0x1u) -#define DCAN_IFMCTL_INTPND_NOINTERRUPT (0x0u) - -#define DCAN_IFMCTL_MSGLST (0x00004000u) -#define DCAN_IFMCTL_MSGLST_SHIFT (0x0000000Eu) -#define DCAN_IFMCTL_MSGLST_MSGLOST (0x1u) -#define DCAN_IFMCTL_MSGLST_NOMSGLOST (0x0u) - -#define DCAN_IFMCTL_NEWDAT (0x00008000u) -#define DCAN_IFMCTL_NEWDAT_SHIFT (0x0000000Fu) -#define DCAN_IFMCTL_NEWDAT_NEWDATA (0x1u) -#define DCAN_IFMCTL_NEWDAT_NONEWDATA (0x0u) - -#define DCAN_IFMCTL_RMTEN (0x00000200u) -#define DCAN_IFMCTL_RMTEN_SHIFT (0x00000009u) -#define DCAN_IFMCTL_RMTEN_DISABLE (0x0u) -#define DCAN_IFMCTL_RMTEN_ENABLE (0x1u) - -#define DCAN_IFMCTL_RXIE (0x00000400u) -#define DCAN_IFMCTL_RXIE_SHIFT (0x0000000Au) -#define DCAN_IFMCTL_RXIE_NOTRIGGER (0x0u) -#define DCAN_IFMCTL_RXIE_TRIGGER (0x1u) - -#define DCAN_IFMCTL_TXIE (0x00000800u) -#define DCAN_IFMCTL_TXIE_SHIFT (0x0000000Bu) -#define DCAN_IFMCTL_TXIE_NOTRIGGER (0x0u) -#define DCAN_IFMCTL_TXIE_TRIGGER (0x1u) - -#define DCAN_IFMCTL_TXRQST (0x00000100u) -#define DCAN_IFMCTL_TXRQST_SHIFT (0x00000008u) -#define DCAN_IFMCTL_TXRQST_NOREQUESTED (0x0u) -#define DCAN_IFMCTL_TXRQST_REQUESTED (0x1u) - -#define DCAN_IFMCTL_UMASK (0x00001000u) -#define DCAN_IFMCTL_UMASK_SHIFT (0x0000000Cu) -#define DCAN_IFMCTL_UMASK_IGNORED (0x0u) -#define DCAN_IFMCTL_UMASK_MASKED (0x1u) - -/* IFxDATA mu */ -#define DCAN_IFDATA_DCAN_IFDATA (0xFFFFFFFFu) -#define DCAN_IFDATA_DCAN_IFDATA_SHIFT (0x00000000u) - - -/* IFxDATB mu */ -#define DCAN_IFDATB_DCAN_IFDATB (0xFFFFFFFFu) -#define DCAN_IFDATB_DCAN_IFDATB_SHIFT (0x00000000u) - -/* IF1CMD */ -#define DCAN_IF1CMD_ARB (0x00200000u) -#define DCAN_IF1CMD_ARB_SHIFT (0x00000015u) - -#define DCAN_IF1CMD_BUSY (0x00008000u) -#define DCAN_IF1CMD_BUSY_SHIFT (0x0000000Fu) -#define DCAN_IF1CMD_BUSY_NOTRANSFER (0x0u) -#define DCAN_IF1CMD_BUSY_TRANSFER (0x1u) - -#define DCAN_IF1CMD_CLRINTPND (0x00080000u) -#define DCAN_IF1CMD_CLRINTPND_SHIFT (0x00000013u) -#define DCAN_IF1CMD_CLRINTPND_CHANGE (0x1u) -#define DCAN_IF1CMD_CLRINTPND_NOCHANGE (0x0u) - -#define DCAN_IF1CMD_CONTROL (0x00100000u) -#define DCAN_IF1CMD_CONTROL_SHIFT (0x00000014u) - -#define DCAN_IF1CMD_DATAA (0x00020000u) -#define DCAN_IF1CMD_DATAA_SHIFT (0x00000011u) - -#define DCAN_IF1CMD_DATAB (0x00010000u) -#define DCAN_IF1CMD_DATAB_SHIFT (0x00000010u) - -#define DCAN_IF1CMD_DMAACTIVE (0x00004000u) -#define DCAN_IF1CMD_DMAACTIVE_SHIFT (0x0000000Eu) -#define DCAN_IF1CMD_DMAACTIVE_ACTIVE (0x1u) -#define DCAN_IF1CMD_DMAACTIVE_INACTIVE (0x0u) - -#define DCAN_IF1CMD_MASK (0x00400000u) -#define DCAN_IF1CMD_MASK_SHIFT (0x00000016u) - -#define DCAN_IF1CMD_MESSAGENUMBER (0x0000000Fu) -#define DCAN_IF1CMD_MESSAGENUMBER_SHIFT (0x00000000u) - -#define DCAN_IF1CMD_TXRQST_NEWDAT (0x00040000u) -#define DCAN_IF1CMD_TXRQST_NEWDAT_SHIFT (0x00000012u) - -#define DCAN_IF1CMD_WR_RD (0x00800000u) -#define DCAN_IF1CMD_WR_RD_SHIFT (0x00000017u) - - -/* IF1MSK */ -#define DCAN_IF1MSK_MDIR (0x40000000u) -#define DCAN_IF1MSK_MDIR_SHIFT (0x00000001Eu) -#define DCAN_IF1MSK_MDIR_NOTUSED (0x0u) -#define DCAN_IF1MSK_MDIR_USED (0x1u) - -#define DCAN_IF1MSK_MSK (0x1FFFFFFFu) -#define DCAN_IF1MSK_MSK_SHIFT (0x00000000u) -#define DCAN_IF1MSK_MSK_NOTUSED (0x0u) -#define DCAN_IF1MSK_MSK_USED (0x1u) - -#define DCAN_IF1MSK_MXTD (0x80000000u) -#define DCAN_IF1MSK_MXTD_SHIFT (0x00000001Fu) -#define DCAN_IF1MSK_MXTD_NOTUSED (0x0u) -#define DCAN_IF1MSK_MXTD_USED (0x1u) - - -/* IF1ARB */ -#define DCAN_IF1ARB_DIR (0x20000000u) -#define DCAN_IF1ARB_DIR_SHIFT (0x0000001Du) -#define DCAN_IF1ARB_DIR_RECEIVE (0x0u) -#define DCAN_IF1ARB_DIR_TRANSMIT (0x1u) - -#define DCAN_IF1ARB_MSGVAL (0x80000000u) -#define DCAN_IF1ARB_MSGVAL_SHIFT (0x0000001Fu) -#define DCAN_IF1ARB_MSGVAL_IGNORED (0x0u) -#define DCAN_IF1ARB_MSGVAL_USED (0x1u) - -#define DCAN_IF1ARB_MSK (0x1FFFFFFFu) -#define DCAN_IF1ARB_MSK_SHIFT (0x000000000u) -#define DCAN_IF1ARB_MSK_RECEIVE (0x0u) -#define DCAN_IF1ARB_MSK_TRANSMIT (0x1u) - -#define DCAN_IF1ARB_XTD (0x40000000u) -#define DCAN_IF1ARB_XTD_SHIFT (0x0000001Eu) -#define DCAN_IF1ARB_XTD_11_BIT (0x0u) -#define DCAN_IF1ARB_XTD_29_BIT (0x1u) - - -/* IF1MCTL */ -#define DCAN_IF1MCTL_DATALENGTHCODE (0x0000000Fu) -#define DCAN_IF1MCTL_DATALENGTHCODE_SHIFT (0x00000000u) - -#define DCAN_IF1MCTL_EOB (0x00000080u) -#define DCAN_IF1MCTL_EOB_SHIFT (0x00000007u) - -#define DCAN_IF1MCTL_INTPND (0x00002000u) -#define DCAN_IF1MCTL_INTPND_SHIFT (0x0000000Du) -#define DCAN_IF1MCTL_INTPND_INTERRUPT (0x1u) -#define DCAN_IF1MCTL_INTPND_NOINTERRUPT (0x0u) - -#define DCAN_IF1MCTL_MSGLST (0x00004000u) -#define DCAN_IF1MCTL_MSGLST_SHIFT (0x0000000Eu) -#define DCAN_IF1MCTL_MSGLST_MSGLOST (0x1u) -#define DCAN_IF1MCTL_MSGLST_NOMSGLOST (0x0u) - -#define DCAN_IF1MCTL_NEWDAT (0x00008000u) -#define DCAN_IF1MCTL_NEWDAT_SHIFT (0x0000000Fu) -#define DCAN_IF1MCTL_NEWDAT_NEWDATA (0x1u) -#define DCAN_IF1MCTL_NEWDAT_NONEWDATA (0x0u) - -#define DCAN_IF1MCTL_RMTEN (0x00000200u) -#define DCAN_IF1MCTL_RMTEN_SHIFT (0x00000009u) -#define DCAN_IF1MCTL_RMTEN_DISABLE (0x0u) -#define DCAN_IF1MCTL_RMTEN_ENABLE (0x1u) - -#define DCAN_IF1MCTL_RXIE (0x00000400u) -#define DCAN_IF1MCTL_RXIE_SHIFT (0x0000000Au) -#define DCAN_IF1MCTL_RXIE_NOTRIGGER (0x0u) -#define DCAN_IF1MCTL_RXIE_TRIGGER (0x1u) - -#define DCAN_IF1MCTL_TXIE (0x00000800u) -#define DCAN_IF1MCTL_TXIE_SHIFT (0x0000000Bu) -#define DCAN_IF1MCTL_TXIE_NOTRIGGER (0x0u) -#define DCAN_IF1MCTL_TXIE_TRIGGER (0x1u) - -#define DCAN_IF1MCTL_TXRQST (0x00000100u) -#define DCAN_IF1MCTL_TXRQST_SHIFT (0x00000008u) -#define DCAN_IF1MCTL_TXRQST_NOREQUESTED (0x0u) -#define DCAN_IF1MCTL_TXRQST_REQUESTED (0x1u) - -#define DCAN_IF1MCTL_UMASK (0x00001000u) -#define DCAN_IF1MCTL_UMASK_SHIFT (0x0000000Cu) -#define DCAN_IF1MCTL_UMASK_IGNORED (0x0u) -#define DCAN_IF1MCTL_UMASK_MASKED (0x1u) - - -/* IF1DATA */ -#define DCAN_IF1DATA_DCAN_IF1DATA (0xFFFFFFFFu) -#define DCAN_IF1DATA_DCAN_IF1DATA_SHIFT (0x00000000u) - - -/* IF1DATB */ -#define DCAN_IF1DATB_DCAN_IF1DATB (0xFFFFFFFFu) -#define DCAN_IF1DATB_DCAN_IF1DATB_SHIFT (0x00000000u) - - -/* IF2CMD */ -#define DCAN_IF2CMD_ARB (0x00200000u) -#define DCAN_IF2CMD_ARB_SHIFT (0x00000015u) - -#define DCAN_IF2CMD_BUSY (0x00008000u) -#define DCAN_IF2CMD_BUSY_SHIFT (0x0000000Fu) -#define DCAN_IF2CMD_BUSY_NOTRANSFER (0x0u) -#define DCAN_IF2CMD_BUSY_TRANSFER (0x1u) - -#define DCAN_IF2CMD_CLRINTPND (0x00080000u) -#define DCAN_IF2CMD_CLRINTPND_SHIFT (0x00000013u) -#define DCAN_IF2CMD_CLRINTPND_CHANGE (0x1u) -#define DCAN_IF2CMD_CLRINTPND_NOCHANGE (0x0u) - -#define DCAN_IF2CMD_CONTROL (0x00100000u) -#define DCAN_IF2CMD_CONTROL_SHIFT (0x00000014u) - -#define DCAN_IF2CMD_DATAA (0x00020000u) -#define DCAN_IF2CMD_DATAA_SHIFT (0x00000011u) - -#define DCAN_IF2CMD_DATAB (0x00010000u) -#define DCAN_IF2CMD_DATAB_SHIFT (0x00000010u) - -#define DCAN_IF2CMD_DMAACTIVE (0x00004000u) -#define DCAN_IF2CMD_DMAACTIVE_SHIFT (0x0000000Eu) -#define DCAN_IF2CMD_DMAACTIVE_ACTIVE (0x1u) -#define DCAN_IF2CMD_DMAACTIVE_INACTIVE (0x0u) - -#define DCAN_IF2CMD_MASK (0x00400000u) -#define DCAN_IF2CMD_MASK_SHIFT (0x00000016u) - -#define DCAN_IF2CMD_MESSAGENUMBER (0x000000FFu) -#define DCAN_IF2CMD_MESSAGENUMBER_SHIFT (0x00000000u) - -#define DCAN_IF2CMD_TXRQST_NEWDAT (0x00040000u) -#define DCAN_IF2CMD_TXRQST_NEWDAT_SHIFT (0x00000012u) - -#define DCAN_IF2CMD_WR_RD (0x00800000u) -#define DCAN_IF2CMD_WR_RD_SHIFT (0x00000017u) - - -/* IF2MSK */ -#define DCAN_IF2MSK_MDIR (0x40000000u) -#define DCAN_IF2MSK_MDIR_SHIFT (0x00000001Eu) -#define DCAN_IF2MSK_MDIR_NOTUSED (0x0u) -#define DCAN_IF2MSK_MDIR_USED (0x1u) - -#define DCAN_IF2MSK_MSK (0x1FFFFFFFu) -#define DCAN_IF2MSK_MSK_SHIFT (0x00000000u) -#define DCAN_IF2MSK_MSK_NOTUSED (0x0u) -#define DCAN_IF2MSK_MSK_USED (0x1u) - -#define DCAN_IF2MSK_MXTD (0x80000000u) -#define DCAN_IF2MSK_MXTD_SHIFT (0x00000001Fu) -#define DCAN_IF2MSK_MXTD_NOTUSED (0x0u) -#define DCAN_IF2MSK_MXTD_USED (0x1u) - - -/* IF2ARB */ -#define DCAN_IF2ARB_DIR (0x20000000u) -#define DCAN_IF2ARB_DIR_SHIFT (0x0000001Du) -#define DCAN_IF2ARB_DIR_RECEIVE (0x0u) -#define DCAN_IF2ARB_DIR_TRANSMIT (0x1u) - -#define DCAN_IF2ARB_MSGVAL (0x80000000u) -#define DCAN_IF2ARB_MSGVAL_SHIFT (0x0000001Fu) -#define DCAN_IF2ARB_MSGVAL_IGNORED (0x0u) -#define DCAN_IF2ARB_MSGVAL_USED (0x1u) - -#define DCAN_IF2ARB_MSK (0x1FFFFFFFu) -#define DCAN_IF2ARB_MSK_SHIFT (0x000000000u) -#define DCAN_IF2ARB_MSK_RECEIVE (0x0u) -#define DCAN_IF2ARB_MSK_TRANSMIT (0x1u) - -#define DCAN_IF2ARB_XTD (0x40000000u) -#define DCAN_IF2ARB_XTD_SHIFT (0x0000001Eu) -#define DCAN_IF2ARB_XTD_11_BIT (0x0u) -#define DCAN_IF2ARB_XTD_29_BIT (0x1u) - - -/* IF2MCTL */ -#define DCAN_IF2MCTL_DATALENGTHCODE (0x0000000Fu) -#define DCAN_IF2MCTL_DATALENGTHCODE_SHIFT (0x00000000u) - -#define DCAN_IF2MCTL_EOB (0x00000080u) -#define DCAN_IF2MCTL_EOB_SHIFT (0x00000007u) - -#define DCAN_IF2MCTL_INTPND (0x00002000u) -#define DCAN_IF2MCTL_INTPND_SHIFT (0x0000000Du) -#define DCAN_IF2MCTL_INTPND_INTERRUPT (0x1u) -#define DCAN_IF2MCTL_INTPND_NOINTERRUPT (0x0u) - -#define DCAN_IF2MCTL_MSGLST (0x00004000u) -#define DCAN_IF2MCTL_MSGLST_SHIFT (0x0000000Eu) -#define DCAN_IF2MCTL_MSGLST_MSGLOST (0x1u) -#define DCAN_IF2MCTL_MSGLST_NOMSGLOST (0x0u) - -#define DCAN_IF2MCTL_NEWDAT (0x00008000u) -#define DCAN_IF2MCTL_NEWDAT_SHIFT (0x0000000Fu) -#define DCAN_IF2MCTL_NEWDAT_NEWDATA (0x1u) -#define DCAN_IF2MCTL_NEWDAT_NONEWDATA (0x0u) - -#define DCAN_IF2MCTL_RMTEN (0x00000200u) -#define DCAN_IF2MCTL_RMTEN_SHIFT (0x00000009u) -#define DCAN_IF2MCTL_RMTEN_DISABLE (0x0u) -#define DCAN_IF2MCTL_RMTEN_ENABLE (0x1u) - -#define DCAN_IF2MCTL_RXIE (0x00000400u) -#define DCAN_IF2MCTL_RXIE_SHIFT (0x0000000Au) -#define DCAN_IF2MCTL_RXIE_NOTRIGGER (0x0u) -#define DCAN_IF2MCTL_RXIE_TRIGGER (0x1u) - -#define DCAN_IF2MCTL_TXIE (0x00000800u) -#define DCAN_IF2MCTL_TXIE_SHIFT (0x0000000Bu) -#define DCAN_IF2MCTL_TXIE_NOTRIGGER (0x0u) -#define DCAN_IF2MCTL_TXIE_TRIGGER (0x1u) - -#define DCAN_IF2MCTL_TXRQST (0x00000100u) -#define DCAN_IF2MCTL_TXRQST_SHIFT (0x00000008u) -#define DCAN_IF2MCTL_TXRQST_NOREQUESTED (0x0u) -#define DCAN_IF2MCTL_TXRQST_REQUESTED (0x1u) - -#define DCAN_IF2MCTL_UMASK (0x00001000u) -#define DCAN_IF2MCTL_UMASK_SHIFT (0x0000000Cu) -#define DCAN_IF2MCTL_UMASK_IGNORED (0x0u) -#define DCAN_IF2MCTL_UMASK_MASKED (0x1u) - - -/* IF2DATA */ -#define DCAN_IF2DATA_DCAN_IF2DATA (0xFFFFFFFFu) -#define DCAN_IF2DATA_DCAN_IF2DATA_SHIFT (0x00000000u) - - -/* IF2DATB */ -#define DCAN_IF2DATB_DCAN_IF2DATB (0xFFFFFFFFu) -#define DCAN_IF2DATB_DCAN_IF2DATB_SHIFT (0x00000000u) - - -/* IF3OBS */ -#define DCAN_IF3OBS_ARB (0x00000002u) -#define DCAN_IF3OBS_ARB_SHIFT (0x00000001u) -#define DCAN_IF3OBS_ARB_DATATOBEREAD (0x1u) -#define DCAN_IF3OBS_ARB_NOTTOBEREAD (0x0u) - -#define DCAN_IF3OBS_CTRL (0x00000004u) -#define DCAN_IF3OBS_CTRL_SHIFT (0x00000002u) -#define DCAN_IF3OBS_CTRL_DATATOBEREAD (0x1u) -#define DCAN_IF3OBS_CTRL_NOTTOBEREAD (0x0u) - -#define DCAN_IF3OBS_DATAA (0x00000008u) -#define DCAN_IF3OBS_DATAA_SHIFT (0x00000003u) -#define DCAN_IF3OBS_DATAA_DATATOBEREAD (0x1u) -#define DCAN_IF3OBS_DATAA_NOTTOBEREAD (0x0u) - -#define DCAN_IF3OBS_DATAB (0x00000010u) -#define DCAN_IF3OBS_DATAB_SHIFT (0x00000004u) -#define DCAN_IF3OBS_DATAB_DATATOBEREAD (0x1u) -#define DCAN_IF3OBS_DATAB_NOTTOBEREAD (0x0u) - -#define DCAN_IF3OBS_IF3SA (0x00000200u) -#define DCAN_IF3OBS_IF3SA_SHIFT (0x00000009u) -#define DCAN_IF3OBS_IF3SA_ALREADYREADOUT (0x0u) -#define DCAN_IF3OBS_IF3SA_STILLTOBEREAD (0x1u) - -#define DCAN_IF3OBS_IF3SC (0x00000400u) -#define DCAN_IF3OBS_IF3SC_SHIFT (0x0000000Au) -#define DCAN_IF3OBS_IF3SC_ALREADYREADOUT (0x0u) -#define DCAN_IF3OBS_IF3SC_STILLTOBEREAD (0x1u) - -#define DCAN_IF3OBS_IF3SDA (0x00000800u) -#define DCAN_IF3OBS_IF3SDA_SHIFT (0x0000000Bu) -#define DCAN_IF3OBS_IF3SDA_ALREADYREADOUT (0x0u) -#define DCAN_IF3OBS_IF3SDA_STILLTOBEREAD (0x1u) - -#define DCAN_IF3OBS_IF3SDB (0x00001000u) -#define DCAN_IF3OBS_IF3SDB_SHIFT (0x0000000Cu) -#define DCAN_IF3OBS_IF3SDB_ALREADYREADOUT (0x0u) -#define DCAN_IF3OBS_IF3SDB_STILLTOBEREAD (0x1u) - -#define DCAN_IF3OBS_IF3SM (0x00000100u) -#define DCAN_IF3OBS_IF3SM_SHIFT (0x00000008u) -#define DCAN_IF3OBS_IF3SM_ALREADYREADOUT (0x0u) -#define DCAN_IF3OBS_IF3SM_STILLTOBEREAD (0x1u) - -#define DCAN_IF3OBS_IF3UPD (0x00008000u) -#define DCAN_IF3OBS_IF3UPD_SHIFT (0x0000000Fu) -#define DCAN_IF3OBS_IF3UPD_NEWDATALOAD (0x1u) -#define DCAN_IF3OBS_IF3UPD_NONEWDATALOAD (0x0u) - -#define DCAN_IF3OBS_MASK (0x00000001u) -#define DCAN_IF3OBS_MASK_SHIFT (0x00000000u) -#define DCAN_IF3OBS_MASK_DATATOBEREAD (0x1u) -#define DCAN_IF3OBS_MASK_NOTTOBEREAD (0x0u) - - -/* IF3MSK */ -#define DCAN_IF3MSK_MDIR (0x40000000u) -#define DCAN_IF3MSK_MDIR_SHIFT (0x00000001Eu) -#define DCAN_IF3MSK_MDIR_NOTUSED (0x0u) -#define DCAN_IF3MSK_MDIR_USED (0x1u) - -#define DCAN_IF3MSK_MSK (0x1FFFFFFFu) -#define DCAN_IF3MSK_MSK_SHIFT (0x00000000u) -#define DCAN_IF3MSK_MSK_NOTUSED (0x0u) -#define DCAN_IF3MSK_MSK_USED (0x1u) - -#define DCAN_IF3MSK_MXTD (0x80000000u) -#define DCAN_IF3MSK_MXTD_SHIFT (0x00000001Fu) -#define DCAN_IF3MSK_MXTD_NOTUSED (0x0u) -#define DCAN_IF3MSK_MXTD_USED (0x1u) - - -/* IF3ARB */ -#define DCAN_IF3ARB_DIR (0x20000000u) -#define DCAN_IF3ARB_DIR_SHIFT (0x0000001Du) -#define DCAN_IF3ARB_DIR_RECEIVE (0x0u) -#define DCAN_IF3ARB_DIR_TRANSMIT (0x1u) - -#define DCAN_IF3ARB_MSGVAL (0x80000000u) -#define DCAN_IF3ARB_MSGVAL_SHIFT (0x0000001Fu) -#define DCAN_IF3ARB_MSGVAL_IGNORED (0x0u) -#define DCAN_IF3ARB_MSGVAL_USED (0x1u) - -#define DCAN_IF3ARB_MSK (0x1FFFFFFFu) -#define DCAN_IF3ARB_MSK_SHIFT (0x000000000u) -#define DCAN_IF3ARB_MSK_RECEIVE (0x0u) -#define DCAN_IF3ARB_MSK_TRANSMIT (0x1u) - -#define DCAN_IF3ARB_XTD (0x40000000u) -#define DCAN_IF3ARB_XTD_SHIFT (0x0000001Eu) -#define DCAN_IF3ARB_XTD_11_BIT (0x0u) -#define DCAN_IF3ARB_XTD_29_BIT (0x1u) - - -/* IF3MCTL */ -#define DCAN_IF3MCTL_DATALENGTHCODE (0x0000000Fu) -#define DCAN_IF3MCTL_DATALENGTHCODE_SHIFT (0x00000000u) - -#define DCAN_IF3MCTL_EOB (0x00000080u) -#define DCAN_IF3MCTL_EOB_SHIFT (0x00000007u) - -#define DCAN_IF3MCTL_INTPND (0x00002000u) -#define DCAN_IF3MCTL_INTPND_SHIFT (0x0000000Du) -#define DCAN_IF3MCTL_INTPND_INTERRUPT (0x1u) -#define DCAN_IF3MCTL_INTPND_NOINTERRUPT (0x0u) - -#define DCAN_IF3MCTL_MSGLST (0x00004000u) -#define DCAN_IF3MCTL_MSGLST_SHIFT (0x0000000Eu) -#define DCAN_IF3MCTL_MSGLST_MSGLOST (0x1u) -#define DCAN_IF3MCTL_MSGLST_NOMSGLOST (0x0u) - -#define DCAN_IF3MCTL_NEWDAT (0x00008000u) -#define DCAN_IF3MCTL_NEWDAT_SHIFT (0x0000000Fu) -#define DCAN_IF3MCTL_NEWDAT_NEWDATA (0x1u) -#define DCAN_IF3MCTL_NEWDAT_NONEWDATA (0x0u) - -#define DCAN_IF3MCTL_RMTEN (0x00000200u) -#define DCAN_IF3MCTL_RMTEN_SHIFT (0x00000009u) -#define DCAN_IF3MCTL_RMTEN_DISABLE (0x0u) -#define DCAN_IF3MCTL_RMTEN_ENABLE (0x1u) - -#define DCAN_IF3MCTL_RXIE (0x00000400u) -#define DCAN_IF3MCTL_RXIE_SHIFT (0x0000000Au) -#define DCAN_IF3MCTL_RXIE_NOTRIGGER (0x0u) -#define DCAN_IF3MCTL_RXIE_TRIGGER (0x1u) - -#define DCAN_IF3MCTL_TXIE (0x00000800u) -#define DCAN_IF3MCTL_TXIE_SHIFT (0x0000000Bu) -#define DCAN_IF3MCTL_TXIE_NOTRIGGER (0x0u) -#define DCAN_IF3MCTL_TXIE_TRIGGER (0x1u) - -#define DCAN_IF3MCTL_TXRQST (0x00000100u) -#define DCAN_IF3MCTL_TXRQST_SHIFT (0x00000008u) -#define DCAN_IF3MCTL_TXRQST_NOREQUESTED (0x0u) -#define DCAN_IF3MCTL_TXRQST_REQUESTED (0x1u) - -#define DCAN_IF3MCTL_UMASK (0x00001000u) -#define DCAN_IF3MCTL_UMASK_SHIFT (0x0000000Cu) -#define DCAN_IF3MCTL_UMASK_IGNORED (0x0u) -#define DCAN_IF3MCTL_UMASK_MASKED (0x1u) - - -/* IF3DATA */ -#define DCAN_IF3DATA_DCAN_IF3DATA (0xFFFFFFFFu) -#define DCAN_IF3DATA_DCAN_IF3DATA_SHIFT (0x00000000u) - - -/* IF3DATB */ -#define DCAN_IF3DATB_DCAN_IF3DATB (0xFFFFFFFFu) -#define DCAN_IF3DATB_DCAN_IF3DATB_SHIFT (0x00000000u) - - -/* IF3UPD12 */ -#define DCAN_IF3UPD12_IF3UPDEN_16_1 (0x0000FFFFu) -#define DCAN_IF3UPD12_IF3UPDEN_16_1_SHIFT (0x00000001u) - -#define DCAN_IF3UPD12_IF3UPDEN_32_17 (0xFFFF0000u) -#define DCAN_IF3UPD12_IF3UPDEN_32_17_SHIFT (0x00000010u) - - -/* IF3UPD34 */ -#define DCAN_IF3UPD34_IF3UPDEN_48_33 (0x0000FFFFu) -#define DCAN_IF3UPD34_IF3UPDEN_48_33_SHIFT (0x00000001u) - -#define DCAN_IF3UPD34_IF3UPDEN_64_49 (0xFFFF0000u) -#define DCAN_IF3UPD34_IF3UPDEN_64_49_SHIFT (0x00000010u) - - -/* IF3UPD56 */ -#define DCAN_IF3UPD56_IF3UPDEN_80_65 (0x0000FFFFu) -#define DCAN_IF3UPD56_IF3UPDEN_80_65_SHIFT (0x00000001u) - -#define DCAN_IF3UPD56_IF3UPDEN_96_81 (0xFFFF0000u) -#define DCAN_IF3UPD56_IF3UPDEN_96_81_SHIFT (0x00000010u) - - -/* IF3UPD78 */ -#define DCAN_IF3UPD78_IF3UPDEN_112_97 (0x0000FFFFu) -#define DCAN_IF3UPD78_IF3UPDEN_112_97_SHIFT (0x00000001u) - -#define DCAN_IF3UPD78_IF3UPDEN_128_113 (0xFFFF0000u) -#define DCAN_IF3UPD78_IF3UPDEN_128_113_SHIFT (0x00000010u) - - -/* TIOC */ -#define DCAN_TIOC_DIR (0x00000004u) -#define DCAN_TIOC_DIR_SHIFT (0x00000002u) -#define DCAN_TIOC_DIR_INPUT (0x0u) -#define DCAN_TIOC_DIR_OUTPUT (0x1u) - -#define DCAN_TIOC_FUNC (0x00000008u) -#define DCAN_TIOC_FUNC_SHIFT (0x00000003u) -#define DCAN_TIOC_FUNC_FUNCTIONAL (0x1u) -#define DCAN_TIOC_FUNC_GIO (0x0u) - -#define DCAN_TIOC_IN (0x00000001u) -#define DCAN_TIOC_IN_SHIFT (0x00000000u) -#define DCAN_TIOC_IN_HIGH (0x1u) -#define DCAN_TIOC_IN_LOW (0x0u) - -#define DCAN_TIOC_OD (0x00010000u) -#define DCAN_TIOC_OD_SHIFT (0x00000010u) -#define DCAN_TIOC_OD_OPEN_DRAIN (0x1u) -#define DCAN_TIOC_OD_PUSH_PULL (0x0u) - -#define DCAN_TIOC_OUT (0x00000002u) -#define DCAN_TIOC_OUT_SHIFT (0x00000001u) -#define DCAN_TIOC_OUT_HIGH (0x1u) -#define DCAN_TIOC_OUT_LOW (0x0u) - -#define DCAN_TIOC_PD (0x00020000u) -#define DCAN_TIOC_PD_SHIFT (0x00000011u) -#define DCAN_TIOC_PD_ACTIVE (0x0u) -#define DCAN_TIOC_PD_DISABLED (0x1u) - -#define DCAN_TIOC_PU (0x00040000u) -#define DCAN_TIOC_PU_SHIFT (0x00000011u) -#define DCAN_TIOC_PU_PULL_DOWN (0x0u) -#define DCAN_TIOC_PU_PULL_UP (0x1u) - - -/* RIOC */ -#define DCAN_RIOC_DIR (0x00000004u) -#define DCAN_RIOC_DIR_SHIFT (0x00000002u) -#define DCAN_RIOC_DIR_INPUT (0x0u) -#define DCAN_RIOC_DIR_OUTPUT (0x1u) - -#define DCAN_RIOC_FUNC (0x00000008u) -#define DCAN_RIOC_FUNC_SHIFT (0x00000003u) -#define DCAN_RIOC_FUNC_FUNCTIONAL (0x1u) -#define DCAN_RIOC_FUNC_GIO (0x0u) - -#define DCAN_RIOC_IN (0x00000001u) -#define DCAN_RIOC_IN_SHIFT (0x00000000u) -#define DCAN_RIOC_IN_HIGH (0x1u) -#define DCAN_RIOC_IN_LOW (0x0u) - -#define DCAN_RIOC_OD (0x00010000u) -#define DCAN_RIOC_OD_SHIFT (0x00000010u) -#define DCAN_RIOC_OD_OPEN_DRAIN (0x1u) -#define DCAN_RIOC_OD_PUSH_PULL (0x0u) - -#define DCAN_RIOC_OUT (0x00000002u) -#define DCAN_RIOC_OUT_SHIFT (0x00000001u) -#define DCAN_RIOC_OUT_HIGH (0x1u) -#define DCAN_RIOC_OUT_LOW (0x0u) - -#define DCAN_RIOC_PD (0x00020000u) -#define DCAN_RIOC_PD_SHIFT (0x00000011u) -#define DCAN_RIOC_PD_ACTIVE (0x0u) -#define DCAN_RIOC_PD_DISABLED (0x1u) - -#define DCAN_RIOC_PU (0x00020000u) -#define DCAN_RIOC_PU_SHIFT (0x00000011u) -#define DCAN_RIOC_PU_PULL_DOWN (0x0u) -#define DCAN_RIOC_PU_PULL_UP (0x1u) - - - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/lib/tiam1808/tiam1808/hw/hw_dspcache.h b/lib/tiam1808/tiam1808/hw/hw_dspcache.h deleted file mode 100644 index 55894f8a1..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_dspcache.h +++ /dev/null @@ -1,205 +0,0 @@ -/** - * \file hw_cache.h - * - * \brief Hardware registers and fields for cache module - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef HW_CACHE_H_ -#define HW_CACHE_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/****************************************************************************** -** DSP MEMORY SYSTEM REGISTER OFFSETS -******************************************************************************/ -#define DSPCACHE_L2CFG (0x0000) -#define DSPCACHE_L1PCFG (0x0020) -#define DSPCACHE_L1PCC (0x0024) -#define DSPCACHE_L1DCFG (0x0040) -#define DSPCACHE_L1DCC (0x0044) -#define DSPCACHE_L2WBAR (0x4000) -#define DSPCACHE_L2WWC (0x4004) -#define DSPCACHE_L2WIBAR (0x4010) -#define DSPCACHE_L2WIWC (0x4014) -#define DSPCACHE_L2IBAR (0x4018) -#define DSPCACHE_L2IWC (0x401C) -#define DSPCACHE_L1PIBAR (0x4020) -#define DSPCACHE_L1PIWC (0x4024) -#define DSPCACHE_L1DWIBAR (0x4030) -#define DSPCACHE_L1DWIWC (0x4034) -#define DSPCACHE_L1DWBAR (0x4040) -#define DSPCACHE_L1DWWC (0x4044) -#define DSPCACHE_L1DIBAR (0x4048) -#define DSPCACHE_L1DIWC (0x404C) -#define DSPCACHE_L2WB (0x5000) -#define DSPCACHE_L2WBINV (0x5004) -#define DSPCACHE_L2INV (0x5008) -#define DSPCACHE_L1PINV (0x5028) -#define DSPCACHE_L1DWB (0x5040) -#define DSPCACHE_L1DWBINV (0x5044) -#define DSPCACHE_L1DINV (0x5048) -#define DSPCACHE_MAR(n) (0x8000 + ((n)*4)) - - -/****************************************************************************** -** FIELD DEFINITION MACROS -******************************************************************************/ -/** - * \registers L1P CACHE - * - * \brief These registers allow for changing L1P cache modes and manually - * initiating cache coherence operations. - */ - -/* L1PCFG */ -#define DSPCACHE_L1PCFG_L1PMODE (0x00000007) -#define DSPCACHE_L1PCFG_L1PMODE_SHIFT (0x00000000) - -/* L1PCC */ -#define DSPCACHE_L1PCC_POPER (0x00010000) -#define DSPCACHE_L1PCC_POPER_SHIFT (0x00000010) -#define DSPCACHE_L1PCC_OPER (0x00000001) -#define DSPCACHE_L1PCC_OPER_SHIFT (0x00000000) - -/* L1PIWC */ -#define DSPCACHE_L1PIWC_L1PIWC (0x0000FFFF) -#define DSPCACHE_L1PIWC_L1PIWC_SHIFT (0x00000000) - -/* L1PINV */ -#define DSPCACHE_L1PINV_I (0x00000001) -#define DSPCACHE_L1PINV_I_SHIFT (0x00000000) - - -/** - * \registers L1D CACHE - * - * \brief These registers allow for changing L1D cache modes and manually - * initiating cache coherence operations. - */ - -/* L1DCFG */ -#define DSPCACHE_L1DCFG_L1DMODE (0x00000007) -#define DSPCACHE_L1DCFG_L1DMODE_SHIFT (0x00000000) - -/* L1DCC */ -#define DSPCACHE_L1DCC_POPER (0x00010000) -#define DSPCACHE_L1DCC_POPER_SHIFT (0x00000010) -#define DSPCACHE_L1DCC_OPER (0x00000001) -#define DSPCACHE_L1DCC_OPER_SHIFT (0x00000000) - -/* L1DWIWC */ -#define DSPCACHE_L1DWIWC_L1DWIWC (0x0000FFFF) -#define DSPCACHE_L1DWIWC_L1DWIWC_SHIFT (0x00000000) - -/* L1DWWC */ -#define DSPCACHE_L1DWWC_L1DWWC (0x0000FFFF) -#define DSPCACHE_L1DWWC_L1DWWC_SHIFT (0x00000000) - -/* L1DIWC */ -#define DSPCACHE_L1DIWC_L1DIWC (0x0000FFFF) -#define DSPCACHE_L1DIWC_L1DIWC_SHIFT (0x00000000) - -/* L1DWB */ -#define DSPCACHE_L1DWB_C (0x00000001) -#define DSPCACHE_L1DWB_C_SHIFT (0x00000000) - -/* L1DWBINV */ -#define DSPCACHE_L1DWBINV_C (0x00000001) -#define DSPCACHE_L1DWBINV_C_SHIFT (0x00000000) - -/* L1DINV */ -#define DSPCACHE_L1DINV_I (0x00000001) -#define DSPCACHE_L1DINV_I_SHIFT (0x00000000) - - -/** - * \registers L2 CACHE - * - * \brief These registers allow for changing L2 cache modes and manually - * initiating cache coherence operations. - */ - -/* L2CFG */ -#define DSPCACHE_L2CFG_L2MODE (0x00000007) -#define DSPCACHE_L2CFG_L2MODE_SHIFT (0x00000000) -#define DSPCACHE_L2CFG_L2CC (0x00000008) -#define DSPCACHE_L2CFG_L2CC_SHIFT (0x00000003) -#define DSPCACHE_L2CFG_ID (0x00000100) -#define DSPCACHE_L2CFG_ID_SHIFT (0x00000008) -#define DSPCACHE_L2CFG_IP (0x00000200) -#define DSPCACHE_L2CFG_IP_SHIFT (0x00000009) -#define DSPCACHE_L2CFG_MMID (0x000F0000) -#define DSPCACHE_L2CFG_MMID_SHIFT (0x00000010) -#define DSPCACHE_L2CFG_NUM_MM (0x0F000000) -#define DSPCACHE_L2CFG_NUM_MM_SHIFT (0x00000018) - -/* L2WWC */ -#define DSPCACHE_L2WWC_L2WWC (0x0000FFFF) -#define DSPCACHE_L2WWC_L2WWC_SHIFT (0x00000000) - -/* L2WIWC */ -#define DSPCACHE_L2WIWC_L2WIWC (0x0000FFFF) -#define DSPCACHE_L2WIWC_L2WIWC_SHIFT (0x00000000) - -/* L2IWC */ -#define DSPCACHE_L2IWC_L2IWC (0x0000FFFF) -#define DSPCACHE_L2IWC_L2IWC_SHIFT (0x00000000) - -/* L2WB */ -#define DSPCACHE_L2WB_C (0x00000001) -#define DSPCACHE_L2WB_C_SHIFT (0x00000000) - -/* L2WBINV */ -#define DSPCACHE_L2WBINV_C (0x00000001) -#define DSPCACHE_L2WBINV_C_SHIFT (0x00000000) - -/* L2INV */ -#define DSPCACHE_L2INV_I (0x00000001) -#define DSPCACHE_L2INV_I_SHIFT (0x00000000) - -/* MAR */ -#define DSPCACHE_MAR_PC (0x00000001) -#define DSPCACHE_MAR_PC_SHIFT (0x00000000) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_dspintc.h b/lib/tiam1808/tiam1808/hw/hw_dspintc.h deleted file mode 100644 index 10134adc9..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_dspintc.h +++ /dev/null @@ -1,176 +0,0 @@ -/** - * \file hw_dspintc.h - * - * \brief Hardware registers and fields for DSP interrupt controller - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef HW_DSPINTC_H_ -#define HW_DSPINTC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/****************************************************************************** -** DSP INTC REGISTER OFFSETS -******************************************************************************/ -/** - * \brief Macros used in conjunction with DSP interrupt controller - * base address for register addressing - * - * \param n - Register instance - * - * \note Minimum unit = 1 byte; Registers are 4 bytes - */ -#define DSPINTC_EVTFLAG(n) (0x00000 + ((n)*4)) -#define DSPINTC_EVTSET(n) (0x00020 + ((n)*4)) -#define DSPINTC_EVTCLR(n) (0x00040 + ((n)*4)) -#define DSPINTC_EVTMASK(n) (0x00080 + ((n)*4)) -#define DSPINTC_MEVTFLAG(n) (0x000A0 + ((n)*4)) -#define DSPINTC_EXPMASK(n) (0x000C0 + ((n)*4)) -#define DSPINTC_MEXPFLAG(n) (0x000E0 + ((n)*4)) -#define DSPINTC_INTMUX(n) (0x00100 + ((n)*4)) -#define DSPINTC_INTXSTAT (0x00180) -#define DSPINTC_INTXCLR (0x00184) -#define DSPINTC_INTDMASK (0x00188) -#define DSPINTC_AEGMUX(n) (0x10140 + ((n)*4)) - - -/****************************************************************************** -** FIELD DEFINITION MACROS -******************************************************************************/ -/** - * \registers EVENT REGISTERS - * - * \brief These registers manage the system events that are received by - * the controller. These include flag, set, and clear registers - * covering all system events. - * - * \param n - Any system event - * - * \note Shifting by (n & 31) ensures 0x1 does not shift by more than - * 31 bits for system event IDs larger than 31. The proper event - * register must first be identified. - */ - -/* Event Flag */ -#define DSPINTC_EVTFLAG_EF(n) (0x1 << ((n) & 31)) - -/* Event Set */ -#define DSPINTC_EVTSET_ES(n) (0x1 << ((n) & 31)) - -/* Event Clear */ -#define DSPINTC_EVTCLR_EC(n) (0x1 << ((n) & 31)) - - -/** - * \registers EVENT COMBINER REGISTERS - * - * \brief These registers allow up to 32 events to be combined into a - * single combined event which can then be used by the interrupt - * selector. - * - * \param n - Any system event - * - * \note Shifting by (n & 31) ensures 0x1 does not shift by more than - * 31 bits for system event IDs larger than 31. The proper event - * combiner register must first be identified. - */ - -/* Event Mask */ -#define DSPINTC_EVTMASK_EM(n) (0x1 << ((n) & 31)) - -/* Masked Event Flag */ -#define DSPINTC_MEVTFLAG_MEF(n) (0x1 << ((n) & 31)) - - -/** - * \registers CPU INTERRUPT SELECTOR REGISTERS - * - * \brief These registers manage which system events trigger the - * available CPU interrupts and also provide interrupt exception - * information. - * - * \param n - Any CPU maskable interrupt - */ - -/* Interrupt Mux */ -#define DSPINTC_INTMUX_INTSEL_SHIFT(n) (((n) & 0x3) * 8) -#define DSPINTC_INTMUX_INTSEL(n) (0x7F << DSPINTC_INTMUX_INTSEL_SHIFT(n)) - -/* Interrupt Exception Status */ -#define DSPINTC_INTXSTAT_SYSINT (0xFF000000u) -#define DSPINTC_INTXSTAT_SYSINT_SHIFT (0x00000018u) -#define DSPINTC_INTXSTAT_CPUINT (0x00FF0000u) -#define DSPINTC_INTXSTAT_CPUINT_SHIFT (0x00000010u) -#define DSPINTC_INTXSTAT_DROP (0x00000001u) -#define DSPINTC_INTXSTAT_DROP_SHIFT (0x00000000u) - -/* Interrupt Exception Clear */ -#define DSPINTC_INTXCLR_CLEAR (0x00000001u) -#define DSPINTC_INTXCLR_CLEAR_SHIFT (0x00000000u) - -/* Dropped Interrupt Mask */ -#define DSPINTC_INTDMASK_IDM(n) (0x1 << (n)) - - -/** - * \registers CPU EXCEPTION REGISTERS - * - * \brief - * - * \param - * - * \note Not yet defined... - */ - -/** - * \registers ADVANCED EVENT GENERATOR MUX REGISTERS - * - * \brief - * - * \param - * - * \note Not yet defined... - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HW_DSPINTC_H_ */ diff --git a/lib/tiam1808/tiam1808/hw/hw_elm.h b/lib/tiam1808/tiam1808/hw/hw_elm.h deleted file mode 100644 index fc71d0b5b..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_elm.h +++ /dev/null @@ -1,396 +0,0 @@ - - -/** - * @Component: ELM - * - * @Filename: hw_elm.h - * - ============================================================================ */ -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - - -#ifndef _HW_ELM_H_ -#define _HW_ELM_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***********************************************************************\ - * Register arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundle arrays Definition -\***********************************************************************/ - -#define ELM_SYNDROMES (0x400u) -#define ELM_SYNDROMES_ELSIZE (0x40u) -#define ELM_SYNDROMES_NELEMS 8 -#define ELM_ERROR_LOCATIONS (0x800u) -#define ELM_ERROR_LOCATIONS_ELSIZE (0x100u) -#define ELM_ERROR_LOCATIONS_NELEMS 8 - -/***********************************************************************\ - * Bundles Definition -\***********************************************************************/ - -#define ELM_SYNDROME_FRAGMENT_0_OFFSET (0x0u) -#define ELM_SYNDROME_FRAGMENT_1_OFFSET (0x4u) -#define ELM_SYNDROME_FRAGMENT_2_OFFSET (0x8u) -#define ELM_SYNDROME_FRAGMENT_3_OFFSET (0xCu) -#define ELM_SYNDROME_FRAGMENT_4_OFFSET (0x10u) -#define ELM_SYNDROME_FRAGMENT_5_OFFSET (0x14u) -#define ELM_SYNDROME_FRAGMENT_6_OFFSET (0x18u) -#define ELM_LOCATION_STATUS_OFFSET (0x0u) -#define ELM_ERROR_LOCATION_0_OFFSET (0x80u) -#define ELM_ERROR_LOCATION_1_OFFSET (0x84u) -#define ELM_ERROR_LOCATION_2_OFFSET (0x88u) -#define ELM_ERROR_LOCATION_3_OFFSET (0x8Cu) -#define ELM_ERROR_LOCATION_4_OFFSET (0x90u) -#define ELM_ERROR_LOCATION_5_OFFSET (0x94u) -#define ELM_ERROR_LOCATION_6_OFFSET (0x98u) -#define ELM_ERROR_LOCATION_7_OFFSET (0x9Cu) -#define ELM_ERROR_LOCATION_8_OFFSET (0xA0u) -#define ELM_ERROR_LOCATION_9_OFFSET (0xA4u) -#define ELM_ERROR_LOCATION_10_OFFSET (0xA8u) -#define ELM_ERROR_LOCATION_11_OFFSET (0xACu) -#define ELM_ERROR_LOCATION_12_OFFSET (0xB0u) -#define ELM_ERROR_LOCATION_13_OFFSET (0xB4u) -#define ELM_ERROR_LOCATION_14_OFFSET (0xB8u) -#define ELM_ERROR_LOCATION_15_OFFSET (0xBCu) - - -/*************************************************************************\ - * Registers Definition -\*************************************************************************/ - -#define ELM_REVISION (0x0) -#define ELM_SYSCONFIG (0x10) -#define ELM_SYSSTATUS (0x14) -#define ELM_IRQSTATUS (0x18) -#define ELM_IRQENABLE (0x1C) -#define ELM_LOCATION_CONFIG (0x20) -#define ELM_PAGE_CTRL (0x80) -#define ELM_SYNDROME_FRAGMENT(n) (0x400 + (n * 4)) -#define ELM_LOCATION_STATUS (0x800) -#define ELM_ERROR_LOCATION(n) (0x880 + (n * 4)) - -/**************************************************************************\ - * Field Definition Macros -\**************************************************************************/ - -/* REVISION */ -#define ELM_REVISION_REVISION (0xFFFFFFFFu) -#define ELM_REVISION_REVISION_SHIFT (0x00000000u) - -#define ELM_REVISION_REV_NUMBER (0x000000FFu) -#define ELM_REVISION_REV_NUMBER_SHIFT (0x00000000u) - - -/* SYSCONFIG */ -#define ELM_SYSCONFIG_AUTOGATING (0x00000001u) -#define ELM_SYSCONFIG_AUTOGATING_SHIFT (0x00000000u) -#define ELM_SYSCONFIG_AUTOGATING_OCP_FREE (0x0u) -#define ELM_SYSCONFIG_AUTOGATING_OCP_GATING (0x1u) - -#define ELM_SYSCONFIG_CLOCKACTIVITYOCP (0x00000100u) -#define ELM_SYSCONFIG_CLOCKACTIVITYOCP_SHIFT (0x00000008u) -#define ELM_SYSCONFIG_CLOCKACTIVITYOCP_OCP_OFF (0x0u) -#define ELM_SYSCONFIG_CLOCKACTIVITYOCP_OCP_ON (0x1u) - -#define ELM_SYSCONFIG_SIDLEMODE (0x00000018u) -#define ELM_SYSCONFIG_SIDLEMODE_SHIFT (0x00000003u) -#define ELM_SYSCONFIG_SIDLEMODE_FORCE_IDLE (0x0u) -#define ELM_SYSCONFIG_SIDLEMODE_NO_IDLE (0x1u) -#define ELM_SYSCONFIG_SIDLEMODE_RESERVED (0x3u) -#define ELM_SYSCONFIG_SIDLEMODE_SMART_IDLE (0x2u) - -#define ELM_SYSCONFIG_SOFTRESET (0x00000002u) -#define ELM_SYSCONFIG_SOFTRESET_SHIFT (0x00000001u) -#define ELM_SYSCONFIG_SOFTRESET_NORMAL (0x0u) -#define ELM_SYSCONFIG_SOFTRESET_RESET (0x1u) - - -/* SYSSTATUS */ -#define ELM_SYSSTATUS_RESETDONE (0x00000001u) -#define ELM_SYSSTATUS_RESETDONE_SHIFT (0x00000000u) -#define ELM_SYSSTATUS_RESETDONE_RST_DONE (0x1u) -#define ELM_SYSSTATUS_RESETDONE_RST_ONGOING (0x0u) - - -/* IRQSTATUS */ -#define ELM_IRQSTATUS_LOC_VALID_0 (0x00000001u) -#define ELM_IRQSTATUS_LOC_VALID_0_SHIFT (0x00000000u) - -#define ELM_IRQSTATUS_LOC_VALID_1 (0x00000002u) -#define ELM_IRQSTATUS_LOC_VALID_1_SHIFT (0x00000001u) - -#define ELM_IRQSTATUS_LOC_VALID_2 (0x00000004u) -#define ELM_IRQSTATUS_LOC_VALID_2_SHIFT (0x00000002u) - -#define ELM_IRQSTATUS_LOC_VALID_3 (0x00000008u) -#define ELM_IRQSTATUS_LOC_VALID_3_SHIFT (0x00000003u) - -#define ELM_IRQSTATUS_LOC_VALID_4 (0x00000010u) -#define ELM_IRQSTATUS_LOC_VALID_4_SHIFT (0x00000004u) - -#define ELM_IRQSTATUS_LOC_VALID_5 (0x00000020u) -#define ELM_IRQSTATUS_LOC_VALID_5_SHIFT (0x00000005u) - -#define ELM_IRQSTATUS_LOC_VALID_6 (0x00000040u) -#define ELM_IRQSTATUS_LOC_VALID_6_SHIFT (0x00000006u) - -#define ELM_IRQSTATUS_LOC_VALID_7 (0x00000080u) -#define ELM_IRQSTATUS_LOC_VALID_7_SHIFT (0x00000007u) -#define ELM_IRQSTATUS_LOC_VALID_7_CLEAR (0x1u) -#define ELM_IRQSTATUS_LOC_VALID_7_COMPLETED (0x1u) -#define ELM_IRQSTATUS_LOC_VALID_7_NO (0x0u) - -#define ELM_IRQSTATUS_PAGE_VALID (0x00000100u) -#define ELM_IRQSTATUS_PAGE_VALID_SHIFT (0x00000008u) -#define ELM_IRQSTATUS_PAGE_VALID_CLEAR (0x1u) -#define ELM_IRQSTATUS_PAGE_VALID_INVALID (0x0u) -#define ELM_IRQSTATUS_PAGE_VALID_VALID (0x1u) - - -/* IRQENABLE */ -#define ELM_IRQENABLE_LOCATION_MASK_0 (0x00000001u) -#define ELM_IRQENABLE_LOCATION_MASK_0_SHIFT (0x00000000u) -#define ELM_IRQENABLE_LOCATION_MASK_0_DISABLE (0x0u) -#define ELM_IRQENABLE_LOCATION_MASK_0_ENABLE (0x1u) - -#define ELM_IRQENABLE_LOCATION_MASK_1 (0x00000002u) -#define ELM_IRQENABLE_LOCATION_MASK_1_SHIFT (0x00000001u) - -#define ELM_IRQENABLE_LOCATION_MASK_2 (0x00000004u) -#define ELM_IRQENABLE_LOCATION_MASK_2_SHIFT (0x00000002u) - -#define ELM_IRQENABLE_LOCATION_MASK_3 (0x00000008u) -#define ELM_IRQENABLE_LOCATION_MASK_3_SHIFT (0x00000003u) - -#define ELM_IRQENABLE_LOCATION_MASK_4 (0x00000010u) -#define ELM_IRQENABLE_LOCATION_MASK_4_SHIFT (0x00000004u) - -#define ELM_IRQENABLE_LOCATION_MASK_5 (0x00000020u) -#define ELM_IRQENABLE_LOCATION_MASK_5_SHIFT (0x00000005u) - -#define ELM_IRQENABLE_LOCATION_MASK_6 (0x00000040u) -#define ELM_IRQENABLE_LOCATION_MASK_6_SHIFT (0x00000006u) - -#define ELM_IRQENABLE_LOCATION_MASK_7 (0x00000080u) -#define ELM_IRQENABLE_LOCATION_MASK_7_SHIFT (0x00000007u) - -#define ELM_IRQENABLE_PAGE_MASK (0x00000100u) -#define ELM_IRQENABLE_PAGE_MASK_SHIFT (0x00000008u) -#define ELM_IRQENABLE_PAGE_MASK_DISABLE (0x0u) -#define ELM_IRQENABLE_PAGE_MASK_ENABLE (0x1u) - - -/* LOCATION_CONFIG */ -#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL (0x00000003u) -#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_SHIFT (0x00000000u) -#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_16BITS (0x2u) -#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_4BITS (0x0u) -#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_8BITS (0x1u) - -#define ELM_LOCATION_CONFIG_ECC_SIZE (0x07FF0000u) -#define ELM_LOCATION_CONFIG_ECC_SIZE_SHIFT (0x00000010u) - - -/* PAGE_CTRL */ -#define ELM_PAGE_CTRL_SECTOR_0 (0x00000001u) -#define ELM_PAGE_CTRL_SECTOR_0_SHIFT (0x00000000u) - -#define ELM_PAGE_CTRL_SECTOR_1 (0x00000002u) -#define ELM_PAGE_CTRL_SECTOR_1_SHIFT (0x00000001u) - -#define ELM_PAGE_CTRL_SECTOR_2 (0x00000004u) -#define ELM_PAGE_CTRL_SECTOR_2_SHIFT (0x00000002u) - -#define ELM_PAGE_CTRL_SECTOR_3 (0x00000008u) -#define ELM_PAGE_CTRL_SECTOR_3_SHIFT (0x00000003u) - -#define ELM_PAGE_CTRL_SECTOR_4 (0x00000010u) -#define ELM_PAGE_CTRL_SECTOR_4_SHIFT (0x00000004u) - -#define ELM_PAGE_CTRL_SECTOR_5 (0x00000020u) -#define ELM_PAGE_CTRL_SECTOR_5_SHIFT (0x00000005u) - -#define ELM_PAGE_CTRL_SECTOR_6 (0x00000040u) -#define ELM_PAGE_CTRL_SECTOR_6_SHIFT (0x00000006u) - -#define ELM_PAGE_CTRL_SECTOR_7 (0x00000080u) -#define ELM_PAGE_CTRL_SECTOR_7_SHIFT (0x00000007u) - - -/* SYNDROME_FRAGMENT_0 */ -#define ELM_SYNDROME_FRAGMENT_0_SYNDROME_0 (0xFFFFFFFFu) -#define ELM_SYNDROME_FRAGMENT_0_SYNDROME_0_SHIFT (0x00000000u) - - -/* SYNDROME_FRAGMENT_1 */ -#define ELM_SYNDROME_FRAGMENT_1_SYNDROME_1 (0xFFFFFFFFu) -#define ELM_SYNDROME_FRAGMENT_1_SYNDROME_1_SHIFT (0x00000000u) - - -/* SYNDROME_FRAGMENT_2 */ -#define ELM_SYNDROME_FRAGMENT_2_SYNDROME_2 (0xFFFFFFFFu) -#define ELM_SYNDROME_FRAGMENT_2_SYNDROME_2_SHIFT (0x00000000u) - - -/* SYNDROME_FRAGMENT_3 */ -#define ELM_SYNDROME_FRAGMENT_3_SYNDROME_3 (0xFFFFFFFFu) -#define ELM_SYNDROME_FRAGMENT_3_SYNDROME_3_SHIFT (0x00000000u) - - -/* SYNDROME_FRAGMENT_4 */ -#define ELM_SYNDROME_FRAGMENT_4_SYNDROME_4 (0xFFFFFFFFu) -#define ELM_SYNDROME_FRAGMENT_4_SYNDROME_4_SHIFT (0x00000000u) - - -/* SYNDROME_FRAGMENT_5 */ -#define ELM_SYNDROME_FRAGMENT_5_SYNDROME_5 (0xFFFFFFFFu) -#define ELM_SYNDROME_FRAGMENT_5_SYNDROME_5_SHIFT (0x00000000u) - - -/* SYNDROME_FRAGMENT_6 */ -#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_6 (0x0000FFFFu) -#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_6_SHIFT (0x00000000u) - -#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000u) -#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID_SHIFT (0x00000010u) - - -/* LOCATION_STATUS */ -#define ELM_LOCATION_STATUS_ECC_CORRECTABLE (0x00000100u) -#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_SHIFT (0x00000008u) -#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_FAIL (0x0u) -#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_SUCCESS (0x1u) - -#define ELM_LOCATION_STATUS_ECC_NB_ERRORS (0x0000001Fu) -#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_0 */ -#define ELM_ERROR_LOCATION_0_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_0_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_1 */ -#define ELM_ERROR_LOCATION_1_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_1_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_2 */ -#define ELM_ERROR_LOCATION_2_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_2_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_3 */ -#define ELM_ERROR_LOCATION_3_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_3_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_4 */ -#define ELM_ERROR_LOCATION_4_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_4_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_5 */ -#define ELM_ERROR_LOCATION_5_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_5_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_6 */ -#define ELM_ERROR_LOCATION_6_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_6_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_7 */ -#define ELM_ERROR_LOCATION_7_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_7_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_8 */ -#define ELM_ERROR_LOCATION_8_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_8_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_9 */ -#define ELM_ERROR_LOCATION_9_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_9_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_10 */ -#define ELM_ERROR_LOCATION_10_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_10_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_11 */ -#define ELM_ERROR_LOCATION_11_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_11_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_12 */ -#define ELM_ERROR_LOCATION_12_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_12_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_13 */ -#define ELM_ERROR_LOCATION_13_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_13_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_14 */ -#define ELM_ERROR_LOCATION_14_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_14_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - -/* ERROR_LOCATION_15 */ -#define ELM_ERROR_LOCATION_15_ECC_ERROR_LOCATION (0x00001FFFu) -#define ELM_ERROR_LOCATION_15_ECC_ERROR_LOCATION_SHIFT (0x00000000u) - - - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/lib/tiam1808/tiam1808/hw/hw_emac.h b/lib/tiam1808/tiam1808/hw/hw_emac.h deleted file mode 100644 index 7e4026139..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_emac.h +++ /dev/null @@ -1,1468 +0,0 @@ -/** - * \file hw_emac.h - * - * \brief EMAC register definitions - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _HW_EMAC_H_ -#define _HW_EMAC_H_ - -#define EMAC_TXREVID (0x0) -#define EMAC_TXCONTROL (0x4) -#define EMAC_TXTEARDOWN (0x8) -#define EMAC_RXREVID (0x10) -#define EMAC_RXCONTROL (0x14) -#define EMAC_RXTEARDOWN (0x18) -#define EMAC_TXINTSTATRAW (0x80) -#define EMAC_TXINTSTATMASKED (0x84) -#define EMAC_TXINTMASKSET (0x88) -#define EMAC_TXINTMASKCLEAR (0x8C) -#define EMAC_MACINVECTOR (0x90) -#define EMAC_MACEOIVECTOR (0x94) -#define EMAC_RXINTSTATRAW (0xA0) -#define EMAC_RXINTSTATMASKED (0xA4) -#define EMAC_RXINTMASKSET (0xA8) -#define EMAC_RXINTMASKCLEAR (0xAC) -#define EMAC_MACINTSTATRAW (0xB0) -#define EMAC_MACINTSTATMASKED (0xB4) -#define EMAC_MACINTMASKSET (0xB8) -#define EMAC_MACINTMASKCLEAR (0xBC) -#define EMAC_RXMBPENABLE (0x100) -#define EMAC_RXUNICASTSET (0x104) -#define EMAC_RXUNICASTCLEAR (0x108) -#define EMAC_RXMAXLEN (0x10C) -#define EMAC_RXBUFFEROFFSET (0x110) -#define EMAC_RXFILTERLOWTHRESH (0x114) -#define EMAC_RXFLOWTHRESH(n) (0x120 + (n * 4)) -#define EMAC_RXFREEBUFFER(n) (0x140 + (n * 4)) -#define EMAC_MACCONTROL (0x160) -#define EMAC_MACSTATUS (0x164) -#define EMAC_EMCONTROL (0x168) -#define EMAC_FIFOCONTROL (0x16C) -#define EMAC_MACCONFIG (0x170) -#define EMAC_SOFTRESET (0x174) -#define EMAC_MACSRCADDRLO (0x1D0) -#define EMAC_MACSRCADDRHI (0x1D4) -#define EMAC_MACHASH1 (0x1D8) -#define EMAC_MACHASH2 (0x1DC) -#define EMAC_BOFFTEST (0x1E0) -#define EMAC_TPACETEST (0x1E4) -#define EMAC_RXPAUSE (0x1E8) -#define EMAC_TXPAUSE (0x1EC) -#define EMAC_RXGOODFRAMES (0x200) -#define EMAC_RXBCASTFRAMES (0x204) -#define EMAC_RXMCASTFRAMES (0x208) -#define EMAC_RXPAUSEFRAMES (0x20C) -#define EMAC_RXCRCERRORS (0x210) -#define EMAC_RXALIGNCODEERRORS (0x214) -#define EMAC_RXOVERSIZED (0x218) -#define EMAC_RXJABBER (0x21C) -#define EMAC_RXUNDERSIZED (0x220) -#define EMAC_RXFRAGMENTS (0x224) -#define EMAC_RXFILTERED (0x228) -#define EMAC_RXQOSFILTERED (0x22C) -#define EMAC_RXOCTETS (0x230) -#define EMAC_TXGOODFRAMES (0x234) -#define EMAC_TXBCASTFRAMES (0x238) -#define EMAC_TXMCASTFRAMES (0x23C) -#define EMAC_TXPAUSEFRAMES (0x240) -#define EMAC_TXDEFERRED (0x244) -#define EMAC_TXCOLLISION (0x248) -#define EMAC_TXSINGLECOLL (0x24C) -#define EMAC_TXMULTICOLL (0x250) -#define EMAC_TXEXCESSIVECOLL (0x254) -#define EMAC_TXLATECOLL (0x258) -#define EMAC_TXUNDERRUN (0x25C) -#define EMAC_TXCARRIERSENSE (0x260) -#define EMAC_TXOCTETS (0x264) -#define EMAC_FRAME64 (0x268) -#define EMAC_FRAME65T127 (0x26C) -#define EMAC_FRAME128T255 (0x270) -#define EMAC_FRAME256T511 (0x274) -#define EMAC_FRAME512T1023 (0x278) -#define EMAC_FRAME1024TUP (0x27C) -#define EMAC_NETOCTETS (0x208) -#define EMAC_RXSOFOVERRUNS (0x284) -#define EMAC_RXMOFOVERRUNS (0x288) -#define EMAC_RXDMAOVERRUNS (0x28C) -#define EMAC_MACADDRLO (0x500) -#define EMAC_MACADDRHI (0x504) -#define EMAC_MACINDEX (0x508) -#define EMAC_TXHDP(n) (0x600 + (n * 4)) -#define EMAC_RXHDP(n) (0x620 + (n * 4)) -#define EMAC_TXCP(n) (0x640 + (n * 4)) -#define EMAC_RXCP(n) (0x660 + (n * 4)) - -/**************************************************************************\ -* Field Definition Macros -\**************************************************************************/ - -/* TXREVID */ - -#define EMAC_TXREVID_TXREV (0xFFFFFFFFu) -#define EMAC_TXREVID_TXREV_SHIFT (0x00000000u) - - -/* TXCONTROL */ - - -#define EMAC_TXCONTROL_TXEN (0x00000001u) -#define EMAC_TXCONTROL_TXEN_SHIFT (0x00000000u) - - -/* TXTEARDOWN */ - -#define EMAC_TXTEARDOWN_TXTDNCH (0x00000007u) -#define EMAC_TXTEARDOWN_TXTDNCH_SHIFT (0x00000000u) -#define EMAC_TXTEARDOWN_TXTDNCH_CHA0 (0x00000000u) -#define EMAC_TXTEARDOWN_TXTDNCH_CHA1 (0x00000001u) -#define EMAC_TXTEARDOWN_TXTDNCH_CHA2 (0x00000002u) -#define EMAC_TXTEARDOWN_TXTDNCH_CHA3 (0x00000003u) -#define EMAC_TXTEARDOWN_TXTDNCH_CHA4 (0x00000004u) -#define EMAC_TXTEARDOWN_TXTDNCH_CHA5 (0x00000005u) -#define EMAC_TXTEARDOWN_TXTDNCH_CHA6 (0x00000006u) -#define EMAC_TXTEARDOWN_TXTDNCH_CHA7 (0x00000007u) - - -/* RXREVID */ - -#define EMAC_RXREVID_RXREV (0xFFFFFFFFu) -#define EMAC_RXREVID_RXREV_SHIFT (0x00000000u) - - -/* RXCONTROL */ - - -#define EMAC_RXCONTROL_RXEN (0x00000001u) -#define EMAC_RXCONTROL_RXEN_SHIFT (0x00000000u) - -/* RXTEARDOWN */ - - - -#define EMAC_RXTEARDOWN_RXTDNCH (0x00000007u) -#define EMAC_RXTEARDOWN_RXTDNCH_SHIFT (0x00000000u) -#define EMAC_RXTEARDOWN_RXTDNCH_CHA0 (0x00000000u) -#define EMAC_RXTEARDOWN_RXTDNCH_CHA1 (0x00000001u) -#define EMAC_RXTEARDOWN_RXTDNCH_CHA2 (0x00000002u) -#define EMAC_RXTEARDOWN_RXTDNCH_CHA3 (0x00000003u) -#define EMAC_RXTEARDOWN_RXTDNCH_CHA4 (0x00000004u) -#define EMAC_RXTEARDOWN_RXTDNCH_CHA5 (0x00000005u) -#define EMAC_RXTEARDOWN_RXTDNCH_CHA6 (0x00000006u) -#define EMAC_RXTEARDOWN_RXTDNCH_CHA7 (0x00000007u) - - -/* TXINTSTATRAW */ - - -#define EMAC_TXINTSTATRAW_TX7PEND (0x00000080u) -#define EMAC_TXINTSTATRAW_TX7PEND_SHIFT (0x00000007u) - -#define EMAC_TXINTSTATRAW_TX6PEND (0x00000040u) -#define EMAC_TXINTSTATRAW_TX6PEND_SHIFT (0x00000006u) - -#define EMAC_TXINTSTATRAW_TX5PEND (0x00000020u) -#define EMAC_TXINTSTATRAW_TX5PEND_SHIFT (0x00000005u) - -#define EMAC_TXINTSTATRAW_TX4PEND (0x00000010u) -#define EMAC_TXINTSTATRAW_TX4PEND_SHIFT (0x00000004u) - -#define EMAC_TXINTSTATRAW_TX3PEND (0x00000008u) -#define EMAC_TXINTSTATRAW_TX3PEND_SHIFT (0x00000003u) - -#define EMAC_TXINTSTATRAW_TX2PEND (0x00000004u) -#define EMAC_TXINTSTATRAW_TX2PEND_SHIFT (0x00000002u) - -#define EMAC_TXINTSTATRAW_TX1PEND (0x00000002u) -#define EMAC_TXINTSTATRAW_TX1PEND_SHIFT (0x00000001u) - -#define EMAC_TXINTSTATRAW_TX0PEND (0x00000001u) -#define EMAC_TXINTSTATRAW_TX0PEND_SHIFT (0x00000000u) - - -/* TXINTSTATMASKED */ - - -#define EMAC_TXINTSTATMASKED_TX7PEND (0x00000080u) -#define EMAC_TXINTSTATMASKED_TX7PEND_SHIFT (0x00000007u) - -#define EMAC_TXINTSTATMASKED_TX6PEND (0x00000040u) -#define EMAC_TXINTSTATMASKED_TX6PEND_SHIFT (0x00000006u) - -#define EMAC_TXINTSTATMASKED_TX5PEND (0x00000020u) -#define EMAC_TXINTSTATMASKED_TX5PEND_SHIFT (0x00000005u) - -#define EMAC_TXINTSTATMASKED_TX4PEND (0x00000010u) -#define EMAC_TXINTSTATMASKED_TX4PEND_SHIFT (0x00000004u) - -#define EMAC_TXINTSTATMASKED_TX3PEND (0x00000008u) -#define EMAC_TXINTSTATMASKED_TX3PEND_SHIFT (0x00000003u) - -#define EMAC_TXINTSTATMASKED_TX2PEND (0x00000004u) -#define EMAC_TXINTSTATMASKED_TX2PEND_SHIFT (0x00000002u) - -#define EMAC_TXINTSTATMASKED_TX1PEND (0x00000002u) -#define EMAC_TXINTSTATMASKED_TX1PEND_SHIFT (0x00000001u) - -#define EMAC_TXINTSTATMASKED_TX0PEND (0x00000001u) -#define EMAC_TXINTSTATMASKED_TX0PEND_SHIFT (0x00000000u) - - -/* TXINTMASKSET */ - - -#define EMAC_TXINTMASKSET_TX7MASK (0x00000080u) -#define EMAC_TXINTMASKSET_TX7MASK_SHIFT (0x00000007u) - -#define EMAC_TXINTMASKSET_TX6MASK (0x00000040u) -#define EMAC_TXINTMASKSET_TX6MASK_SHIFT (0x00000006u) - -#define EMAC_TXINTMASKSET_TX5MASK (0x00000020u) -#define EMAC_TXINTMASKSET_TX5MASK_SHIFT (0x00000005u) - -#define EMAC_TXINTMASKSET_TX4MASK (0x00000010u) -#define EMAC_TXINTMASKSET_TX4MASK_SHIFT (0x00000004u) - -#define EMAC_TXINTMASKSET_TX3MASK (0x00000008u) -#define EMAC_TXINTMASKSET_TX3MASK_SHIFT (0x00000003u) - -#define EMAC_TXINTMASKSET_TX2MASK (0x00000004u) -#define EMAC_TXINTMASKSET_TX2MASK_SHIFT (0x00000002u) - -#define EMAC_TXINTMASKSET_TX1MASK (0x00000002u) -#define EMAC_TXINTMASKSET_TX1MASK_SHIFT (0x00000001u) - -#define EMAC_TXINTMASKSET_TX0MASK (0x00000001u) -#define EMAC_TXINTMASKSET_TX0MASK_SHIFT (0x00000000u) - - -/* TXINTMASKCLEAR */ - - -#define EMAC_TXINTMASKCLEAR_TX7MASK (0x00000080u) -#define EMAC_TXINTMASKCLEAR_TX7MASK_SHIFT (0x00000007u) - -#define EMAC_TXINTMASKCLEAR_TX6MASK (0x00000040u) -#define EMAC_TXINTMASKCLEAR_TX6MASK_SHIFT (0x00000006u) - -#define EMAC_TXINTMASKCLEAR_TX5MASK (0x00000020u) -#define EMAC_TXINTMASKCLEAR_TX5MASK_SHIFT (0x00000005u) - -#define EMAC_TXINTMASKCLEAR_TX4MASK (0x00000010u) -#define EMAC_TXINTMASKCLEAR_TX4MASK_SHIFT (0x00000004u) - -#define EMAC_TXINTMASKCLEAR_TX3MASK (0x00000008u) -#define EMAC_TXINTMASKCLEAR_TX3MASK_SHIFT (0x00000003u) - -#define EMAC_TXINTMASKCLEAR_TX2MASK (0x00000004u) -#define EMAC_TXINTMASKCLEAR_TX2MASK_SHIFT (0x00000002u) - -#define EMAC_TXINTMASKCLEAR_TX1MASK (0x00000002u) -#define EMAC_TXINTMASKCLEAR_TX1MASK_SHIFT (0x00000001u) - -#define EMAC_TXINTMASKCLEAR_TX0MASK (0x00000001u) -#define EMAC_TXINTMASKCLEAR_TX0MASK_SHIFT (0x00000000u) - - -/* MACINVECTOR */ - - -#define EMAC_MACINVECTOR_STATPEND (0x08000000u) -#define EMAC_MACINVECTOR_STATPEND_SHIFT (0x0000001Bu) - -#define EMAC_MACINVECTOR_HOSTPEND (0x04000000u) -#define EMAC_MACINVECTOR_HOSTPEND_SHIFT (0x0000001Au) - -#define EMAC_MACINVECTOR_LINKINT0 (0x02000000u) -#define EMAC_MACINVECTOR_LINKINT0_SHIFT (0x00000019u) - -#define EMAC_MACINVECTOR_USERINT0 (0x01000000u) -#define EMAC_MACINVECTOR_USERINT0_SHIFT (0x00000018u) - -#define EMAC_MACINVECTOR_TXPEND (0x00FF0000u) -#define EMAC_MACINVECTOR_TXPEND_SHIFT (0x00000010u) - -#define EMAC_MACINVECTOR_RXTHRESHPEND (0x0000FF00u) -#define EMAC_MACINVECTOR_RXTHRESHPEND_SHIFT (0x00000008u) - -#define EMAC_MACINVECTOR_RXPEND (0x000000FFu) -#define EMAC_MACINVECTOR_RXPEND_SHIFT (0x00000000u) - - -/* MACEOIVECTOR */ - - -#define EMAC_MACEOIVECTOR_INTVECT (0x0000001Fu) -#define EMAC_MACEOIVECTOR_INTVECT_SHIFT (0x00000000u) -/*----INTVECT Tokens----*/ -#define EMAC_MACEOIVECTOR_INTVECT_C0RXTHRESH (0x00000000u) -#define EMAC_MACEOIVECTOR_INTVECT_C0RX (0x00000001u) -#define EMAC_MACEOIVECTOR_INTVECT_C0TX (0x00000002u) -#define EMAC_MACEOIVECTOR_INTVECT_C0MISC (0x00000003u) -#define EMAC_MACEOIVECTOR_INTVECT_C1RXTHRESH (0x00000004u) -#define EMAC_MACEOIVECTOR_INTVECT_C1RX (0x00000005u) -#define EMAC_MACEOIVECTOR_INTVECT_C1TX (0x00000006u) -#define EMAC_MACEOIVECTOR_INTVECT_C1MISC (0x00000007u) - - -/* RXINTSTATRAW */ - - -#define EMAC_RXINTSTATRAW_RX7THRESHPEND (0x00008000u) -#define EMAC_RXINTSTATRAW_RX7THRESHPEND_SHIFT (0x0000000Fu) - -#define EMAC_RXINTSTATRAW_RX6THRESHPEND (0x00004000u) -#define EMAC_RXINTSTATRAW_RX6THRESHPEND_SHIFT (0x0000000Eu) - -#define EMAC_RXINTSTATRAW_RX5THRESHPEND (0x00002000u) -#define EMAC_RXINTSTATRAW_RX5THRESHPEND_SHIFT (0x0000000Du) - -#define EMAC_RXINTSTATRAW_RX4THRESHPEND (0x00001000u) -#define EMAC_RXINTSTATRAW_RX4THRESHPEND_SHIFT (0x0000000Cu) - -#define EMAC_RXINTSTATRAW_RX3THRESHPEND (0x00000800u) -#define EMAC_RXINTSTATRAW_RX3THRESHPEND_SHIFT (0x0000000Bu) - -#define EMAC_RXINTSTATRAW_RX2THRESHPEND (0x00000400u) -#define EMAC_RXINTSTATRAW_RX2THRESHPEND_SHIFT (0x0000000Au) - -#define EMAC_RXINTSTATRAW_RX1THRESHPEND (0x00000200u) -#define EMAC_RXINTSTATRAW_RX1THRESHPEND_SHIFT (0x00000009u) - -#define EMAC_RXINTSTATRAW_RX0THRESHPEND (0x00000100u) -#define EMAC_RXINTSTATRAW_RX0THRESHPEND_SHIFT (0x00000008u) - -#define EMAC_RXINTSTATRAW_RX7PEND (0x00000080u) -#define EMAC_RXINTSTATRAW_RX7PEND_SHIFT (0x00000007u) - -#define EMAC_RXINTSTATRAW_RX6PEND (0x00000040u) -#define EMAC_RXINTSTATRAW_RX6PEND_SHIFT (0x00000006u) - -#define EMAC_RXINTSTATRAW_RX5PEND (0x00000020u) -#define EMAC_RXINTSTATRAW_RX5PEND_SHIFT (0x00000005u) - -#define EMAC_RXINTSTATRAW_RX4PEND (0x00000010u) -#define EMAC_RXINTSTATRAW_RX4PEND_SHIFT (0x00000004u) - -#define EMAC_RXINTSTATRAW_RX3PEND (0x00000008u) -#define EMAC_RXINTSTATRAW_RX3PEND_SHIFT (0x00000003u) - -#define EMAC_RXINTSTATRAW_RX2PEND (0x00000004u) -#define EMAC_RXINTSTATRAW_RX2PEND_SHIFT (0x00000002u) - -#define EMAC_RXINTSTATRAW_RX1PEND (0x00000002u) -#define EMAC_RXINTSTATRAW_RX1PEND_SHIFT (0x00000001u) - -#define EMAC_RXINTSTATRAW_RX0PEND (0x00000001u) -#define EMAC_RXINTSTATRAW_RX0PEND_SHIFT (0x00000000u) - - -/* RXINTSTATMASKED */ - - -#define EMAC_RXINTSTATMASKED_RX7THRESHPEND (0x00008000u) -#define EMAC_RXINTSTATMASKED_RX7THRESHPEND_SHIFT (0x0000000Fu) - -#define EMAC_RXINTSTATMASKED_RX6THRESHPEND (0x00004000u) -#define EMAC_RXINTSTATMASKED_RX6THRESHPEND_SHIFT (0x0000000Eu) - -#define EMAC_RXINTSTATMASKED_RX5THRESHPEND (0x00002000u) -#define EMAC_RXINTSTATMASKED_RX5THRESHPEND_SHIFT (0x0000000Du) - -#define EMAC_RXINTSTATMASKED_RX4THRESHPEND (0x00001000u) -#define EMAC_RXINTSTATMASKED_RX4THRESHPEND_SHIFT (0x0000000Cu) - -#define EMAC_RXINTSTATMASKED_RX3THRESHPEND (0x00000800u) -#define EMAC_RXINTSTATMASKED_RX3THRESHPEND_SHIFT (0x0000000Bu) - -#define EMAC_RXINTSTATMASKED_RX2THRESHPEND (0x00000400u) -#define EMAC_RXINTSTATMASKED_RX2THRESHPEND_SHIFT (0x0000000Au) - -#define EMAC_RXINTSTATMASKED_RX1THRESHPEND (0x00000200u) -#define EMAC_RXINTSTATMASKED_RX1THRESHPEND_SHIFT (0x00000009u) - -#define EMAC_RXINTSTATMASKED_RX0THRESHPEND (0x00000100u) -#define EMAC_RXINTSTATMASKED_RX0THRESHPEND_SHIFT (0x00000008u) - -#define EMAC_RXINTSTATMASKED_RX7PEND (0x00000080u) -#define EMAC_RXINTSTATMASKED_RX7PEND_SHIFT (0x00000007u) - -#define EMAC_RXINTSTATMASKED_RX6PEND (0x00000040u) -#define EMAC_RXINTSTATMASKED_RX6PEND_SHIFT (0x00000006u) - -#define EMAC_RXINTSTATMASKED_RX5PEND (0x00000020u) -#define EMAC_RXINTSTATMASKED_RX5PEND_SHIFT (0x00000005u) - -#define EMAC_RXINTSTATMASKED_RX4PEND (0x00000010u) -#define EMAC_RXINTSTATMASKED_RX4PEND_SHIFT (0x00000004u) - -#define EMAC_RXINTSTATMASKED_RX3PEND (0x00000008u) -#define EMAC_RXINTSTATMASKED_RX3PEND_SHIFT (0x00000003u) - -#define EMAC_RXINTSTATMASKED_RX2PEND (0x00000004u) -#define EMAC_RXINTSTATMASKED_RX2PEND_SHIFT (0x00000002u) - -#define EMAC_RXINTSTATMASKED_RX1PEND (0x00000002u) -#define EMAC_RXINTSTATMASKED_RX1PEND_SHIFT (0x00000001u) - -#define EMAC_RXINTSTATMASKED_RX0PEND (0x00000001u) -#define EMAC_RXINTSTATMASKED_RX0PEND_SHIFT (0x00000000u) - - -/* RXINTMASKSET */ - - -#define EMAC_RXINTMASKSET_RX7THRESHMASK (0x00008000u) -#define EMAC_RXINTMASKSET_RX7THRESHMASK_SHIFT (0x0000000Fu) - -#define EMAC_RXINTMASKSET_RX6THRESHMASK (0x00004000u) -#define EMAC_RXINTMASKSET_RX6THRESHMASK_SHIFT (0x0000000Eu) - -#define EMAC_RXINTMASKSET_RX5THRESHMASK (0x00002000u) -#define EMAC_RXINTMASKSET_RX5THRESHMASK_SHIFT (0x0000000Du) - -#define EMAC_RXINTMASKSET_RX4THRESHMASK (0x00001000u) -#define EMAC_RXINTMASKSET_RX4THRESHMASK_SHIFT (0x0000000Cu) - -#define EMAC_RXINTMASKSET_RX3THRESHMASK (0x00000800u) -#define EMAC_RXINTMASKSET_RX3THRESHMASK_SHIFT (0x0000000Bu) - -#define EMAC_RXINTMASKSET_RX2THRESHMASK (0x00000400u) -#define EMAC_RXINTMASKSET_RX2THRESHMASK_SHIFT (0x0000000Au) - -#define EMAC_RXINTMASKSET_RX1THRESHMASK (0x00000200u) -#define EMAC_RXINTMASKSET_RX1THRESHMASK_SHIFT (0x00000009u) - -#define EMAC_RXINTMASKSET_RX0THRESHMASK (0x00000100u) -#define EMAC_RXINTMASKSET_RX0THRESHMASK_SHIFT (0x00000008u) - -#define EMAC_RXINTMASKSET_RX7MASK (0x00000080u) -#define EMAC_RXINTMASKSET_RX7MASK_SHIFT (0x00000007u) - -#define EMAC_RXINTMASKSET_RX6MASK (0x00000040u) -#define EMAC_RXINTMASKSET_RX6MASK_SHIFT (0x00000006u) - -#define EMAC_RXINTMASKSET_RX5MASK (0x00000020u) -#define EMAC_RXINTMASKSET_RX5MASK_SHIFT (0x00000005u) - -#define EMAC_RXINTMASKSET_RX4MASK (0x00000010u) -#define EMAC_RXINTMASKSET_RX4MASK_SHIFT (0x00000004u) - -#define EMAC_RXINTMASKSET_RX3MASK (0x00000008u) -#define EMAC_RXINTMASKSET_RX3MASK_SHIFT (0x00000003u) - -#define EMAC_RXINTMASKSET_RX2MASK (0x00000004u) -#define EMAC_RXINTMASKSET_RX2MASK_SHIFT (0x00000002u) - -#define EMAC_RXINTMASKSET_RX1MASK (0x00000002u) -#define EMAC_RXINTMASKSET_RX1MASK_SHIFT (0x00000001u) - -#define EMAC_RXINTMASKSET_RX0MASK (0x00000001u) -#define EMAC_RXINTMASKSET_RX0MASK_SHIFT (0x00000000u) - - -/* RXINTMASKCLEAR */ - - -#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK (0x00008000u) -#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK_SHIFT (0x0000000Fu) - -#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK (0x00004000u) -#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK_SHIFT (0x0000000Eu) - -#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK (0x00002000u) -#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK_SHIFT (0x0000000Du) - -#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK (0x00001000u) -#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK_SHIFT (0x0000000Cu) - -#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK (0x00000800u) -#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK_SHIFT (0x0000000Bu) - -#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK (0x00000400u) -#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK_SHIFT (0x0000000Au) - -#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK (0x00000200u) -#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK_SHIFT (0x00000009u) - -#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK (0x00000100u) -#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK_SHIFT (0x00000008u) - -#define EMAC_RXINTMASKCLEAR_RX7MASK (0x00000080u) -#define EMAC_RXINTMASKCLEAR_RX7MASK_SHIFT (0x00000007u) - -#define EMAC_RXINTMASKCLEAR_RX6MASK (0x00000040u) -#define EMAC_RXINTMASKCLEAR_RX6MASK_SHIFT (0x00000006u) - -#define EMAC_RXINTMASKCLEAR_RX5MASK (0x00000020u) -#define EMAC_RXINTMASKCLEAR_RX5MASK_SHIFT (0x00000005u) - -#define EMAC_RXINTMASKCLEAR_RX4MASK (0x00000010u) -#define EMAC_RXINTMASKCLEAR_RX4MASK_SHIFT (0x00000004u) - -#define EMAC_RXINTMASKCLEAR_RX3MASK (0x00000008u) -#define EMAC_RXINTMASKCLEAR_RX3MASK_SHIFT (0x00000003u) - -#define EMAC_RXINTMASKCLEAR_RX2MASK (0x00000004u) -#define EMAC_RXINTMASKCLEAR_RX2MASK_SHIFT (0x00000002u) - -#define EMAC_RXINTMASKCLEAR_RX1MASK (0x00000002u) -#define EMAC_RXINTMASKCLEAR_RX1MASK_SHIFT (0x00000001u) - -#define EMAC_RXINTMASKCLEAR_RX0MASK (0x00000001u) -#define EMAC_RXINTMASKCLEAR_RX0MASK_SHIFT (0x00000000u) - - -/* MACINTSTATRAW */ - - -#define EMAC_MACINTSTATRAW_HOSTPEND (0x00000002u) -#define EMAC_MACINTSTATRAW_HOSTPEND_SHIFT (0x00000001u) - -#define EMAC_MACINTSTATRAW_STATPEND (0x00000001u) -#define EMAC_MACINTSTATRAW_STATPEND_SHIFT (0x00000000u) - - -/* MACINTSTATMASKED */ - - -#define EMAC_MACINTSTATMASKED_HOSTPEND (0x00000002u) -#define EMAC_MACINTSTATMASKED_HOSTPEND_SHIFT (0x00000001u) - -#define EMAC_MACINTSTATMASKED_STATPEND (0x00000001u) -#define EMAC_MACINTSTATMASKED_STATPEND_SHIFT (0x00000000u) - - -/* MACINTMASKSET */ - - -#define EMAC_MACINTMASKSET_HOSTMASK (0x00000002u) -#define EMAC_MACINTMASKSET_HOSTMASK_SHIFT (0x00000001u) - -#define EMAC_MACINTMASKSET_STATMASK (0x00000001u) -#define EMAC_MACINTMASKSET_STATMASK_SHIFT (0x00000000u) - - -/* MACINTMASKCLEAR */ - - -#define EMAC_MACINTMASKCLEAR_HOSTMASK (0x00000002u) -#define EMAC_MACINTMASKCLEAR_HOSTMASK_SHIFT (0x00000001u) - -#define EMAC_MACINTMASKCLEAR_STATMASK (0x00000001u) -#define EMAC_MACINTMASKCLEAR_STATMASK_SHIFT (0x00000000u) - - -/* RXMBPENABLE */ - - -#define EMAC_RXMBPENABLE_RXPASSCRC (0x40000000u) -#define EMAC_RXMBPENABLE_RXPASSCRC_SHIFT (0x0000001Eu) -#define EMAC_RXMBPENABLE_RXQOSEN (0x20000000u) -#define EMAC_RXMBPENABLE_RXQOSEN_SHIFT (0x0000001Du) -#define EMAC_RXMBPENABLE_RXNOCHAIN (0x10000000u) -#define EMAC_RXMBPENABLE_RXNOCHAIN_SHIFT (0x0000001Cu) -#define EMAC_RXMBPENABLE_RXCMFEN (0x01000000u) -#define EMAC_RXMBPENABLE_RXCMFEN_SHIFT (0x00000018u) -#define EMAC_RXMBPENABLE_RXCSFEN (0x00800000u) -#define EMAC_RXMBPENABLE_RXCSFEN_SHIFT (0x00000017u) -#define EMAC_RXMBPENABLE_RXCEFEN (0x00400000u) -#define EMAC_RXMBPENABLE_RXCEFEN_SHIFT (0x00000016u) -#define EMAC_RXMBPENABLE_RXCAFEN (0x00200000u) -#define EMAC_RXMBPENABLE_RXCAFEN_SHIFT (0x00000015u) -/*----RXCAFEN Tokens----*/ -#define EMAC_RXMBPENABLE_RXPROMCH (0x00070000u) -#define EMAC_RXMBPENABLE_RXPROMCH_SHIFT (0x00000010u) -#define EMAC_RXMBPENABLE_RXPROMCH_CHA0 (0x00000000u) -#define EMAC_RXMBPENABLE_RXPROMCH_CHA1 (0x00000001u) -#define EMAC_RXMBPENABLE_RXPROMCH_CHA2 (0x00000002u) -#define EMAC_RXMBPENABLE_RXPROMCH_CHA3 (0x00000003u) -#define EMAC_RXMBPENABLE_RXPROMCH_CHA4 (0x00000004u) -#define EMAC_RXMBPENABLE_RXPROMCH_CHA5 (0x00000005u) -#define EMAC_RXMBPENABLE_RXPROMCH_CHA6 (0x00000006u) -#define EMAC_RXMBPENABLE_RXPROMCH_CHA7 (0x00000007u) - - -#define EMAC_RXMBPENABLE_RXBROADEN (0x00002000u) -#define EMAC_RXMBPENABLE_RXBROADEN_SHIFT (0x0000000Du) -#define EMAC_RXMBPENABLE_RXBROADCH (0x00000700u) -#define EMAC_RXMBPENABLE_RXBROADCH_SHIFT (0x00000008u) -/*----RXBROADCH Tokens----*/ -#define EMAC_RXMBPENABLE_RXBROADCH_CHA0 (0x00000000u) -#define EMAC_RXMBPENABLE_RXBROADCH_CHA1 (0x00000001u) -#define EMAC_RXMBPENABLE_RXBROADCH_CHA2 (0x00000002u) -#define EMAC_RXMBPENABLE_RXBROADCH_CHA3 (0x00000003u) -#define EMAC_RXMBPENABLE_RXBROADCH_CHA4 (0x00000004u) -#define EMAC_RXMBPENABLE_RXBROADCH_CHA5 (0x00000005u) -#define EMAC_RXMBPENABLE_RXBROADCH_CHA6 (0x00000006u) -#define EMAC_RXMBPENABLE_RXBROADCH_CHA7 (0x00000007u) - - -#define EMAC_RXMBPENABLE_RXMULTEN (0x00000020u) -#define EMAC_RXMBPENABLE_RXMULTEN_SHIFT (0x00000005u) -#define EMAC_RXMBPENABLE_RXMULTCH (0x00000007u) -#define EMAC_RXMBPENABLE_RXMULTCH_SHIFT (0x00000000u) -/*----RXMULTCH Tokens----*/ -#define EMAC_RXMBPENABLE_RXMULTCH_CHA0 (0x00000000u) -#define EMAC_RXMBPENABLE_RXMULTCH_CHA1 (0x00000001u) -#define EMAC_RXMBPENABLE_RXMULTCH_CHA2 (0x00000002u) -#define EMAC_RXMBPENABLE_RXMULTCH_CHA3 (0x00000003u) -#define EMAC_RXMBPENABLE_RXMULTCH_CHA4 (0x00000004u) -#define EMAC_RXMBPENABLE_RXMULTCH_CHA5 (0x00000005u) -#define EMAC_RXMBPENABLE_RXMULTCH_CHA6 (0x00000006u) -#define EMAC_RXMBPENABLE_RXMULTCH_CHA7 (0x00000007u) - - -/* RXUNICASTSET */ - - -#define EMAC_RXUNICASTSET_RXCH7EN (0x00000080u) -#define EMAC_RXUNICASTSET_RXCH7EN_SHIFT (0x00000007u) -#define EMAC_RXUNICASTSET_RXCH6EN (0x00000040u) -#define EMAC_RXUNICASTSET_RXCH6EN_SHIFT (0x00000006u) -#define EMAC_RXUNICASTSET_RXCH5EN (0x00000020u) -#define EMAC_RXUNICASTSET_RXCH5EN_SHIFT (0x00000005u) -#define EMAC_RXUNICASTSET_RXCH4EN (0x00000010u) -#define EMAC_RXUNICASTSET_RXCH4EN_SHIFT (0x00000004u) -#define EMAC_RXUNICASTSET_RXCH3EN (0x00000008u) -#define EMAC_RXUNICASTSET_RXCH3EN_SHIFT (0x00000003u) -#define EMAC_RXUNICASTSET_RXCH2EN (0x00000004u) -#define EMAC_RXUNICASTSET_RXCH2EN_SHIFT (0x00000002u) -#define EMAC_RXUNICASTSET_RXCH1EN (0x00000002u) -#define EMAC_RXUNICASTSET_RXCH1EN_SHIFT (0x00000001u) -#define EMAC_RXUNICASTSET_RXCH0EN (0x00000001u) -#define EMAC_RXUNICASTSET_RXCH0EN_SHIFT (0x00000000u) - -/* RXUNICASTCLEAR */ - - -#define EMAC_RXUNICASTCLEAR_RXCH7EN (0x00000080u) -#define EMAC_RXUNICASTCLEAR_RXCH7EN_SHIFT (0x00000007u) -#define EMAC_RXUNICASTCLEAR_RXCH6EN (0x00000040u) -#define EMAC_RXUNICASTCLEAR_RXCH6EN_SHIFT (0x00000006u) -#define EMAC_RXUNICASTCLEAR_RXCH5EN (0x00000020u) -#define EMAC_RXUNICASTCLEAR_RXCH5EN_SHIFT (0x00000005u) -#define EMAC_RXUNICASTCLEAR_RXCH4EN (0x00000010u) -#define EMAC_RXUNICASTCLEAR_RXCH4EN_SHIFT (0x00000004u) -#define EMAC_RXUNICASTCLEAR_RXCH3EN (0x00000008u) -#define EMAC_RXUNICASTCLEAR_RXCH3EN_SHIFT (0x00000003u) -#define EMAC_RXUNICASTCLEAR_RXCH2EN (0x00000004u) -#define EMAC_RXUNICASTCLEAR_RXCH2EN_SHIFT (0x00000002u) -#define EMAC_RXUNICASTCLEAR_RXCH1EN (0x00000002u) -#define EMAC_RXUNICASTCLEAR_RXCH1EN_SHIFT (0x00000001u) -#define EMAC_RXUNICASTCLEAR_RXCH0EN (0x00000001u) -#define EMAC_RXUNICASTCLEAR_RXCH0EN_SHIFT (0x00000000u) - -/* RXMAXLEN */ - - -#define EMAC_RXMAXLEN_RXMAXLEN (0x0000FFFFu) -#define EMAC_RXMAXLEN_RXMAXLEN_SHIFT (0x00000000u) - - -/* RXBUFFEROFFSET */ - - -#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET (0x0000FFFFu) -#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET_SHIFT (0x00000000u) - - -/* RXFILTERLOWTHRESH */ - - -#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH (0x000000FFu) -#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH_SHIFT (0x00000000u) - - -/* RX0FLOWTHRESH */ - - -#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH (0x000000FFu) -#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH_SHIFT (0x00000000u) - - -/* RX1FLOWTHRESH */ - - -#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH (0x000000FFu) -#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH_SHIFT (0x00000000u) - - -/* RX2FLOWTHRESH */ - - -#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH (0x000000FFu) -#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH_SHIFT (0x00000000u) - - -/* RX3FLOWTHRESH */ - - -#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH (0x000000FFu) -#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH_SHIFT (0x00000000u) - - -/* RX4FLOWTHRESH */ - - -#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH (0x000000FFu) -#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH_SHIFT (0x00000000u) - - -/* RX5FLOWTHRESH */ - - -#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH (0x000000FFu) -#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH_SHIFT (0x00000000u) - - -/* RX6FLOWTHRESH */ - - -#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH (0x000000FFu) -#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH_SHIFT (0x00000000u) - - -/* RX7FLOWTHRESH */ - - -#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH (0x000000FFu) -#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH_SHIFT (0x00000000u) - - -/* RX0FREEBUFFER */ - - -#define EMAC_RX0FREEBUFFER_RX0FREEBUF (0x0000FFFFu) -#define EMAC_RX0FREEBUFFER_RX0FREEBUF_SHIFT (0x00000000u) - - -/* RX1FREEBUFFER */ - - -#define EMAC_RX1FREEBUFFER_RX1FREEBUF (0x0000FFFFu) -#define EMAC_RX1FREEBUFFER_RX1FREEBUF_SHIFT (0x00000000u) - - -/* RX2FREEBUFFER */ - - -#define EMAC_RX2FREEBUFFER_RX2FREEBUF (0x0000FFFFu) -#define EMAC_RX2FREEBUFFER_RX2FREEBUF_SHIFT (0x00000000u) - - -/* RX3FREEBUFFER */ - - -#define EMAC_RX3FREEBUFFER_RX3FREEBUF (0x0000FFFFu) -#define EMAC_RX3FREEBUFFER_RX3FREEBUF_SHIFT (0x00000000u) - - -/* RX4FREEBUFFER */ - - -#define EMAC_RX4FREEBUFFER_RX4FREEBUF (0x0000FFFFu) -#define EMAC_RX4FREEBUFFER_RX4FREEBUF_SHIFT (0x00000000u) - - -/* RX5FREEBUFFER */ - - -#define EMAC_RX5FREEBUFFER_RX5FREEBUF (0x0000FFFFu) -#define EMAC_RX5FREEBUFFER_RX5FREEBUF_SHIFT (0x00000000u) - - -/* RX6FREEBUFFER */ - - -#define EMAC_RX6FREEBUFFER_RX6FREEBUF (0x0000FFFFu) -#define EMAC_RX6FREEBUFFER_RX6FREEBUF_SHIFT (0x00000000u) - - -/* RX7FREEBUFFER */ - - -#define EMAC_RX7FREEBUFFER_RX7FREEBUF (0x0000FFFFu) -#define EMAC_RX7FREEBUFFER_RX7FREEBUF_SHIFT (0x00000000u) - - -/* MACCONTROL */ - - - - - -#define EMAC_MACCONTROL_RMIISPEED (0x00008000u) -#define EMAC_MACCONTROL_RMIISPEED_SHIFT (0x0000000Fu) -#define EMAC_MACCONTROL_RXOFFLENBLOCK (0x00004000u) -#define EMAC_MACCONTROL_RXOFFLENBLOCK_SHIFT (0x0000000Eu) -#define EMAC_MACCONTROL_RXOWNERSHIP (0x00002000u) -#define EMAC_MACCONTROL_RXOWNERSHIP_SHIFT (0x0000000Du) -#define EMAC_MACCONTROL_CMDIDLE (0x00000800u) -#define EMAC_MACCONTROL_CMDIDLE_SHIFT (0x0000000Bu) -#define EMAC_MACCONTROL_TXSHORTGAPEN (0x00000400u) -#define EMAC_MACCONTROL_TXSHORTGAPEN_SHIFT (0x0000000Au) -#define EMAC_MACCONTROL_TXPTYPE (0x00000200u) -#define EMAC_MACCONTROL_TXPTYPE_SHIFT (0x00000009u) -#define EMAC_MACCONTROL_TXPACE (0x00000040u) -#define EMAC_MACCONTROL_TXPACE_SHIFT (0x00000006u) -#define EMAC_MACCONTROL_GMIIEN (0x00000020u) -#define EMAC_MACCONTROL_GMIIEN_SHIFT (0x00000005u) -#define EMAC_MACCONTROL_TXFLOWEN (0x00000010u) -#define EMAC_MACCONTROL_TXFLOWEN_SHIFT (0x00000004u) -#define EMAC_MACCONTROL_RXBUFFERFLOWEN (0x00000008u) -#define EMAC_MACCONTROL_RXBUFFERFLOWEN_SHIFT (0x00000003u) -#define EMAC_MACCONTROL_LOOPBACK (0x00000002u) -#define EMAC_MACCONTROL_LOOPBACK_SHIFT (0x00000001u) -#define EMAC_MACCONTROL_FULLDUPLEX (0x00000001u) -#define EMAC_MACCONTROL_FULLDUPLEX_SHIFT (0x00000000u) - - -/* MACSTATUS */ - -#define EMAC_MACSTATUS_IDLE (0x80000000u) -#define EMAC_MACSTATUS_IDLE_SHIFT (0x0000001Fu) -#define EMAC_MACSTATUS_TXERRCODE (0x00F00000u) -#define EMAC_MACSTATUS_TXERRCODE_SHIFT (0x00000014u) -/*----TXERRCODE Tokens----*/ -#define EMAC_MACSTATUS_TXERRCODE_NOERROR (0x00000000u) -#define EMAC_MACSTATUS_TXERRCODE_SOPERROR (0x00000001u) -#define EMAC_MACSTATUS_TXERRCODE_OWNERSHIP (0x00000002u) -#define EMAC_MACSTATUS_TXERRCODE_NOEOP (0x00000003u) -#define EMAC_MACSTATUS_TXERRCODE_NULLPTR (0x00000004u) -#define EMAC_MACSTATUS_TXERRCODE_NULLEN (0x00000005u) -#define EMAC_MACSTATUS_TXERRCODE_LENERROR (0x00000006u) - - -#define EMAC_MACSTATUS_TXERRCH (0x00070000u) -#define EMAC_MACSTATUS_TXERRCH_SHIFT (0x00000010u) -/*----TXERRCH Tokens----*/ -#define EMAC_MACSTATUS_TXERRCH_CHA0 (0x00000000u) -#define EMAC_MACSTATUS_TXERRCH_CHA1 (0x00000001u) -#define EMAC_MACSTATUS_TXERRCH_CHA2 (0x00000002u) -#define EMAC_MACSTATUS_TXERRCH_CHA3 (0x00000003u) -#define EMAC_MACSTATUS_TXERRCH_CHA4 (0x00000004u) -#define EMAC_MACSTATUS_TXERRCH_CHA5 (0x00000005u) -#define EMAC_MACSTATUS_TXERRCH_CHA6 (0x00000006u) -#define EMAC_MACSTATUS_TXERRCH_CHA7 (0x00000007u) - -#define EMAC_MACSTATUS_RXERRCODE (0x0000F000u) -#define EMAC_MACSTATUS_RXERRCODE_SHIFT (0x0000000Cu) -/*----RXERRCODE Tokens----*/ -#define EMAC_MACSTATUS_RXERRCODE_NOERROR (0x00000000u) -#define EMAC_MACSTATUS_RXERRCODE_OWNERSHIP (0x00000002u) -#define EMAC_MACSTATUS_RXERRCODE_NULLPTR (0x00000004u) - - -#define EMAC_MACSTATUS_RXERRCH (0x00000700u) -#define EMAC_MACSTATUS_RXERRCH_SHIFT (0x00000008u) -/*----RXERRCH Tokens----*/ -#define EMAC_MACSTATUS_RXERRCH_CHA0 (0x00000000u) -#define EMAC_MACSTATUS_RXERRCH_CHA1 (0x00000001u) -#define EMAC_MACSTATUS_RXERRCH_CHA2 (0x00000002u) -#define EMAC_MACSTATUS_RXERRCH_CHA3 (0x00000003u) -#define EMAC_MACSTATUS_RXERRCH_CHA4 (0x00000004u) -#define EMAC_MACSTATUS_RXERRCH_CHA5 (0x00000005u) -#define EMAC_MACSTATUS_RXERRCH_CHA6 (0x00000006u) -#define EMAC_MACSTATUS_RXERRCH_CHA7 (0x00000007u) - - - - -#define EMAC_MACSTATUS_RXQOSACT (0x00000004u) -#define EMAC_MACSTATUS_RXQOSACT_SHIFT (0x00000002u) -#define EMAC_MACSTATUS_RXFLOWACT (0x00000002u) -#define EMAC_MACSTATUS_RXFLOWACT_SHIFT (0x00000001u) -#define EMAC_MACSTATUS_TXFLOWACT (0x00000001u) -#define EMAC_MACSTATUS_TXFLOWACT_SHIFT (0x00000000u) - -/* EMCONTROL */ - - -#define EMAC_EMCONTROL_SOFT (0x00000002u) -#define EMAC_EMCONTROL_SOFT_SHIFT (0x00000001u) - -#define EMAC_EMCONTROL_FREE (0x00000001u) -#define EMAC_EMCONTROL_FREE_SHIFT (0x00000000u) - - -/* FIFOCONTROL */ - - -#define EMAC_FIFOCONTROL_TXCELLTHRESH (0x00000003u) -#define EMAC_FIFOCONTROL_TXCELLTHRESH_SHIFT (0x00000000u) - - -/* MACCONFIG */ - -#define EMAC_MACCONFIG_TXCELLDEPTH (0xFF000000u) -#define EMAC_MACCONFIG_TXCELLDEPTH_SHIFT (0x00000018u) - -#define EMAC_MACCONFIG_RXCELLDEPTH (0x00FF0000u) -#define EMAC_MACCONFIG_RXCELLDEPTH_SHIFT (0x00000010u) - -#define EMAC_MACCONFIG_ADDRESSTYPE (0x0000FF00u) -#define EMAC_MACCONFIG_ADDRESSTYPE_SHIFT (0x00000008u) - -#define EMAC_MACCONFIG_MACCFIG (0x000000FFu) -#define EMAC_MACCONFIG_MACCFIG_SHIFT (0x00000000u) - - -/* SOFTRESET */ - - -#define EMAC_SOFTRESET_SOFTRESET (0x00000001u) -#define EMAC_SOFTRESET_SOFTRESET_SHIFT (0x00000000u) - -/* MACSRCADDRLO */ - - -#define EMAC_MACSRCADDRLO_MACSRCADDR0 (0x0000FF00u) -#define EMAC_MACSRCADDRLO_MACSRCADDR0_SHIFT (0x00000008u) -#define EMAC_MACSRCADDRLO_MACSRCADDR1 (0x000000FFu) -#define EMAC_MACSRCADDRLO_MACSRCADDR1_SHIFT (0x00000000u) - - -/* MACSRCADDRHI */ - -#define EMAC_MACSRCADDRHI_MACSRCADDR2 (0xFF000000u) -#define EMAC_MACSRCADDRHI_MACSRCADDR2_SHIFT (0x00000018u) - -#define EMAC_MACSRCADDRHI_MACSRCADDR3 (0x00FF0000u) -#define EMAC_MACSRCADDRHI_MACSRCADDR3_SHIFT (0x00000010u) - -#define EMAC_MACSRCADDRHI_MACSRCADDR4 (0x0000FF00u) -#define EMAC_MACSRCADDRHI_MACSRCADDR4_SHIFT (0x00000008u) - -#define EMAC_MACSRCADDRHI_MACSRCADDR5 (0x000000FFu) -#define EMAC_MACSRCADDRHI_MACSRCADDR5_SHIFT (0x00000000u) - - -/* MACHASH1 */ - -#define EMAC_MACHASH1_MACHASH1 (0xFFFFFFFFu) -#define EMAC_MACHASH1_MACHASH1_SHIFT (0x00000000u) - - -/* MACHASH2 */ - -#define EMAC_MACHASH2_MACHASH2 (0xFFFFFFFFu) -#define EMAC_MACHASH2_MACHASH2_SHIFT (0x00000000u) - - -/* BOFFTEST */ - - -#define EMAC_BOFFTEST_RNDNUM (0x03FF0000u) -#define EMAC_BOFFTEST_RNDNUM_SHIFT (0x00000010u) - -#define EMAC_BOFFTEST_COLLCOUNT (0x0000F000u) -#define EMAC_BOFFTEST_COLLCOUNT_SHIFT (0x0000000Cu) - - -#define EMAC_BOFFTEST_TXBACKOFF (0x000003FFu) -#define EMAC_BOFFTEST_TXBACKOFF_SHIFT (0x00000000u) - - -/* TPACETEST */ - - -#define EMAC_TPACETEST_PACEVAL (0x0000001Fu) -#define EMAC_TPACETEST_PACEVAL_SHIFT (0x00000000u) - - -/* RXPAUSE */ - - -#define EMAC_RXPAUSE_PAUSETIMER (0x0000FFFFu) -#define EMAC_RXPAUSE_PAUSETIMER_SHIFT (0x00000000u) - - -/* TXPAUSE */ - - -#define EMAC_TXPAUSE_PAUSETIMER (0x0000FFFFu) -#define EMAC_TXPAUSE_PAUSETIMER_SHIFT (0x00000000u) - - -/* RXGOODFRAMES */ - -#define EMAC_RXGOODFRAMES_COUNT (0xFFFFFFFFu) -#define EMAC_RXGOODFRAMES_COUNT_SHIFT (0x00000000u) - - -/* RXBCASTFRAMES */ - -#define EMAC_RXBCASTFRAMES_COUNT (0xFFFFFFFFu) -#define EMAC_RXBCASTFRAMES_COUNT_SHIFT (0x00000000u) - - -/* RXMCASTFRAMES */ - -#define EMAC_RXMCASTFRAMES_COUNT (0xFFFFFFFFu) -#define EMAC_RXMCASTFRAMES_COUNT_SHIFT (0x00000000u) - - -/* RXPAUSEFRAMES */ - -#define EMAC_RXPAUSEFRAMES_COUNT (0xFFFFFFFFu) -#define EMAC_RXPAUSEFRAMES_COUNT_SHIFT (0x00000000u) - - -/* RXCRCERRORS */ - -#define EMAC_RXCRCERRORS_COUNT (0xFFFFFFFFu) -#define EMAC_RXCRCERRORS_COUNT_SHIFT (0x00000000u) - - -/* RXALIGNCODEERRORS */ - -#define EMAC_RXALIGNCODEERRORS_COUNT (0xFFFFFFFFu) -#define EMAC_RXALIGNCODEERRORS_COUNT_SHIFT (0x00000000u) - - -/* RXOVERSIZED */ - -#define EMAC_RXOVERSIZED_COUNT (0xFFFFFFFFu) -#define EMAC_RXOVERSIZED_COUNT_SHIFT (0x00000000u) - - -/* RXJABBER */ - -#define EMAC_RXJABBER_COUNT (0xFFFFFFFFu) -#define EMAC_RXJABBER_COUNT_SHIFT (0x00000000u) - - -/* RXUNDERSIZED */ - -#define EMAC_RXUNDERSIZED_COUNT (0xFFFFFFFFu) -#define EMAC_RXUNDERSIZED_COUNT_SHIFT (0x00000000u) - - -/* RXFRAGMENTS */ - -#define EMAC_RXFRAGMENTS_COUNT (0xFFFFFFFFu) -#define EMAC_RXFRAGMENTS_COUNT_SHIFT (0x00000000u) - - -/* RXFILTERED */ - -#define EMAC_RXFILTERED_COUNT (0xFFFFFFFFu) -#define EMAC_RXFILTERED_COUNT_SHIFT (0x00000000u) - - -/* RXQOSFILTERED */ - -#define EMAC_RXQOSFILTERED_COUNT (0xFFFFFFFFu) -#define EMAC_RXQOSFILTERED_COUNT_SHIFT (0x00000000u) - - -/* RXOCTETS */ - -#define EMAC_RXOCTETS_COUNT (0xFFFFFFFFu) -#define EMAC_RXOCTETS_COUNT_SHIFT (0x00000000u) - - -/* TXGOODFRAMES */ - -#define EMAC_TXGOODFRAMES_COUNT (0xFFFFFFFFu) -#define EMAC_TXGOODFRAMES_COUNT_SHIFT (0x00000000u) - - -/* TXBCASTFRAMES */ - -#define EMAC_TXBCASTFRAMES_COUNT (0xFFFFFFFFu) -#define EMAC_TXBCASTFRAMES_COUNT_SHIFT (0x00000000u) - - -/* TXMCASTFRAMES */ - -#define EMAC_TXMCASTFRAMES_COUNT (0xFFFFFFFFu) -#define EMAC_TXMCASTFRAMES_COUNT_SHIFT (0x00000000u) - - -/* TXPAUSEFRAMES */ - -#define EMAC_TXPAUSEFRAMES_COUNT (0xFFFFFFFFu) -#define EMAC_TXPAUSEFRAMES_COUNT_SHIFT (0x00000000u) - - -/* TXDEFERRED */ - -#define EMAC_TXDEFERRED_COUNT (0xFFFFFFFFu) -#define EMAC_TXDEFERRED_COUNT_SHIFT (0x00000000u) - - -/* TXCOLLISION */ - -#define EMAC_TXCOLLISION_COUNT (0xFFFFFFFFu) -#define EMAC_TXCOLLISION_COUNT_SHIFT (0x00000000u) - - -/* TXSINGLECOLL */ - -#define EMAC_TXSINGLECOLL_COUNT (0xFFFFFFFFu) -#define EMAC_TXSINGLECOLL_COUNT_SHIFT (0x00000000u) - - -/* TXMULTICOLL */ - -#define EMAC_TXMULTICOLL_COUNT (0xFFFFFFFFu) -#define EMAC_TXMULTICOLL_COUNT_SHIFT (0x00000000u) - - -/* TXEXCESSIVECOLL */ - -#define EMAC_TXEXCESSIVECOLL_COUNT (0xFFFFFFFFu) -#define EMAC_TXEXCESSIVECOLL_COUNT_SHIFT (0x00000000u) - - -/* TXLATECOLL */ - -#define EMAC_TXLATECOLL_COUNT (0xFFFFFFFFu) -#define EMAC_TXLATECOLL_COUNT_SHIFT (0x00000000u) - - -/* TXUNDERRUN */ - -#define EMAC_TXUNDERRUN_COUNT (0xFFFFFFFFu) -#define EMAC_TXUNDERRUN_COUNT_SHIFT (0x00000000u) - - -/* TXCARRIERSENSE */ - -#define EMAC_TXCARRIERSENSE_COUNT (0xFFFFFFFFu) -#define EMAC_TXCARRIERSENSE_COUNT_SHIFT (0x00000000u) - - -/* TXOCTETS */ - -#define EMAC_TXOCTETS_COUNT (0xFFFFFFFFu) -#define EMAC_TXOCTETS_COUNT_SHIFT (0x00000000u) - - -/* FRAME64 */ - -#define EMAC_FRAME64_COUNT (0xFFFFFFFFu) -#define EMAC_FRAME64_COUNT_SHIFT (0x00000000u) - - -/* FRAME65T127 */ - -#define EMAC_FRAME65T127_COUNT (0xFFFFFFFFu) -#define EMAC_FRAME65T127_COUNT_SHIFT (0x00000000u) - - -/* FRAME128T255 */ - -#define EMAC_FRAME128T255_COUNT (0xFFFFFFFFu) -#define EMAC_FRAME128T255_COUNT_SHIFT (0x00000000u) - - -/* FRAME256T511 */ - -#define EMAC_FRAME256T511_COUNT (0xFFFFFFFFu) -#define EMAC_FRAME256T511_COUNT_SHIFT (0x00000000u) - - -/* FRAME512T1023 */ - -#define EMAC_FRAME512T1023_COUNT (0xFFFFFFFFu) -#define EMAC_FRAME512T1023_COUNT_SHIFT (0x00000000u) - - -/* FRAME1024TUP */ - -#define EMAC_FRAME1024TUP_COUNT (0xFFFFFFFFu) -#define EMAC_FRAME1024TUP_COUNT_SHIFT (0x00000000u) - - -/* NETOCTETS */ - -#define EMAC_NETOCTETS_COUNT (0xFFFFFFFFu) -#define EMAC_NETOCTETS_COUNT_SHIFT (0x00000000u) - - -/* RXSOFOVERRUNS */ - -#define EMAC_RXSOFOVERRUNS_COUNT (0xFFFFFFFFu) -#define EMAC_RXSOFOVERRUNS_COUNT_SHIFT (0x00000000u) - - -/* RXMOFOVERRUNS */ - -#define EMAC_RXMOFOVERRUNS_COUNT (0xFFFFFFFFu) -#define EMAC_RXMOFOVERRUNS_COUNT_SHIFT (0x00000000u) - - -/* RXDMAOVERRUNS */ - -#define EMAC_RXDMAOVERRUNS_COUNT (0xFFFFFFFFu) -#define EMAC_RXDMAOVERRUNS_COUNT_SHIFT (0x00000000u) - - -/* MACADDRLO */ - - -#define EMAC_MACADDRLO_VALID (0x00100000u) -#define EMAC_MACADDRLO_VALID_SHIFT (0x00000014u) -#define EMAC_MACADDRLO_MATCHFILT (0x00080000u) -#define EMAC_MACADDRLO_MATCHFILT_SHIFT (0x00000013u) -#define EMAC_MACADDRLO_CHANNEL (0x00070000u) -#define EMAC_MACADDRLO_CHANNEL_SHIFT (0x00000010u) -#define EMAC_MACADDRLO_MACADDR0 (0x0000FF00u) -#define EMAC_MACADDRLO_MACADDR0_SHIFT (0x00000008u) -#define EMAC_MACADDRLO_MACADDR1 (0x000000FFu) -#define EMAC_MACADDRLO_MACADDR1_SHIFT (0x00000000u) - - -/* MACADDRHI */ - -#define EMAC_MACADDRHI_MACADDR2 (0xFF000000u) -#define EMAC_MACADDRHI_MACADDR2_SHIFT (0x00000018u) - -#define EMAC_MACADDRHI_MACADDR3 (0x00FF0000u) -#define EMAC_MACADDRHI_MACADDR3_SHIFT (0x00000010u) - -#define EMAC_MACADDRHI_MACADDR4 (0x0000FF00u) -#define EMAC_MACADDRHI_MACADDR4_SHIFT (0x00000008u) - -#define EMAC_MACADDRHI_MACADDR5 (0x000000FFu) -#define EMAC_MACADDRHI_MACADDR5_SHIFT (0x00000000u) - - -/* MACINDEX */ - - -#define EMAC_MACINDEX_MACINDEX (0x0000001Fu) -#define EMAC_MACINDEX_MACINDEX_SHIFT (0x00000000u) - - -/* TX0HDP */ - -#define EMAC_TX0HDP_TX0HDP (0xFFFFFFFFu) -#define EMAC_TX0HDP_TX0HDP_SHIFT (0x00000000u) - - -/* TX1HDP */ - -#define EMAC_TX1HDP_TX1HDP (0xFFFFFFFFu) -#define EMAC_TX1HDP_TX1HDP_SHIFT (0x00000000u) - - -/* TX2HDP */ - -#define EMAC_TX2HDP_TX2HDP (0xFFFFFFFFu) -#define EMAC_TX2HDP_TX2HDP_SHIFT (0x00000000u) - - -/* TX3HDP */ - -#define EMAC_TX3HDP_TX3HDP (0xFFFFFFFFu) -#define EMAC_TX3HDP_TX3HDP_SHIFT (0x00000000u) - - -/* TX4HDP */ - -#define EMAC_TX4HDP_TX4HDP (0xFFFFFFFFu) -#define EMAC_TX4HDP_TX4HDP_SHIFT (0x00000000u) - - -/* TX5HDP */ - -#define EMAC_TX5HDP_TX5HDP (0xFFFFFFFFu) -#define EMAC_TX5HDP_TX5HDP_SHIFT (0x00000000u) - - -/* TX6HDP */ - -#define EMAC_TX6HDP_TX6HDP (0xFFFFFFFFu) -#define EMAC_TX6HDP_TX6HDP_SHIFT (0x00000000u) - - -/* TX7HDP */ - -#define EMAC_TX7HDP_TX7HDP (0xFFFFFFFFu) -#define EMAC_TX7HDP_TX7HDP_SHIFT (0x00000000u) - - -/* RX0HDP */ - -#define EMAC_RX0HDP_RX0HDP (0xFFFFFFFFu) -#define EMAC_RX0HDP_RX0HDP_SHIFT (0x00000000u) - - -/* RX1HDP */ - -#define EMAC_RX1HDP_RX1HDP (0xFFFFFFFFu) -#define EMAC_RX1HDP_RX1HDP_SHIFT (0x00000000u) - - -/* RX2HDP */ - -#define EMAC_RX2HDP_RX2HDP (0xFFFFFFFFu) -#define EMAC_RX2HDP_RX2HDP_SHIFT (0x00000000u) - - -/* RX3HDP */ - -#define EMAC_RX3HDP_RX3HDP (0xFFFFFFFFu) -#define EMAC_RX3HDP_RX3HDP_SHIFT (0x00000000u) - - -/* RX4HDP */ - -#define EMAC_RX4HDP_RX4HDP (0xFFFFFFFFu) -#define EMAC_RX4HDP_RX4HDP_SHIFT (0x00000000u) - - -/* RX5HDP */ - -#define EMAC_RX5HDP_RX5HDP (0xFFFFFFFFu) -#define EMAC_RX5HDP_RX5HDP_SHIFT (0x00000000u) - - -/* RX6HDP */ - -#define EMAC_RX6HDP_RX6HDP (0xFFFFFFFFu) -#define EMAC_RX6HDP_RX6HDP_SHIFT (0x00000000u) - - -/* RX7HDP */ - -#define EMAC_RX7HDP_RX7HDP (0xFFFFFFFFu) -#define EMAC_RX7HDP_RX7HDP_SHIFT (0x00000000u) - - -/* TX0CP */ - -#define EMAC_TX0CP_TX0CP (0xFFFFFFFFu) -#define EMAC_TX0CP_TX0CP_SHIFT (0x00000000u) - - -/* TX1CP */ - -#define EMAC_TX1CP_TX1CP (0xFFFFFFFFu) -#define EMAC_TX1CP_TX1CP_SHIFT (0x00000000u) - - -/* TX2CP */ - -#define EMAC_TX2CP_TX2CP (0xFFFFFFFFu) -#define EMAC_TX2CP_TX2CP_SHIFT (0x00000000u) - - -/* TX3CP */ - -#define EMAC_TX3CP_TX3CP (0xFFFFFFFFu) -#define EMAC_TX3CP_TX3CP_SHIFT (0x00000000u) - - -/* TX4CP */ - -#define EMAC_TX4CP_TX4CP (0xFFFFFFFFu) -#define EMAC_TX4CP_TX4CP_SHIFT (0x00000000u) - - -/* TX5CP */ - -#define EMAC_TX5CP_TX5CP (0xFFFFFFFFu) -#define EMAC_TX5CP_TX5CP_SHIFT (0x00000000u) - - -/* TX6CP */ - -#define EMAC_TX6CP_TX6CP (0xFFFFFFFFu) -#define EMAC_TX6CP_TX6CP_SHIFT (0x00000000u) - - -/* TX7CP */ - -#define EMAC_TX7CP_TX7CP (0xFFFFFFFFu) -#define EMAC_TX7CP_TX7CP_SHIFT (0x00000000u) - - -/* RX0CP */ - -#define EMAC_RX0CP_RX0CP (0xFFFFFFFFu) -#define EMAC_RX0CP_RX0CP_SHIFT (0x00000000u) - - -/* RX1CP */ - -#define EMAC_RX1CP_RX1CP (0xFFFFFFFFu) -#define EMAC_RX1CP_RX1CP_SHIFT (0x00000000u) - - -/* RX2CP */ - -#define EMAC_RX2CP_RX2CP (0xFFFFFFFFu) -#define EMAC_RX2CP_RX2CP_SHIFT (0x00000000u) - - -/* RX3CP */ - -#define EMAC_RX3CP_RX3CP (0xFFFFFFFFu) -#define EMAC_RX3CP_RX3CP_SHIFT (0x00000000u) - - -/* RX4CP */ - -#define EMAC_RX4CP_RX4CP (0xFFFFFFFFu) -#define EMAC_RX4CP_RX4CP_SHIFT (0x00000000u) - - -/* RX5CP */ - -#define EMAC_RX5CP_RX5CP (0xFFFFFFFFu) -#define EMAC_RX5CP_RX5CP_SHIFT (0x00000000u) - - -/* RX6CP */ - -#define EMAC_RX6CP_RX6CP (0xFFFFFFFFu) -#define EMAC_RX6CP_RX6CP_SHIFT (0x00000000u) - - -/* RX7CP */ - -#define EMAC_RX7CP_RX7CP (0xFFFFFFFFu) -#define EMAC_RX7CP_RX7CP_SHIFT (0x00000000u) - - -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_emac_ctrl.h b/lib/tiam1808/tiam1808/hw/hw_emac_ctrl.h deleted file mode 100644 index c25873bad..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_emac_ctrl.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * \file hw_emac_ctrl.h - * - * \brief EMAC ctrl register definitions - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _HW_EMAC_CTRL_H_ -#define _HW_EMAC_CTRL_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define EMAC_CTRL_REVID (0x0u) -#define EMAC_CTRL_SOFTRESET (0x4u) -#define EMAC_CTRL_INTCONTROL (0xCu) -#define EMAC_CTRL_C0RXTHRESHEN (0x10u) -#define EMAC_CTRL_CnRXEN(n) (0x14u + (n << 4)) -#define EMAC_CTRL_CnTXEN(n) (0x18u + (n << 4)) -#define EMAC_CTRL_CnMISCEN(n) (0x1Cu + (n << 4)) -#define EMAC_CTRL_CnRXTHRESHEN(n) (0x20u + (n << 4)) -#define EMAC_CTRL_C0RXTHRESHSTAT (0x40u) -#define EMAC_CTRL_C0RXSTAT (0x44u) -#define EMAC_CTRL_C0TXSTAT (0x48u) -#define EMAC_CTRL_C0MISCSTAT (0x4Cu) -#define EMAC_CTRL_C1RXTHRESHSTAT (0x50u) -#define EMAC_CTRL_C1RXSTAT (0x54u) -#define EMAC_CTRL_C1TXSTAT (0x58u) -#define EMAC_CTRL_C1MISCSTAT (0x5Cu) -#define EMAC_CTRL_C2RXTHRESHSTAT (0x60u) -#define EMAC_CTRL_C2RXSTAT (0x64u) -#define EMAC_CTRL_C2TXSTAT (0x68u) -#define EMAC_CTRL_C2MISCSTAT (0x6Cu) -#define EMAC_CTRL_C0RXIMAX (0x70u) -#define EMAC_CTRL_C0TXIMAX (0x74u) -#define EMAC_CTRL_C1RXIMAX (0x78u) -#define EMAC_CTRL_C1TXIMAX (0x7Cu) -#define EMAC_CTRL_C2RXIMAX (0x80u) -#define EMAC_CTRL_C2TXIMAX (0x84u) - -/**************************************************************************\ -* Field Definition Macros -\**************************************************************************/ - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_lcdc.h b/lib/tiam1808/tiam1808/hw/hw_lcdc.h deleted file mode 100644 index a3363212a..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_lcdc.h +++ /dev/null @@ -1,802 +0,0 @@ - - -/** - * @Component: LCD - * - * @Filename: ../../CredDataBase/lcd_cred.h - * - ============================================================================ */ -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - - -#ifndef _HW_LCDC_H_ -#define _HW_LCDC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***********************************************************************\ - * Register arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundle arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundles Definition -\***********************************************************************/ - - - -/*************************************************************************\ - * Registers Definition -\*************************************************************************/ - -#define LCDC_PID (0x0) -#define LCDC_LCD_CTRL (0x4) -#define LCDC_LCD_STAT (0x8) -#define LCDC_LIDD_CTRL (0xC) -#define LCDC_LIDD_CS_CONF(n) (0x10 + ((n) * 0xC)) -#define LCDC_LIDD_CS_ADDR(n) (0x14 + ((n) * 0xC)) -#define LCDC_LIDD_CS_DATA(n) (0x18 + ((n) * 0xC)) -#define LCDC_LIDD_CS0_CONF (0x10) -#define LCDC_LIDD_CS0_ADDR (0x14) -#define LCDC_LIDD_CS0_DATA (0x18) -#define LCDC_LIDD_CS1_CONF (0x1C) -#define LCDC_LIDD_CS1_ADDR (0x20) -#define LCDC_LIDD_CS2_DATA (0x24) -#define LCDC_RASTER_CTRL (0x28) -#define LCDC_RASTER_TIMING_0 (0x2C) -#define LCDC_RASTER_TIMING_1 (0x30) -#define LCDC_RASTER_TIMING_2 (0x34) -#define LCDC_RASTER_TIMING(n) (0x2C + (n * 4)) -#define LCDC_RASTER_SUBPANEL (0x38) -#define LCDC_RASTER_SUBPANEL2 (0x3C) -#define LCDC_LCDDMA_CTRL (0x40) -#define LCDC_LCDDMA_FB0_BASE (0x44) -#define LCDC_LCDDMA_FB0_CEILING (0x48) -#define LCDC_LCDDMA_FB1_BASE (0x4C) -#define LCDC_LCDDMA_FB1_CEILING (0x50) -#define LCDC_SYSCONFIG (0x54) -#define LCDC_IRQSTATUS_RAW (0x58) -#define LCDC_IRQSTATUS (0x5C) -#define LCDC_IRQENABLE_SET (0x60) -#define LCDC_IRQENABLE_CLEAR (0x64) -#define LCDC_IRQEOI_VECTOR (0x68) -#define LCDC_CLKC_ENABLE (0x6C) -#define LCDC_CLKC_RESET (0x70) - -/**************************************************************************\ - * Field Definition Macros -\**************************************************************************/ - -/* PID */ -#define LCDC_PID_CUSTOM (0x000000C0u) -#define LCDC_PID_CUSTOM_SHIFT (0x00000006u) - -#define LCDC_PID_FUNC (0x0FFF0000u) -#define LCDC_PID_FUNC_SHIFT (0x00000010u) - -#define LCDC_PID_MAJOR (0x00000700u) -#define LCDC_PID_MAJOR_SHIFT (0x00000008u) - -#define LCDC_PID_MINOR (0x0000003Fu) -#define LCDC_PID_MINOR_SHIFT (0x00000000u) - -#define LCDC_PID_RTL (0x0000F800u) -#define LCDC_PID_RTL_SHIFT (0x0000000Bu) - -#define LCDC_PID_SCHEME (0xC0000000u) -#define LCDC_PID_SCHEME_SHIFT (0x0000001Eu) - - -/* CTRL */ -#define LCDC_LCD_CTRL_AUTO_UFLOW_RESTART (0x00000002u) -#define LCDC_LCD_CTRL_AUTO_UFLOW_RESTART_SHIFT (0x00000001u) -#define LCDC_LCD_CTRL_AUTO_UFLOW_RESTART_AUTO (0x1u) -#define LCDC_LCD_CTRL_AUTO_UFLOW_RESTART_MANUAL (0x0u) - -#define LCDC_LCD_CTRL_CLKDIV (0x0000FF00u) -#define LCDC_LCD_CTRL_CLKDIV_SHIFT (0x00000008u) - -#define LCDC_LCD_CTRL_MODESEL (0x00000001u) -#define LCDC_LCD_CTRL_MODESEL_SHIFT (0x00000000u) -#define LCDC_LCD_CTRL_MODESEL_LIDD (0x0u) -#define LCDC_LCD_CTRL_MODESEL_RASTER (0x1u) - - -#define LCDC_LIDD_CTRL_DONE_INT_EN (0x00000400u) -#define LCDC_LIDD_CTRL_DONE_INT_EN_SHIFT (0x0000000Au) - - -#define LCDC_LIDD_CTRL_ALEPOL (0x00000008u) -#define LCDC_LIDD_CTRL_ALEPOL_SHIFT (0x00000003u) -#define LCDC_LIDD_CTRL_ALEPOL_INVERT (0x1u) -#define LCDC_LIDD_CTRL_ALEPOL_NOINVERT (0x0u) - -#define LCDC_LIDD_CTRL_CS0_E0_POL (0x00000040u) -#define LCDC_LIDD_CTRL_CS0_E0_POL_SHIFT (0x00000006u) -#define LCDC_LIDD_CTRL_CS0_E0_POL_INVERT (0x1u) -#define LCDC_LIDD_CTRL_CS0_E0_POL_NOINVERT (0x0u) - -#define LCDC_LIDD_CTRL_CS1_E1_POL (0x00000080u) -#define LCDC_LIDD_CTRL_CS1_E1_POL_SHIFT (0x00000007u) -#define LCDC_LIDD_CTRL_CS1_E1_POL_INVERT (0x1u) -#define LCDC_LIDD_CTRL_CS1_E1_POL_NOINVERT (0x0u) - -#define LCDC_LIDD_CTRL_DMA_CS0_CS1 (0x00000200u) -#define LCDC_LIDD_CTRL_DMA_CS0_CS1_SHIFT (0x00000009u) -#define LCDC_LIDD_CTRL_DMA_CS0_CS1_DMACS0 (0x0u) -#define LCDC_LIDD_CTRL_DMA_CS0_CS1_DMACS1 (0x1u) - -#define LCDC_LIDD_CTRL_LIDD_DMA_EN (0x00000100u) -#define LCDC_LIDD_CTRL_LIDD_DMA_EN_SHIFT (0x00000008u) -#define LCDC_LIDD_CTRL_LIDD_DMA_EN_ACTIVATE (0x1u) -#define LCDC_LIDD_CTRL_LIDD_DMA_EN_DEACTIVATE (0x0u) - -#define LCDC_LIDD_CTRL_LIDD_MODE_SEL (0x00000007u) -#define LCDC_LIDD_CTRL_LIDD_MODE_SEL_SHIFT (0x00000000u) -#define LCDC_LIDD_CTRL_LIDD_MODE_SEL_ASYNC_MPU68 (0x1u) -#define LCDC_LIDD_CTRL_LIDD_MODE_SEL_ASYNC_MPU80 (0x3u) -#define LCDC_LIDD_CTRL_LIDD_MODE_SEL_HITACHI (0x4u) -#define LCDC_LIDD_CTRL_LIDD_MODE_SEL_SYNC_MPU68 (0x0u) -#define LCDC_LIDD_CTRL_LIDD_MODE_SEL_SYNC_MPU80 (0x2u) - -#define LCDC_LIDD_CTRL_RS_EN_POL (0x00000010u) -#define LCDC_LIDD_CTRL_RS_EN_POL_SHIFT (0x00000004u) -#define LCDC_LIDD_CTRL_RS_EN_POL_INVERT (0x1u) -#define LCDC_LIDD_CTRL_RS_EN_POL_NOINVERT (0x0u) - -#define LCDC_LIDD_CTRL_WS_DIR_POL (0x00000020u) -#define LCDC_LIDD_CTRL_WS_DIR_POL_SHIFT (0x00000005u) -#define LCDC_LIDD_CTRL_WS_DIR_POL_ (0x1u) -#define LCDC_LIDD_CTRL_WS_DIR_POL_NOINVERT (0x0u) - - -/* LIDD_CS0_CONF */ -#define LCDC_LIDD_CS0_CONF_R_HOLD (0x0000003Cu) -#define LCDC_LIDD_CS0_CONF_R_HOLD_SHIFT (0x00000002u) - -#define LCDC_LIDD_CS0_CONF_R_STROBE (0x00000FC0u) -#define LCDC_LIDD_CS0_CONF_R_STROBE_SHIFT (0x00000006u) - -#define LCDC_LIDD_CS0_CONF_R_SU (0x0001F000u) -#define LCDC_LIDD_CS0_CONF_R_SU_SHIFT (0x0000000Cu) - -#define LCDC_LIDD_CS0_CONF_TA (0x00000003u) -#define LCDC_LIDD_CS0_CONF_TA_SHIFT (0x00000000u) - -#define LCDC_LIDD_CS0_CONF_W_HOLD (0x001E0000u) -#define LCDC_LIDD_CS0_CONF_W_HOLD_SHIFT (0x00000011u) - -#define LCDC_LIDD_CS0_CONF_W_STROBE (0x07E00000u) -#define LCDC_LIDD_CS0_CONF_W_STROBE_SHIFT (0x00000015u) - -#define LCDC_LIDD_CS0_CONF_W_SU (0xF8000000u) -#define LCDC_LIDD_CS0_CONF_W_SU_SHIFT (0x0000001Bu) - - - -/* LIDD_CS0_ADDR */ -#define LCDC_LIDD_CS0_ADDR_ADR_INDX (0x0000FFFFu) -#define LCDC_LIDD_CS0_ADDR_ADR_INDX_SHIFT (0x00000000u) - - - -/* LIDD_CS0_DATA */ -#define LCDC_LIDD_CS0_DATA_DATA (0x0000FFFFu) -#define LCDC_LIDD_CS0_DATA_DATA_SHIFT (0x00000000u) - - - - -/* LIDD_CS1_CONF */ -#define LCDC_LIDD_CS1_CONF_R_HOLD (0x0000003Cu) -#define LCDC_LIDD_CS1_CONF_R_HOLD_SHIFT (0x00000002u) - -#define LCDC_LIDD_CS1_CONF_R_STROBE (0x00000FC0u) -#define LCDC_LIDD_CS1_CONF_R_STROBE_SHIFT (0x00000006u) - -#define LCDC_LIDD_CS1_CONF_R_SU (0x0001F000u) -#define LCDC_LIDD_CS1_CONF_R_SU_SHIFT (0x0000000Cu) - -#define LCDC_LIDD_CS1_CONF_TA (0x00000003u) -#define LCDC_LIDD_CS1_CONF_TA_SHIFT (0x00000000u) - -#define LCDC_LIDD_CS1_CONF_W_HOLD (0x001E0000u) -#define LCDC_LIDD_CS1_CONF_W_HOLD_SHIFT (0x00000011u) - -#define LCDC_LIDD_CS1_CONF_W_STROBE (0x07E00000u) -#define LCDC_LIDD_CS1_CONF_W_STROBE_SHIFT (0x00000015u) - -#define LCDC_LIDD_CS1_CONF_W_SU (0xF8000000u) -#define LCDC_LIDD_CS1_CONF_W_SU_SHIFT (0x0000001Bu) - - -/* LIDD_CS1_ADDR */ -#define LCDC_LIDD_CS1_ADDR_ADR_INDX (0x0000FFFFu) -#define LCDC_LIDD_CS1_ADDR_ADR_INDX_SHIFT (0x00000000u) - - - - -/* RASTER_CTRL */ -#define LCDC_RASTER_CTRL_ACTVID_EN_VBLANK (0x08000000u) -#define LCDC_RASTER_CTRL_ACTVID_EN_VBLANK_SHIFT (0x0000001Bu) -#define LCDC_RASTER_CTRL_ACTVID_EN_VBLANK_NOACTVID (0x0u) -#define LCDC_RASTER_CTRL_ACTVID_EN_VBLANK_TOGGLEACTVID (0x1u) - -#define LCDC_RASTER_CTRL_FIFO_DMA_DELAY (0x000FF000u) -#define LCDC_RASTER_CTRL_FIFO_DMA_DELAY_SHIFT (0x0000000Cu) -#define LCDC_RASTER_CTRL_FIFO_DMA_DELAY_DISABLED (0x0u) - -#define LCDC_RASTER_CTRL_MONO8B (0x00000200u) -#define LCDC_RASTER_CTRL_MONO8B_SHIFT (0x00000009u) -#define LCDC_RASTER_CTRL_MONO8B_4PIXEL (0x0u) -#define LCDC_RASTER_CTRL_MONO8B_8PIXEL (0x1u) - -#define LCDC_RASTER_CTRL_MONO_COLOR (0x00000002u) -#define LCDC_RASTER_CTRL_MONO_COLOR_SHIFT (0x00000001u) -#define LCDC_RASTER_CTRL_MONO_COLOR_COLOR (0x0u) -#define LCDC_RASTER_CTRL_MONO_COLOR_MONO (0x1u) - -#define LCDC_RASTER_CTRL_NIB_MODE (0x00400000u) -#define LCDC_RASTER_CTRL_NIB_MODE_SHIFT (0x00000016u) -#define LCDC_RASTER_CTRL_NIB_MODE_DISABLED (0x0u) -#define LCDC_RASTER_CTRL_NIB_MODE_ENABLED (0x1u) - -#define LCDC_RASTER_CTRL_PLM (0x00300000u) -#define LCDC_RASTER_CTRL_PLM_SHIFT (0x00000014u) -#define LCDC_RASTER_CTRL_PLM_DATA (0x00000002u) -#define LCDC_RASTER_CTRL_PLM_PALETTE (0x00000001u) -#define LCDC_RASTER_CTRL_PLM_PALETTE_DATA (0x00000000u) - -#define LCDC_RASTER_CTRL_RASTER_EN (0x00000001u) -#define LCDC_RASTER_CTRL_RASTER_EN_SHIFT (0x00000000u) -#define LCDC_RASTER_CTRL_RASTER_EN_DISABLED (0x0u) -#define LCDC_RASTER_CTRL_RASTER_EN_ENABLED (0x1u) - -#define LCDC_RASTER_CTRL_RD_ORDER (0x00000100u) -#define LCDC_RASTER_CTRL_RD_ORDER_SHIFT (0x00000008u) -#define LCDC_RASTER_CTRL_RD_ORDER_H2L (0x1u) -#define LCDC_RASTER_CTRL_RD_ORDER_L2H (0x0u) - -#define LCDC_RASTER_CTRL_STN_565 (0x01000000u) -#define LCDC_RASTER_CTRL_STN_565_SHIFT (0x00000018u) -#define LCDC_RASTER_CTRL_STN_565_12BPP (0x0u) -#define LCDC_RASTER_CTRL_STN_565_16BPP (0x1u) - -#define LCDC_RASTER_CTRL_TFT24 (0x02000000u) -#define LCDC_RASTER_CTRL_TFT24_SHIFT (0x00000019u) -#define LCDC_RASTER_CTRL_TFT24_OFF (0x0u) -#define LCDC_RASTER_CTRL_TFT24_ON (0x1u) - -#define LCDC_RASTER_CTRL_TFT24UNPACKED (0x04000000u) -#define LCDC_RASTER_CTRL_TFT24UNPACKED_SHIFT (0x0000001Au) -#define LCDC_RASTER_CTRL_TFT24UNPACKED_PACKED (0x0u) -#define LCDC_RASTER_CTRL_TFT24UNPACKED_UNPACKED (0x1u) - -#define LCDC_RASTER_CTRL_TFT_ALT_MAP (0x00800000u) -#define LCDC_RASTER_CTRL_TFT_ALT_MAP_SHIFT (0x00000017u) -#define LCDC_RASTER_CTRL_TFT_ALT_MAP_565 (0x1u) -#define LCDC_RASTER_CTRL_TFT_ALT_MAP_ALIGN (0x0u) - -#define LCDC_RASTER_CTRL_TFT_STN (0x00000080u) -#define LCDC_RASTER_CTRL_TFT_STN_SHIFT (0x00000007u) -#define LCDC_RASTER_CTRL_TFT_STN_STN (0x0u) -#define LCDC_RASTER_CTRL_TFT_STN_TFT (0x1u) - - -#define LCDC_RASTER_CTRL_FUF_EN (0x00000040u) -#define LCDC_RASTER_CTRL_FUF_EN_SHIFT (0x00000006u) - -#define LCDC_RASTER_CTRL_SL_EN (0x00000020u) -#define LCDC_RASTER_CTRL_SL_EN_SHIFT (0x00000005u) - -#define LCDC_RASTER_CTRL_PL_EN (0x00000010u) -#define LCDC_RASTER_CTRL_PL_EN_SHIFT (0x00000004u) - -#define LCDC_RASTER_CTRL_DONE_EN (0x00000008u) -#define LCDC_RASTER_CTRL_DONE_EN_SHIFT (0x00000003u) - -#define LCDC_RASTER_CTRL_AC_EN (0x00000004u) -#define LCDC_RASTER_CTRL_AC_EN_SHIFT (0x00000002u) - - - -/* RASTER_TIMING_0 */ -#define LCDC_RASTER_TIMING_0_HBP (0xFF000000u) -#define LCDC_RASTER_TIMING_0_HBP_SHIFT (0x00000018u) - -#define LCDC_RASTER_TIMING_0_HFP (0x00FF0000u) -#define LCDC_RASTER_TIMING_0_HFP_SHIFT (0x00000010u) - -#define LCDC_RASTER_TIMING_0_HSW (0x0000FC00u) -#define LCDC_RASTER_TIMING_0_HSW_SHIFT (0x0000000Au) - -#define LCDC_RASTER_TIMING_0_PPL (0x000003F0u) -#define LCDC_RASTER_TIMING_0_PPL_SHIFT (0x00000004u) - -#define LCDC_RASTER_TIMING_0_PPLMSB (0x00000008u) -#define LCDC_RASTER_TIMING_0_PPLMSB_SHIFT (0x00000003u) - - - -/* RASTER_TIMING_1 */ -#define LCDC_RASTER_TIMING_1_LPP (0x000003FFu) -#define LCDC_RASTER_TIMING_1_LPP_SHIFT (0x00000000u) - -#define LCDC_RASTER_TIMING_1_VBP (0xFF000000u) -#define LCDC_RASTER_TIMING_1_VBP_SHIFT (0x00000018u) - -#define LCDC_RASTER_TIMING_1_VFP (0x00FF0000u) -#define LCDC_RASTER_TIMING_1_VFP_SHIFT (0x00000010u) - -#define LCDC_RASTER_TIMING_1_VSW (0x0000FC00u) -#define LCDC_RASTER_TIMING_1_VSW_SHIFT (0x0000000Au) - - - -/* RASTER_TIMING_2 */ -#define LCDC_RASTER_TIMING_2_ACB (0x0000FF00u) -#define LCDC_RASTER_TIMING_2_ACB_SHIFT (0x00000008u) - -#define LCDC_RASTER_TIMING_2_ACB_I (0x000F0000u) -#define LCDC_RASTER_TIMING_2_ACB_I_SHIFT (0x00000010u) - -#define LCDC_RASTER_TIMING_2_BIAS (0x00800000u) -#define LCDC_RASTER_TIMING_2_BIAS_SHIFT (0x00000017u) -#define LCDC_RASTER_TIMING_2_BIAS_ACTIVE_HIGH (0x0u) -#define LCDC_RASTER_TIMING_2_BIAS_ACTIVE_LOW (0x1u) - -#define LCDC_RASTER_TIMING_2_HBP_HIGHBITS (0x00000030u) -#define LCDC_RASTER_TIMING_2_HBP_HIGHBITS_SHIFT (0x00000006u) - -#define LCDC_RASTER_TIMING_2_HFP_HIGHBITS (0x00000003u) -#define LCDC_RASTER_TIMING_2_HFP_HIGHBITS_SHIFT (0x00000000u) - -#define LCDC_RASTER_TIMING_2_IEO (0x00800000u) -#define LCDC_RASTER_TIMING_2_IEO_SHIFT (0x00000017u) -#define LCDC_RASTER_TIMING_2_IEO_ACTIVE_HIGH (0x0u) -#define LCDC_RASTER_TIMING_2_IEO_ACTIVE_LOW (0x1u) - -#define LCDC_RASTER_TIMING_2_IHS (0x00200000u) -#define LCDC_RASTER_TIMING_2_IHS_SHIFT (0x00000015u) -#define LCDC_RASTER_TIMING_2_IHS_ACTIVE_HIGH (0x0u) -#define LCDC_RASTER_TIMING_2_IHS_ACTIVE_LOW (0x1u) - -#define LCDC_RASTER_TIMING_2_IPC (0x00400000u) -#define LCDC_RASTER_TIMING_2_IPC_SHIFT (0x00000016u) -#define LCDC_RASTER_TIMING_2_IPC_FALLING (0x1u) -#define LCDC_RASTER_TIMING_2_IPC_RISING (0x0u) - -#define LCDC_RASTER_TIMING_2_IVS (0x00100000u) -#define LCDC_RASTER_TIMING_2_IVS_SHIFT (0x00000014u) -#define LCDC_RASTER_TIMING_2_IVS_ACTIVE_HIGH (0x0u) -#define LCDC_RASTER_TIMING_2_IVS_ACTIVE_LOW (0x1u) - -#define LCDC_RASTER_TIMING_2_LPP_B10 (0x04000000u) -#define LCDC_RASTER_TIMING_2_LPP_B10_SHIFT (0x0000001Au) - -#define LCDC_RASTER_TIMING_2_PHSVS_ON_OFF (0x02000000u) -#define LCDC_RASTER_TIMING_2_PHSVS_ON_OFF_SHIFT (0x00000019u) -#define LCDC_RASTER_TIMING_2_PHSVS_ON_OFF_BIT24 (0x1u) -#define LCDC_RASTER_TIMING_2_PHSVS_ON_OFF_OPPOSITE_EDGE (0x0u) - -#define LCDC_RASTER_TIMING_2_PHSVS_RF (0x01000000u) -#define LCDC_RASTER_TIMING_2_PHSVS_RF_SHIFT (0x00000018u) -#define LCDC_RASTER_TIMING_2_PHSVS_RF_FALLING (0x0u) -#define LCDC_RASTER_TIMING_2_PHSVS_RF_RISING (0x1u) - -#define LCDC_RASTER_TIMING_2_SYNC_CTRL (0x02000000u) -#define LCDC_RASTER_TIMING_2_SYNC_CTRL_SHIFT (0x00000019u) -#define LCDC_RASTER_TIMING_2_SYNC_CTRL_BIT24 (0x1u) -#define LCDC_RASTER_TIMING_2_SYNC_CTRL_OPPOSITE_EDGE (0x0u) - -#define LCDC_RASTER_TIMING_2_SYNC_EDGE (0x01000000u) -#define LCDC_RASTER_TIMING_2_SYNC_EDGE_SHIFT (0x00000018u) -#define LCDC_RASTER_TIMING_2_SYNC_EDGE_FALLING (0x0u) -#define LCDC_RASTER_TIMING_2_SYNC_EDGE_RISING (0x1u) - - - -/* RASTER_SUBPANEL */ -#define LCDC_RASTER_SUBPANEL_DPD (0x0000FFFFu) -#define LCDC_RASTER_SUBPANEL_DPD_SHIFT (0x00000000u) - -#define LCDC_RASTER_SUBPANEL_DPDMSB (0x000000FFu) -#define LCDC_RASTER_SUBPANEL_DPDMSB_SHIFT (0x00000000u) - -#define LCDC_RASTER_SUBPANEL_HOLS (0x20000000u) -#define LCDC_RASTER_SUBPANEL_HOLS_SHIFT (0x0000001Du) -#define LCDC_RASTER_SUBPANEL_HOLS_DATA_BOTTOM (0x1u) -#define LCDC_RASTER_SUBPANEL_HOLS_DATA_TOP (0x0u) - -#define LCDC_RASTER_SUBPANEL_LPPT (0x03FF0000u) -#define LCDC_RASTER_SUBPANEL_LPPT_SHIFT (0x00000010u) - -#define LCDC_RASTER_SUBPANEL_LPPT_B10 (0x00000100u) -#define LCDC_RASTER_SUBPANEL_LPPT_B10_SHIFT (0x00000008u) - -#define LCDC_RASTER_SUBPANEL_SPEN (0x80000000u) -#define LCDC_RASTER_SUBPANEL_SPEN_SHIFT (0x0000001Fu) -#define LCDC_RASTER_SUBPANEL_SPEN_DISABLED (0x0u) -#define LCDC_RASTER_SUBPANEL_SPEN_ENABLED (0x1u) - - - -/* LCDDMA_CTRL */ -#define LCDC_LCDDMA_CTRL_BIGENDIAN (0x00000002u) -#define LCDC_LCDDMA_CTRL_BIGENDIAN_SHIFT (0x00000001u) - -#define LCDC_LCDDMA_CTRL_EOF_INTEN (0x00000004) -#define LCDC_LCDDMA_CTRL_EOF_INTEN_SHIFT (0x00000002u) - -#define LCDC_LCDDMA_CTRL_BURST_SIZE (0x00000070u) -#define LCDC_LCDDMA_CTRL_BURST_SIZE_SHIFT (0x00000004u) -#define LCDC_LCDDMA_CTRL_BURST_SIZE_EIGHT (0x00000003u) -#define LCDC_LCDDMA_CTRL_BURST_SIZE_FOUR (0x00000002u) -#define LCDC_LCDDMA_CTRL_BURST_SIZE_ONE (0x00000000u) -#define LCDC_LCDDMA_CTRL_BURST_SIZE_SIXTEEN (0x00000004u) -#define LCDC_LCDDMA_CTRL_BURST_SIZE_TWO (0x00000001u) - -#define LCDC_LCDDMA_CTRL_BYTE_SWAP (0x00000008u) -#define LCDC_LCDDMA_CTRL_BYTE_SWAP_SHIFT (0x00000003u) - -#define LCDC_LCDDMA_CTRL_DMA_MASTER_PRIO (0x00070000u) -#define LCDC_LCDDMA_CTRL_DMA_MASTER_PRIO_SHIFT (0x00000010u) - -#define LCDC_LCDDMA_CTRL_FRAME_MODE (0x00000001u) -#define LCDC_LCDDMA_CTRL_FRAME_MODE_SHIFT (0x00000000u) -#define LCDC_LCDDMA_CTRL_FRAME_MODE_ONE (0x0u) -#define LCDC_LCDDMA_CTRL_FRAME_MODE_TWO (0x1u) - -#define LCDC_LCDDMA_CTRL_TH_FIFO_READY (0x00000700u) -#define LCDC_LCDDMA_CTRL_TH_FIFO_READY_SHIFT (0x00000008u) -#define LCDC_LCDDMA_CTRL_TH_FIFO_READY_EIGHT (0x00000000u) -#define LCDC_LCDDMA_CTRL_TH_FIFO_READY_FIVE_TWELVE (0x00000006u) -#define LCDC_LCDDMA_CTRL_TH_FIFO_READY_ONE_TWENTY_EIGHT (0x00000004u) -#define LCDC_LCDDMA_CTRL_TH_FIFO_READY_SIXTEEN (0x00000001u) -#define LCDC_LCDDMA_CTRL_TH_FIFO_READY_SIXTY_FOUR (0x00000003u) -#define LCDC_LCDDMA_CTRL_TH_FIFO_READY_THIRTY_TWO (0x00000002u) -#define LCDC_LCDDMA_CTRL_TH_FIFO_READY_TWO_FIFTY_SIX (0x00000005u) - - -/* LCDDMA_FB0_BASE */ -#define LCDC_LCDDMA_FB0_BASE_FB0_BASE (0xFFFFFFFCu) -#define LCDC_LCDDMA_FB0_BASE_FB0_BASE_SHIFT (0x00000002u) - - -/* LCDDMA_FB0_CEILING */ -#define LCDC_LCDDMA_FB0_CEILING_FB0_CEIL (0xFFFFFFFCu) -#define LCDC_LCDDMA_FB0_CEILING_FB0_CEIL_SHIFT (0x00000002u) - - -/* LCDDMA_FB1_BASE */ -#define LCDC_LCDDMA_FB1_BASE_FB1_BASE (0xFFFFFFFCu) -#define LCDC_LCDDMA_FB1_BASE_FB1_BASE_SHIFT (0x00000002u) - - -/* LCDDMA_FB1_CEILING */ -#define LCDC_LCDDMA_FB1_CEILING_FB1_CEIL (0xFFFFFFFCu) -#define LCDC_LCDDMA_FB1_CEILING_FB1_CEIL_SHIFT (0x00000002u) - - -/* SYSCONFIG */ -#define LCDC_SYSCONFIG_IDLEMODE (0x000000C0u) -#define LCDC_SYSCONFIG_IDLEMODE_SHIFT (0x00000004u) -#define LCDC_SYSCONFIG_IDLEMODE_FORCE (0x0u) -#define LCDC_SYSCONFIG_IDLEMODE_NOIDLE (0x1u) -#define LCDC_SYSCONFIG_IDLEMODE_SMART (0x2u) -#define LCDC_SYSCONFIG_IDLEMODE_WAKEUP (0x3u) - -#define LCDC_SYSCONFIG_STANDBYMODE (0x00000030u) -#define LCDC_SYSCONFIG_STANDBYMODE_SHIFT (0x00000002u) -#define LCDC_SYSCONFIG_STANDBYMODE_FORCE (0x0u) -#define LCDC_SYSCONFIG_STANDBYMODE_NOSTANDBY (0x1u) -#define LCDC_SYSCONFIG_STANDBYMODE_SMART (0x2u) -#define LCDC_SYSCONFIG_STANDBYMODE_WAKEUP (0x3u) - - -/* IRQSTATUS_RAW */ -#define LCDC_IRQSTATUS_RAW_ACB (0x00000008u) -#define LCDC_IRQSTATUS_RAW_ACB_SHIFT (0x00000003u) -#define LCDC_IRQSTATUS_RAW_ACB_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_RAW_ACB_INACTIVE (0x0u) -#define LCDC_IRQSTATUS_RAW_ACB_SET (0x1u) - -#define LCDC_IRQSTATUS_RAW_DONE (0x00000001u) -#define LCDC_IRQSTATUS_RAW_DONE_SHIFT (0x00000000u) -#define LCDC_IRQSTATUS_RAW_DONE_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_RAW_DONE_INACTIVE (0x0u) -#define LCDC_IRQSTATUS_RAW_DONE_SET (0x1u) - -#define LCDC_IRQSTATUS_RAW_EOF0 (0x00000100u) -#define LCDC_IRQSTATUS_RAW_EOF0_SHIFT (0x00000008u) -#define LCDC_IRQSTATUS_RAW_EOF0_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_RAW_EOF0_INACTIVE (0x0u) -#define LCDC_IRQSTATUS_RAW_EOF0_SET (0x1u) - -#define LCDC_IRQSTATUS_RAW_EOF1 (0x00000200u) -#define LCDC_IRQSTATUS_RAW_EOF1_SHIFT (0x00000009u) -#define LCDC_IRQSTATUS_RAW_EOF1_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_RAW_EOF1_INACTIVE (0x0u) -#define LCDC_IRQSTATUS_RAW_EOF1_SET (0x1u) - -#define LCDC_IRQSTATUS_RAW_FUF (0x00000020u) -#define LCDC_IRQSTATUS_RAW_FUF_SHIFT (0x00000005u) -#define LCDC_IRQSTATUS_RAW_FUF_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_RAW_FUF_INACTIVE (0x0u) -#define LCDC_IRQSTATUS_RAW_FUF_SET (0x1u) - -#define LCDC_IRQSTATUS_RAW_PL (0x00000040u) -#define LCDC_IRQSTATUS_RAW_PL_SHIFT (0x00000006u) -#define LCDC_IRQSTATUS_RAW_PL_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_RAW_PL_INACTIVE (0x0u) -#define LCDC_IRQSTATUS_RAW_PL_SET (0x1u) - -#define LCDC_IRQSTATUS_RAW_RECURRENT_RASTER (0x00000002u) -#define LCDC_IRQSTATUS_RAW_RECURRENT_RASTER_SHIFT (0x00000001u) -#define LCDC_IRQSTATUS_RAW_RECURRENT_RASTER_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_RAW_RECURRENT_RASTER_INACTIVE (0x0u) -#define LCDC_IRQSTATUS_RAW_RECURRENT_RASTER_SET (0x1u) - -#define LCDC_IRQSTATUS_RAW_SYNC (0x00000004u) -#define LCDC_IRQSTATUS_RAW_SYNC_SHIFT (0x00000002u) -#define LCDC_IRQSTATUS_RAW_SYNC_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_RAW_SYNC_INACTIVE (0x0u) -#define LCDC_IRQSTATUS_RAW_SYNC_SET (0x1u) - - -/* IRQSTATUS */ -#define LCDC_IRQSTATUS_ACB (0x00000008u) -#define LCDC_IRQSTATUS_ACB_SHIFT (0x00000003u) -#define LCDC_IRQSTATUS_ACB_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_ACB_CLEAR (0x1u) -#define LCDC_IRQSTATUS_ACB_INACTIVE (0x0u) - -#define LCDC_IRQSTATUS_DONE (0x00000001u) -#define LCDC_IRQSTATUS_DONE_SHIFT (0x00000000u) -#define LCDC_IRQSTATUS_DONE_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_DONE_CLEAR (0x1u) -#define LCDC_IRQSTATUS_DONE_INACTIVE (0x0u) - -#define LCDC_IRQSTATUS_EOF0 (0x00000100u) -#define LCDC_IRQSTATUS_EOF0_SHIFT (0x00000008u) -#define LCDC_IRQSTATUS_EOF0_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_EOF0_CLEAR (0x1u) -#define LCDC_IRQSTATUS_EOF0_INACTIVE (0x0u) - -#define LCDC_IRQSTATUS_EOF1 (0x00000200u) -#define LCDC_IRQSTATUS_EOF1_SHIFT (0x00000009u) -#define LCDC_IRQSTATUS_EOF1_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_EOF1_CLEAR (0x1u) -#define LCDC_IRQSTATUS_EOF1_INACTIVE (0x0u) - -#define LCDC_IRQSTATUS_FUF (0x00000020u) -#define LCDC_IRQSTATUS_FUF_SHIFT (0x00000005u) -#define LCDC_IRQSTATUS_FUF_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_FUF_CLEAR (0x1u) -#define LCDC_IRQSTATUS_FUF_INACTIVE (0x0u) - -#define LCDC_IRQSTATUS_PL (0x00000040u) -#define LCDC_IRQSTATUS_PL_SHIFT (0x00000006u) -#define LCDC_IRQSTATUS_PL_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_PL_CLEAR (0x1u) -#define LCDC_IRQSTATUS_PL_INACTIVE (0x0u) - -#define LCDC_IRQSTATUS_RECURRENT_RASTER (0x00000002u) -#define LCDC_IRQSTATUS_RECURRENT_RASTER_SHIFT (0x00000001u) -#define LCDC_IRQSTATUS_RECURRENT_RASTER_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_RECURRENT_RASTER_CLEAR (0x1u) -#define LCDC_IRQSTATUS_RECURRENT_RASTER_INACTIVE (0x0u) - -#define LCDC_IRQSTATUS_SYNC (0x00000004u) -#define LCDC_IRQSTATUS_SYNC_SHIFT (0x00000002u) -#define LCDC_IRQSTATUS_SYNC_ACTIVE (0x1u) -#define LCDC_IRQSTATUS_SYNC_CLEAR (0x1u) -#define LCDC_IRQSTATUS_SYNC_INACTIVE (0x0u) - -#define LCDC_LCD_STAT_EOF1 (0x00000200u) -#define LCDC_LCD_STAT_EOF1_SHIFT (0x00000009u) - -#define LCDC_LCD_STAT_EOF0 (0x00000100u) -#define LCDC_LCD_STAT_EOF0_SHIFT (0x00000008u) - -#define LCDC_LCD_STAT_PL (0x00000040u) -#define LCDC_LCD_STAT_PL_SHIFT (0x00000006u) - -#define LCDC_LCD_STAT_FUF (0x00000020u) -#define LCDC_LCD_STAT_FUF_SHIFT (0x00000005u) - -#define LCDC_LCD_STAT_ABC (0x00000008u) -#define LCDC_LCD_STAT_ABC_SHIFT (0x00000003u) - -#define LCDC_LCD_STAT_SYNC (0x00000004u) -#define LCDC_LCD_STAT_SYNC_SHIFT (0x00000002u) - -#define LCDC_LCD_STAT_DONE (0x00000001u) -#define LCDC_LCD_STAT_DONE_SHIFT (0x00000000u) - - - -/* IRQENABLE_SET */ -#define LCDC_IRQENABLE_SET_ACB (0x00000008u) -#define LCDC_IRQENABLE_SET_ACB_SHIFT (0x00000003u) -#define LCDC_IRQENABLE_SET_ACB_DISABLED (0x0u) -#define LCDC_IRQENABLE_SET_ACB_ENABLED (0x1u) -#define LCDC_IRQENABLE_SET_ACB_SET (0x1u) - -#define LCDC_IRQENABLE_SET_DONE (0x00000001u) -#define LCDC_IRQENABLE_SET_DONE_SHIFT (0x00000000u) -#define LCDC_IRQENABLE_SET_DONE_DISABLED (0x0u) -#define LCDC_IRQENABLE_SET_DONE_ENABLED (0x1u) -#define LCDC_IRQENABLE_SET_DONE_SET (0x1u) - -#define LCDC_IRQENABLE_SET_EOF0 (0x00000100u) -#define LCDC_IRQENABLE_SET_EOF0_SHIFT (0x00000008u) -#define LCDC_IRQENABLE_SET_EOF0_DISABLED (0x0u) -#define LCDC_IRQENABLE_SET_EOF0_ENABLED (0x1u) -#define LCDC_IRQENABLE_SET_EOF0_SET (0x1u) - -#define LCDC_IRQENABLE_SET_EOF1 (0x00000200u) -#define LCDC_IRQENABLE_SET_EOF1_SHIFT (0x00000009u) -#define LCDC_IRQENABLE_SET_EOF1_DISABLED (0x0u) -#define LCDC_IRQENABLE_SET_EOF1_ENABLED (0x1u) -#define LCDC_IRQENABLE_SET_EOF1_SET (0x1u) - -#define LCDC_IRQENABLE_SET_FUF (0x00000020u) -#define LCDC_IRQENABLE_SET_FUF_SHIFT (0x00000005u) -#define LCDC_IRQENABLE_SET_FUF_SET (0x1u) - -#define LCDC_IRQENABLE_SET_PL (0x00000040u) -#define LCDC_IRQENABLE_SET_PL_SHIFT (0x00000006u) -#define LCDC_IRQENABLE_SET_PL_DISABLED (0x0u) -#define LCDC_IRQENABLE_SET_PL_ENABLED (0x1u) -#define LCDC_IRQENABLE_SET_PL_SET (0x1u) - -#define LCDC_IRQENABLE_SET_RECURRENT_RASTER (0x00000002u) -#define LCDC_IRQENABLE_SET_RECURRENT_RASTER_SHIFT (0x00000001u) -#define LCDC_IRQENABLE_SET_RECURRENT_RASTER_DISABLED (0x0u) -#define LCDC_IRQENABLE_SET_RECURRENT_RASTER_ENABLED (0x1u) -#define LCDC_IRQENABLE_SET_RECURRENT_RASTER_SET (0x1u) - -#define LCDC_IRQENABLE_SET_SYNC (0x00000004u) -#define LCDC_IRQENABLE_SET_SYNC_SHIFT (0x00000002u) -#define LCDC_IRQENABLE_SET_SYNC_DISABLED (0x0u) -#define LCDC_IRQENABLE_SET_SYNC_ENABLED (0x1u) -#define LCDC_IRQENABLE_SET_SYNC_SET (0x1u) - - -/* IRQENABLE_CLEAR */ -#define LCDC_IRQENABLE_CLEAR_ACB (0x00000008u) -#define LCDC_IRQENABLE_CLEAR_ACB_SHIFT (0x00000003u) -#define LCDC_IRQENABLE_CLEAR_ACB_CLEAR (0x1u) -#define LCDC_IRQENABLE_CLEAR_ACB_DISABLED (0x0u) -#define LCDC_IRQENABLE_CLEAR_ACB_ENABLED (0x1u) - -#define LCDC_IRQENABLE_CLEAR_DONE (0x00000001u) -#define LCDC_IRQENABLE_CLEAR_DONE_SHIFT (0x00000000u) -#define LCDC_IRQENABLE_CLEAR_DONE_CLEAR (0x1u) -#define LCDC_IRQENABLE_CLEAR_DONE_DISABLED (0x0u) -#define LCDC_IRQENABLE_CLEAR_DONE_ENABLED (0x1u) - -#define LCDC_IRQENABLE_CLEAR_EOF0 (0x00000100u) -#define LCDC_IRQENABLE_CLEAR_EOF0_SHIFT (0x00000008u) -#define LCDC_IRQENABLE_CLEAR_EOF0_CLEAR (0x1u) -#define LCDC_IRQENABLE_CLEAR_EOF0_DISABLED (0x0u) -#define LCDC_IRQENABLE_CLEAR_EOF0_ENABLED (0x1u) - -#define LCDC_IRQENABLE_CLEAR_EOF1 (0x00000200u) -#define LCDC_IRQENABLE_CLEAR_EOF1_SHIFT (0x00000009u) -#define LCDC_IRQENABLE_CLEAR_EOF1_CLEAR (0x1u) -#define LCDC_IRQENABLE_CLEAR_EOF1_DISABLED (0x0u) -#define LCDC_IRQENABLE_CLEAR_EOF1_ENABLED (0x1u) - -#define LCDC_IRQENABLE_CLEAR_FUF (0x00000020u) -#define LCDC_IRQENABLE_CLEAR_FUF_SHIFT (0x00000005u) -#define LCDC_IRQENABLE_CLEAR_FUF_CLEAR (0x1u) - -#define LCDC_IRQENABLE_CLEAR_PL (0x00000040u) -#define LCDC_IRQENABLE_CLEAR_PL_SHIFT (0x00000006u) -#define LCDC_IRQENABLE_CLEAR_PL_CLEAR (0x1u) -#define LCDC_IRQENABLE_CLEAR_PL_DISABLED (0x0u) -#define LCDC_IRQENABLE_CLEAR_PL_ENABLED (0x1u) - -#define LCDC_IRQENABLE_CLEAR_RECURRENT_RASTER (0x00000002u) -#define LCDC_IRQENABLE_CLEAR_RECURRENT_RASTER_SHIFT (0x00000001u) -#define LCDC_IRQENABLE_CLEAR_RECURRENT_RASTER_CLEAR (0x1u) -#define LCDC_IRQENABLE_CLEAR_RECURRENT_RASTER_DISABLED (0x0u) -#define LCDC_IRQENABLE_CLEAR_RECURRENT_RASTER_ENABLED (0x1u) - -#define LCDC_IRQENABLE_CLEAR_SYNC (0x00000004u) -#define LCDC_IRQENABLE_CLEAR_SYNC_SHIFT (0x00000002u) -#define LCDC_IRQENABLE_CLEAR_SYNC_CLEAR (0x1u) -#define LCDC_IRQENABLE_CLEAR_SYNC_DISABLED (0x0u) -#define LCDC_IRQENABLE_CLEAR_SYNC_ENABLED (0x1u) - -/* CLKC_ENABLE */ -#define LCDC_CLKC_ENABLE_CORE (0x00000001u) -#define LCDC_CLKC_ENABLE_CORE_SHIFT (0x00000000u) -#define LCDC_CLKC_ENABLE_CORE_DISABLE (0x0u) -#define LCDC_CLKC_ENABLE_CORE_ENABLE (0x1u) - -#define LCDC_CLKC_ENABLE_DMA (0x00000004u) -#define LCDC_CLKC_ENABLE_DMA_SHIFT (0x00000002u) -#define LCDC_CLKC_ENABLE_DMA_DISABLE (0x0u) -#define LCDC_CLKC_ENABLE_DMA_ENABLE (0x1u) - -#define LCDC_CLKC_ENABLE_LIDD (0x00000002u) -#define LCDC_CLKC_ENABLE_LIDD_SHIFT (0x00000001u) -#define LCDC_CLKC_ENABLE_LIDD_DISABLE (0x0u) -#define LCDC_CLKC_ENABLE_LIDD_ENABLE (0x1u) - - - -/* CLKC_RESET */ -#define LCDC_CLKC_RESET_CORE (0x00000001u) -#define LCDC_CLKC_RESET_CORE_SHIFT (0x00000000u) -#define LCDC_CLKC_RESET_CORE_DISABLE (0x0u) -#define LCDC_CLKC_RESET_CORE_ENABLE (0x1u) - -#define LCDC_CLKC_RESET_DMA (0x00000004u) -#define LCDC_CLKC_RESET_DMA_SHIFT (0x00000002u) -#define LCDC_CLKC_RESET_DMA_DISABLE (0x0u) -#define LCDC_CLKC_RESET_DMA_ENABLE (0x1u) - -#define LCDC_CLKC_RESET_LIDD (0x00000002u) -#define LCDC_CLKC_RESET_LIDD_SHIFT (0x00000001u) -#define LCDC_CLKC_RESET_LIDD_DISABLE (0x0u) -#define LCDC_CLKC_RESET_LIDD_ENABLE (0x1u) - -#define LCDC_CLKC_RESET_MAIN (0x00000008u) -#define LCDC_CLKC_RESET_MAIN_SHIFT (0x00000003u) -#define LCDC_CLKC_RESET_MAIN_DISABLE (0x0u) -#define LCDC_CLKC_RESET_MAIN_ENABLE (0x1u) - - - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_mailbox.h b/lib/tiam1808/tiam1808/hw/hw_mailbox.h deleted file mode 100644 index 2f14467aa..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_mailbox.h +++ /dev/null @@ -1,206 +0,0 @@ - - -/** - * @Component: MAILBOX - * - * @Filename: mailbox_cred.h - * - ============================================================================ */ -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - - -#ifndef __HW_MAILBOX_H__ -#define __HW_MAILBOX_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***********************************************************************\ - * Register arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundle arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundles Definition -\***********************************************************************/ - - - -/*************************************************************************\ - * Registers Definition -\*************************************************************************/ - -#define MAILBOX_REVISION (0x0) -#define MAILBOX_SYSCONFIG (0x10) -#define MAILBOX_MESSAGE(n) (0x40 + ((n) * 4)) -#define MAILBOX_FIFOSTATUS(n) (0x80 + ((n) * 4)) -#define MAILBOX_MESSAGESTATUS(n) (0xc0 + ((n) * 4)) -#define MAILBOX_IRQSTATUS_RAW(n) (0x100 + ((n) * 0x10)) -#define MAILBOX_IRQSTATUS_CLR(n) (0x104 + ((n) * 0x10)) -#define MAILBOX_IRQENABLE_SET(n) (0x108 + ((n) * 0x10)) -#define MAILBOX_IRQENABLE_CLR(n) (0x10c + ((n) * 0x10)) - -/**************************************************************************\ - * Field Definition Macros -\**************************************************************************/ - -/* REVISION */ -#define MAILBOX_REVISION_CUSTOM (0x000000C0u) -#define MAILBOX_REVISION_CUSTOM_SHIFT (0x00000006u) - -#define MAILBOX_REVISION_FUNC (0x0FFF0000u) -#define MAILBOX_REVISION_FUNC_SHIFT (0x00000010u) - -#define MAILBOX_REVISION_MAJOR (0x00000700u) -#define MAILBOX_REVISION_MAJOR_SHIFT (0x00000008u) - -#define MAILBOX_REVISION_MINOR (0x0000003Fu) -#define MAILBOX_REVISION_MINOR_SHIFT (0x00000000u) - -#define MAILBOX_REVISION_RES (0x30000000u) -#define MAILBOX_REVISION_RES_SHIFT (0x0000001Cu) - -#define MAILBOX_REVISION_RTL (0x0000F800u) -#define MAILBOX_REVISION_RTL_SHIFT (0x0000000Bu) - -#define MAILBOX_REVISION_SCHEME (0xC0000000u) -#define MAILBOX_REVISION_SCHEME_SHIFT (0x0000001Eu) - - -/* SYSCONFIG */ -#define MAILBOX_SYSCONFIG_SIDLEMODE (0x0000000Cu) -#define MAILBOX_SYSCONFIG_SIDLEMODE_SHIFT (0x00000002u) -#define MAILBOX_SYSCONFIG_SIDLEMODE_FORCEIDLE (0x0u) -#define MAILBOX_SYSCONFIG_SIDLEMODE_NOIDLE (0x1u) -#define MAILBOX_SYSCONFIG_SIDLEMODE_RESERVED (0x3u) -#define MAILBOX_SYSCONFIG_SIDLEMODE_SMARTIDLE (0x2u) - -#define MAILBOX_SYSCONFIG_SOFTRESET (0x00000001u) -#define MAILBOX_SYSCONFIG_SOFTRESET_SHIFT (0x00000000u) -#define MAILBOX_SYSCONFIG_SOFTRESET_AUTO (0x0u) -#define MAILBOX_SYSCONFIG_SOFTRESET_MANUAL (0x1u) - - -/* MESSAGE */ -#define MAILBOX_MESSAGE_MESSAGEVALUEMBM (0xFFFFFFFFu) -#define MAILBOX_MESSAGE_MESSAGEVALUEMBM_SHIFT (0x00000000u) - -/* FIFOSTATUS_0 */ -#define MAILBOX_FIFOSTATUS_FIFOFULLMBM (0x00000001u) -#define MAILBOX_FIFOSTATUS_FIFOFULLMBM_SHIFT (0x00000000u) -#define MAILBOX_FIFOSTATUS_FIFOFULLMBM_FULL (0x1u) -#define MAILBOX_FIFOSTATUS_FIFOFULLMBM_NOTFULL (0x0u) - -/* MESSAGESTATUS */ -#define MAILBOX_MESSAGESTATUS_NBOFMSGMBM (0x00000007u) -#define MAILBOX_MESSAGESTATUS_NBOFMSGMBM_SHIFT (0x00000000u) - -/* IRQSTATUS_RAW */ -#define MAILBOX_IRQSTATUS_RAW_NEWMSGSTATUSUUMB(m) (0x1u << ((m)*2)) -#define MAILBOX_IRQSTATUS_RAW_NEWMSGSTATUSUUMB_SHIFT(m) ((m)*2) -#define MAILBOX_IRQSTATUS_RAW_NEWMSGSTATUSUUMB_EVENTPENDING (0x1u) -#define MAILBOX_IRQSTATUS_RAW_NEWMSGSTATUSUUMB_NOACTION (0x0u) -#define MAILBOX_IRQSTATUS_RAW_NEWMSGSTATUSUUMB_NOEVENT (0x0u) -#define MAILBOX_IRQSTATUS_RAW_NEWMSGSTATUSUUMB_SETEVENT (0x1u) - -#define MAILBOX_IRQSTATUS_RAW_NOTFULLSTATUSUUMB(m) (0x1u << (((m)*2)+1)) -#define MAILBOX_IRQSTATUS_RAW_NOTFULLSTATUSUUMB_SHIFT(m) (((m)*2)+1) -#define MAILBOX_IRQSTATUS_RAW_NOTFULLSTATUSUUMB_EVENTPENDING (0x1u) -#define MAILBOX_IRQSTATUS_RAW_NOTFULLSTATUSUUMB_NOACTION (0x0u) -#define MAILBOX_IRQSTATUS_RAW_NOTFULLSTATUSUUMB_NOEVENT (0x0u) -#define MAILBOX_IRQSTATUS_RAW_NOTFULLSTATUSUUMB_SETEVENT (0x1u) - - -/* IRQSTATUS_CLR */ -#define MAILBOX_IRQSTATUS_CLR_NEWMSGSTATUSUUMB(m) (0x1u << ((m)*2)) -#define MAILBOX_IRQSTATUS_CLR_NEWMSGSTATUSUUMB_SHIFT(m) ((m)*2) -#define MAILBOX_IRQSTATUS_CLR_NEWMSGSTATUSUUMB_EVENTPENDING (0x1u) -#define MAILBOX_IRQSTATUS_CLR_NEWMSGSTATUSUUMB_NOACTION (0x0u) -#define MAILBOX_IRQSTATUS_CLR_NEWMSGSTATUSUUMB_NOEVENT (0x0u) -#define MAILBOX_IRQSTATUS_CLR_NEWMSGSTATUSUUMB_SETEVENT (0x1u) - -#define MAILBOX_IRQSTATUS_CLR_NOTFULLSTATUSUUMB(m) (0x1u << (((m)*2)+1)) -#define MAILBOX_IRQSTATUS_CLR_NOTFULLSTATUSUUMB_SHIFT(m) (((m)*2)+1) -#define MAILBOX_IRQSTATUS_CLR_NOTFULLSTATUSUUMB_EVENTPENDING (0x1u) -#define MAILBOX_IRQSTATUS_CLR_NOTFULLSTATUSUUMB_NOACTION (0x0u) -#define MAILBOX_IRQSTATUS_CLR_NOTFULLSTATUSUUMB_NOEVENT (0x0u) -#define MAILBOX_IRQSTATUS_CLR_NOTFULLSTATUSUUMB_SETEVENT (0x1u) - - -/* IRQENABLE_SET */ -#define MAILBOX_IRQENABLE_SET_NEWMSGSTATUSUUMB(m) (0x1u << ((m)*2)) -#define MAILBOX_IRQENABLE_SET_NEWMSGSTATUSUUMB_SHIFT(m) ((m)*2) -#define MAILBOX_IRQENABLE_SET_NEWMSGSTATUSUUMB_EVENTPENDING (0x1u) -#define MAILBOX_IRQENABLE_SET_NEWMSGSTATUSUUMB_NOACTION (0x0u) -#define MAILBOX_IRQENABLE_SET_NEWMSGSTATUSUUMB_NOEVENT (0x0u) -#define MAILBOX_IRQENABLE_SET_NEWMSGSTATUSUUMB_SETEVENT (0x1u) - -#define MAILBOX_IRQENABLE_SET_NOTFULLSTATUSUUMB(m) (0x1u << (((m)*2)+1)) -#define MAILBOX_IRQENABLE_SET_NOTFULLSTATUSUUMB_SHIFT(m) (((m)*2)+1) -#define MAILBOX_IRQENABLE_SET_NOTFULLSTATUSUUMB_EVENTPENDING (0x1u) -#define MAILBOX_IRQENABLE_SET_NOTFULLSTATUSUUMB_NOACTION (0x0u) -#define MAILBOX_IRQENABLE_SET_NOTFULLSTATUSUUMB_NOEVENT (0x0u) -#define MAILBOX_IRQENABLE_SET_NOTFULLSTATUSUUMB_SETEVENT (0x1u) - - -/* IRQENABLE_CLR */ -#define MAILBOX_IRQENABLE_CLR_NEWMSGSTATUSUUMB(m) (0x1u << ((m)*2)) -#define MAILBOX_IRQENABLE_CLR_NEWMSGSTATUSUUMB_SHIFT(m) ((m)*2) -#define MAILBOX_IRQENABLE_CLR_NEWMSGSTATUSUUMB_EVENTPENDING (0x1u) -#define MAILBOX_IRQENABLE_CLR_NEWMSGSTATUSUUMB_NOACTION (0x0u) -#define MAILBOX_IRQENABLE_CLR_NEWMSGSTATUSUUMB_NOEVENT (0x0u) -#define MAILBOX_IRQENABLE_CLR_NEWMSGSTATUSUUMB_SETEVENT (0x1u) - -#define MAILBOX_IRQENABLE_CLR_NOTFULLSTATUSUUMB(m) (0x1u << (((m)*2)+1)) -#define MAILBOX_IRQENABLE_CLR_NOTFULLSTATUSUUMB_SHIFT(m) (((m)*2)+1) -#define MAILBOX_IRQENABLE_CLR_NOTFULLSTATUSUUMB_EVENTPENDING (0x1u) -#define MAILBOX_IRQENABLE_CLR_NOTFULLSTATUSUUMB_NOACTION (0x0u) -#define MAILBOX_IRQENABLE_CLR_NOTFULLSTATUSUUMB_NOEVENT (0x0u) -#define MAILBOX_IRQENABLE_CLR_NOTFULLSTATUSUUMB_SETEVENT (0x1u) - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_pllc_C6748.h b/lib/tiam1808/tiam1808/hw/hw_pllc_C6748.h deleted file mode 100644 index 54cfbe0d8..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_pllc_C6748.h +++ /dev/null @@ -1,371 +0,0 @@ -/** - * \file hw_pllc_C6748.h - * - * \brief Hardware definitions for PLLC on C6748 - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - - -#ifndef _HW_PLLC_H_ -#define _HW_PLLC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define PLLC_REVID (0x0) -#define PLLC_RSTYPE (0xE4) -#define PLLC_PLLCTL (0x100) -#define PLLC_OCSEL (0x104) -#define PLLC_PLLM (0x110) -#define PLLC_PREDIV (0x114) -#define PLLC_PLLDIV1 (0x118) -#define PLLC_PLLDIV2 (0x11C) -#define PLLC_PLLDIV3 (0x120) -#define PLLC_OSCDIV (0x124) -#define PLLC_POSTDIV (0x128) -#define PLLC_PLLCMD (0x138) -#define PLLC_PLLSTAT (0x13C) -#define PLLC_ALNCTL (0x140) -#define PLLC_DCHANGE (0x144) -#define PLLC_CKEN (0x148) -#define PLLC_CKSTAT (0x14C) -#define PLLC_SYSTAT (0x150) -#define PLLC_PLLDIV4 (0x160) -#define PLLC_PLLDIV5 (0x164) -#define PLLC_PLLDIV6 (0x168) -#define PLLC_PLLDIV7 (0x16C) -#define PLLC_EMUCNT0 (0x1F0) -#define PLLC_EMUCNT1 (0x1F4) - -/**************************************************************************\ -* Field Definition Macros -\**************************************************************************/ - -/* REVID */ - -#define PLLC_REVID_REV (0xFFFFFFFFu) -#define PLLC_REVID_REV_SHIFT (0x00000000u) - - -/* RSTYPE */ - - -#define PLLC_RSTYPE_PLLSWRST (0x00000004u) -#define PLLC_RSTYPE_PLLSWRST_SHIFT (0x00000002u) - -#define PLLC_RSTYPE_XWRST (0x00000002u) -#define PLLC_RSTYPE_XWRST_SHIFT (0x00000001u) - -#define PLLC_RSTYPE_POR (0x00000001u) -#define PLLC_RSTYPE_POR_SHIFT (0x00000000u) - - -/* PLLCTL */ - - -#define PLLC_PLLCTL_EXTCLKSRC (0x00000200u) -#define PLLC_PLLCTL_EXTCLKSRC_SHIFT (0x00000009u) - -#define PLLC_PLLCTL_CLKMODE (0x00000100u) -#define PLLC_PLLCTL_CLKMODE_SHIFT (0x00000008u) - -#define PLLC_PLLCTL_PLLENSRC (0x00000020u) -#define PLLC_PLLCTL_PLLENSRC_SHIFT (0x00000005u) - -#define PLLC_PLLCTL_PLLDIS (0x00000010u) -#define PLLC_PLLCTL_PLLDIS_SHIFT (0x00000004u) - -#define PLLC_PLLCTL_PLLRST (0x00000008u) -#define PLLC_PLLCTL_PLLRST_SHIFT (0x00000003u) - -#define PLLC_PLLCTL_PLLPWRDN (0x00000002u) -#define PLLC_PLLCTL_PLLPWRDN_SHIFT (0x00000001u) - -#define PLLC_PLLCTL_PLLEN (0x00000001u) -#define PLLC_PLLCTL_PLLEN_SHIFT (0x00000000u) - - -/* OCSEL */ - - -#define PLLC_OCSEL_OCSRC (0x0000001Fu) -#define PLLC_OCSEL_OCSRC_SHIFT (0x00000000u) -/*----OCSRC Tokens----*/ -#define PLLC_OCSEL_OCSRC_CLKIN (0x00000014u) -#define PLLC_OCSEL_OCSRC_SYSCLK1 (0x00000017u) -#define PLLC_OCSEL_OCSRC_SYSCLK2 (0x00000018u) -#define PLLC_OCSEL_OCSRC_SYSCLK3 (0x00000019u) -#define PLLC_OCSEL_OCSRC_SYSCLK4 (0x0000001au) -#define PLLC_OCSEL_OCSRC_SYSCLK5 (0x0000001bu) -#define PLLC_OCSEL_OCSRC_SYSCLK6 (0x0000001cu) -#define PLLC_OCSEL_OCSRC_SYSCLK7 (0x0000001du) -#define PLLC_OCSEL_OCSRC_RSVD (0x0000001eu) - - -/* PLLM */ - - -#define PLLC_PLLM_PLLM (0x0000001Fu) -#define PLLC_PLLM_PLLM_SHIFT (0x00000000u) - - -/* PREDIV */ - - -#define PLLC_PREDIV_PREDEN (0x00008000u) -#define PLLC_PREDIV_PREDEN_SHIFT (0x0000000Fu) - -#define PLLC_PREDIV_RATIO (0x0000001Fu) -#define PLLC_PREDIV_RATIO_SHIFT (0x00000000u) - - -/* PLLDIV1 */ - - -#define PLLC_PLLDIV1_D1EN (0x00008000u) -#define PLLC_PLLDIV1_D1EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV1_RATIO (0x0000001Fu) -#define PLLC_PLLDIV1_RATIO_SHIFT (0x00000000u) - - -/* PLLDIV2 */ - - -#define PLLC_PLLDIV2_D2EN (0x00008000u) -#define PLLC_PLLDIV2_D2EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV2_RATIO (0x0000001Fu) -#define PLLC_PLLDIV2_RATIO_SHIFT (0x00000000u) - - -/* PLLDIV3 */ - - -#define PLLC_PLLDIV3_D3EN (0x00008000u) -#define PLLC_PLLDIV3_D3EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV3_RATIO (0x0000001Fu) -#define PLLC_PLLDIV3_RATIO_SHIFT (0x00000000u) - - -/* OSCDIV */ - - -#define PLLC_OSCDIV_OD1EN (0x00008000u) -#define PLLC_OSCDIV_OD1EN_SHIFT (0x0000000Fu) - -#define PLLC_OSCDIV_RATIO (0x0000001Fu) -#define PLLC_OSCDIV_RATIO_SHIFT (0x00000000u) - - -/* POSTDIV */ - - -#define PLLC_POSTDIV_POSTDEN (0x00008000u) -#define PLLC_POSTDIV_POSTDEN_SHIFT (0x0000000Fu) - -#define PLLC_POSTDIV_RATIO (0x0000001Fu) -#define PLLC_POSTDIV_RATIO_SHIFT (0x00000000u) - - -/* PLLCMD */ - - -#define PLLC_PLLCMD_GOSET (0x00000001u) -#define PLLC_PLLCMD_GOSET_SHIFT (0x00000000u) - -/* PLLSTAT */ - - -#define PLLC_PLLSTAT_STABLE (0x00000004u) -#define PLLC_PLLSTAT_STABLE_SHIFT (0x00000002u) - -#define PLLC_PLLSTAT_GOSTAT (0x00000001u) -#define PLLC_PLLSTAT_GOSTAT_SHIFT (0x00000000u) - - -/* ALNCTL */ - - -#define PLLC_ALNCTL_ALN7 (0x00000040u) -#define PLLC_ALNCTL_ALN7_SHIFT (0x00000006u) - -#define PLLC_ALNCTL_ALN6 (0x00000020u) -#define PLLC_ALNCTL_ALN6_SHIFT (0x00000005u) - -#define PLLC_ALNCTL_ALN5 (0x00000010u) -#define PLLC_ALNCTL_ALN5_SHIFT (0x00000004u) - -#define PLLC_ALNCTL_ALN4 (0x00000008u) -#define PLLC_ALNCTL_ALN4_SHIFT (0x00000003u) - -#define PLLC_ALNCTL_ALN3 (0x00000004u) -#define PLLC_ALNCTL_ALN3_SHIFT (0x00000002u) - -#define PLLC_ALNCTL_ALN2 (0x00000002u) -#define PLLC_ALNCTL_ALN2_SHIFT (0x00000001u) - -#define PLLC_ALNCTL_ALN1 (0x00000001u) -#define PLLC_ALNCTL_ALN1_SHIFT (0x00000000u) - -/* DCHANGE */ - - -#define PLLC_DCHANGE_SYS7 (0x00000040u) -#define PLLC_DCHANGE_SYS7_SHIFT (0x00000006u) - -#define PLLC_DCHANGE_SYS6 (0x00000020u) -#define PLLC_DCHANGE_SYS6_SHIFT (0x00000005u) - -#define PLLC_DCHANGE_SYS5 (0x00000010u) -#define PLLC_DCHANGE_SYS5_SHIFT (0x00000004u) - -#define PLLC_DCHANGE_SYS4 (0x00000008u) -#define PLLC_DCHANGE_SYS4_SHIFT (0x00000003u) - -#define PLLC_DCHANGE_SYS3 (0x00000004u) -#define PLLC_DCHANGE_SYS3_SHIFT (0x00000002u) - -#define PLLC_DCHANGE_SYS2 (0x00000002u) -#define PLLC_DCHANGE_SYS2_SHIFT (0x00000001u) - -#define PLLC_DCHANGE_SYS1 (0x00000001u) -#define PLLC_DCHANGE_SYS1_SHIFT (0x00000000u) - -/* CKEN */ - - -#define PLLC_CKEN_OBSEN (0x00000002u) -#define PLLC_CKEN_OBSEN_SHIFT (0x00000001u) - -#define PLLC_CKEN_AUXEN (0x00000001u) -#define PLLC_CKEN_AUXEN_SHIFT (0x00000000u) - - -/* CKSTAT */ - - -#define PLLC_CKSTAT_OBSON (0x00000002u) -#define PLLC_CKSTAT_OBSON_SHIFT (0x00000001u) - -#define PLLC_CKSTAT_AUXEN (0x00000001u) -#define PLLC_CKSTAT_AUXEN_SHIFT (0x00000000u) - -/* SYSTAT */ - - -#define PLLC_SYSTAT_SYS7ON (0x00000040u) -#define PLLC_SYSTAT_SYS7ON_SHIFT (0x00000006u) - -#define PLLC_SYSTAT_SYS6ON (0x00000020u) -#define PLLC_SYSTAT_SYS6ON_SHIFT (0x00000005u) - -#define PLLC_SYSTAT_SYS5ON (0x00000010u) -#define PLLC_SYSTAT_SYS5ON_SHIFT (0x00000004u) - -#define PLLC_SYSTAT_SYS4ON (0x00000008u) -#define PLLC_SYSTAT_SYS4ON_SHIFT (0x00000003u) - -#define PLLC_SYSTAT_SYS3ON (0x00000004u) -#define PLLC_SYSTAT_SYS3ON_SHIFT (0x00000002u) - -#define PLLC_SYSTAT_SYS2ON (0x00000002u) -#define PLLC_SYSTAT_SYS2ON_SHIFT (0x00000001u) - -#define PLLC_SYSTAT_SYS1ON (0x00000001u) -#define PLLC_SYSTAT_SYS1ON_SHIFT (0x00000000u) - - -/* PLLDIV4 */ - - -#define PLLC_PLLDIV4_D4EN (0x00008000u) -#define PLLC_PLLDIV4_D4EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV4_RATIO (0x0000001Fu) -#define PLLC_PLLDIV4_RATIO_SHIFT (0x00000000u) - - -/* PLLDIV5 */ - - -#define PLLC_PLLDIV5_D5EN (0x00008000u) -#define PLLC_PLLDIV5_D5EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV5_RATIO (0x0000001Fu) -#define PLLC_PLLDIV5_RATIO_SHIFT (0x00000000u) - - -/* PLLDIV6 */ - - -#define PLLC_PLLDIV6_D6EN (0x00008000u) -#define PLLC_PLLDIV6_D6EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV6_RATIO (0x0000001Fu) -#define PLLC_PLLDIV6_RATIO_SHIFT (0x00000000u) - - -/* PLLDIV7 */ - - -#define PLLC_PLLDIV7_D7EN (0x00008000u) -#define PLLC_PLLDIV7_D7EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV7_RATIO (0x0000001Fu) -#define PLLC_PLLDIV7_RATIO_SHIFT (0x00000000u) - - -/* EMUCNT0 */ - -#define PLLC_EMUCNT0_COUNT (0xFFFFFFFFu) -#define PLLC_EMUCNT0_COUNT_SHIFT (0x00000000u) - - -/* EMUCNT1 */ - -#define PLLC_EMUCNT1_COUNT (0xFFFFFFFFu) -#define PLLC_EMUCNT1_COUNT_SHIFT (0x00000000u) - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_pllc_OMAPL138.h b/lib/tiam1808/tiam1808/hw/hw_pllc_OMAPL138.h deleted file mode 100644 index b62a6438f..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_pllc_OMAPL138.h +++ /dev/null @@ -1,371 +0,0 @@ -/** - * \file hw_pllc_OMAPL138.h - * - * \brief Hardware definitions for PLLC on OMAPL138 - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - - -#ifndef _HW_PLLC_H_ -#define _HW_PLLC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define PLLC_REVID (0x0) -#define PLLC_RSTYPE (0xE4) -#define PLLC_PLLCTL (0x100) -#define PLLC_OCSEL (0x104) -#define PLLC_PLLM (0x110) -#define PLLC_PREDIV (0x114) -#define PLLC_PLLDIV1 (0x118) -#define PLLC_PLLDIV2 (0x11C) -#define PLLC_PLLDIV3 (0x120) -#define PLLC_OSCDIV (0x124) -#define PLLC_POSTDIV (0x128) -#define PLLC_PLLCMD (0x138) -#define PLLC_PLLSTAT (0x13C) -#define PLLC_ALNCTL (0x140) -#define PLLC_DCHANGE (0x144) -#define PLLC_CKEN (0x148) -#define PLLC_CKSTAT (0x14C) -#define PLLC_SYSTAT (0x150) -#define PLLC_PLLDIV4 (0x160) -#define PLLC_PLLDIV5 (0x164) -#define PLLC_PLLDIV6 (0x168) -#define PLLC_PLLDIV7 (0x16C) -#define PLLC_EMUCNT0 (0x1F0) -#define PLLC_EMUCNT1 (0x1F4) - -/**************************************************************************\ -* Field Definition Macros -\**************************************************************************/ - -/* REVID */ - -#define PLLC_REVID_REV (0xFFFFFFFFu) -#define PLLC_REVID_REV_SHIFT (0x00000000u) - - -/* RSTYPE */ - - -#define PLLC_RSTYPE_PLLSWRST (0x00000004u) -#define PLLC_RSTYPE_PLLSWRST_SHIFT (0x00000002u) - -#define PLLC_RSTYPE_XWRST (0x00000002u) -#define PLLC_RSTYPE_XWRST_SHIFT (0x00000001u) - -#define PLLC_RSTYPE_POR (0x00000001u) -#define PLLC_RSTYPE_POR_SHIFT (0x00000000u) - - -/* PLLCTL */ - - -#define PLLC_PLLCTL_EXTCLKSRC (0x00000200u) -#define PLLC_PLLCTL_EXTCLKSRC_SHIFT (0x00000009u) - -#define PLLC_PLLCTL_CLKMODE (0x00000100u) -#define PLLC_PLLCTL_CLKMODE_SHIFT (0x00000008u) - -#define PLLC_PLLCTL_PLLENSRC (0x00000020u) -#define PLLC_PLLCTL_PLLENSRC_SHIFT (0x00000005u) - -#define PLLC_PLLCTL_PLLDIS (0x00000010u) -#define PLLC_PLLCTL_PLLDIS_SHIFT (0x00000004u) - -#define PLLC_PLLCTL_PLLRST (0x00000008u) -#define PLLC_PLLCTL_PLLRST_SHIFT (0x00000003u) - -#define PLLC_PLLCTL_PLLPWRDN (0x00000002u) -#define PLLC_PLLCTL_PLLPWRDN_SHIFT (0x00000001u) - -#define PLLC_PLLCTL_PLLEN (0x00000001u) -#define PLLC_PLLCTL_PLLEN_SHIFT (0x00000000u) - - -/* OCSEL */ - - -#define PLLC_OCSEL_OCSRC (0x0000001Fu) -#define PLLC_OCSEL_OCSRC_SHIFT (0x00000000u) -/*----OCSRC Tokens----*/ -#define PLLC_OCSEL_OCSRC_CLKIN (0x00000014u) -#define PLLC_OCSEL_OCSRC_SYSCLK1 (0x00000017u) -#define PLLC_OCSEL_OCSRC_SYSCLK2 (0x00000018u) -#define PLLC_OCSEL_OCSRC_SYSCLK3 (0x00000019u) -#define PLLC_OCSEL_OCSRC_SYSCLK4 (0x0000001au) -#define PLLC_OCSEL_OCSRC_SYSCLK5 (0x0000001bu) -#define PLLC_OCSEL_OCSRC_SYSCLK6 (0x0000001cu) -#define PLLC_OCSEL_OCSRC_SYSCLK7 (0x0000001du) -#define PLLC_OCSEL_OCSRC_RSVD (0x0000001eu) - - -/* PLLM */ - - -#define PLLC_PLLM_PLLM (0x0000001Fu) -#define PLLC_PLLM_PLLM_SHIFT (0x00000000u) - - -/* PREDIV */ - - -#define PLLC_PREDIV_PREDEN (0x00008000u) -#define PLLC_PREDIV_PREDEN_SHIFT (0x0000000Fu) - -#define PLLC_PREDIV_RATIO (0x0000001Fu) -#define PLLC_PREDIV_RATIO_SHIFT (0x00000000u) - - -/* PLLDIV1 */ - - -#define PLLC_PLLDIV1_D1EN (0x00008000u) -#define PLLC_PLLDIV1_D1EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV1_RATIO (0x0000001Fu) -#define PLLC_PLLDIV1_RATIO_SHIFT (0x00000000u) - - -/* PLLDIV2 */ - - -#define PLLC_PLLDIV2_D2EN (0x00008000u) -#define PLLC_PLLDIV2_D2EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV2_RATIO (0x0000001Fu) -#define PLLC_PLLDIV2_RATIO_SHIFT (0x00000000u) - - -/* PLLDIV3 */ - - -#define PLLC_PLLDIV3_D3EN (0x00008000u) -#define PLLC_PLLDIV3_D3EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV3_RATIO (0x0000001Fu) -#define PLLC_PLLDIV3_RATIO_SHIFT (0x00000000u) - - -/* OSCDIV */ - - -#define PLLC_OSCDIV_OD1EN (0x00008000u) -#define PLLC_OSCDIV_OD1EN_SHIFT (0x0000000Fu) - -#define PLLC_OSCDIV_RATIO (0x0000001Fu) -#define PLLC_OSCDIV_RATIO_SHIFT (0x00000000u) - - -/* POSTDIV */ - - -#define PLLC_POSTDIV_POSTDEN (0x00008000u) -#define PLLC_POSTDIV_POSTDEN_SHIFT (0x0000000Fu) - -#define PLLC_POSTDIV_RATIO (0x0000001Fu) -#define PLLC_POSTDIV_RATIO_SHIFT (0x00000000u) - - -/* PLLCMD */ - - -#define PLLC_PLLCMD_GOSET (0x00000001u) -#define PLLC_PLLCMD_GOSET_SHIFT (0x00000000u) - -/* PLLSTAT */ - - -#define PLLC_PLLSTAT_STABLE (0x00000004u) -#define PLLC_PLLSTAT_STABLE_SHIFT (0x00000002u) - -#define PLLC_PLLSTAT_GOSTAT (0x00000001u) -#define PLLC_PLLSTAT_GOSTAT_SHIFT (0x00000000u) - - -/* ALNCTL */ - - -#define PLLC_ALNCTL_ALN7 (0x00000040u) -#define PLLC_ALNCTL_ALN7_SHIFT (0x00000006u) - -#define PLLC_ALNCTL_ALN6 (0x00000020u) -#define PLLC_ALNCTL_ALN6_SHIFT (0x00000005u) - -#define PLLC_ALNCTL_ALN5 (0x00000010u) -#define PLLC_ALNCTL_ALN5_SHIFT (0x00000004u) - -#define PLLC_ALNCTL_ALN4 (0x00000008u) -#define PLLC_ALNCTL_ALN4_SHIFT (0x00000003u) - -#define PLLC_ALNCTL_ALN3 (0x00000004u) -#define PLLC_ALNCTL_ALN3_SHIFT (0x00000002u) - -#define PLLC_ALNCTL_ALN2 (0x00000002u) -#define PLLC_ALNCTL_ALN2_SHIFT (0x00000001u) - -#define PLLC_ALNCTL_ALN1 (0x00000001u) -#define PLLC_ALNCTL_ALN1_SHIFT (0x00000000u) - -/* DCHANGE */ - - -#define PLLC_DCHANGE_SYS7 (0x00000040u) -#define PLLC_DCHANGE_SYS7_SHIFT (0x00000006u) - -#define PLLC_DCHANGE_SYS6 (0x00000020u) -#define PLLC_DCHANGE_SYS6_SHIFT (0x00000005u) - -#define PLLC_DCHANGE_SYS5 (0x00000010u) -#define PLLC_DCHANGE_SYS5_SHIFT (0x00000004u) - -#define PLLC_DCHANGE_SYS4 (0x00000008u) -#define PLLC_DCHANGE_SYS4_SHIFT (0x00000003u) - -#define PLLC_DCHANGE_SYS3 (0x00000004u) -#define PLLC_DCHANGE_SYS3_SHIFT (0x00000002u) - -#define PLLC_DCHANGE_SYS2 (0x00000002u) -#define PLLC_DCHANGE_SYS2_SHIFT (0x00000001u) - -#define PLLC_DCHANGE_SYS1 (0x00000001u) -#define PLLC_DCHANGE_SYS1_SHIFT (0x00000000u) - -/* CKEN */ - - -#define PLLC_CKEN_OBSEN (0x00000002u) -#define PLLC_CKEN_OBSEN_SHIFT (0x00000001u) - -#define PLLC_CKEN_AUXEN (0x00000001u) -#define PLLC_CKEN_AUXEN_SHIFT (0x00000000u) - - -/* CKSTAT */ - - -#define PLLC_CKSTAT_OBSON (0x00000002u) -#define PLLC_CKSTAT_OBSON_SHIFT (0x00000001u) - -#define PLLC_CKSTAT_AUXEN (0x00000001u) -#define PLLC_CKSTAT_AUXEN_SHIFT (0x00000000u) - -/* SYSTAT */ - - -#define PLLC_SYSTAT_SYS7ON (0x00000040u) -#define PLLC_SYSTAT_SYS7ON_SHIFT (0x00000006u) - -#define PLLC_SYSTAT_SYS6ON (0x00000020u) -#define PLLC_SYSTAT_SYS6ON_SHIFT (0x00000005u) - -#define PLLC_SYSTAT_SYS5ON (0x00000010u) -#define PLLC_SYSTAT_SYS5ON_SHIFT (0x00000004u) - -#define PLLC_SYSTAT_SYS4ON (0x00000008u) -#define PLLC_SYSTAT_SYS4ON_SHIFT (0x00000003u) - -#define PLLC_SYSTAT_SYS3ON (0x00000004u) -#define PLLC_SYSTAT_SYS3ON_SHIFT (0x00000002u) - -#define PLLC_SYSTAT_SYS2ON (0x00000002u) -#define PLLC_SYSTAT_SYS2ON_SHIFT (0x00000001u) - -#define PLLC_SYSTAT_SYS1ON (0x00000001u) -#define PLLC_SYSTAT_SYS1ON_SHIFT (0x00000000u) - - -/* PLLDIV4 */ - - -#define PLLC_PLLDIV4_D4EN (0x00008000u) -#define PLLC_PLLDIV4_D4EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV4_RATIO (0x0000001Fu) -#define PLLC_PLLDIV4_RATIO_SHIFT (0x00000000u) - - -/* PLLDIV5 */ - - -#define PLLC_PLLDIV5_D5EN (0x00008000u) -#define PLLC_PLLDIV5_D5EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV5_RATIO (0x0000001Fu) -#define PLLC_PLLDIV5_RATIO_SHIFT (0x00000000u) - - -/* PLLDIV6 */ - - -#define PLLC_PLLDIV6_D6EN (0x00008000u) -#define PLLC_PLLDIV6_D6EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV6_RATIO (0x0000001Fu) -#define PLLC_PLLDIV6_RATIO_SHIFT (0x00000000u) - - -/* PLLDIV7 */ - - -#define PLLC_PLLDIV7_D7EN (0x00008000u) -#define PLLC_PLLDIV7_D7EN_SHIFT (0x0000000Fu) - -#define PLLC_PLLDIV7_RATIO (0x0000001Fu) -#define PLLC_PLLDIV7_RATIO_SHIFT (0x00000000u) - - -/* EMUCNT0 */ - -#define PLLC_EMUCNT0_COUNT (0xFFFFFFFFu) -#define PLLC_EMUCNT0_COUNT_SHIFT (0x00000000u) - - -/* EMUCNT1 */ - -#define PLLC_EMUCNT1_COUNT (0xFFFFFFFFu) -#define PLLC_EMUCNT1_COUNT_SHIFT (0x00000000u) - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_pllss_C6A811x.h b/lib/tiam1808/tiam1808/hw/hw_pllss_C6A811x.h deleted file mode 100644 index b7b90dcbf..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_pllss_C6A811x.h +++ /dev/null @@ -1,812 +0,0 @@ -/** - * \file hw_pllss_C6A811x.h - * - * \brief Hardware definitions for PLLSS on C6A811x - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - - -#ifndef _HW_PLLSS_C6A811x_H_ -#define _HW_PLLSS_C6A811x_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/*************************************************************************\ - * Register Definition Macros -\*************************************************************************/ - -#define PLLSS_CONTROL_REVISION (0x0000) -#define PLLSS_CONTROL_HWINFO (0x0004) -#define PLLSS_CONTROL_SYSCONFIG (0x0010) -#define PLLSS_PLLSS_MMR_LOCK (0x0040) -#define PLLSS_MPUPLL_PWRCTRL (0x0048) -#define PLLSS_MPUPLL_CLKCTRL (0x004C) -#define PLLSS_MPUPLL_TENABLE (0x0050) -#define PLLSS_MPUPLL_TENABLEDIV (0x0054) -#define PLLSS_MPUPLL_M2NDIV (0x0058) -#define PLLSS_MPUPLL_MN2DIV (0x005C) -#define PLLSS_MPUPLL_FRACDIV (0x0060) -#define PLLSS_MPUPLL_BWCTRL (0x0064) -#define PLLSS_MPUPLL_FRACCTRL (0x0068) -#define PLLSS_MPUPLL_STATUS (0x006C) -#define PLLSS_MPUPLL_M3DIV (0x0070) -#define PLLSS_MPUPLL_RAMPCTRL (0x0074) -#define PLLSS_DSPPLL_PWRCTRL (0x0080) -#define PLLSS_DSPPLL_CLKCTRL (0x0084) -#define PLLSS_DSPPLL_TENABLE (0x0088) -#define PLLSS_DSPPLL_TENABLEDIV (0x008C) -#define PLLSS_DSPPLL_M2NDIV (0x0090) -#define PLLSS_DSPPLL_MN2DIV (0x0094) -#define PLLSS_DSPPLL_FRACDIV (0x0098) -#define PLLSS_DSPPLL_BWCTRL (0x009C) -#define PLLSS_DSPPLL_FRACCTRL (0x00A0) -#define PLLSS_DSPPLL_STATUS (0x00A4) -#define PLLSS_SGXPLL_PWRCTRL (0x00B0) -#define PLLSS_SGXPLL_CLKCTRL (0x00B4) -#define PLLSS_SGXPLL_TENABLE (0x00B8) -#define PLLSS_SGXPLL_TENABLEDIV (0x00BC) -#define PLLSS_SGXPLL_M2NDIV (0x00C0) -#define PLLSS_SGXPLL_MN2DIV (0x00C4) -#define PLLSS_SGXPLL_FRACDIV (0x00C8) -#define PLLSS_SGXPLL_BWCTRL (0x00CC) -#define PLLSS_SGXPLL_FRACCTRL (0x00D0) -#define PLLSS_SGXPLL_STATUS (0x00D4) -#define PLLSS_ISSPLL_PWRCTRL (0x0140) -#define PLLSS_ISSPLL_CLKCTRL (0x0144) -#define PLLSS_ISSPLL_TENABLE (0x0148) -#define PLLSS_ISSPLL_TENABLEDIV (0x014C) -#define PLLSS_ISSPLL_M2NDIV (0x0150) -#define PLLSS_ISSPLL_MN2DIV (0x0154) -#define PLLSS_ISSPLL_FRACDIV (0x0158) -#define PLLSS_ISSPLL_BWCTRL (0x015C) -#define PLLSS_ISSPLL_FRACCTRL (0x0160) -#define PLLSS_ISSPLL_STATUS (0x0164) -#define PLLSS_VIDEO0PLL_PWRCTRL (0x01A0) -#define PLLSS_VIDEO0PLL_CLKCTRL (0x01A4) -#define PLLSS_VIDEO0PLL_TENABLE (0x01A8) -#define PLLSS_VIDEO0PLL_TENABLEDIV (0x01AC) -#define PLLSS_VIDEO0PLL_M2NDIV (0x01B0) -#define PLLSS_VIDEO0PLL_MN2DIV (0x01B4) -#define PLLSS_VIDEO0PLL_FRACDIV (0x01B8) -#define PLLSS_VIDEO0PLL_BWCTRL (0x01BC) -#define PLLSS_VIDEO0PLL_FRACCTRL (0x01C0) -#define PLLSS_VIDEO0PLL_STATUS (0x01C4) -#define PLLSS_VIDEO1PLL_PWRCTRL (0x01D0) -#define PLLSS_VIDEO1PLL_CLKCTRL (0x01D4) -#define PLLSS_VIDEO1PLL_TENABLE (0x01D8) -#define PLLSS_VIDEO1PLL_TENABLEDIV (0x01DC) -#define PLLSS_VIDEO1PLL_M2NDIV (0x01E0) -#define PLLSS_VIDEO1PLL_MN2DIV (0x01E4) -#define PLLSS_VIDEO1PLL_FRACDIV (0x01E8) -#define PLLSS_VIDEO1PLL_BWCTRL (0x01EC) -#define PLLSS_VIDEO1PLL_FRACCTRL (0x01F0) -#define PLLSS_VIDEO1PLL_STATUS (0x01F4) -#define PLLSS_HDMIPLL_PWRCTRL (0x0200) -#define PLLSS_HDMIPLL_CLKCTRL (0x0204) -#define PLLSS_HDMIPLL_TENABLE (0x0208) -#define PLLSS_HDMIPLL_TENABLEDIV (0x020C) -#define PLLSS_HDMIPLL_M2NDIV (0x0210) -#define PLLSS_HDMIPLL_MN2DIV (0x0214) -#define PLLSS_HDMIPLL_FRACDIV (0x0218) -#define PLLSS_HDMIPLL_BWCTRL (0x021C) -#define PLLSS_HDMIPLL_FRACCTRL (0x0220) -#define PLLSS_HDMIPLL_STATUS (0x0224) -#define PLLSS_AUDIOPLL_PWRCTRL (0x0230) -#define PLLSS_AUDIOPLL_CLKCTRL (0x0234) -#define PLLSS_AUDIOPLL_TENABLE (0x0238) -#define PLLSS_AUDIOPLL_TENABLEDIV (0x023C) -#define PLLSS_AUDIOPLL_M2NDIV (0x0240) -#define PLLSS_AUDIOPLL_MN2DIV (0x0244) -#define PLLSS_AUDIOPLL_FRACDIV (0x0248) -#define PLLSS_AUDIOPLL_BWCTRL (0x024C) -#define PLLSS_AUDIOPLL_FRACCTRL (0x0250) -#define PLLSS_AUDIOPLL_STATUS (0x0254) -#define PLLSS_USBPLL_PWRCTRL (0x0260) -#define PLLSS_USBPLL_CLKCTRL (0x0264) -#define PLLSS_USBPLL_TENABLE (0x0268) -#define PLLSS_USBPLL_TENABLEDIV (0x026C) -#define PLLSS_USBPLL_M2NDIV (0x0270) -#define PLLSS_USBPLL_MN2DIV (0x0274) -#define PLLSS_USBPLL_FRACDIV (0x0278) -#define PLLSS_USBPLL_BWCTRL (0x027C) -#define PLLSS_USBPLL_FRACCTRL (0x0280) -#define PLLSS_USBPLL_STATUS (0x0284) -#define PLLSS_DDRPLL_PWRCTRL (0x0290) -#define PLLSS_DDRPLL_CLKCTRL (0x0294) -#define PLLSS_DDRPLL_TENABLE (0x0298) -#define PLLSS_DDRPLL_TENABLEDIV (0x029C) -#define PLLSS_DDRPLL_M2NDIV (0x02A0) -#define PLLSS_DDRPLL_MN2DIV (0x02A4) -#define PLLSS_DDRPLL_FRACDIV (0x02A8) -#define PLLSS_DDRPLL_BWCTRL (0x02AC) -#define PLLSS_DDRPLL_FRACCTRL (0x02B0) -#define PLLSS_DDRPLL_STATUS (0x02B4) -#define PLLSS_OSC_SRC (0x02C0) -#define PLLSS_ARM_CLKSRC (0x02C4) -#define PLLSS_VIDEO_PLL_CLKSRC (0x02C8) -#define PLLSS_MLB_ATL_CLKSRC (0x02CC) -#define PLLSS_McASP345_AUX_CLKSRC (0x02D0) -#define PLLSS_McASP_AHCLK_CLKSRC (0x02D4) -#define PLLSS_McBSP_UART_CLKSRC (0x02D8) -#define PLLSS_DMTIMER_CLKSRC (0x02E0) -#define PLLSS_CLKOUT_MUX (0x02E4) -#define PLLSS_RMII_REFCLK_SRC (0x02E8) -#define PLLSS_SECSS_CLK_SRC (0x02EC) -#define PLLSS_SYSCLK_18_SRC (0x02F0) -#define PLLSS_WDT0_SRC (0x02F4) -#define PLLSS_DSS_CLKSRC (0x02FC) -#define PLLSS_TIMER_CLK_CHANGE (0x0320) -#define PLLSS_DEEPSLEEP_CTRL (0x0324) -#define PLLSS_DEEPSLEEP_STATUS (0x0328) - -/**************************************************************************\ -* Field Definition Macros -\**************************************************************************/ - -/** @brief PLLSS_CONTROL_REVISION register fields */ - -#define PLLSS_CONTROL_REVISION_IP_REV_SCHEME (0xC0000000u) -#define PLLSS_CONTROL_REVISION_IP_REV_SCHEME_SHIFT (0x1Eu) - -#define PLLSS_CONTROL_REVISION_IP_REV_FUNC (0x0FFF0000u) -#define PLLSS_CONTROL_REVISION_IP_REV_FUNC_SHIFT (0x10u) - -#define PLLSS_CONTROL_REVISION_IP_REV_RTL (0x0000F800u) -#define PLLSS_CONTROL_REVISION_IP_REV_RTL_SHIFT (0xBu) - -#define PLLSS_CONTROL_REVISION_IP_REV_MAJOR (0x00000700u) -#define PLLSS_CONTROL_REVISION_IP_REV_MAJOR_SHIFT (0x8u) - -#define PLLSS_CONTROL_REVISION_IP_REV_CUSTOM (0x000000C0u) -#define PLLSS_CONTROL_REVISION_IP_REV_CUSTOM_SHIFT (0x6u) - -#define PLLSS_CONTROL_REVISION_IP_REV_MINOR (0x0000003Fu) -#define PLLSS_CONTROL_REVISION_IP_REV_MINOR_SHIFT (0x0u) - -/** @brief PLLSS_CONTROL_HWINFO register fields */ - -#define PLLSS_CONTROL_HWINFO_IP_HWINFO (0x7FFFFFFFu) -#define PLLSS_CONTROL_HWINFO_IP_HWINFO_SHIFT (0x0u) - -/** @brief PLLSS_CONTROL_SYSCONFIG register fields */ - -#define PLLSS_CONTROL_SYSCONFIG_STANDBY (0x00000030u) -#define PLLSS_CONTROL_SYSCONFIG_STANDBY_SHIFT (0x4u) - -#define PLLSS_CONTROL_SYSCONFIG_IDLEMODE (0x0000000Cu) -#define PLLSS_CONTROL_SYSCONFIG_IDLEMODE_SHIFT (0x2u) - -#define PLLSS_CONTROL_SYSCONFIG_FREEEMU (0x00000002u) -#define PLLSS_CONTROL_SYSCONFIG_FREEEMU_SHIFT (0x1u) - -/** @brief PLLSS_MMR_LOCK register fields */ - -#define PLLSS_MMR_LOCK_LOCK (0x1F125B64u) -#define PLLSS_MMR_LOCK_UNLOCK (0x1EDA4C3Du) - -/** @brief PLLSS_MPUPLL_PWRCTRL register fields */ - -#define PLLSS_MPUPLL_PWRCTRL_OFFMODE (0x00000001u) -#define PLLSS_MPUPLL_PWRCTRL_OFFMODE_SHIFT (0x0u) - -/** @brief PLLSS_MPUPLL_CLKCTRL register fields */ - -#define PLLSS_MPUPLL_CLKCTRL_CYCLESLIPEN (0x80000000u) -#define PLLSS_MPUPLL_CLKCTRL_CYCLESLIPEN_SHIFT (0x1Fu) - -#define PLLSS_MPUPLL_CLKCTRL_ENSSC (0x40000000u) -#define PLLSS_MPUPLL_CLKCTRL_ENSSC_SHIFT (0x1Eu) - -#define PLLSS_MPUPLL_CLKCTRL_NWELLTRIM (0x1F000000u) -#define PLLSS_MPUPLL_CLKCTRL_NWELLTRIM_SHIFT (0x18u) - -#define PLLSS_MPUPLL_CLKCTRL_IDLE (0x00800000u) -#define PLLSS_MPUPLL_CLKCTRL_IDLE_SHIFT (0x17u) - -#define PLLSS_MPUPLL_CLKCTRL_STBYRET (0x00200000u) -#define PLLSS_MPUPLL_CLKCTRL_STBYRET_SHIFT (0x15u) - -#define PLLSS_MPUPLL_CLKCTRL_CLKOUTEN (0x00100000u) -#define PLLSS_MPUPLL_CLKCTRL_CLKOUTEN_SHIFT (0x14u) - -#define PLLSS_MPUPLL_CLKCTRL_ULOWCLKEN (0x00040000u) -#define PLLSS_MPUPLL_CLKCTRL_ULOWCLKEN_SHIFT (0x12u) - -#define PLLSS_MPUPLL_CLKCTRL_CLKDCOLDOPWDNZ (0x00020000u) -#define PLLSS_MPUPLL_CLKCTRL_CLKDCOLDOPWDNZ_SHIFT (0x11u) - -#define PLLSS_MPUPLL_CLKCTRL_M2PWDNZ (0x00010000u) -#define PLLSS_MPUPLL_CLKCTRL_M2PWDNZ_SHIFT (0x10u) - -#define PLLSS_MPUPLL_CLKCTRL_M3PWDNZ (0x00008000u) -#define PLLSS_MPUPLL_CLKCTRL_M3PWDNZ_SHIFT (0xFu) - -#define PLLSS_MPUPLL_CLKCTRL_STOPMODE (0x00004000u) -#define PLLSS_MPUPLL_CLKCTRL_STOPMODE_SHIFT (0xEu) - -#define PLLSS_MPUPLL_CLKCTRL_LOWCURRSTDBY (0x00002000u) -#define PLLSS_MPUPLL_CLKCTRL_LOWCURRSTDBY_SHIFT (0xDu) - -#define PLLSS_MPUPLL_CLKCTRL_LPMODE (0x00001000u) -#define PLLSS_MPUPLL_CLKCTRL_LPMODE_SHIFT (0xCu) - -#define PLLSS_MPUPLL_CLKCTRL_DRIFTGUARDEN (0x00000800u) -#define PLLSS_MPUPLL_CLKCTRL_DRIFTGUARDEN_SHIFT (0xBu) - -#define PLLSS_MPUPLL_CLKCTRL_REGM4XEN (0x00000400u) -#define PLLSS_MPUPLL_CLKCTRL_REGM4XEN_SHIFT (0xAu) - -#define PLLSS_MPUPLL_CLKCTRL_RELAXED_LOCK (0x00000100u) -#define PLLSS_MPUPLL_CLKCTRL_RELAXED_LOCK_SHIFT (0x8u) - -#define PLLSS_MPUPLL_CLKCTRL_TINITZ (0x00000001u) -#define PLLSS_MPUPLL_CLKCTRL_TINITZ_SHIFT (0x0u) - -/** @brief PLLSS_MPUPLL_TENABLE register fields */ - -#define PLLSS_MPUPLL_TENABLE_TENABLE (0x00000001u) -#define PLLSS_MPUPLL_TENABLE_TENABLE_SHIFT (0x0u) - -/** @brief PLLSS_MPUPLL_TENABLEDIV register fields */ - -#define PLLSS_MPUPLL_TENABLEDIV_TENABLEDIV (0x00000001u) -#define PLLSS_MPUPLL_TENABLEDIV_TENABLEDIV_SHIFT (0x0u) - -/** @brief PLLSS_MPUPLL_M2NDIV register fields */ - -#define PLLSS_MPUPLL_M2NDIV_M2 (0x001F0000u) -#define PLLSS_MPUPLL_M2NDIV_M2_SHIFT (0x10u) - -#define PLLSS_MPUPLL_M2NDIV_N (0x0000007Fu) -#define PLLSS_MPUPLL_M2NDIV_N_SHIFT (0x0u) - -/** @brief PLLSS_MPUPLL_MN2DIV register fields */ - -#define PLLSS_MPUPLL_MN2DIV_N2 (0x000F0000u) -#define PLLSS_MPUPLL_MN2DIV_N2_SHIFT (0x10u) - -#define PLLSS_MPUPLL_MN2DIV_M (0x00000FFFu) -#define PLLSS_MPUPLL_MN2DIV_M_SHIFT (0x0u) - -/** @brief PLLSS_MPUPLL_FRACDIV register fields */ - -#define PLLSS_MPUPLL_FRACDIV_FRACTIONALM (0x0003FFFFu) -#define PLLSS_MPUPLL_FRACDIV_FRACTIONALM_SHIFT (0x0u) - -/** @brief PLLSS_MPUPLL_BWCTRL register fields */ - -#define PLLSS_MPUPLL_BWCTRL_BWCONTROL (0x00000006u) -#define PLLSS_MPUPLL_BWCTRL_BWCONTROL_SHIFT (0x1u) - -/** @brief PLLSS_MPUPLL_FRACCTRL register fields */ - -#define PLLSS_MPUPLL_FRACCTRL_DOWNSPREAD (0x80000000u) -#define PLLSS_MPUPLL_FRACCTRL_DOWNSPREAD_SHIFT (0x1Fu) - -#define PLLSS_MPUPLL_FRACCTRL_ModFreqDividerExponent (0x70000000u) -#define PLLSS_MPUPLL_FRACCTRL_ModFreqDividerExponent_SHIFT (0x1Cu) - -#define PLLSS_MPUPLL_FRACCTRL_ModFreqDividerMantissa (0x0FE00000u) -#define PLLSS_MPUPLL_FRACCTRL_ModFreqDividerMantissa_SHIFT (0x15u) - -#define PLLSS_MPUPLL_FRACCTRL_DeltaMStepInteger (0x000C0000u) -#define PLLSS_MPUPLL_FRACCTRL_DeltaMStepInteger_SHIFT (0x12u) - -#define PLLSS_MPUPLL_FRACCTRL_DeltaMStepFraction (0x0003FFFFu) -#define PLLSS_MPUPLL_FRACCTRL_DeltaMStepFraction_SHIFT (0x0u) - -/** @brief PLLSS_MPUPLL_STATUS register fields */ - -#define PLLSS_MPUPLL_STATUS_SSACK (0x40000000u) -#define PLLSS_MPUPLL_STATUS_SSACK_SHIFT (0x1Eu) - -#define PLLSS_MPUPLL_STATUS_LDOPWDN (0x20000000u) -#define PLLSS_MPUPLL_STATUS_LDOPWDN_SHIFT (0x1Du) - -#define PLLSS_MPUPLL_STATUS_RECAL_BSTATUS3 (0x10000000u) -#define PLLSS_MPUPLL_STATUS_RECAL_BSTATUS3_SHIFT (0x1Cu) - -#define PLLSS_MPUPLL_STATUS_RECAL_OPPIN (0x08000000u) -#define PLLSS_MPUPLL_STATUS_RECAL_OPPIN_SHIFT (0x1Bu) - -#define PLLSS_MPUPLL_STATUS_PHASELOCK (0x00000400u) -#define PLLSS_MPUPLL_STATUS_PHASELOCK_SHIFT (0xAu) - -#define PLLSS_MPUPLL_STATUS_FREQLOCK (0x00000200u) -#define PLLSS_MPUPLL_STATUS_FREQLOCK_SHIFT (0x9u) - -#define PLLSS_MPUPLL_STATUS_BYPASSACK (0x00000100u) -#define PLLSS_MPUPLL_STATUS_BYPASSACK_SHIFT (0x8u) - -#define PLLSS_MPUPLL_STATUS_STBYRETACK (0x00000080u) -#define PLLSS_MPUPLL_STATUS_STBYRETACK_SHIFT (0x7u) - -#define PLLSS_MPUPLL_STATUS_LOSSREF (0x00000040u) -#define PLLSS_MPUPLL_STATUS_LOSSREF_SHIFT (0x6u) - -#define PLLSS_MPUPLL_STATUS_CLKOUTENACK (0x00000020u) -#define PLLSS_MPUPLL_STATUS_CLKOUTENACK_SHIFT (0x5u) - -#define PLLSS_MPUPLL_STATUS_LOCK2 (0x00000010u) -#define PLLSS_MPUPLL_STATUS_LOCK2_SHIFT (0x4u) - -#define PLLSS_MPUPLL_STATUS_M2CHANGEACK (0x00000008u) -#define PLLSS_MPUPLL_STATUS_M2CHANGEACK_SHIFT (0x3u) - -#define PLLSS_MPUPLL_STATUS_LIMP (0x00000004u) -#define PLLSS_MPUPLL_STATUS_LIMP_SHIFT (0x2u) - -#define PLLSS_MPUPLL_STATUS_HIGHJITTER (0x00000002u) -#define PLLSS_MPUPLL_STATUS_HIGHJITTER_SHIFT (0x1u) - -#define PLLSS_MPUPLL_STATUS_BYPASS (0x00000001u) -#define PLLSS_MPUPLL_STATUS_BYPASS_SHIFT (0x0u) - -/** @brief PLLSS_MPUPLL_M3DIV register fields */ - -#define PLLSS_MPUPLL_M3DIV_M3 (0x0000001Fu) -#define PLLSS_MPUPLL_M3DIV_M3_SHIFT (0x0u) - -/** @brief PLLSS_MPUPLL_RAMPCTRL register fields */ - -#define PLLSS_MPUPLL_RAMPCTRL_CLKRAMPLEVEL (0x00180000u) -#define PLLSS_MPUPLL_RAMPCTRL_CLKRAMPLEVEL_SHIFT (0x13u) - -#define PLLSS_MPUPLL_RAMPCTRL_CLKRAMPRATE (0x00070000u) -#define PLLSS_MPUPLL_RAMPCTRL_CLKRAMPRATE_SHIFT (0x10u) - -#define PLLSS_MPUPLL_RAMPCTRL_RELOCK_RAMP_EN (0x00000001u) -#define PLLSS_MPUPLL_RAMPCTRL_RELOCK_RAMP_EN_SHIFT (0x0u) - -/** @brief PLLSS_PLL_PWRCTRL register fields */ - -#define PLLSS_PLL_PWRCTRL_PONIN (0x00000020u) -#define PLLSS_PLL_PWRCTRL_PONIN_SHIFT (0x5u) - -#define PLLSS_PLL_PWRCTRL_PGOODIN (0x00000010u) -#define PLLSS_PLL_PWRCTRL_PGOODIN_SHIFT (0x4u) - -#define PLLSS_PLL_PWRCTRL_RET (0x00000008u) -#define PLLSS_PLL_PWRCTRL_RET_SHIFT (0x3u) - -#define PLLSS_PLL_PWRCTRL_ISORET (0x00000004u) -#define PLLSS_PLL_PWRCTRL_ISORET_SHIFT (0x2u) - -#define PLLSS_PLL_PWRCTRL_ISOSCAN (0x00000002u) -#define PLLSS_PLL_PWRCTRL_ISOSCAN_SHIFT (0x1u) - -#define PLLSS_PLL_PWRCTRL_OFFMODE (0x00000001u) -#define PLLSS_PLL_PWRCTRL_OFFMODE_SHIFT (0x0u) - -/** @brief PLLSS_PLL_CLKCTRL register fields */ - -#define PLLSS_PLL_CLKCTRL_CYCLESLIPEN (0x80000000u) -#define PLLSS_PLL_CLKCTRL_CYCLESLIPEN_SHIFT (0x1Fu) - -#define PLLSS_PLL_CLKCTRL_ENSSC (0x40000000u) -#define PLLSS_PLL_CLKCTRL_ENSSC_SHIFT (0x1Eu) - -#define PLLSS_PLL_CLKCTRL_NWELLTRIM (0x1F000000u) -#define PLLSS_PLL_CLKCTRL_NWELLTRIM_SHIFT (0x18u) - -#define PLLSS_PLL_CLKCTRL_IDLE (0x00800000u) -#define PLLSS_PLL_CLKCTRL_IDLE_SHIFT (0x17u) - -#define PLLSS_PLL_CLKCTRL_BYPASSACKZ (0x00400000u) -#define PLLSS_PLL_CLKCTRL_BYPASSACKZ_SHIFT (0x16u) - -#define PLLSS_PLL_CLKCTRL_STBYRET (0x00200000u) -#define PLLSS_PLL_CLKCTRL_STBYRET_SHIFT (0x15u) - -#define PLLSS_PLL_CLKCTRL_CLKOUTEN (0x00100000u) -#define PLLSS_PLL_CLKCTRL_CLKOUTEN_SHIFT (0x14u) - -#define PLLSS_PLL_CLKCTRL_ULOWCLKEN (0x00040000u) -#define PLLSS_PLL_CLKCTRL_ULOWCLKEN_SHIFT (0x12u) - -#define PLLSS_PLL_CLKCTRL_CLKDCOLDOPWDNZ (0x00020000u) -#define PLLSS_PLL_CLKCTRL_CLKDCOLDOPWDNZ_SHIFT (0x11u) - -#define PLLSS_PLL_CLKCTRL_M2PWDNZ (0x00010000u) -#define PLLSS_PLL_CLKCTRL_M2PWDNZ_SHIFT (0x10u) - -#define PLLSS_PLL_CLKCTRL_SELFREQDCO (0x00001C00u) -#define PLLSS_PLL_CLKCTRL_SELFREQDCO_SHIFT (0xAu) - -#define PLLSS_PLL_CLKCTRL_RELAXED_LOCK (0x00000100u) -#define PLLSS_PLL_CLKCTRL_RELAXED_LOCK_SHIFT (0x8u) - -#define PLLSS_PLL_CLKCTRL_TINITZ (0x00000001u) -#define PLLSS_PLL_CLKCTRL_TINITZ_SHIFT (0x0u) - -/** @brief PLLSS_PLL_TENABLE register fields */ - -#define PLLSS_PLL_TENABLE_TENABLE (0x00000001u) -#define PLLSS_PLL_TENABLE_TENABLE_SHIFT (0x0u) - -/** @brief PLLSS_PLL_TENABLEDIV register fields */ - -#define PLLSS_PLL_TENABLEDIV_TENABLEDIV (0x00000001u) -#define PLLSS_PLL_TENABLEDIV_TENABLEDIV_SHIFT (0x0u) - -/** @brief PLLSS_PLL_M2NDIV register fields */ - -#define PLLSS_PLL_M2NDIV_M2 (0x007F0000u) -#define PLLSS_PLL_M2NDIV_M2_SHIFT (0x10u) - -#define PLLSS_PLL_M2NDIV_N (0x000000FFu) -#define PLLSS_PLL_M2NDIV_N_SHIFT (0x0u) - -/** @brief PLLSS_PLL_MN2DIV register fields */ - -#define PLLSS_PLL_MN2DIV_N2 (0x000F0000u) -#define PLLSS_PLL_MN2DIV_N2_SHIFT (0x10u) - -#define PLLSS_PLL_MN2DIV_M (0x00000FFFu) -#define PLLSS_PLL_MN2DIV_M_SHIFT (0x0u) - -/** @brief PLLSS_PLL_FRACDIV register fields */ - -#define PLLSS_PLL_FRACDIV_REGSD (0xFF000000u) -#define PLLSS_PLL_FRACDIV_REGSD_SHIFT (0x18u) - -#define PLLSS_PLL_FRACDIV_FRACTIONALM (0x0003FFFFu) -#define PLLSS_PLL_FRACDIV_FRACTIONALM_SHIFT (0x0u) - -/** @brief PLLSS_PLL_BWCTRL register fields */ - -#define PLLSS_PLL_BWCTRL_BWCONTROL (0x00000006u) -#define PLLSS_PLL_BWCTRL_BWCONTROL_SHIFT (0x1u) - -#define PLLSS_PLL_BWCTRL_BW_INCR_DECRZ (0x00000001u) -#define PLLSS_PLL_BWCTRL_BW_INCR_DECRZ_SHIFT (0x0u) - -/** @brief PLLSS_PLL_FRACCTRL register fields */ - -#define PLLSS_PLL_FRACCTRL_DOWNSPREAD (0x80000000u) -#define PLLSS_PLL_FRACCTRL_DOWNSPREAD_SHIFT (0x1Fu) - -#define PLLSS_PLL_FRACCTRL_MFDEXP (0x70000000u) -#define PLLSS_PLL_FRACCTRL_MFDEXP_SHIFT (0x1Cu) - -#define PLLSS_PLL_FRACCTRL_MFDMAN (0x0FE00000u) -#define PLLSS_PLL_FRACCTRL_MFDMAN_SHIFT (0x15u) - -#define PLLSS_PLL_FRACCTRL_DMSINT (0x001C0000u) -#define PLLSS_PLL_FRACCTRL_DMSINT_SHIFT (0x12u) - -#define PLLSS_PLL_FRACCTRL_DMSFRAC (0x0003FFFFu) -#define PLLSS_PLL_FRACCTRL_DMSFRAC_SHIFT (0x0u) - -/** @brief PLLSS_PLL_STATUS register fields */ - -#define PLLSS_PLL_STATUS_PONOUT (0x80000000u) -#define PLLSS_PLL_STATUS_PONOUT_SHIFT (0x1Fu) - -#define PLLSS_PLL_STATUS_PGOODOUT (0x40000000u) -#define PLLSS_PLL_STATUS_PGOODOUT_SHIFT (0x1Eu) - -#define PLLSS_PLL_STATUS_LDOPWDN (0x20000000u) -#define PLLSS_PLL_STATUS_LDOPWDN_SHIFT (0x1Du) - -#define PLLSS_PLL_STATUS_RECALBSTATUS3 (0x10000000u) -#define PLLSS_PLL_STATUS_RECALBSTATUS3_SHIFT (0x1Cu) - -#define PLLSS_PLL_STATUS_RECALOPPIN (0x08000000u) -#define PLLSS_PLL_STATUS_RECALOPPIN_SHIFT (0x1Bu) - -#define PLLSS_PLL_STATUS_PHASELOCK (0x00000400u) -#define PLLSS_PLL_STATUS_PHASELOCK_SHIFT (0xAu) - -#define PLLSS_PLL_STATUS_FREQLOCK (0x00000200u) -#define PLLSS_PLL_STATUS_FREQLOCK_SHIFT (0x9u) - -#define PLLSS_PLL_STATUS_BYPASSACK (0x00000100u) -#define PLLSS_PLL_STATUS_BYPASSACK_SHIFT (0x8u) - -#define PLLSS_PLL_STATUS_STBYRETACK (0x00000080u) -#define PLLSS_PLL_STATUS_STBYRETACK_SHIFT (0x7u) - -#define PLLSS_PLL_STATUS_LOSSREF (0x00000040u) -#define PLLSS_PLL_STATUS_LOSSREF_SHIFT (0x6u) - -#define PLLSS_PLL_STATUS_CLKOUTACK (0x00000020u) -#define PLLSS_PLL_STATUS_CLKOUTACK_SHIFT (0x5u) - -#define PLLSS_PLL_STATUS_LOCK2 (0x00000010u) -#define PLLSS_PLL_STATUS_LOCK2_SHIFT (0x4u) - -#define PLLSS_PLL_STATUS_M2CHANGEACK (0x00000008u) -#define PLLSS_PLL_STATUS_M2CHANGEACK_SHIFT (0x3u) - -#define PLLSS_PLL_STATUS_SSCACK (0x00000004u) -#define PLLSS_PLL_STATUS_SSCACK_SHIFT (0x2u) - -#define PLLSS_PLL_STATUS_HIGHJITTER (0x00000002u) -#define PLLSS_PLL_STATUS_HIGHJITTER_SHIFT (0x1u) - -#define PLLSS_PLL_STATUS_BYPASS (0x00000001u) -#define PLLSS_PLL_STATUS_BYPASS_SHIFT (0x0u) - -/** @brief PLLSS_OSC_SRC register fields */ - -#define PLLSS_OSC_SRC_GEM_PLL_SOURCE (0x80000000u) -#define PLLSS_OSC_SRC_GEM_PLL_SOURCE_SHIFT (0x1Fu) - -#define PLLSS_OSC_SRC_SGX_PLL_SOURCE (0x40000000u) -#define PLLSS_OSC_SRC_SGX_PLL_SOURCE_SHIFT (0x1Eu) - -#define PLLSS_OSC_SRC_ISS_PLL_SOURCE (0x10000000u) -#define PLLSS_OSC_SRC_ISS_PLL_SOURCE_SHIFT (0x1Cu) - -#define PLLSS_OSC_SRC_USB_PLL_SOURCE (0x04000000u) -#define PLLSS_OSC_SRC_USB_PLL_SOURCE_SHIFT (0x1Au) - -#define PLLSS_OSC_SRC_DDR_PLL_SOURCE (0x02000000u) -#define PLLSS_OSC_SRC_DDR_PLL_SOURCE_SHIFT (0x19u) - -#define PLLSS_OSC_SRC_AUDIO_PLL_SOURCE (0x01000000u) -#define PLLSS_OSC_SRC_AUDIO_PLL_SOURCE_SHIFT (0x18u) - -#define PLLSS_OSC_SRC_HDMI_PLL_SOURCE (0x00040000u) -#define PLLSS_OSC_SRC_HDMI_PLL_SOURCE_SHIFT (0x12u) - -#define PLLSS_OSC_SRC_VIDEO1_PLL_SOURCE (0x00020000u) -#define PLLSS_OSC_SRC_VIDEO1_PLL_SOURCE_SHIFT (0x11u) - -#define PLLSS_OSC_SRC_VIDEO0_PLL_SOURCE (0x00010000u) -#define PLLSS_OSC_SRC_VIDEO0_PLL_SOURCE_SHIFT (0x10u) - -/** @brief PLLSS_ARM_CLKSRC register fields */ - -#define PLLSS_ARM_CLKSRC_ARM_SOURCE (0x00000001u) -#define PLLSS_ARM_CLKSRC_ARM_SOURCE_SHIFT (0x0u) - -/** @brief PLLSS_VIDEO_PLL_CLKSRC register fields */ - -#define PLLSS_VIDEO_PLL_CLKSRC_HD_VENC_G_CLK_SOURCE (0x01000000u) -#define PLLSS_VIDEO_PLL_CLKSRC_HD_VENC_G_CLK_SOURCE_SHIFT (0x18u) - -#define PLLSS_VIDEO_PLL_CLKSRC_TPPSSSTSO_MUX_SOURCE (0x000C0000u) -#define PLLSS_VIDEO_PLL_CLKSRC_TPPSSSTSO_MUX_SOURCE_SHIFT (0x12u) - -#define PLLSS_VIDEO_PLL_CLKSRC_VIDEO_PLL_OUT_MUX_SOURCE (0x00000300u) -#define PLLSS_VIDEO_PLL_CLKSRC_VIDEO_PLL_OUT_MUX_SOURCE_SHIFT (0x8u) - -/** @brief PLLSS_MLB_ATL_CLKSRC register fields */ - -#define PLLSS_MLB_ATL_CLKSRC_ATL_SOURCE (0x00030000u) -#define PLLSS_MLB_ATL_CLKSRC_ATL_SOURCE_SHIFT (0x10u) - -#define PLLSS_MLB_ATL_CLKSRC_MLB_SOURCE (0x00000001u) -#define PLLSS_MLB_ATL_CLKSRC_MLB_SOURCE_SHIFT (0x0u) - -/** @brief PLLSS_McASP345_AUX_CLKSRC register fields */ - -#define PLLSS_McASP345_AUX_CLKSRC_McASP5_AUX_SOURCE (0x00070000u) -#define PLLSS_McASP345_AUX_CLKSRC_McASP5_AUX_SOURCE_SHIFT (0x10u) - -#define PLLSS_McASP345_AUX_CLKSRC_McASP4_AUX_SOURCE (0x00000700u) -#define PLLSS_McASP345_AUX_CLKSRC_McASP4_AUX_SOURCE_SHIFT (0x8u) - -#define PLLSS_McASP345_AUX_CLKSRC_McASP3_AUX_SOURCE (0x00000007u) -#define PLLSS_McASP345_AUX_CLKSRC_McASP3_AUX_SOURCE_SHIFT (0x0u) - -/** @brief PLLSS_McASP_AHCLK_CLKSRC register fields */ - -#define PLLSS_McASP_AHCLK_CLKSRC_McASP5_AHCLKX_SOURCE (0x0E000000u) -#define PLLSS_McASP_AHCLK_CLKSRC_McASP5_AHCLKX_SOURCE_SHIFT (0x19u) - -#define PLLSS_McASP_AHCLK_CLKSRC_McASP4_AHCLKX_SOURCE (0x01C00000u) -#define PLLSS_McASP_AHCLK_CLKSRC_McASP4_AHCLKX_SOURCE_SHIFT (0x16u) - -#define PLLSS_McASP_AHCLK_CLKSRC_McASP3_AHCLKX_SOURCE (0x00380000u) -#define PLLSS_McASP_AHCLK_CLKSRC_McASP3_AHCLKX_SOURCE_SHIFT (0x13u) - -#define PLLSS_McASP_AHCLK_CLKSRC_McASP2_AHCLKX_SOURCE (0x00070000u) -#define PLLSS_McASP_AHCLK_CLKSRC_McASP2_AHCLKX_SOURCE_SHIFT (0x10u) - -#define PLLSS_McASP_AHCLK_CLKSRC_McASP1_AHCLKR_SOURCE (0x00000E00u) -#define PLLSS_McASP_AHCLK_CLKSRC_McASP1_AHCLKR_SOURCE_SHIFT (0x9u) - -#define PLLSS_McASP_AHCLK_CLKSRC_McASP1_AHCLKX_SOURCE (0x000001C0u) -#define PLLSS_McASP_AHCLK_CLKSRC_McASP1_AHCLKX_SOURCE_SHIFT (0x6u) - -#define PLLSS_McASP_AHCLK_CLKSRC_McASP0_AHCLKR_SOURCE (0x00000038u) -#define PLLSS_McASP_AHCLK_CLKSRC_McASP0_AHCLKR_SOURCE_SHIFT (0x3u) - -#define PLLSS_McASP_AHCLK_CLKSRC_McASP0_AHCLKX_SOURCE (0x00000007u) -#define PLLSS_McASP_AHCLK_CLKSRC_McASP0_AHCLKX_SOURCE_SHIFT (0x0u) - -/** @brief PLLSS_McBSP_UART_CLKSRC register fields */ - -#define PLLSS_McBSP_UART_CLKSRC_UART5_CLK_SOURCE (0x00000180u) -#define PLLSS_McBSP_UART_CLKSRC_UART5_CLK_SOURCE_SHIFT (0x7u) - -#define PLLSS_McBSP_UART_CLKSRC_UART4_CLK_SOURCE (0x00000060u) -#define PLLSS_McBSP_UART_CLKSRC_UART4_CLK_SOURCE_SHIFT (0x5u) - -#define PLLSS_McBSP_UART_CLKSRC_UART3_CLK_SOURCE (0x00000018u) -#define PLLSS_McBSP_UART_CLKSRC_UART3_CLK_SOURCE_SHIFT (0x3u) - -#define PLLSS_McBSP_UART_CLKSRC_McBSP_CLKS_SOURCE (0x00000007u) -#define PLLSS_McBSP_UART_CLKSRC_McBSP_CLKS_SOURCE_SHIFT (0x0u) - -/** @brief PLLSS_DMTIMER_CLKSRC register fields */ - -#define PLLSS_DMTIMER_CLKSRC_DMTIMER7_SOURCE (0xF0000000u) -#define PLLSS_DMTIMER_CLKSRC_DMTIMER7_SOURCE_SHIFT (0x1Cu) - -#define PLLSS_DMTIMER_CLKSRC_DMTIMER6_SOURCE (0x0F000000u) -#define PLLSS_DMTIMER_CLKSRC_DMTIMER6_SOURCE_SHIFT (0x18u) - -#define PLLSS_DMTIMER_CLKSRC_DMTIMER5_SOURCE (0x00F00000u) -#define PLLSS_DMTIMER_CLKSRC_DMTIMER5_SOURCE_SHIFT (0x14u) - -#define PLLSS_DMTIMER_CLKSRC_DMTIMER4_SOURCE (0x000F0000u) -#define PLLSS_DMTIMER_CLKSRC_DMTIMER4_SOURCE_SHIFT (0x10u) - -#define PLLSS_DMTIMER_CLKSRC_DMTIMER3_SOURCE (0x0000F000u) -#define PLLSS_DMTIMER_CLKSRC_DMTIMER3_SOURCE_SHIFT (0xCu) - -#define PLLSS_DMTIMER_CLKSRC_DMTIMER2_SOURCE (0x00000F00u) -#define PLLSS_DMTIMER_CLKSRC_DMTIMER2_SOURCE_SHIFT (0x8u) - -#define PLLSS_DMTIMER_CLKSRC_DMTIMER1_SOURCE (0x000000F0u) -#define PLLSS_DMTIMER_CLKSRC_DMTIMER1_SOURCE_SHIFT (0x4u) - -#define PLLSS_DMTIMER_CLKSRC_DMTIMER8_SOURCE (0x0000000Fu) -#define PLLSS_DMTIMER_CLKSRC_DMTIMER8_SOURCE_SHIFT (0x0u) - -/** @brief PLLSS_CLKOUT_MUX register fields */ - -#define PLLSS_CLKOUT_MUX_CLKOUT1_MUX (0x000F0000u) -#define PLLSS_CLKOUT_MUX_CLKOUT1_MUX_SHIFT (0x10u) - -#define PLLSS_CLKOUT_MUX_CLKOUT0_MUX (0x0000000Fu) -#define PLLSS_CLKOUT_MUX_CLKOUT0_MUX_SHIFT (0x0u) - -/** @brief PLLSS_RMII_REFCLK_SRC register fields */ - -#define PLLSS_RMII_REFCLK_SRC_GMAC_50_CLK_MUX_SEL (0x00020000u) -#define PLLSS_RMII_REFCLK_SRC_GMAC_50_CLK_MUX_SEL_SHIFT (0x11u) - -#define PLLSS_RMII_REFCLK_SRC_GMAC_125_CLK_MUX_SEL (0x00010000u) -#define PLLSS_RMII_REFCLK_SRC_GMAC_125_CLK_MUX_SEL_SHIFT (0x10u) - -#define PLLSS_RMII_REFCLK_SRC_CPTS_RFT_CLK (0x0000000Eu) -#define PLLSS_RMII_REFCLK_SRC_CPTS_RFT_CLK_SHIFT (0x1u) - -#define PLLSS_RMII_REFCLK_SRC_REFCLK_SOURCE (0x00000001u) -#define PLLSS_RMII_REFCLK_SRC_REFCLK_SOURCE_SHIFT (0x0u) - -/** @brief PLLSS_SECSS_CLK_SRC register fields */ - -#define PLLSS_SECSS_CLK_SRC_SECSSCLK_SOURCE (0x00000001u) -#define PLLSS_SECSS_CLK_SRC_SECSSCLK_SOURCE_SHIFT (0x0u) - -/** @brief PLLSS_SYSCLK18_CLKSRC register fields */ - -#define PLLSS_SYSCLK18_CLKSRC_SYSCLK18_SOURCE (0x00000001u) -#define PLLSS_SYSCLK18_CLKSRC_SYSCLK18_SOURCE_SHIFT (0x0u) - -/** @brief PLLSS_WDT0_CLKSRC register fields */ - -#define PLLSS_WDT0_CLKSRC_WDT0_SOURCE (0x00000001u) -#define PLLSS_WDT0_CLKSRC_WDT0_SOURCE_SHIFT (0x0u) - -/** @brief PLLSS_EMIF_CLK_GATE register fields */ - -#define PLLSS_EMIF_CLK_GATE_DDR0_CKE_STATUS (0x00000004u) -#define PLLSS_EMIF_CLK_GATE_DDR0_CKE_STATUS_SHIFT (0x2u) - -#define PLLSS_EMIF_CLK_GATE_DDRPHY0_CLK_GATE (0x00000001u) -#define PLLSS_EMIF_CLK_GATE_DDRPHY0_CLK_GATE_SHIFT (0x0u) - -/** @brief PLLSS_DMTIMER_CLK_CHANGE register fields */ - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER7_IDLESTATUS (0x00008000u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER7_IDLESTATUS_SHIFT (0xFu) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER6_IDLESTATUS (0x00004000u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER6_IDLESTATUS_SHIFT (0xEu) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER5_IDLESTATUS (0x00002000u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER5_IDLESTATUS_SHIFT (0xDu) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER4_IDLESTATUS (0x00001000u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER4_IDLESTATUS_SHIFT (0xCu) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER3_IDLESTATUS (0x00000800u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER3_IDLESTATUS_SHIFT (0xBu) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER2_IDLESTATUS (0x00000400u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER2_IDLESTATUS_SHIFT (0xAu) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER1_IDLESTATUS (0x00000200u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER1_IDLESTATUS_SHIFT (0x9u) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER8_IDLESTATUS (0x00000100u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER8_IDLESTATUS_SHIFT (0x8u) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER7_IDLEREQ (0x00000080u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER7_IDLEREQ_SHIFT (0x7u) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER6_IDLEREQ (0x00000040u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER6_IDLEREQ_SHIFT (0x6u) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER5_IDLEREQ (0x00000020u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER5_IDLEREQ_SHIFT (0x5u) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER4_IDLEREQ (0x00000010u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER4_IDLEREQ_SHIFT (0x4u) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER3_IDLEREQ (0x00000008u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER3_IDLEREQ_SHIFT (0x3u) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER2_IDLEREQ (0x00000004u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER2_IDLEREQ_SHIFT (0x2u) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER1_IDLEREQ (0x00000002u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER1_IDLEREQ_SHIFT (0x1u) - -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER8_IDLEREQ (0x00000001u) -#define PLLSS_DMTIMER_CLK_CHANGE_DMTIMER8_IDLEREQ_SHIFT (0x0u) - -/** @brief PLLSS_DEEPSLEEP_CTRL register fields */ - -#define PLLSS_DEEPSLEEP_CTRL_DSENABLE (0x00020000u) -#define PLLSS_DEEPSLEEP_CTRL_DSENABLE_SHIFT (0x11u) - -#define PLLSS_DEEPSLEEP_CTRL_DSPOLARITY (0x00010000u) -#define PLLSS_DEEPSLEEP_CTRL_DSPOLARITY_SHIFT (0x10u) - -#define PLLSS_DEEPSLEEP_CTRL_DSCOUNT (0x0000FFFFu) -#define PLLSS_DEEPSLEEP_CTRL_DSCOUNT_SHIFT (0x0u) - -/** @brief PLLSS_DEEPSLEEP_STATUS register fields */ - -#define PLLSS_DEEPSLEEP_STATUS_DSCOMPLETE (0x00000001u) -#define PLLSS_DEEPSLEEP_STATUS_DSCOMPLETE_SHIFT (0x0u) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_prcm_C6A811x.h b/lib/tiam1808/tiam1808/hw/hw_prcm_C6A811x.h deleted file mode 100644 index b02e94b43..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_prcm_C6A811x.h +++ /dev/null @@ -1,1327 +0,0 @@ -/** - * \file hw_prcm_C6A811x.h - * - * \brief This file contains the PRCM information for C6A811x SoC - * - * - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _HW_PRCM_C6A811X_H_ -#define _HW_PRCM_C6A811X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/*************************************************************************\ - * Register Definition Macros -\*************************************************************************/ - -/** @brief PRM_DEVICE register offsets */ -#define PRM_DEVICE_PRM_RSTCTRL (0xA0) -#define PRM_DEVICE_PRM_RSTTIME (0xA4) -#define PRM_DEVICE_PRM_RSTST (0xA8) - -/** @brief CM_DEVICE register offsets */ -#define CM_DEVICE_CM_CLKOUT_CTRL (0x0) - -/** @brief OCP_SOCKET_PRM register offsets */ -#define OCP_SOCKET_PRM_REVISION_PRM (0x0) - -/** @brief CM_DPLL register offsets */ -#define CM_DPLL_CM_SYSCLK3_CLKSEL (0x8) -#define CM_DPLL_CM_SYSCLK10_CLKSEL (0x24) -#define CM_DPLL_CM_VPB3_CLKSEL (0x40) -#define CM_DPLL_CM_VPC1_CLKSEL (0x44) -#define CM_DPLL_CM_VPD1_CLKSEL (0x48) -#define CM_DPLL_CM_SYSCLK19_CLKSEL (0x4C) -#define CM_DPLL_CM_SYSCLK20_CLKSEL (0x50) -#define CM_DPLL_CM_SYSCLK21_CLKSEL (0x54) -#define CM_DPLL_CM_SYSCLK22_CLKSEL (0x58) -#define CM_DPLL_CM_APA_CLKSEL (0x5C) -#define CM_DPLL_CM_SYSCLK14_CLKSEL (0x70) -#define CM_DPLL_CM_SYSCLK16_CLKSEL (0x74) -#define CM_DPLL_CM_SYSCLK18_CLKSEL (0x78) -#define CM_DPLL_CM_AUDIOCLK_MCASP0_CLKSEL (0x7C) -#define CM_DPLL_CM_AUDIOCLK_MCASP1_CLKSEL (0x80) -#define CM_DPLL_CM_AUDIOCLK_MCASP2_CLKSEL (0x84) -#define CM_DPLL_CM_AUDIOCLK_MCBSP_CLKSEL (0x88) -#define CM_DPLL_CM_HDMI_CLKSEL (0xAC) -#define CM_DPLL_CM_SYSCLK23_CLKSEL (0xB0) - -/** @brief CM_ACTIVE register offsets */ -#define CM_ACTIVE_CM_GEM_CLKSTCTRL (0x0) -#define CM_ACTIVE_CM_ACTIVE_GEM_CLKCTRL (0x20) - -/** @brief CM_DEFAULT register offsets */ -#define CM_DEFAULT_DMM_CLKCTRL (0x28) -#define CM_DEFAULT_TPPSS_CLKCTRL (0x54) -#define CM_DEFAULT_USB_CLKCTRL (0x58) -#define CM_DEFAULT_DUCATI_CLKCTRL (0x60) -#define CM_DEFAULT_PCI_CLKCTRL (0x78) - -/** @brief CM_DSS register offsets */ -#define CM_DSS_CLKSTCTRL (0x0) -#define CM_DSS_DSS_CLKCTRL (0x20) -#define CM_DSS_HDMI_CLKCTRL (0x24) - -/** @brief CM_SGX register offsets */ -#define CM_SGX_CLKSTCTRL (0x0) -#define CM_SGX_SGX_CLKCTRL (0x20) - -/** @brief PRM_ACTIVE register offsets */ -#define PRM_ACTIVE_PWRSTCTRL (0x0) -#define PRM_ACTIVE_PWRSTST (0x4) -#define PRM_ACTIVE_RSTCTRL (0x10) -#define PRM_ACTIVE_RSTST (0x14) - -/** @brief PRM_DEFAULT register offsets */ -#define PRM_DEFAULT_PWRSTCTRL (0x0) -#define PRM_DEFAULT_RSTCTRL (0x10) -#define PRM_DEFAULT_RSTST (0x14) - -/** @brief PRM_DSS register offsets */ -#define PRM_DSS_PWRSTCTRL (0x0) -#define PRM_DSS_PWRSTST (0x4) -#define PRM_DSS_RSTCTRL (0x10) -#define PRM_DSS_RSTST (0x14) - -/** @brief PRM_SGX register offsets */ -#define PRM_SGX_PWRSTCTRL (0x0) -#define PRM_SGX_RSTCTRL (0x4) -#define PRM_SGX_PWRSTST (0x10) -#define PRM_SGX_RSTST (0x14) - -/** @brief CM_ALWON register offsets */ -#define CM_ALWON_L3_SLOW_CLKSTCTRL (0x0) -#define CM_ALWON_ETHERNET_CLKSTCTRL (0x4) -#define CM_ALWON_L3_MED_CLKSTCTRL (0x8) -#define CM_ALWON_MMU_CLKSTCTRL (0xC) -#define CM_ALWON_MMUCFG_CLKSTCTRL (0x10) -#define CM_ALWON_OCMC_0_CLKSTCTRL (0x14) -#define CM_ALWON_VCP_CLKSTCTRL (0x18) -#define CM_ALWON_MPU_CLKSTCTRL (0x1C) -#define CM_ALWON_SYSCLK4_CLKSTCTRL (0x20) -#define CM_ALWON_SYSCLK5_CLKSTCTRL (0x24) -#define CM_ALWON_SYSCLK6_CLKSTCTRL (0x28) -#define CM_ALWON_RTC_CLKSTCTRL (0x2C) -#define CM_ALWON_L3_FAST_CLKSTCTRL (0x30) -#define CM_ALWON_MCASP0_CLKCTRL (0x140) -#define CM_ALWON_MCASP1_CLKCTRL (0x144) -#define CM_ALWON_MCASP2_CLKCTRL (0x148) -#define CM_ALWON_MCBSP_CLKCTRL (0x14C) -#define CM_ALWON_UART_0_CLKCTRL (0x150) -#define CM_ALWON_UART_1_CLKCTRL (0x154) -#define CM_ALWON_UART_2_CLKCTRL (0x158) -#define CM_ALWON_GPIO_0_CLKCTRL (0x15C) -#define CM_ALWON_GPIO_1_CLKCTRL (0x160) -#define CM_ALWON_I2C_0_CLKCTRL (0x164) -#define CM_ALWON_I2C_1_CLKCTRL (0x168) -#define CM_ALWON_MCASP_3_4_5_CLKCTRL (0x16C) -#define CM_ALWON_ATL_CLKCTRL (0x170) -#define CM_ALWON_MLB_CLKCTRL (0x174) -#define CM_ALWON_PATA_CLKCTRL (0x178) -#define CM_ALWON_TIMER_4_CLKCTRL (0x17C) -#define CM_ALWON_UART_3_CLKCTRL (0x180) -#define CM_ALWON_UART_4_CLKCTRL (0x184) -#define CM_ALWON_UART_5_CLKCTRL (0x188) -#define CM_ALWON_WDTIMER_CLKCTRL (0x18C) -#define CM_ALWON_SPI_CLKCTRL (0x190) -#define CM_ALWON_MAILBOX_CLKCTRL (0x194) -#define CM_ALWON_SPINBOX_CLKCTRL (0x198) -#define CM_ALWON_MMUDATA_CLKCTRL (0x19C) -#define CM_ALWON_MMUCFG_CLKCTRL (0x1A8) -#define CM_ALWON_SDIO_CLKCTRL (0x1B0) -#define CM_ALWON_OCMC_0_CLKCTRL (0x1B4) -#define CM_ALWON_VCP_CLKCTRL (0x1B8) -#define CM_ALWON_SMARTCARD_0_CLKCTRL (0x1BC) -#define CM_ALWON_SMARTCARD_1_CLKCTRL (0x1C0) -#define CM_ALWON_CONTROL_CLKCTRL (0x1C4) -#define CM_ALWON_SECSS_CLKCTRL (0x1C8) -#define CM_ALWON_GPMC_CLKCTRL (0x1D0) -#define CM_ALWON_ETHERNET_0_CLKCTRL (0x1D4) -#define CM_ALWON_MPU_CLKCTRL (0x1DC) -#define CM_ALWON_DEBUGSS_CLKCTRL (0x1E0) -#define CM_ALWON_L3_CLKCTRL (0x1E4) -#define CM_ALWON_L4HS_CLKCTRL (0x1E8) -#define CM_ALWON_L4LS_CLKCTRL (0x1EC) -#define CM_ALWON_RTC_CLKCTRL (0x1F0) -#define CM_ALWON_TPCC_CLKCTRL (0x1F4) -#define CM_ALWON_TPTC0_CLKCTRL (0x1F8) -#define CM_ALWON_TPTC1_CLKCTRL (0x1FC) -#define CM_ALWON_TPTC2_CLKCTRL (0x200) -#define CM_ALWON_TPTC3_CLKCTRL (0x204) -#define CM_ALWON_SR_0_CLKCTRL (0x208) -#define CM_ALWON_SR_1_CLKCTRL (0x20C) -#define CM_ALWON_SR_2_CLKCTRL (0x210) -#define CM_ALWON_SR_3_CLKCTRL (0x214) -#define CM_ALWON_DCAN_0_1_CLKCTRL (0x218) -#define CM_ALWON_MMCHS_0_CLKCTRL (0x21C) -#define CM_ALWON_MMCHS_1_CLKCTRL (0x220) -#define CM_ALWON_MMCHS_2_CLKCTRL (0x224) -#define CM_ALWON_CUST_EFUSE_CLKCTRL (0x228) - -/** @brief PRM_ALWON register offsets */ -#define PRM_ALWON_RSTST (0x14) - -/**************************************************************************\ - * Field Definition Macros -\**************************************************************************/ - -/** @brief PRM_DEVICE_PRM_RSTCTRL register fields */ - -#define PRM_DEVICE_PRM_RSTCTRL_RST_GLOBAL_COLD_SW (0x00000002u) -#define PRM_DEVICE_PRM_RSTCTRL_RST_GLOBAL_COLD_SW_SHIFT (0x1u) - -#define PRM_DEVICE_PRM_RSTCTRL_RST_GLOBAL_WARM_SW (0x00000001u) -#define PRM_DEVICE_PRM_RSTCTRL_RST_GLOBAL_WARM_SW_SHIFT (0x0u) - -/** @brief PRM_DEVICE_PRM_RSTTIME register fields */ - -#define PRM_DEVICE_PRM_RSTTIME_RSTTIME2 (0x00001F00u) -#define PRM_DEVICE_PRM_RSTTIME_RSTTIME2_SHIFT (0x8u) - -#define PRM_DEVICE_PRM_RSTTIME_RSTTIME1 (0x000000FFu) -#define PRM_DEVICE_PRM_RSTTIME_RSTTIME1_SHIFT (0x0u) - -/** @brief PRM_DEVICE_PRM_RSTST register fields */ - -#define PRM_DEVICE_PRM_RSTST_ICEPICK_RST (0x00000200u) -#define PRM_DEVICE_PRM_RSTST_ICEPICK_RST_SHIFT (0x9u) - -#define PRM_DEVICE_PRM_RSTST_EXTERNAL_WARM_RST (0x00000020u) -#define PRM_DEVICE_PRM_RSTST_EXTERNAL_WARM_RST_SHIFT (0x5u) - -#define PRM_DEVICE_PRM_RSTST_SECURE_WDT_RST (0x00000010u) -#define PRM_DEVICE_PRM_RSTST_SECURE_WDT_RST_SHIFT (0x4u) - -#define PRM_DEVICE_PRM_RSTST_MPU_WDT_RST (0x00000008u) -#define PRM_DEVICE_PRM_RSTST_MPU_WDT_RST_SHIFT (0x3u) - -#define PRM_DEVICE_PRM_RSTST_MPU_SECURITY_VIOL_RST (0x00000004u) -#define PRM_DEVICE_PRM_RSTST_MPU_SECURITY_VIOL_RST_SHIFT (0x2u) - -#define PRM_DEVICE_PRM_RSTST_GLOBAL_WARM_SW_RST (0x00000002u) -#define PRM_DEVICE_PRM_RSTST_GLOBAL_WARM_SW_RST_SHIFT (0x1u) - -#define PRM_DEVICE_PRM_RSTST_GLOBAL_COLD_RST (0x00000001u) -#define PRM_DEVICE_PRM_RSTST_GLOBAL_COLD_RST_SHIFT (0x0u) - -/** @brief CM_DEVICE_CM_CLKOUT_CTRL register fields */ - -#define CM_DEVICE_CM_CLKOUT_CTRL_CLKOUT2EN (0x00000080u) -#define CM_DEVICE_CM_CLKOUT_CTRL_CLKOUT2EN_SHIFT (0x7u) - -#define CM_DEVICE_CM_CLKOUT_CTRL_CLKOUT2DIV (0x00000038u) -#define CM_DEVICE_CM_CLKOUT_CTRL_CLKOUT2DIV_SHIFT (0x3u) - -#define CM_DEVICE_CM_CLKOUT_CTRL_CLKOUT2SOURCE (0x00000003u) -#define CM_DEVICE_CM_CLKOUT_CTRL_CLKOUT2SOURCE_SHIFT (0x0u) - -/** @brief OCP_SOCKET_PRM_REVISION_PRM register fields */ - -#define OCP_SOCKET_PRM_REVISION_PRM_Rev (0x000000FFu) -#define OCP_SOCKET_PRM_REVISION_PRM_Rev_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_SYSCLK3_CLKSEL register fields */ - -#define CM_DPLL_CM_SYSCLK3_CLKSEL_CLKSEL (0x00000007u) -#define CM_DPLL_CM_SYSCLK3_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_SYSCLK10_CLKSEL register fields */ - -#define CM_DPLL_CM_SYSCLK10_CLKSEL_CLKSEL (0x00000007u) -#define CM_DPLL_CM_SYSCLK10_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_VPB3_CLKSEL register fields */ - -#define CM_DPLL_CM_VPB3_CLKSEL_CLKSEL (0x00000003u) -#define CM_DPLL_CM_VPB3_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_VPC1_CLKSEL register fields */ - -#define CM_DPLL_CM_VPC1_CLKSEL_CLKSEL (0x00000003u) -#define CM_DPLL_CM_VPC1_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_VPD1_CLKSEL register fields */ - -#define CM_DPLL_CM_VPD1_CLKSEL_CLKSEL (0x00000007u) -#define CM_DPLL_CM_VPD1_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_SYSCLK19_CLKSEL register fields */ - -#define CM_DPLL_CM_SYSCLK19_CLKSEL_CLKSEL (0x00000007u) -#define CM_DPLL_CM_SYSCLK19_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_SYSCLK20_CLKSEL register fields */ - -#define CM_DPLL_CM_SYSCLK20_CLKSEL_CLKSEL (0x00000007u) -#define CM_DPLL_CM_SYSCLK20_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_SYSCLK21_CLKSEL register fields */ - -#define CM_DPLL_CM_SYSCLK21_CLKSEL_CLKSEL (0x00000007u) -#define CM_DPLL_CM_SYSCLK21_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_SYSCLK22_CLKSEL register fields */ - -#define CM_DPLL_CM_SYSCLK22_CLKSEL_CLKSEL (0x00000007u) -#define CM_DPLL_CM_SYSCLK22_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_APA_CLKSEL register fields */ - -#define CM_DPLL_CM_APA_CLKSEL_CLKSEL (0x00000007u) -#define CM_DPLL_CM_APA_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_SYSCLK14_CLKSEL register fields */ - -#define CM_DPLL_CM_SYSCLK14_CLKSEL_CLKSEL (0x00000003u) -#define CM_DPLL_CM_SYSCLK14_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_SYSCLK16_CLKSEL register fields */ - -#define CM_DPLL_CM_SYSCLK16_CLKSEL_CLKSEL (0x00000001u) -#define CM_DPLL_CM_SYSCLK16_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_SYSCLK18_CLKSEL register fields */ - -#define CM_DPLL_CM_SYSCLK18_CLKSEL_CLKSEL (0x00000001u) -#define CM_DPLL_CM_SYSCLK18_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_AUDIOCLK_MCASP0_CLKSEL register fields */ - -#define CM_DPLL_CM_AUDIOCLK_MCASP0_CLKSEL_CLKSEL (0x00000003u) -#define CM_DPLL_CM_AUDIOCLK_MCASP0_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_AUDIOCLK_MCASP1_CLKSEL register fields */ - -#define CM_DPLL_CM_AUDIOCLK_MCASP1_CLKSEL_CLKSEL (0x00000003u) -#define CM_DPLL_CM_AUDIOCLK_MCASP1_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_AUDIOCLK_MCASP2_CLKSEL register fields */ - -#define CM_DPLL_CM_AUDIOCLK_MCASP2_CLKSEL_CLKSEL (0x00000003u) -#define CM_DPLL_CM_AUDIOCLK_MCASP2_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_AUDIOCLK_MCBSP_CLKSEL register fields */ - -#define CM_DPLL_CM_AUDIOCLK_MCBSP_CLKSEL_CLKSEL (0x00000003u) -#define CM_DPLL_CM_AUDIOCLK_MCBSP_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_HDMI_CLKSEL register fields */ - -#define CM_DPLL_CM_HDMI_CLKSEL_CLKSEL (0x00000003u) -#define CM_DPLL_CM_HDMI_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_DPLL_CM_SYSCLK23_CLKSEL register fields */ - -#define CM_DPLL_CM_SYSCLK23_CLKSEL_CLKSEL (0x00000007u) -#define CM_DPLL_CM_SYSCLK23_CLKSEL_CLKSEL_SHIFT (0x0u) - -/** @brief CM_ACTIVE_CM_GEM_CLKSTCTRL register fields */ - -#define CM_ACTIVE_CM_GEM_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ACTIVE_CM_GEM_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ACTIVE_CM_ACTIVE_GEM_CLKCTRL register fields */ - -#define CM_ACTIVE_CM_ACTIVE_GEM_CLKCTRL_STBYST (0x00040000u) -#define CM_ACTIVE_CM_ACTIVE_GEM_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_ACTIVE_CM_ACTIVE_GEM_CLKCTRL_IDLEST (0x00030000u) -#define CM_ACTIVE_CM_ACTIVE_GEM_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ACTIVE_CM_ACTIVE_GEM_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ACTIVE_CM_ACTIVE_GEM_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_DEFAULT_DMM_CLKCTRL register fields */ - -#define CM_DEFAULT_DMM_CLKCTRL_IDLEST (0x00030000u) -#define CM_DEFAULT_DMM_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_DEFAULT_DMM_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_DEFAULT_DMM_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_DEFAULT_TPPSS_CLKCTRL register fields */ - -#define CM_DEFAULT_TPPSS_CLKCTRL_STBYST (0x00040000u) -#define CM_DEFAULT_TPPSS_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_DEFAULT_TPPSS_CLKCTRL_IDLEST (0x00030000u) -#define CM_DEFAULT_TPPSS_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_DEFAULT_TPPSS_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_DEFAULT_TPPSS_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_DEFAULT_USB_CLKCTRL register fields */ - -#define CM_DEFAULT_USB_CLKCTRL_STBYST (0x00040000u) -#define CM_DEFAULT_USB_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_DEFAULT_USB_CLKCTRL_IDLEST (0x00030000u) -#define CM_DEFAULT_USB_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_DEFAULT_USB_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_DEFAULT_USB_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_DEFAULT_DUCATI_CLKCTRL register fields */ - -#define CM_DEFAULT_DUCATI_CLKCTRL_STBYST (0x00040000u) -#define CM_DEFAULT_DUCATI_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_DEFAULT_DUCATI_CLKCTRL_IDLEST (0x00030000u) -#define CM_DEFAULT_DUCATI_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_DEFAULT_DUCATI_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_DEFAULT_DUCATI_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_DEFAULT_PCI_CLKCTRL register fields */ - -#define CM_DEFAULT_PCI_CLKCTRL_STBYST (0x00040000u) -#define CM_DEFAULT_PCI_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_DEFAULT_PCI_CLKCTRL_IDLEST (0x00030000u) -#define CM_DEFAULT_PCI_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_DEFAULT_PCI_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_DEFAULT_PCI_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_DSS_CLKSTCTRL register fields */ - -#define CM_DSS_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_DSS_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_DSS_DSS_CLKCTRL register fields */ - -#define CM_DSS_DSS_CLKCTRL_STBYST (0x00040000u) -#define CM_DSS_DSS_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_DSS_DSS_CLKCTRL_IDLEST (0x00030000u) -#define CM_DSS_DSS_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_DSS_DSS_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_DSS_DSS_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_DSS_HDMI_CLKCTRL register fields */ - -#define CM_DSS_HDMI_CLKCTRL_IDLEST (0x00030000u) -#define CM_DSS_HDMI_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_DSS_HDMI_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_DSS_HDMI_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_SGX_CLKSTCTRL register fields */ - -#define CM_SGX_CLKSTCTRL_CLKACTIVITY_SGX_GCLK (0x00000100u) -#define CM_SGX_CLKSTCTRL_CLKACTIVITY_SGX_GCLK_SHIFT (0x8u) - -#define CM_SGX_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_SGX_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_SGX_SGX_CLKCTRL register fields */ - -#define CM_SGX_SGX_CLKCTRL_STBYST (0x00040000u) -#define CM_SGX_SGX_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_SGX_SGX_CLKCTRL_IDLEST (0x00030000u) -#define CM_SGX_SGX_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_SGX_SGX_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_SGX_SGX_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief PRM_ACTIVE_PWRSTCTRL register fields */ - -#define PRM_ACTIVE_PWRSTCTRL_Active_MEM_ONState (0x00030000u) -#define PRM_ACTIVE_PWRSTCTRL_Active_MEM_ONState_SHIFT (0x10u) - -#define PRM_ACTIVE_PWRSTCTRL_LowPowerStateChange (0x00000010u) -#define PRM_ACTIVE_PWRSTCTRL_LowPowerStateChange_SHIFT (0x4u) - -#define PRM_ACTIVE_PWRSTCTRL_PowerState (0x00000003u) -#define PRM_ACTIVE_PWRSTCTRL_PowerState_SHIFT (0x0u) - -/** @brief PRM_ACTIVE_PWRSTST register fields */ - -#define PRM_ACTIVE_PWRSTST_InTransition (0x00100000u) -#define PRM_ACTIVE_PWRSTST_InTransition_SHIFT (0x14u) - -#define PRM_ACTIVE_PWRSTST_Active_MEM_StateSt (0x00000030u) -#define PRM_ACTIVE_PWRSTST_Active_MEM_StateSt_SHIFT (0x4u) - -#define PRM_ACTIVE_PWRSTST_LogicStateSt (0x00000004u) -#define PRM_ACTIVE_PWRSTST_LogicStateSt_SHIFT (0x2u) - -#define PRM_ACTIVE_PWRSTST_PowerStateSt (0x00000003u) -#define PRM_ACTIVE_PWRSTST_PowerStateSt_SHIFT (0x0u) - -/** @brief PRM_ACTIVE_RSTCTRL register fields */ - -#define PRM_ACTIVE_RSTCTRL_GEM_SW_RST (0x00000002u) -#define PRM_ACTIVE_RSTCTRL_GEM_SW_RST_SHIFT (0x1u) - -#define PRM_ACTIVE_RSTCTRL_GEM_LRST (0x00000001u) -#define PRM_ACTIVE_RSTCTRL_GEM_LRST_SHIFT (0x0u) - -/** @brief PRM_ACTIVE_RSTST register fields */ - -#define PRM_ACTIVE_RSTST_EMULATION_GEM_RST (0x00000010u) -#define PRM_ACTIVE_RSTST_EMULATION_GEM_RST_SHIFT (0x4u) - -#define PRM_ACTIVE_RSTST_GEM_LRST_REQ (0x00000008u) -#define PRM_ACTIVE_RSTST_GEM_LRST_REQ_SHIFT (0x3u) - -#define PRM_ACTIVE_RSTST_GEM_GRST (0x00000002u) -#define PRM_ACTIVE_RSTST_GEM_GRST_SHIFT (0x1u) - -#define PRM_ACTIVE_RSTST_GEM_LRST (0x00000001u) -#define PRM_ACTIVE_RSTST_GEM_LRST_SHIFT (0x0u) - -/** @brief PRM_DEFAULT_PWRSTCTRL */ - -#define PRM_DEFAULT_PWRSTCTRL_POWERSTATE (0x00000003u) -#define PRM_DEFAULT_PWRSTCTRL_POWERSTATE_SHIFT (0x0u) - -/** @brief PRM_DEFAULT_RSTCTRL register fields */ - -#define PRM_DEFAULT_RSTCTRL_PCI_LRST (0x00000080u) -#define PRM_DEFAULT_RSTCTRL_PCI_LRST_SHIFT (0x7u) - -#define PRM_DEFAULT_RSTCTRL_DUCATI_RST3 (0x00000010u) -#define PRM_DEFAULT_RSTCTRL_DUCATI_RST3_SHIFT (0x4u) - -#define PRM_DEFAULT_RSTCTRL_DUCATI_M3_RST2 (0x00000008u) -#define PRM_DEFAULT_RSTCTRL_DUCATI_M3_RST2_SHIFT (0x3u) - -#define PRM_DEFAULT_RSTCTRL_DUCATI_M3_RST1 (0x00000004u) -#define PRM_DEFAULT_RSTCTRL_DUCATI_M3_RST1_SHIFT (0x2u) - -#define PRM_DEFAULT_RSTCTRL_TPPSS_SW_RST (0x00000002u) -#define PRM_DEFAULT_RSTCTRL_TPPSS_SW_RST_SHIFT (0x1u) - -#define PRM_DEFAULT_RSTCTRL_TPPSS_LRST (0x00000001u) -#define PRM_DEFAULT_RSTCTRL_TPPSS_LRST_SHIFT (0x0u) - -/** @brief PRM_DEFAULT_RSTST register fields */ - -#define PRM_DEFAULT_RSTST_ICECRUSHER_m3_2_RST (0x00004000u) -#define PRM_DEFAULT_RSTST_ICECRUSHER_m3_2_RST_SHIFT (0xEu) - -#define PRM_DEFAULT_RSTST_ICECRUSHER_M3_1_RST (0x00002000u) -#define PRM_DEFAULT_RSTST_ICECRUSHER_M3_1_RST_SHIFT (0xDu) - -#define PRM_DEFAULT_RSTST_EMULATION_M3_2_RST (0x00001000u) -#define PRM_DEFAULT_RSTST_EMULATION_M3_2_RST_SHIFT (0xCu) - -#define PRM_DEFAULT_RSTST_EMULATION_M3_1_RST (0x00000800u) -#define PRM_DEFAULT_RSTST_EMULATION_M3_1_RST_SHIFT (0xBu) - -#define PRM_DEFAULT_RSTST_ICECRUSHER_TPPSS_RST (0x00000400u) -#define PRM_DEFAULT_RSTST_ICECRUSHER_TPPSS_RST_SHIFT (0xAu) - -#define PRM_DEFAULT_RSTST_EMULATION_TPPSS_RST (0x00000200u) -#define PRM_DEFAULT_RSTST_EMULATION_TPPSS_RST_SHIFT (0x9u) - -#define PRM_DEFAULT_RSTST_PCI_LRST (0x00000080u) -#define PRM_DEFAULT_RSTST_PCI_LRST_SHIFT (0x7u) - -#define PRM_DEFAULT_RSTST_DUCATI_RST3 (0x00000010u) -#define PRM_DEFAULT_RSTST_DUCATI_RST3_SHIFT (0x4u) - -#define PRM_DEFAULT_RSTST_DUCATI_M3_RST2 (0x00000008u) -#define PRM_DEFAULT_RSTST_DUCATI_M3_RST2_SHIFT (0x3u) - -#define PRM_DEFAULT_RSTST_DUCATI_M3_RST1 (0x00000004u) -#define PRM_DEFAULT_RSTST_DUCATI_M3_RST1_SHIFT (0x2u) - -#define PRM_DEFAULT_RSTST_TPPSS_RST (0x00000002u) -#define PRM_DEFAULT_RSTST_TPPSS_RST_SHIFT (0x1u) - -#define PRM_DEFAULT_RSTST_TPPSS_LRST (0x00000001u) -#define PRM_DEFAULT_RSTST_TPPSS_LRST_SHIFT (0x0u) - -/** @brief PRM_DSS_PWRSTCTRL register fields */ - -#define PRM_DSS_PWRSTCTRL_DSS_MEM_ONState (0x00030000u) -#define PRM_DSS_PWRSTCTRL_DSS_MEM_ONState_SHIFT (0x10u) - -#define PRM_DSS_PWRSTCTRL_LowPowerStateChange (0x00000010u) -#define PRM_DSS_PWRSTCTRL_LowPowerStateChange_SHIFT (0x4u) - -#define PRM_DSS_PWRSTCTRL_PowerState (0x00000003u) -#define PRM_DSS_PWRSTCTRL_PowerState_SHIFT (0x0u) - -/** @brief PRM_DSS_PWRSTST register fields */ - -#define PRM_DSS_PWRSTST_InTransition (0x00100000u) -#define PRM_DSS_PWRSTST_InTransition_SHIFT (0x14u) - -#define PRM_DSS_PWRSTST_DSS_MEM_StateSt (0x00000030u) -#define PRM_DSS_PWRSTST_DSS_MEM_StateSt_SHIFT (0x4u) - -#define PRM_DSS_PWRSTST_LogicStateSt (0x00000004u) -#define PRM_DSS_PWRSTST_LogicStateSt_SHIFT (0x2u) - -#define PRM_DSS_PWRSTST_PowerStateSt (0x00000003u) -#define PRM_DSS_PWRSTST_PowerStateSt_SHIFT (0x0u) - -/** @brief PRM_DSS_RSTCTRL register fields */ - -#define PRM_DSS_RSTCTRL_DSS_RST (0x00000004u) -#define PRM_DSS_RSTCTRL_DSS_RST_SHIFT (0x2u) - -/** @brief PRM_DSS_RSTST register fields */ - -#define PRM_DSS_RSTST_DSS_RST (0x00000004u) -#define PRM_DSS_RSTST_DSS_RST_SHIFT (0x2u) - -/** @brief PRM_SGX_PWRSTCTRL register fields */ - -#define PRM_SGX_PWRSTCTRL_SGX_MEM_ONState (0x00030000u) -#define PRM_SGX_PWRSTCTRL_SGX_MEM_ONState_SHIFT (0x10u) - -#define PRM_SGX_PWRSTCTRL_LowPowerStateChange (0x00000010u) -#define PRM_SGX_PWRSTCTRL_LowPowerStateChange_SHIFT (0x4u) - -#define PRM_SGX_PWRSTCTRL_PowerState (0x00000003u) -#define PRM_SGX_PWRSTCTRL_PowerState_SHIFT (0x0u) - -/** @brief PRM_SGX_RSTCTRL register fields */ - -#define PRM_SGX_RSTCTRL_SGX_RST (0x00000001u) -#define PRM_SGX_RSTCTRL_SGX_RST_SHIFT (0x0u) - -/** @brief PRM_SGX_PWRSTST register fields */ - -#define PRM_SGX_PWRSTST_InTransition (0x00100000u) -#define PRM_SGX_PWRSTST_InTransition_SHIFT (0x14u) - -#define PRM_SGX_PWRSTST_SGX_MEM_StateSt (0x00000030u) -#define PRM_SGX_PWRSTST_SGX_MEM_StateSt_SHIFT (0x4u) - -#define PRM_SGX_PWRSTST_LogicStateSt (0x00000004u) -#define PRM_SGX_PWRSTST_LogicStateSt_SHIFT (0x2u) - -#define PRM_SGX_PWRSTST_PowerStateSt (0x00000003u) -#define PRM_SGX_PWRSTST_PowerStateSt_SHIFT (0x0u) - -/** @brief PRM_SGX_RSTST register fields */ - -#define PRM_SGX_RSTST_SGX_RST (0x00000001u) -#define PRM_SGX_RSTST_SGX_RST_SHIFT (0x0u) - -/** @brief CM_ALWON_L3_SLOW_CLKSTCTRL register fields */ - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_SDIO_CLKADPI_GCLK (0x08000000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_SDIO_CLKADPI_GCLK_SHIFT (0x1Bu) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK (0x04000000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK_SHIFT (0x1Au) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK (0x02000000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK_SHIFT (0x19u) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK (0x01000000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK_SHIFT (0x18u) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK (0x00800000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK_SHIFT (0x17u) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK (0x00400000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK_SHIFT (0x16u) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK (0x00200000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK_SHIFT (0x15u) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER1_GCLK (0x00100000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER1_GCLK_SHIFT (0x14u) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER0_GCLK (0x00080000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_TIMER0_GCLK_SHIFT (0x13u) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_SPI_GSYSCLK (0x00020000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_SPI_GSYSCLK_SHIFT (0x11u) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_I2C_GSYSCLK (0x00010000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_I2C_GSYSCLK_SHIFT (0x10u) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK (0x00008000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT (0xFu) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_GPIO_0_GDBCLK (0x00004000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_GPIO_0_GDBCLK_SHIFT (0xEu) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_UART_GFCLK (0x00002000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_UART_GFCLK_SHIFT (0xDu) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_MCBSP_AUX_GCLK (0x00001000u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_MCBSP_AUX_GCLK_SHIFT (0xCu) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_MCASP2_AUX_GCLK (0x00000800u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_MCASP2_AUX_GCLK_SHIFT (0xBu) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_MCASP1_AUX_GCLK (0x00000400u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_MCASP1_AUX_GCLK_SHIFT (0xAu) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_MCASP0_AUX_GCLK (0x00000200u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKACTIVITY_MCASP0_AUX_GCLK_SHIFT (0x9u) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_L3_SLOW_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_ETHERNET_CLKSTCTRL register fields */ - -#define CM_ALWON_ETHERNET_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_ETHERNET_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_L3_MED_CLKSTCTRL register fields */ - -#define CM_ALWON_L3_MED_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_L3_MED_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_MMU_CLKSTCTRL register fields */ - -#define CM_ALWON_MMU_CLKSTCTRL_CLKACTIVITY_MMU_GCLK (0x00000100u) -#define CM_ALWON_MMU_CLKSTCTRL_CLKACTIVITY_MMU_GCLK_SHIFT (0x8u) - -#define CM_ALWON_MMU_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_MMU_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_MMUCFG_CLKSTCTRL register fields */ - -#define CM_ALWON_MMUCFG_CLKSTCTRL_CLKACTIVITY_MMU_CFG_GCLK (0x00000100u) -#define CM_ALWON_MMUCFG_CLKSTCTRL_CLKACTIVITY_MMU_CFG_GCLK_SHIFT (0x8u) - -#define CM_ALWON_MMUCFG_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_MMUCFG_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_OCMC_0_CLKSTCTRL register fields */ - -#define CM_ALWON_OCMC_0_CLKSTCTRL_CLKACTIVITY_VCP_GCLK (0x00000100u) -#define CM_ALWON_OCMC_0_CLKSTCTRL_CLKACTIVITY_VCP_GCLK_SHIFT (0x8u) - -#define CM_ALWON_OCMC_0_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_OCMC_0_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_VCP_CLKSTCTRL register fields */ - -#define CM_ALWON_VCP_CLKSTCTRL_CLKACTIVITY_OCMC_1_GCLK (0x00000100u) -#define CM_ALWON_VCP_CLKSTCTRL_CLKACTIVITY_OCMC_1_GCLK_SHIFT (0x8u) - -#define CM_ALWON_VCP_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_VCP_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_MPU_CLKSTCTRL register fields */ - -#define CM_ALWON_MPU_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_MPU_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_SYSCLK4_CLKSTCTRL register fields */ - -#define CM_ALWON_SYSCLK4_CLKSTCTRL_CLKACTIVITY_L3_F_EN_GCLK (0x00000800u) -#define CM_ALWON_SYSCLK4_CLKSTCTRL_CLKACTIVITY_L3_F_EN_GCLK_SHIFT (0xBu) - -#define CM_ALWON_SYSCLK4_CLKSTCTRL_CLKACTIVITY_L3_S_GCLK (0x00000400u) -#define CM_ALWON_SYSCLK4_CLKSTCTRL_CLKACTIVITY_L3_S_GCLK_SHIFT (0xAu) - -#define CM_ALWON_SYSCLK4_CLKSTCTRL_CLKACTIVITY_L3_M_GCLK (0x00000200u) -#define CM_ALWON_SYSCLK4_CLKSTCTRL_CLKACTIVITY_L3_M_GCLK_SHIFT (0x9u) - -#define CM_ALWON_SYSCLK4_CLKSTCTRL_CLKACTIVITY_SYSCLK4_GCLK (0x00000100u) -#define CM_ALWON_SYSCLK4_CLKSTCTRL_CLKACTIVITY_SYSCLK4_GCLK_SHIFT (0x8u) - -#define CM_ALWON_SYSCLK4_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_SYSCLK4_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_SYSCLK5_CLKSTCTRL register fields */ - -#define CM_ALWON_SYSCLK5_CLKSTCTRL_CLKACTIVITY_DEBUG_CLKA_GCLK (0x00000200u) -#define CM_ALWON_SYSCLK5_CLKSTCTRL_CLKACTIVITY_DEBUG_CLKA_GCLK_SHIFT (0x9u) - -#define CM_ALWON_SYSCLK5_CLKSTCTRL_CLKACTIVITY_SYSCLK5_GCLK (0x00000100u) -#define CM_ALWON_SYSCLK5_CLKSTCTRL_CLKACTIVITY_SYSCLK5_GCLK_SHIFT (0x8u) - -#define CM_ALWON_SYSCLK5_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_SYSCLK5_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_SYSCLK6_CLKSTCTRL register fields */ - -#define CM_ALWON_SYSCLK6_CLKSTCTRL_CLKACTIVITY_SYSCLK6_GCLK (0x00000100u) -#define CM_ALWON_SYSCLK6_CLKSTCTRL_CLKACTIVITY_SYSCLK6_GCLK_SHIFT (0x8u) - -#define CM_ALWON_SYSCLK6_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_SYSCLK6_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_RTC_CLKSTCTRL register fields */ - -#define CM_ALWON_RTC_CLKSTCTRL_CLKACTIVITY_RTC_GCLK (0x00000100u) -#define CM_ALWON_RTC_CLKSTCTRL_CLKACTIVITY_RTC_GCLK_SHIFT (0x8u) - -#define CM_ALWON_RTC_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_RTC_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_L3_FAST_CLKSTCTRL register fields */ - -#define CM_ALWON_L3_FAST_CLKSTCTRL_CLKACTIVITY_FAST_GCLK (0x00000100u) -#define CM_ALWON_L3_FAST_CLKSTCTRL_CLKACTIVITY_FAST_GCLK_SHIFT (0x8u) - -#define CM_ALWON_L3_FAST_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define CM_ALWON_L3_FAST_CLKSTCTRL_CLKTRCTRL_SHIFT (0x0u) - -/** @brief CM_ALWON_MCASP0_CLKCTRL register fields */ - -#define CM_ALWON_MCASP0_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MCASP0_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MCASP0_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MCASP0_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_MCASP1_CLKCTRL register fields */ - -#define CM_ALWON_MCASP1_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MCASP1_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MCASP1_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MCASP1_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_MCASP2_CLKCTRL register fields */ - -#define CM_ALWON_MCASP2_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MCASP2_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MCASP2_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MCASP2_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_MCBSP_CLKCTRL register fields */ - -#define CM_ALWON_MCBSP_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MCBSP_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MCBSP_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MCBSP_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_UART_0_CLKCTRL register fields */ - -#define CM_ALWON_UART_0_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_UART_0_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_UART_0_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_UART_0_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_UART_1_CLKCTRL register fields */ - -#define CM_ALWON_UART_1_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_UART_1_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_UART_1_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_UART_1_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_UART_2_CLKCTRL register fields */ - -#define CM_ALWON_UART_2_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_UART_2_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_UART_2_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_UART_2_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_GPIO_0_CLKCTRL register fields */ - -#define CM_ALWON_GPIO_0_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_GPIO_0_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_GPIO_0_CLKCTRL_OPTFCLKEN_DBCLK (0x00000100u) -#define CM_ALWON_GPIO_0_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT (0x8u) - -#define CM_ALWON_GPIO_0_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_GPIO_0_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_GPIO_1_CLKCTRL register fields */ - -#define CM_ALWON_GPIO_1_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_GPIO_1_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_GPIO_1_CLKCTRL_OPTFCLKEN_DBCLK (0x00000100u) -#define CM_ALWON_GPIO_1_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT (0x8u) - -#define CM_ALWON_GPIO_1_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_GPIO_1_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_I2C_0_CLKCTRL register fields */ - -#define CM_ALWON_I2C_0_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_I2C_0_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_I2C_0_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_I2C_0_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_I2C_1_CLKCTRL register fields */ - -#define CM_ALWON_I2C_1_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_I2C_1_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_I2C_1_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_I2C_1_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_MCASP_3_4_5_CLKCTRL register fields */ - -#define CM_ALWON_MCASP_3_4_5_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MCASP_3_4_5_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MCASP_3_4_5_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MCASP_3_4_5_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_ATL_CLKCTRL register fields */ - -#define CM_ALWON_ATL_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_ATL_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_ATL_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_ATL_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_MLB_CLKCTRL register fields */ - -#define CM_ALWON_MLB_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MLB_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MLB_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MLB_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_PATA_CLKCTRL register fields */ - -#define CM_ALWON_PATA_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_PATA_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_PATA_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_PATA_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_TIMER_4_CLKCTRL register fields */ - -#define CM_ALWON_TIMER_4_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_TIMER_4_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_TIMER_4_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_TIMER_4_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_UART_3_CLKCTRL register fields */ - -#define CM_ALWON_UART_3_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_UART_3_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_UART_3_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_UART_3_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_UART_4_CLKCTRL register fields */ - -#define CM_ALWON_UART_4_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_UART_4_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_UART_4_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_UART_4_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_UART_5_CLKCTRL register fields */ - -#define CM_ALWON_UART_5_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_UART_5_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_UART_5_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_UART_5_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_WDTIMER_CLKCTRL register fields */ - -#define CM_ALWON_WDTIMER_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_WDTIMER_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_WDTIMER_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_WDTIMER_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_SPI_CLKCTRL register fields */ - -#define CM_ALWON_SPI_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_SPI_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_SPI_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_SPI_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_MAILBOX_CLKCTRL register fields */ - -#define CM_ALWON_MAILBOX_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MAILBOX_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MAILBOX_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MAILBOX_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_SPINBOX_CLKCTRL register fields */ - -#define CM_ALWON_SPINBOX_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_SPINBOX_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_SPINBOX_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_SPINBOX_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_MMUDATA_CLKCTRL register fields */ - -#define CM_ALWON_MMUDATA_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MMUDATA_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MMUDATA_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MMUDATA_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_MMUCFG_CLKCTRL register fields */ - -#define CM_ALWON_MMUCFG_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MMUCFG_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MMUCFG_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MMUCFG_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_SDIO_CLKCTRL register fields */ - -#define CM_ALWON_SDIO_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_SDIO_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_SDIO_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_SDIO_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_OCMC_0_CLKCTRL register fields */ - -#define CM_ALWON_OCMC_0_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_OCMC_0_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_OCMC_0_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_OCMC_0_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_VCP_CLKCTRL register fields */ - -#define CM_ALWON_VCP_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_VCP_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_VCP_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_VCP_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_SMARTCARD_0_CLKCTRL register fields */ - -#define CM_ALWON_SMARTCARD_0_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_SMARTCARD_0_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_SMARTCARD_0_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_SMARTCARD_0_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_SMARTCARD_1_CLKCTRL register fields */ - -#define CM_ALWON_SMARTCARD_1_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_SMARTCARD_1_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_SMARTCARD_1_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_SMARTCARD_1_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_CONTROL_CLKCTRL register fields */ - -#define CM_ALWON_CONTROL_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_CONTROL_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_CONTROL_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_CONTROL_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_SECSS_CLKCTRL register fields */ - -#define CM_ALWON_SECSS_CLKCTRL_STBYST (0x00040000u) -#define CM_ALWON_SECSS_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_ALWON_SECSS_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_SECSS_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_SECSS_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_SECSS_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_GPMC_CLKCTRL register fields */ - -#define CM_ALWON_GPMC_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_GPMC_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_GPMC_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_GPMC_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_ETHERNET_0_CLKCTRL register fields */ - -#define CM_ALWON_ETHERNET_0_CLKCTRL_STBYST (0x00040000u) -#define CM_ALWON_ETHERNET_0_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_ALWON_ETHERNET_0_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_ETHERNET_0_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_ETHERNET_0_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_ETHERNET_0_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_MPU_CLKCTRL register fields */ - -#define CM_ALWON_MPU_CLKCTRL_STBYST (0x00040000u) -#define CM_ALWON_MPU_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_ALWON_MPU_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MPU_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MPU_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MPU_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_DEBUGSS_CLKCTRL register fields */ - -#define CM_ALWON_DEBUGSS_CLKCTRL_STM_PMD_CLKDIVSEL (0x38000000u) -#define CM_ALWON_DEBUGSS_CLKCTRL_STM_PMD_CLKDIVSEL_SHIFT (0x1Bu) - -#define CM_ALWON_DEBUGSS_CLKCTRL_TRC_PMD_CLKDIVSEL (0x07000000u) -#define CM_ALWON_DEBUGSS_CLKCTRL_TRC_PMD_CLKDIVSEL_SHIFT (0x18u) - -#define CM_ALWON_DEBUGSS_CLKCTRL_STM_PMD_CLKSEL (0x00C00000u) -#define CM_ALWON_DEBUGSS_CLKCTRL_STM_PMD_CLKSEL_SHIFT (0x16u) - -#define CM_ALWON_DEBUGSS_CLKCTRL_TRC_PMD_CLKSEL (0x00300000u) -#define CM_ALWON_DEBUGSS_CLKCTRL_TRC_PMD_CLKSEL_SHIFT (0x14u) - -#define CM_ALWON_DEBUGSS_CLKCTRL_STBYST (0x00040000u) -#define CM_ALWON_DEBUGSS_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_ALWON_DEBUGSS_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_DEBUGSS_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_DEBUGSS_CLKCTRL_OPTCLK_DEBUG_CLKA (0x00000200u) -#define CM_ALWON_DEBUGSS_CLKCTRL_OPTCLK_DEBUG_CLKA_SHIFT (0x9u) - -#define CM_ALWON_DEBUGSS_CLKCTRL_OPTCLK_DEBUG_SYSCLK (0x00000100u) -#define CM_ALWON_DEBUGSS_CLKCTRL_OPTCLK_DEBUG_SYSCLK_SHIFT (0x8u) - -#define CM_ALWON_DEBUGSS_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_DEBUGSS_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_L3_CLKCTRL register fields */ - -#define CM_ALWON_L3_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_L3_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_L3_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_L3_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_L4HS_CLKCTRL register fields */ - -#define CM_ALWON_L4HS_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_L4HS_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_L4HS_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_L4HS_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_L4LS_CLKCTRL register fields */ - -#define CM_ALWON_L4LS_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_L4LS_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_L4LS_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_L4LS_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_RTC_CLKCTRL register fields */ - -#define CM_ALWON_RTC_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_RTC_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_RTC_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_RTC_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_TPCC_CLKCTRL register fields */ - -#define CM_ALWON_TPCC_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_TPCC_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_TPCC_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_TPCC_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_TPTC0_CLKCTRL register fields */ - -#define CM_ALWON_TPTC0_CLKCTRL_STBYST (0x00040000u) -#define CM_ALWON_TPTC0_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_ALWON_TPTC0_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_TPTC0_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_TPTC0_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_TPTC0_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_TPTC1_CLKCTRL register fields */ - -#define CM_ALWON_TPTC1_CLKCTRL_STBYST (0x00040000u) -#define CM_ALWON_TPTC1_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_ALWON_TPTC1_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_TPTC1_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_TPTC1_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_TPTC1_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_TPTC2_CLKCTRL register fields */ - -#define CM_ALWON_TPTC2_CLKCTRL_STBYST (0x00040000u) -#define CM_ALWON_TPTC2_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_ALWON_TPTC2_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_TPTC2_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_TPTC2_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_TPTC2_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_TPTC3_CLKCTRL register fields */ - -#define CM_ALWON_TPTC3_CLKCTRL_STBYST (0x00040000u) -#define CM_ALWON_TPTC3_CLKCTRL_STBYST_SHIFT (0x12u) - -#define CM_ALWON_TPTC3_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_TPTC3_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_TPTC3_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_TPTC3_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_SR_0_CLKCTRL register fields */ - -#define CM_ALWON_SR_0_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_SR_0_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_SR_0_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_SR_0_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_SR_1_CLKCTRL register fields */ - -#define CM_ALWON_SR_1_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_SR_1_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_SR_1_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_SR_1_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_SR_2_CLKCTRL register fields */ - -#define CM_ALWON_SR_2_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_SR_2_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_SR_2_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_SR_2_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_SR_3_CLKCTRL register fields */ - -#define CM_ALWON_SR_3_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_SR_3_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_SR_3_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_SR_3_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_DCAN_0_1_CLKCTRL register fields */ - -#define CM_ALWON_DCAN_0_1_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_DCAN_0_1_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_DCAN_0_1_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_DCAN_0_1_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_MMCHS_0_CLKCTRL register fields */ - -#define CM_ALWON_MMCHS_0_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MMCHS_0_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MMCHS_0_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MMCHS_0_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_MMCHS_1_CLKCTRL register fields */ - -#define CM_ALWON_MMCHS_1_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MMCHS_1_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MMCHS_1_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MMCHS_1_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_MMCHS_2_CLKCTRL register fields */ - -#define CM_ALWON_MMCHS_2_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_MMCHS_2_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_MMCHS_2_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_MMCHS_2_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief CM_ALWON_CUST_EFUSE_CLKCTRL register fields */ - -#define CM_ALWON_CUST_EFUSE_CLKCTRL_IDLEST (0x00030000u) -#define CM_ALWON_CUST_EFUSE_CLKCTRL_IDLEST_SHIFT (0x10u) - -#define CM_ALWON_CUST_EFUSE_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_ALWON_CUST_EFUSE_CLKCTRL_MODULEMODE_SHIFT (0x0u) - -/** @brief PRM_ALWON_RSTST register fields */ - -#define PRM_ALWON_RSTST_ICECRUSHER_SEC_M3_RST (0x00000080u) -#define PRM_ALWON_RSTST_ICECRUSHER_SEC_M3_RST_SHIFT (0x7u) - -#define PRM_ALWON_RSTST_ICECRUSHER_MPU_RST (0x00000040u) -#define PRM_ALWON_RSTST_ICECRUSHER_MPU_RST_SHIFT (0x6u) - -#define PRM_ALWON_RSTST_EMULATION_MPU_RST (0x00000020u) -#define PRM_ALWON_RSTST_EMULATION_MPU_RST_SHIFT (0x5u) - -#define PRM_ALWON_RSTST_EMULATION_SEC_M3_RST (0x00000010u) -#define PRM_ALWON_RSTST_EMULATION_SEC_M3_RST_SHIFT (0x4u) - -/** @brief Common CLKCTRL register fields and tokens */ - -#define CM_X_CLKCTRL_MODULEMODE (0x00000003u) -#define CM_X_CLKCTRL_MODULEMODE_SHIFT (0x0u) -#define CM_X_CLKCTRL_MODULEMODE_DISABLE (0x0u) -#define CM_X_CLKCTRL_MODULEMODE_ENABLE (0x2u) - -#define CM_X_CLKCTRL_IDLEST (0x00030000u) -#define CM_X_CLKCTRL_IDLEST_SHIFT (0x10u) -#define CM_X_CLKCTRL_IDLEST_FUNC (0x0u) -#define CM_X_CLKCTRL_IDLEST_TRANS (0x1u) -#define CM_X_CLKCTRL_IDLEST_IDLE (0x2u) -#define CM_X_CLKCTRL_IDLEST_DISABLE (0x3u) - -#define CM_X_CLKCTRL_STBYST (0x00040000u) -#define CM_X_CLKCTRL_STBYST_SHIFT (0x12u) -#define CM_X_CLKCTRL_STBYST_FUNC (0x0u) -#define CM_X_CLKCTRL_STBYST_STANDBY (0x1u) - -#define CM_X_CLKCTRL_OPTFCLKEN_DBCLK (0x00000100u) -#define CM_X_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT (0x8u) -#define CM_X_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_DIS (0x0u) -#define CM_X_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN (0x1u) - -#ifdef __cplusplus -} -#endif - -#endif /* _HW_PRCM_C6A811X_H_ */ diff --git a/lib/tiam1808/tiam1808/hw/hw_psc_C6748.h b/lib/tiam1808/tiam1808/hw/hw_psc_C6748.h deleted file mode 100644 index 18675e1e5..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_psc_C6748.h +++ /dev/null @@ -1,285 +0,0 @@ -/** - * \file hw_psc_C6748.h - * - * \brief Hardware registers and fields for PSC module - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _HW_PSC_H_ -#define _HW_PSC_H_ - -/* NOTE1 - * The actual number of MDCTL and MDSTAT register depend on number of - * LPSC modules in a PSC. The number of MDCTL/MDSTAT registers defined - * here would be a superset - * e.g. PSC0 has 16 MDCTL/MDSTAT register, PSC1 has 32 MDCTL/MDSTAT - * registers */ - - -/* NOTE2 - * Please refer to the device specific PSC user guide to see what - * register bit fields apply to individual registers - * e.g. For PSC0 MERRPR0 bits 14,15 exist but for PSC1 MERRPR0 - * these bits are RESERVED */ - -typedef enum { - HW_PSC_CC0 = 0, - HW_PSC_TC0 = 1, - HW_PSC_TC1 = 2, - HW_PSC_EMIFA = 3, - HW_PSC_SPI0 = 4, - HW_PSC_MMCSD0 = 5, - HW_PSC_AINTC = 6, - HW_PSC_ARM_RAMROM = 7, - HW_PSC_UART0 = 9, - HW_PSC_SCR0_SS = 10, - HW_PSC_SCR1_SS = 11, - HW_PSC_SCR2_SS = 12, - HW_PSC_PRU = 13, - HW_PSC_ARM = 14, - HW_PSC_DSP = 15 - -} Psc0Peripheral; - -typedef enum { - HW_PSC_CC1 = 0, - HW_PSC_USB0 = 1, - HW_PSC_USB1 = 2, - HW_PSC_GPIO = 3, - HW_PSC_UHPI = 4, - HW_PSC_EMAC = 5, - HW_PSC_DDR2_MDDR = 6, - HW_PSC_MCASP0 = 7, - HW_PSC_SATA = 8, - HW_PSC_VPIF = 9, - HW_PSC_SPI1 = 10, - HW_PSC_I2C1 = 11, - HW_PSC_UART1 = 12, - HW_PSC_UART2 = 13, - HW_PSC_MCBSP0 = 14, - HW_PSC_MCBSP1 = 15, - HW_PSC_LCDC = 16, - HW_PSC_EHRPWM = 17, - HW_PSC_MMCSD1 = 18, - HW_PSC_UPP = 19, - HW_PSC_ECAP0_1_2 = 20, - HW_PSC_TC2 = 21, - HW_PSC_SCRF0_SS = 24, - HW_PSC_SCRF1_SS = 25, - HW_PSC_SCRF2_SS = 26, - HW_PSC_SCRF6_SS = 27, - HW_PSC_SCRF7_SS = 28, - HW_PSC_SCRF8_SS = 29, - HW_PSC_BR_F7 = 30, - HW_PSC_SHRAM = 31 -} Psc1Peripheral; - -#define PSC_POWERDOMAIN_ALWAYS_ON 0 -#define PSC_POWERDOMAIN_PD_DSP 1 - -#define PSC_REVID (0x0) -#define PSC_INTEVAL (0x18) -#define PSC_MERRPR0 (0x40) -#define PSC_MERRCR0 (0x50) -#define PSC_PERRPR (0x60) -#define PSC_PERRCR (0x68) -#define PSC_PTCMD (0x120) -#define PSC_PTSTAT (0x128) -#define PSC_PDSTAT0 (0x200) -#define PSC_PDSTAT1 (0x204) -#define PSC_PDCTL0 (0x300) -#define PSC_PDCTL1 (0x304) -#define PSC_PDCFG0 (0x400) -#define PSC_PDCFG1 (0x404) -#define PSC_MDSTAT(n) (0x800 + (n * 4)) -#define PSC_MDCTL(n) (0xA00 + (n * 4)) - -/****************************************************************************** -** FIELD DEFINITION MACROS -******************************************************************************/ - -/* REVID */ - -#define PSC_REVID_REV (0xFFFFFFFFu) -#define PSC_REVID_REV_SHIFT (0x00000000u) - -/* INTEVAL */ - -#define PSC_INTEVAL_ALLEV (0x00000001u) -#define PSC_INTEVAL_ALLEV_SHIFT (0x00000000u) - -/* MERRPR0 */ -#define PSC_MERRPR0_M15 (0x0000C000u) -#define PSC_MERRPR0_M15_SHIFT (0x0000000Eu) -#define PSC_MERRPR0_M14 (0x00006000u) -#define PSC_MERRPR0_M14_SHIFT (0x0000000Du) - -/* MERRCR0 */ -#define PSC_MERRCR0_M15 (0x0000C000u) -#define PSC_MERRCR0_M15_SHIFT (0x0000000Eu) -#define PSC_MERRCR0_M14 (0x00006000u) -#define PSC_MERRCR0_M14_SHIFT (0x0000000Du) - -/* PERRPR */ -#define PSC_PERRPR_P1 (0x00000002u) -#define PSC_PERRPR_P1_SHIFT (0x00000001u) -#define PSC_PERRPR_P0 (0x00000001u) -#define PSC_PERRPR_P0_SHIFT (0x00000000u) - -/* PERRCR */ -#define PSC_PERRCR_P1 (0x00000002u) -#define PSC_PERRCR_P1_SHIFT (0x00000001u) -#define PSC_PERRCR_P0 (0x00000001u) -#define PSC_PERRCR_P0_SHIFT (0x00000000u) - -/* PTCMD */ -#define PSC_PTCMD_GO1 (0x00000002u) -#define PSC_PTCMD_GO1_SHIFT (0x00000001u) -#define PSC_PTCMD_GO0 (0x00000001u) -#define PSC_PTCMD_GO0_SHIFT (0x00000000u) - -/* PTSTAT */ -#define PSC_PTSTAT_GOSTAT1 (0x00000002u) -#define PSC_PTSTAT_GOSTAT1_SHIFT (0x00000001u) -#define PSC_PTSTAT_GOSTAT0 (0x00000001u) -#define PSC_PTSTAT_GOSTAT0_SHIFT (0x00000000u) - -/* PDSTAT0 */ -#define PSC_PDSTAT0_EMUIHB (0x00000800u) -#define PSC_PDSTAT0_EMUIHB_SHIFT (0x0000000Bu) -#define PSC_PDSTAT0_STATE (0x0000001Fu) -#define PSC_PDSTAT0_STATE_SHIFT (0x00000000u) - -/* PDSTAT1 */ -#define PSC_PDSTAT1_EMUIHB (0x00000800u) -#define PSC_PDSTAT1_EMUIHB_SHIFT (0x0000000Bu) -#define PSC_PDSTAT1_STATE (0x0000001Fu) -#define PSC_PDSTAT1_STATE_SHIFT (0x00000000u) - -/* PDCTL0 */ -#define PSC_PDCTL0_WAKECNT (0x00FF0000u) -#define PSC_PDCTL0_WAKECNT_SHIFT (0x00000010u) -#define PSC_PDCTL0_PDMODE (0x0000F000u) -#define PSC_PDCTL0_PDMODE_SHIFT (0x0000000Cu) -#define PSC_PDCTL0_EMUIHBIE (0x00000200u) -#define PSC_PDCTL0_EMUIHBIE_SHIFT (0x00000009u) -#define PSC_PDCTL0_NEXT (0x00000001u) -#define PSC_PDCTL0_NEXT_SHIFT (0x00000000u) - -/* PDCTL1 */ -#define PSC_PDCTL1_WAKECNT (0x00FF0000u) -#define PSC_PDCTL1_WAKECNT_SHIFT (0x00000010u) -#define PSC_PDCTL1_PDMODE (0x0000F000u) -#define PSC_PDCTL1_PDMODE_SHIFT (0x0000000Cu) -/*----PDMODE Tokens----*/ -#define PSC_PDCTL1_PDMODE_OFF (0x00000000u) -#define PSC_PDCTL1_PDMODE_RAM_OFF (0x00000008u) -#define PSC_PDCTL1_PDMODE_DEEP_SLEEP (0x00000009u) -#define PSC_PDCTL1_PDMODE_LIGHT_SLEEP (0x0000000Au) -#define PSC_PDCTL1_PDMODE_RETENTION (0x0000000Bu) -#define PSC_PDCTL1_PDMODE_ON (0x0000000Fu) - -#define PSC_PDCTL1_EMUIHBIE (0x00000200u) -#define PSC_PDCTL1_EMUIHBIE_SHIFT (0x00000009u) -#define PSC_PDCTL1_NEXT (0x00000001u) -#define PSC_PDCTL1_NEXT_SHIFT (0x00000000u) - -/* PDCFG0 */ -#define PSC_PDCFG0_PDLOCK (0x00000008u) -#define PSC_PDCFG0_PDLOCK_SHIFT (0x00000003u) -#define PSC_PDCFG0_ICEPICK (0x00000004u) -#define PSC_PDCFG0_ICEPICK_SHIFT (0x00000002u) -#define PSC_PDCFG0_RAM_PSM (0x00000002u) -#define PSC_PDCFG0_RAM_PSM_SHIFT (0x00000001u) -#define PSC_PDCFG0_ALWAYSON (0x00000001u) -#define PSC_PDCFG0_ALWAYSON_SHIFT (0x00000000u) - -/* PDCFG1 */ -#define PSC_PDCFG1_PDLOCK (0x00000008u) -#define PSC_PDCFG1_PDLOCK_SHIFT (0x00000003u) -#define PSC_PDCFG1_ICEPICK (0x00000004u) -#define PSC_PDCFG1_ICEPICK_SHIFT (0x00000002u) -#define PSC_PDCFG1_RAM_PSM (0x00000002u) -#define PSC_PDCFG1_RAM_PSM_SHIFT (0x00000001u) -#define PSC_PDCFG1_ALWAYSON (0x00000001u) -#define PSC_PDCFG1_ALWAYSON_SHIFT (0x00000000u) - -/* MDSTAT */ -#define PSC_MDSTAT_EMUIHB (0x00020000u) -#define PSC_MDSTAT_EMUIHB_SHIFT (0x00000011u) -#define PSC_MDSTAT_EMURST (0x00010000u) -#define PSC_MDSTAT_EMURST_SHIFT (0x00000010u) -#define PSC_MDSTAT_MCKOUT (0x00001000u) -#define PSC_MDSTAT_MCKOUT_SHIFT (0x0000000Cu) -#define PSC_MDSTAT_MRSTDONE (0x00000800u) -#define PSC_MDSTAT_MRSTDONE_SHIFT (0x0000000Bu) -#define PSC_MDSTAT_MRST (0x00000400u) -#define PSC_MDSTAT_MRST_SHIFT (0x0000000Au) -#define PSC_MDSTAT_LRSTDONE (0x00000200u) -#define PSC_MDSTAT_LRSTDONE_SHIFT (0x00000009u) -#define PSC_MDSTAT_LRST (0x00000100u) -#define PSC_MDSTAT_LRST_SHIFT (0x00000008u) -#define PSC_MDSTAT_STATE (0x0000003Fu) -#define PSC_MDSTAT_STATE_SHIFT (0x00000000u) -/*----STATE Tokens----*/ -#define PSC_MDSTAT_STATE_SWRSTDISABLE (0x00000000u) -#define PSC_MDSTAT_STATE_SYNCRST (0x00000001u) -#define PSC_MDSTAT_STATE_AUTOSLEEP (0x00000004u) -#define PSC_MDSTAT_STATE_AUTOWAKE (0x00000005u) - -/* MDCTL */ -#define PSC_MDCTL_FORCE (0x80000000u) -#define PSC_MDCTL_FORCE_SHIFT (0x0000001Fu) - -#define PSC_MDCTL_EMUIHBIE (0x00000400u) -#define PSC_MDCTL_EMUIHBIE_SHIFT (0x0000000Au) - -#define PSC_MDCTL_EMURSTIE (0x00000200u) -#define PSC_MDCTL_EMURSTIE_SHIFT (0x00000009u) - -#define PSC_MDCTL_LRST (0x00000100u) -#define PSC_MDCTL_LRST_SHIFT (0x00000008u) -#define PSC_MDCTL_NEXT (0x0000001Fu) -#define PSC_MDCTL_NEXT_SHIFT (0x00000000u) -/*----NEXT Tokens----*/ -#define PSC_MDCTL_NEXT_SWRSTDISABLE (0x00000000u) -#define PSC_MDCTL_NEXT_SYNCRST (0x00000001u) -#define PSC_MDCTL_NEXT_DISABLE (0x00000002u) -#define PSC_MDCTL_NEXT_ENABLE (0x00000003u) -#define PSC_MDCTL_NEXT_AUTOWAKE (0x00000005u) - -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_psc_OMAPL138.h b/lib/tiam1808/tiam1808/hw/hw_psc_OMAPL138.h deleted file mode 100644 index 337157142..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_psc_OMAPL138.h +++ /dev/null @@ -1,285 +0,0 @@ -/** - * \file hw_psc_OMAPL138.h - * - * \brief Hardware definitions for OMAPL138 - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _HW_PSC_H_ -#define _HW_PSC_H_ - -/* NOTE1 - * The actual number of MDCTL and MDSTAT register depend on number of - * LPSC modules in a PSC. The number of MDCTL/MDSTAT registers defined - * here would be a superset - * e.g. PSC0 has 16 MDCTL/MDSTAT register, PSC1 has 32 MDCTL/MDSTAT - * registers */ - - -/* NOTE2 - * Please refer to the device specific PSC user guide to see what - * register bit fields apply to individual registers - * e.g. For PSC0 MERRPR0 bits 14,15 exist but for PSC1 MERRPR0 - * these bits are RESERVED */ - -typedef enum { - HW_PSC_CC0 = 0, - HW_PSC_TC0 = 1, - HW_PSC_TC1 = 2, - HW_PSC_EMIFA = 3, - HW_PSC_SPI0 = 4, - HW_PSC_MMCSD0 = 5, - HW_PSC_AINTC = 6, - HW_PSC_ARM_RAMROM = 7, - HW_PSC_UART0 = 9, - HW_PSC_SCR0_SS = 10, - HW_PSC_SCR1_SS = 11, - HW_PSC_SCR2_SS = 12, - HW_PSC_PRU = 13, - HW_PSC_ARM = 14, - HW_PSC_DSP = 15 - -} Psc0Peripheral; - -typedef enum { - HW_PSC_CC1 = 0, - HW_PSC_USB0 = 1, - HW_PSC_USB1 = 2, - HW_PSC_GPIO = 3, - HW_PSC_UHPI = 4, - HW_PSC_EMAC = 5, - HW_PSC_DDR2_MDDR = 6, - HW_PSC_MCASP0 = 7, - HW_PSC_SATA = 8, - HW_PSC_VPIF = 9, - HW_PSC_SPI1 = 10, - HW_PSC_I2C1 = 11, - HW_PSC_UART1 = 12, - HW_PSC_UART2 = 13, - HW_PSC_MCBSP0 = 14, - HW_PSC_MCBSP1 = 15, - HW_PSC_LCDC = 16, - HW_PSC_EHRPWM = 17, - HW_PSC_MMCSD1 = 18, - HW_PSC_UPP = 19, - HW_PSC_ECAP0_1_2 = 20, - HW_PSC_TC2 = 21, - HW_PSC_SCRF0_SS = 24, - HW_PSC_SCRF1_SS = 25, - HW_PSC_SCRF2_SS = 26, - HW_PSC_SCRF6_SS = 27, - HW_PSC_SCRF7_SS = 28, - HW_PSC_SCRF8_SS = 29, - HW_PSC_BR_F7 = 30, - HW_PSC_SHRAM = 31 -} Psc1Peripheral; - -#define PSC_POWERDOMAIN_ALWAYS_ON 0 -#define PSC_POWERDOMAIN_PD_DSP 1 - -#define PSC_REVID (0x0) -#define PSC_INTEVAL (0x18) -#define PSC_MERRPR0 (0x40) -#define PSC_MERRCR0 (0x50) -#define PSC_PERRPR (0x60) -#define PSC_PERRCR (0x68) -#define PSC_PTCMD (0x120) -#define PSC_PTSTAT (0x128) -#define PSC_PDSTAT0 (0x200) -#define PSC_PDSTAT1 (0x204) -#define PSC_PDCTL0 (0x300) -#define PSC_PDCTL1 (0x304) -#define PSC_PDCFG0 (0x400) -#define PSC_PDCFG1 (0x404) -#define PSC_MDSTAT(n) (0x800 + (n * 4)) -#define PSC_MDCTL(n) (0xA00 + (n * 4)) - -/**************************************************************************\ -* Field Definition Macros -\**************************************************************************/ - -/* REVID */ - -#define PSC_REVID_REV (0xFFFFFFFFu) -#define PSC_REVID_REV_SHIFT (0x00000000u) - -/* INTEVAL */ - -#define PSC_INTEVAL_ALLEV (0x00000001u) -#define PSC_INTEVAL_ALLEV_SHIFT (0x00000000u) - -/* MERRPR0 */ -#define PSC_MERRPR0_M15 (0x0000C000u) -#define PSC_MERRPR0_M15_SHIFT (0x0000000Eu) -#define PSC_MERRPR0_M14 (0x00006000u) -#define PSC_MERRPR0_M14_SHIFT (0x0000000Du) - -/* MERRCR0 */ -#define PSC_MERRCR0_M15 (0x0000C000u) -#define PSC_MERRCR0_M15_SHIFT (0x0000000Eu) -#define PSC_MERRCR0_M14 (0x00006000u) -#define PSC_MERRCR0_M14_SHIFT (0x0000000Du) - -/* PERRPR */ -#define PSC_PERRPR_P1 (0x00000002u) -#define PSC_PERRPR_P1_SHIFT (0x00000001u) -#define PSC_PERRPR_P0 (0x00000001u) -#define PSC_PERRPR_P0_SHIFT (0x00000000u) - -/* PERRCR */ -#define PSC_PERRCR_P1 (0x00000002u) -#define PSC_PERRCR_P1_SHIFT (0x00000001u) -#define PSC_PERRCR_P0 (0x00000001u) -#define PSC_PERRCR_P0_SHIFT (0x00000000u) - -/* PTCMD */ -#define PSC_PTCMD_GO1 (0x00000002u) -#define PSC_PTCMD_GO1_SHIFT (0x00000001u) -#define PSC_PTCMD_GO0 (0x00000001u) -#define PSC_PTCMD_GO0_SHIFT (0x00000000u) - -/* PTSTAT */ -#define PSC_PTSTAT_GOSTAT1 (0x00000002u) -#define PSC_PTSTAT_GOSTAT1_SHIFT (0x00000001u) -#define PSC_PTSTAT_GOSTAT0 (0x00000001u) -#define PSC_PTSTAT_GOSTAT0_SHIFT (0x00000000u) - -/* PDSTAT0 */ -#define PSC_PDSTAT0_EMUIHB (0x00000800u) -#define PSC_PDSTAT0_EMUIHB_SHIFT (0x0000000Bu) -#define PSC_PDSTAT0_STATE (0x0000001Fu) -#define PSC_PDSTAT0_STATE_SHIFT (0x00000000u) - -/* PDSTAT1 */ -#define PSC_PDSTAT1_EMUIHB (0x00000800u) -#define PSC_PDSTAT1_EMUIHB_SHIFT (0x0000000Bu) -#define PSC_PDSTAT1_STATE (0x0000001Fu) -#define PSC_PDSTAT1_STATE_SHIFT (0x00000000u) - -/* PDCTL0 */ -#define PSC_PDCTL0_WAKECNT (0x00FF0000u) -#define PSC_PDCTL0_WAKECNT_SHIFT (0x00000010u) -#define PSC_PDCTL0_PDMODE (0x0000F000u) -#define PSC_PDCTL0_PDMODE_SHIFT (0x0000000Cu) -#define PSC_PDCTL0_EMUIHBIE (0x00000200u) -#define PSC_PDCTL0_EMUIHBIE_SHIFT (0x00000009u) -#define PSC_PDCTL0_NEXT (0x00000001u) -#define PSC_PDCTL0_NEXT_SHIFT (0x00000000u) - -/* PDCTL1 */ -#define PSC_PDCTL1_WAKECNT (0x00FF0000u) -#define PSC_PDCTL1_WAKECNT_SHIFT (0x00000010u) -#define PSC_PDCTL1_PDMODE (0x0000F000u) -#define PSC_PDCTL1_PDMODE_SHIFT (0x0000000Cu) -/*----PDMODE Tokens----*/ -#define PSC_PDCTL1_PDMODE_OFF (0x00000000u) -#define PSC_PDCTL1_PDMODE_RAM_OFF (0x00000008u) -#define PSC_PDCTL1_PDMODE_DEEP_SLEEP (0x00000009u) -#define PSC_PDCTL1_PDMODE_LIGHT_SLEEP (0x0000000Au) -#define PSC_PDCTL1_PDMODE_RETENTION (0x0000000Bu) -#define PSC_PDCTL1_PDMODE_ON (0x0000000Fu) - -#define PSC_PDCTL1_EMUIHBIE (0x00000200u) -#define PSC_PDCTL1_EMUIHBIE_SHIFT (0x00000009u) -#define PSC_PDCTL1_NEXT (0x00000001u) -#define PSC_PDCTL1_NEXT_SHIFT (0x00000000u) - -/* PDCFG0 */ -#define PSC_PDCFG0_PDLOCK (0x00000008u) -#define PSC_PDCFG0_PDLOCK_SHIFT (0x00000003u) -#define PSC_PDCFG0_ICEPICK (0x00000004u) -#define PSC_PDCFG0_ICEPICK_SHIFT (0x00000002u) -#define PSC_PDCFG0_RAM_PSM (0x00000002u) -#define PSC_PDCFG0_RAM_PSM_SHIFT (0x00000001u) -#define PSC_PDCFG0_ALWAYSON (0x00000001u) -#define PSC_PDCFG0_ALWAYSON_SHIFT (0x00000000u) - -/* PDCFG1 */ -#define PSC_PDCFG1_PDLOCK (0x00000008u) -#define PSC_PDCFG1_PDLOCK_SHIFT (0x00000003u) -#define PSC_PDCFG1_ICEPICK (0x00000004u) -#define PSC_PDCFG1_ICEPICK_SHIFT (0x00000002u) -#define PSC_PDCFG1_RAM_PSM (0x00000002u) -#define PSC_PDCFG1_RAM_PSM_SHIFT (0x00000001u) -#define PSC_PDCFG1_ALWAYSON (0x00000001u) -#define PSC_PDCFG1_ALWAYSON_SHIFT (0x00000000u) - -/* MDSTAT */ -#define PSC_MDSTAT_EMUIHB (0x00020000u) -#define PSC_MDSTAT_EMUIHB_SHIFT (0x00000011u) -#define PSC_MDSTAT_EMURST (0x00010000u) -#define PSC_MDSTAT_EMURST_SHIFT (0x00000010u) -#define PSC_MDSTAT_MCKOUT (0x00001000u) -#define PSC_MDSTAT_MCKOUT_SHIFT (0x0000000Cu) -#define PSC_MDSTAT_MRSTDONE (0x00000800u) -#define PSC_MDSTAT_MRSTDONE_SHIFT (0x0000000Bu) -#define PSC_MDSTAT_MRST (0x00000400u) -#define PSC_MDSTAT_MRST_SHIFT (0x0000000Au) -#define PSC_MDSTAT_LRSTDONE (0x00000200u) -#define PSC_MDSTAT_LRSTDONE_SHIFT (0x00000009u) -#define PSC_MDSTAT_LRST (0x00000100u) -#define PSC_MDSTAT_LRST_SHIFT (0x00000008u) -#define PSC_MDSTAT_STATE (0x0000003Fu) -#define PSC_MDSTAT_STATE_SHIFT (0x00000000u) -/*----STATE Tokens----*/ -#define PSC_MDSTAT_STATE_SWRSTDISABLE (0x00000000u) -#define PSC_MDSTAT_STATE_SYNCRST (0x00000001u) -#define PSC_MDSTAT_STATE_AUTOSLEEP (0x00000004u) -#define PSC_MDSTAT_STATE_AUTOWAKE (0x00000005u) - -/* MDCTL */ -#define PSC_MDCTL_FORCE (0x80000000u) -#define PSC_MDCTL_FORCE_SHIFT (0x0000001Fu) - -#define PSC_MDCTL_EMUIHBIE (0x00000400u) -#define PSC_MDCTL_EMUIHBIE_SHIFT (0x0000000Au) - -#define PSC_MDCTL_EMURSTIE (0x00000200u) -#define PSC_MDCTL_EMURSTIE_SHIFT (0x00000009u) - -#define PSC_MDCTL_LRST (0x00000100u) -#define PSC_MDCTL_LRST_SHIFT (0x00000008u) -#define PSC_MDCTL_NEXT (0x0000001Fu) -#define PSC_MDCTL_NEXT_SHIFT (0x00000000u) -/*----NEXT Tokens----*/ -#define PSC_MDCTL_NEXT_SWRSTDISABLE (0x00000000u) -#define PSC_MDCTL_NEXT_SYNCRST (0x00000001u) -#define PSC_MDCTL_NEXT_DISABLE (0x00000002u) -#define PSC_MDCTL_NEXT_ENABLE (0x00000003u) -#define PSC_MDCTL_NEXT_AUTOWAKE (0x00000005u) - -#endif diff --git a/lib/tiam1808/tiam1808/hw/hw_syscfg0_C6748.h b/lib/tiam1808/tiam1808/hw/hw_syscfg0_C6748.h deleted file mode 100644 index ed1b9393f..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_syscfg0_C6748.h +++ /dev/null @@ -1,2170 +0,0 @@ -/** - * \file hw_syscfg0_C6748.h - * - * \brief Hardware registers and fields for SYSCFG0 module - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _HW_SYSCFG0_H_ -#define _HW_SYSCFG0_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define SYSCFG0_REVID (0x0) -#define SYSCFG0_DIEIDR0 (0x8) -#define SYSCFG0_DIEIDR1 (0xC) -#define SYSCFG0_DIEIDR2 (0x10) -#define SYSCFG0_DIEIDR3 (0x14) -#define SYSCFG0_DEVIDR0 (0x18) -#define SYSCFG0_BOOTCFG (0x20) -#define SYSCFG0_KICK0R (0x38) -#define SYSCFG0_KICK1R (0x3C) -#define SYSCFG0_HOST0CFG (0x40) -#define SYSCFG0_IRAWSTAT (0xE0) -#define SYSCFG0_IENSTAT (0xE4) -#define SYSCFG0_IENSET (0xE8) -#define SYSCFG0_IENCLR (0xEC) -#define SYSCFG0_EOI (0xF0) -#define SYSCFG0_FLTADDRR (0xF4) -#define SYSCFG0_FLTSTAT (0xF8) -#define SYSCFG0_MSTPRI0 (0x110) -#define SYSCFG0_MSTPRI1 (0x114) -#define SYSCFG0_MSTPRI2 (0x118) -#define SYSCFG0_PINMUX(n) (0x120 + (n * 4)) -#define SYSCFG0_SUSPSRC (0x170) -#define SYSCFG0_CHIPSIG (0x174) -#define SYSCFG0_CHIPSIG_CLR (0x178) -#define SYSCFG0_CFGCHIP0 (0x17C) -#define SYSCFG0_CFGCHIP1 (0x180) -#define SYSCFG0_CFGCHIP2 (0x184) -#define SYSCFG0_CFGCHIP3 (0x188) -#define SYSCFG0_CFGCHIP4 (0x18C) - -/****************************************************************************** -** FIELD DEFINITION MACROS -******************************************************************************/ - -/* REVID */ - -#define SYSCFG_REVID_REVID (0xFFFFFFFFu) -#define SYSCFG_REVID_REVID_SHIFT (0x00000000u) - - -/* DIEIDR0 */ - -#define SYSCFG_DIEIDR0_DIEID0 (0xFFFFFFFFu) -#define SYSCFG_DIEIDR0_DIEID0_SHIFT (0x00000000u) - - -/* DIEIDR1 */ - -#define SYSCFG_DIEIDR1_DIEID1 (0xFFFFFFFFu) -#define SYSCFG_DIEIDR1_DIEID1_SHIFT (0x00000000u) - - -/* DIEIDR2 */ - -#define SYSCFG_DIEIDR2_DIEID2 (0xFFFFFFFFu) -#define SYSCFG_DIEIDR2_DIEID2_SHIFT (0x00000000u) - - -/* DIEIDR3 */ - -#define SYSCFG_DIEIDR3_DIEID3 (0xFFFFFFFFu) -#define SYSCFG_DIEIDR3_DIEID3_SHIFT (0x00000000u) - - -/* DEVIDR0 */ - -#define SYSCFG_DEVIDR0_DEVID0 (0xFFFFFFFFu) -#define SYSCFG_DEVIDR0_DEVID0_SHIFT (0x00000000u) - - -/* BOOTCFG */ - - -#define SYSCFG_BOOTCFG_SMARTRFLX (0x0FFF0000u) -#define SYSCFG_BOOTCFG_SMARTRFLX_SHIFT (0x00000010u) - -#define SYSCFG_BOOTCFG_BOOTMODE (0x0000FFFFu) -#define SYSCFG_BOOTCFG_BOOTMODE_SHIFT (0x00000000u) - - -/* CHIPREVIDR */ - - -#define SYSCFG_CHIPREVIDR_CHIPREVID (0x0000003Fu) -#define SYSCFG_CHIPREVIDR_CHIPREVID_SHIFT (0x00000000u) - - -/* KICK0R */ - -#define SYSCFG_KICK0R_KICK0 (0xFFFFFFFFu) -#define SYSCFG_KICK0R_KICK0_SHIFT (0x00000000u) - -/* Unlock/Lock code for KICK0 */ -#define SYSCFG_KICK0R_UNLOCK (0x83E70B13u) - - -/* KICK1R */ - -#define SYSCFG_KICK1R_KICK1 (0xFFFFFFFFu) -#define SYSCFG_KICK1R_KICK1_SHIFT (0x00000000u) - -/* Unlock/Lock code for KICK1 */ -#define SYSCFG_KICK1R_UNLOCK (0x95A4F1E0u) - -/* HOST0CFG */ - -#define SYSCFG_HOST0CFG_BOOTRDY (0x80000000u) -#define SYSCFG_HOST0CFG_BOOTRDY_SHIFT (0x0000001Fu) - - - -/* HOST1CFG */ - -#define SYSCFG_HOST1CFG_BOOTRDY (0x80000000u) -#define SYSCFG_HOST1CFG_BOOTRDY_SHIFT (0x0000001Fu) - - -#define SYSCFG_HOST1CFG_DSP_ISTP_RST_VAL (0x003FFFFFu) -#define SYSCFG_HOST1CFG_DSP_ISTP_RST_VAL_SHIFT (0x00000000u) - - -/* IRAWSTAT */ - - -#define SYSCFG_IRAWSTAT_ADDRERR (0x00000002u) -#define SYSCFG_IRAWSTAT_ADDRERR_SHIFT (0x00000001u) - -#define SYSCFG_IRAWSTAT_PROTERR (0x00000001u) -#define SYSCFG_IRAWSTAT_PROTERR_SHIFT (0x00000000u) - - -/* IENSTAT */ - - -#define SYSCFG_IENSTAT_ADDRERR (0x00000002u) -#define SYSCFG_IENSTAT_ADDRERR_SHIFT (0x00000001u) - -#define SYSCFG_IENSTAT_PROTERR (0x00000001u) -#define SYSCFG_IENSTAT_PROTERR_SHIFT (0x00000000u) - - -/* IENSET */ - - -#define SYSCFG_IENSET_ADDRERR_EN (0x00000002u) -#define SYSCFG_IENSET_ADDRERR_EN_SHIFT (0x00000001u) - -#define SYSCFG_IENSET_PROTERR_EN (0x00000001u) -#define SYSCFG_IENSET_PROTERR_EN_SHIFT (0x00000000u) - - -/* IENCLR */ - - -#define SYSCFG_IENCLR_ADDRERR_CLR (0x00000002u) -#define SYSCFG_IENCLR_ADDRERR_CLR_SHIFT (0x00000001u) - -#define SYSCFG_IENCLR_PROTERR_CLR (0x00000001u) -#define SYSCFG_IENCLR_PROTERR_CLR_SHIFT (0x00000000u) - - -/* EOI */ - - -#define SYSCFG_EOI_EOIVECT (0x000000FFu) -#define SYSCFG_EOI_EOIVECT_SHIFT (0x00000000u) - - -/* FLTADDRR */ - -#define SYSCFG_FLTADDRR_FLTADDR (0xFFFFFFFFu) -#define SYSCFG_FLTADDRR_FLTADDR_SHIFT (0x00000000u) - - -/* FLTSTAT */ - -#define SYSCFG_FLTSTAT_ID (0xFF000000u) -#define SYSCFG_FLTSTAT_ID_SHIFT (0x00000018u) - -#define SYSCFG_FLTSTAT_MSTID (0x00FF0000u) -#define SYSCFG_FLTSTAT_MSTID_SHIFT (0x00000010u) - - -#define SYSCFG_FLTSTAT_PRIVID (0x00001E00u) -#define SYSCFG_FLTSTAT_PRIVID_SHIFT (0x00000009u) - - -#define SYSCFG_FLTSTAT_NOSECACC (0x00000080u) -#define SYSCFG_FLTSTAT_NOSECACC_SHIFT (0x00000007u) - - -#define SYSCFG_FLTSTAT_TYPE (0x0000003Fu) -#define SYSCFG_FLTSTAT_TYPE_SHIFT (0x00000000u) -/*----TYPE Tokens----*/ -#define SYSCFG_FLTSTAT_TYPE_NOFLT (0x00000000u) -#define SYSCFG_FLTSTAT_TYPE_USREXE (0x00000001u) -#define SYSCFG_FLTSTAT_TYPE_USRWR (0x00000002u) -#define SYSCFG_FLTSTAT_TYPE_USRRD (0x00000004u) -#define SYSCFG_FLTSTAT_TYPE_SPREXE (0x00000008u) -#define SYSCFG_FLTSTAT_TYPE_SPRWR (0x00000010u) -#define SYSCFG_FLTSTAT_TYPE_SPRRD (0x00000020u) - - -/* MSTPRI0 */ - - -#define SYSCFG_MSTPRI0_SATA (0x00700000u) -#define SYSCFG_MSTPRI0_SATA_SHIFT (0x00000014u) - - -#define SYSCFG_MSTPRI0_UPP (0x00070000u) -#define SYSCFG_MSTPRI0_UPP_SHIFT (0x00000010u) - - -#define SYSCFG_MSTPRI0_DSP_CFG (0x00007000u) -#define SYSCFG_MSTPRI0_DSP_CFG_SHIFT (0x0000000Cu) - - -#define SYSCFG_MSTPRI0_DSP_MDMA (0x00000700u) -#define SYSCFG_MSTPRI0_DSP_MDMA_SHIFT (0x00000008u) - - -#define SYSCFG_MSTPRI0_ARM_D (0x00000070u) -#define SYSCFG_MSTPRI0_ARM_D_SHIFT (0x00000004u) - - -#define SYSCFG_MSTPRI0_ARM_I (0x00000007u) -#define SYSCFG_MSTPRI0_ARM_I_SHIFT (0x00000000u) - - -/* MSTPRI1 */ - - -#define SYSCFG_MSTPRI1_VPIF_DMA_1 (0x70000000u) -#define SYSCFG_MSTPRI1_VPIF_DMA_1_SHIFT (0x0000001Cu) - - -#define SYSCFG_MSTPRI1_VPIF_DMA_0 (0x07000000u) -#define SYSCFG_MSTPRI1_VPIF_DMA_0_SHIFT (0x00000018u) - - -#define SYSCFG_MSTPRI1_EDMA31TC0 (0x00070000u) -#define SYSCFG_MSTPRI1_EDMA31TC0_SHIFT (0x00000010u) - - -#define SYSCFG_MSTPRI1_EDMA30TC1 (0x00007000u) -#define SYSCFG_MSTPRI1_EDMA30TC1_SHIFT (0x0000000Cu) - - -#define SYSCFG_MSTPRI1_EDMA30TC0 (0x00000700u) -#define SYSCFG_MSTPRI1_EDMA30TC0_SHIFT (0x00000008u) - - -#define SYSCFG_MSTPRI1_PRU1 (0x00000070u) -#define SYSCFG_MSTPRI1_PRU1_SHIFT (0x00000004u) - - -#define SYSCFG_MSTPRI1_PRU0 (0x00000007u) -#define SYSCFG_MSTPRI1_PRU0_SHIFT (0x00000000u) - - -/* MSTPRI2 */ - - -#define SYSCFG_MSTPRI2_LCDC (0x70000000u) -#define SYSCFG_MSTPRI2_LCDC_SHIFT (0x0000001Cu) - - -#define SYSCFG_MSTPRI2_USB1 (0x07000000u) -#define SYSCFG_MSTPRI2_USB1_SHIFT (0x00000018u) - - -#define SYSCFG_MSTPRI2_UHPI (0x00700000u) -#define SYSCFG_MSTPRI2_UHPI_SHIFT (0x00000014u) - - -#define SYSCFG_MSTPRI2_USB0CDMA (0x00007000u) -#define SYSCFG_MSTPRI2_USB0CDMA_SHIFT (0x0000000Cu) - - -#define SYSCFG_MSTPRI2_USB0CFG (0x00000700u) -#define SYSCFG_MSTPRI2_USB0CFG_SHIFT (0x00000008u) - - -#define SYSCFG_MSTPRI2_EMAC (0x00000007u) -#define SYSCFG_MSTPRI2_EMAC_SHIFT (0x00000000u) - - -/* PINMUX0 */ - -#define SYSCFG_PINMUX0_PINMUX0_31_28 (0xF0000000u) -#define SYSCFG_PINMUX0_PINMUX0_31_28_SHIFT (0x0000001Cu) -/*----PINMUX0_31_28 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_31_28_RESERVED1 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_31_28_ALARM (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_31_28_UART2_CTS (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_31_28_GPIO0_8 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_27_24 (0x0F000000u) -#define SYSCFG_PINMUX0_PINMUX0_27_24_SHIFT (0x00000018u) -/*----PINMUX0_27_24 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_27_24_AMUTE0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_27_24_PRU0_R30_16 (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_27_24_UART2_RTS (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_27_24_GPIO0_9 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_23_20 (0x00F00000u) -#define SYSCFG_PINMUX0_PINMUX0_23_20_SHIFT (0x00000014u) -/*----PINMUX0_23_20 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_23_20_AHCLKX0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_23_20_USB_REFCLKIN (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_23_20_UART1_CTS (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_23_20_GPIO0_10 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_19_16 (0x000F0000u) -#define SYSCFG_PINMUX0_PINMUX0_19_16_SHIFT (0x00000010u) -/*----PINMUX0_19_16 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_19_16_AHCLKR0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_19_16_PRU0_R30_18 (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_19_16_UART1_RTS (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_19_16_GPIO0_11 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_15_12 (0x0000F000u) -#define SYSCFG_PINMUX0_PINMUX0_15_12_SHIFT (0x0000000Cu) -/*----PINMUX0_15_12 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_15_12_AFSX0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_15_12_OBSERVE0_LOS (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_15_12_GPIO0_12 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_11_8 (0x00000F00u) -#define SYSCFG_PINMUX0_PINMUX0_11_8_SHIFT (0x00000008u) -/*----PINMUX0_11_8 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_11_8_AFSR0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_11_8_OBSERVE0_SYNC (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_11_8_GPIO0_13 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_7_4 (0x000000F0u) -#define SYSCFG_PINMUX0_PINMUX0_7_4_SHIFT (0x00000004u) -/*----PINMUX0_7_4 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_7_4_ACLKX0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_7_4_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_7_4_PRU0_R30_19 (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_7_4_GPIO0_14 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX0_PINMUX0_3_0_SHIFT (0x00000000u) -/*----PINMUX0_3_0 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_3_0_ACLKR0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_3_0_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_3_0_PRU0_R30_20 (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_3_0_GPIO0_15 (0x00000008u) - - -/* PINMUX1 */ - -#define SYSCFG_PINMUX1_PINMUX1_31_28 (0xF0000000u) -#define SYSCFG_PINMUX1_PINMUX1_31_28_SHIFT (0x0000001Cu) -/*----PINMUX1_31_28 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_31_28_AXR0_8 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_31_28_CLKS1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_31_28_ECAP1 (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_31_28_GPIO0_0 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_27_24 (0x0F000000u) -#define SYSCFG_PINMUX1_PINMUX1_27_24_SHIFT (0x00000018u) -/*----PINMUX1_27_24 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_27_24_AXR0_9 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_27_24_DX1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_27_24_OBSERVE0_PHY_STATE2 (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_27_24_GPIO0_1 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_23_20 (0x00F00000u) -#define SYSCFG_PINMUX1_PINMUX1_23_20_SHIFT (0x00000014u) -/*----PINMUX1_23_20 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_23_20_AXR0_10 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_23_20_DR1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_23_20_OBSERVE0_PHY_STATE1 (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_23_20_GPIO0_2 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_19_16 (0x000F0000u) -#define SYSCFG_PINMUX1_PINMUX1_19_16_SHIFT (0x00000010u) -/*----PINMUX1_19_16 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_19_16_AXR0_11 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_19_16_FSX1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_19_16_OBSERVE0_PHY_STATE0 (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_19_16_GPIO0_3 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_15_12 (0x0000F000u) -#define SYSCFG_PINMUX1_PINMUX1_15_12_SHIFT (0x0000000Cu) -/*----PINMUX1_15_12 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_15_12_AXR0_12 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_15_12_FSR1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_15_12_OBSERVE0_PHY_READY (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_15_12_GPIO0_4 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_11_8 (0x00000F00u) -#define SYSCFG_PINMUX1_PINMUX1_11_8_SHIFT (0x00000008u) -/*----PINMUX1_11_8 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_11_8_AXR0_13 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_11_8_CLKX1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_11_8_OBSERVE0_COMINIT (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_11_8_GPIO0_5 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_7_4 (0x000000F0u) -#define SYSCFG_PINMUX1_PINMUX1_7_4_SHIFT (0x00000004u) -/*----PINMUX1_7_4 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_7_4_AXR0_14 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_7_4_CLKR1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_7_4_OBSERVE0_COMWAKE (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_7_4_GPIO0_6 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX1_PINMUX1_3_0_SHIFT (0x00000000u) -/*----PINMUX1_3_0 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_3_0_AXR0_15 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_3_0_EPWM0TZ0 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_3_0_ECAP2 (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_3_0_GPIO0_7 (0x00000008u) - - -/* PINMUX2 */ - -#define SYSCFG_PINMUX2_PINMUX2_31_28 (0xF0000000u) -#define SYSCFG_PINMUX2_PINMUX2_31_28_SHIFT (0x0000001Cu) -/*----PINMUX2_31_28 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_31_28_AXR0_0 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_31_28_ECAP0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_31_28_GPIO8_7 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_31_28_MII_TXD0 (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_27_24 (0x0F000000u) -#define SYSCFG_PINMUX2_PINMUX2_27_24_SHIFT (0x00000018u) -/*----PINMUX2_27_24 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_27_24_AXR0_1 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_27_24_DX0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_27_24_GPIO1_9 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_27_24_MII_TXD1 (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_23_20 (0x00F00000u) -#define SYSCFG_PINMUX2_PINMUX2_23_20_SHIFT (0x00000014u) -/*----PINMUX2_23_20 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_23_20_AXR0_2 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_23_20_DR0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_23_20_GPIO1_10 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_23_20_MII_TXD2 (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_19_16 (0x000F0000u) -#define SYSCFG_PINMUX2_PINMUX2_19_16_SHIFT (0x00000010u) -/*----PINMUX2_19_16 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_19_16_AXR0_3 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_19_16_FSX0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_19_16_GPIO1_11 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_19_16_MII_TXD3 (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_15_12 (0x0000F000u) -#define SYSCFG_PINMUX2_PINMUX2_15_12_SHIFT (0x0000000Cu) -/*----PINMUX2_15_12 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_15_12_AXR0_4 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_15_12_FSR0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_15_12_GPIO1_12 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_15_12_MII_COL (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_11_8 (0x00000F00u) -#define SYSCFG_PINMUX2_PINMUX2_11_8_SHIFT (0x00000008u) -/*----PINMUX2_11_8 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_11_8_AXR0_5 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_11_8_CLKX0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_11_8_GPIO1_13 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_11_8_MII_TXCLK (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_7_4 (0x000000F0u) -#define SYSCFG_PINMUX2_PINMUX2_7_4_SHIFT (0x00000004u) -/*----PINMUX2_7_4 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_7_4_AXR0_6 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_7_4_CLKR0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_7_4_GPIO1_14 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_7_4_MII_TXEN (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX2_PINMUX2_3_0_SHIFT (0x00000000u) -/*----PINMUX2_3_0 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_3_0_AXR0_7 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_3_0_EPWM1TZ0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_3_0_PRU0_R30_17 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_3_0_GPIO1_15 (0x00000008u) - - -/* PINMUX3 */ - -#define SYSCFG_PINMUX3_PINMUX3_31_28 (0xF0000000u) -#define SYSCFG_PINMUX3_PINMUX3_31_28_SHIFT (0x0000001Cu) -/*----PINMUX3_31_28 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_31_28_NSPI0_SCS2 (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_31_28_UART0_RTS (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_31_28_GPIO8_1 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_31_28_MII_RXD0 (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_27_24 (0x0F000000u) -#define SYSCFG_PINMUX3_PINMUX3_27_24_SHIFT (0x00000018u) -/*----PINMUX3_27_24 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_27_24_NSPI0_SCS3 (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_27_24_UART0_CTS (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_27_24_GPIO8_2 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_27_24_MII_RXD1 (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_23_20 (0x00F00000u) -#define SYSCFG_PINMUX3_PINMUX3_23_20_SHIFT (0x00000014u) -/*----PINMUX3_23_20 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_23_20_NSPI0_SCS4 (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_23_20_UART0_TXD (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_23_20_GPIO8_3 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_23_20_MII_RXD2 (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_19_16 (0x000F0000u) -#define SYSCFG_PINMUX3_PINMUX3_19_16_SHIFT (0x00000010u) -/*----PINMUX3_19_16 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_19_16_NSPI0_SCS5 (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_19_16_UART0_RXD (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_19_16_GPIO8_4 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_19_16_MII_RXD3 (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_15_12 (0x0000F000u) -#define SYSCFG_PINMUX3_PINMUX3_15_12_SHIFT (0x0000000Cu) -/*----PINMUX3_15_12 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_15_12_SPI0_SIMO0 (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_15_12_EPWMSYNCO (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_15_12_GPIO8_5 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_15_12_MII_CRS (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_11_8 (0x00000F00u) -#define SYSCFG_PINMUX3_PINMUX3_11_8_SHIFT (0x00000008u) -/*----PINMUX3_11_8 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_11_8_SPI0_SOMI0 (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_11_8_EPWMSYNCI (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_11_8_GPIO8_6 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_11_8_MII_RXER (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_7_4 (0x000000F0u) -#define SYSCFG_PINMUX3_PINMUX3_7_4_SHIFT (0x00000004u) -/*----PINMUX3_7_4 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_7_4_NSPI0_ENA (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_7_4_EPWM0B (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_7_4_PRU0_R30_6 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_7_4_MII_RXDV (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX3_PINMUX3_3_0_SHIFT (0x00000000u) -/*----PINMUX3_3_0 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_3_0_SPI0_CLK (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_3_0_EPWM0A (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_3_0_GPIO1_8 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_3_0_MII_RXCLK (0x00000008u) - - -/* PINMUX4 */ - -#define SYSCFG_PINMUX4_PINMUX4_31_28 (0xF0000000u) -#define SYSCFG_PINMUX4_PINMUX4_31_28_SHIFT (0x0000001Cu) -/*----PINMUX4_31_28 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_31_28_NSPI1_SCS2 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_31_28_UART1_TXD (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_31_28_CP_POD (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_31_28_GPIO1_0 (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_27_24 (0x0F000000u) -#define SYSCFG_PINMUX4_PINMUX4_27_24_SHIFT (0x00000018u) -/*----PINMUX4_27_24 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_27_24_NSPI1_SCS3 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_27_24_UART1_RXD (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_27_24_LED (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_27_24_GPIO1_1 (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_23_20 (0x00F00000u) -#define SYSCFG_PINMUX4_PINMUX4_23_20_SHIFT (0x00000014u) -/*----PINMUX4_23_20 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_23_20_NSPI1_SCS4 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_23_20_UART2_TXD (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_23_20_I2C1_SDA (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_23_20_GPIO1_2 (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_19_16 (0x000F0000u) -#define SYSCFG_PINMUX4_PINMUX4_19_16_SHIFT (0x00000010u) -/*----PINMUX4_19_16 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_19_16_NSPI1_SCS5 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_19_16_UART2_RXD (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_19_16_I2C1_SCL (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_19_16_GPIO1_3 (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_15_12 (0x0000F000u) -#define SYSCFG_PINMUX4_PINMUX4_15_12_SHIFT (0x0000000Cu) -/*----PINMUX4_15_12 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_15_12_NSPI1_SCS6 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_15_12_I2C0_SDA (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_15_12_TM64P3_OUT12 (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_15_12_GPIO1_4 (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_11_8 (0x00000F00u) -#define SYSCFG_PINMUX4_PINMUX4_11_8_SHIFT (0x00000008u) -/*----PINMUX4_11_8 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_11_8_NSPI1_SCS7 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_11_8_I2C0_SCL (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_11_8_TM64P2_OUT12 (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_11_8_GPIO1_5 (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_7_4 (0x000000F0u) -#define SYSCFG_PINMUX4_PINMUX4_7_4_SHIFT (0x00000004u) -/*----PINMUX4_7_4 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_7_4_NSPI0_SCS0 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_7_4_TM64P1_OUT12 (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_7_4_GPIO1_6 (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_7_4_MDIO_D (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX4_PINMUX4_3_0_SHIFT (0x00000000u) -/*----PINMUX4_3_0 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_3_0_NSPI0_SCS1 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_3_0_TM64P0_OUT12 (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_3_0_GPIO1_7 (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_3_0_MDIO_CLK (0x00000008u) - - -/* PINMUX5 */ - -#define SYSCFG_PINMUX5_PINMUX5_31_28 (0xF0000000u) -#define SYSCFG_PINMUX5_PINMUX5_31_28_SHIFT (0x0000001Cu) -/*----PINMUX5_31_28 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_31_28_EMA_BA0 (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_31_28_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_31_28_GPIO2_8 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_27_24 (0x0F000000u) -#define SYSCFG_PINMUX5_PINMUX5_27_24_SHIFT (0x00000018u) -/*----PINMUX5_27_24 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_27_24_EMA_BA1 (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_27_24_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_27_24_GPIO2_9 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_23_20 (0x00F00000u) -#define SYSCFG_PINMUX5_PINMUX5_23_20_SHIFT (0x00000014u) -/*----PINMUX5_23_20 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_23_20_SPI1_SIMO0 (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_23_20_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_23_20_GPIO2_10 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_19_16 (0x000F0000u) -#define SYSCFG_PINMUX5_PINMUX5_19_16_SHIFT (0x00000010u) -/*----PINMUX5_19_16 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_19_16_SPI1_SOMI0 (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_19_16_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_19_16_GPIO2_11 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_15_12 (0x0000F000u) -#define SYSCFG_PINMUX5_PINMUX5_15_12_SHIFT (0x0000000Cu) -/*----PINMUX5_15_12 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_15_12_NSPI1_ENA (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_15_12_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_15_12_GPIO2_12 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_11_8 (0x00000F00u) -#define SYSCFG_PINMUX5_PINMUX5_11_8_SHIFT (0x00000008u) -/*----PINMUX5_11_8 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_11_8_SPI1_CLK (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_11_8_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_11_8_GPIO2_13 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_7_4 (0x000000F0u) -#define SYSCFG_PINMUX5_PINMUX5_7_4_SHIFT (0x00000004u) -/*----PINMUX5_7_4 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_7_4_NSPI1_SCS0 (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_7_4_EPWM1B (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_7_4_PRU0_R30_7 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_7_4_GPIO2_14 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX5_PINMUX5_3_0_SHIFT (0x00000000u) -/*----PINMUX5_3_0 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_3_0_NSPI1_SCS1 (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_3_0_EPWM1A (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_3_0_PRU0_R30_8 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_3_0_GPIO2_15 (0x00000008u) - - -/* PINMUX6 */ - -#define SYSCFG_PINMUX6_PINMUX6_31_28 (0xF0000000u) -#define SYSCFG_PINMUX6_PINMUX6_31_28_SHIFT (0x0000001Cu) -/*----PINMUX6_31_28 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_31_28_NEMA_CS0 (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_31_28_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_31_28_GPIO2_0 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_27_24 (0x0F000000u) -#define SYSCFG_PINMUX6_PINMUX6_27_24_SHIFT (0x00000018u) -/*----PINMUX6_27_24 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_27_24_EMA_WAIT1 (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_27_24_PRU0_R30_1 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_27_24_GPIO2_1 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_23_20 (0x00F00000u) -#define SYSCFG_PINMUX6_PINMUX6_23_20_SHIFT (0x00000014u) -/*----PINMUX6_23_20 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_23_20_NEMA_WE_DQM1 (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_23_20_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_23_20_GPIO2_2 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_19_16 (0x000F0000u) -#define SYSCFG_PINMUX6_PINMUX6_19_16_SHIFT (0x00000010u) -/*----PINMUX6_19_16 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_19_16_NEMA_WE_DQM0 (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_19_16_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_19_16_GPIO2_3 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_15_12 (0x0000F000u) -#define SYSCFG_PINMUX6_PINMUX6_15_12_SHIFT (0x0000000Cu) -/*----PINMUX6_15_12 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_15_12_NEMA_CAS (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_15_12_PRU0_R30_2 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_15_12_GPIO2_4 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_11_8 (0x00000F00u) -#define SYSCFG_PINMUX6_PINMUX6_11_8_SHIFT (0x00000008u) -/*----PINMUX6_11_8 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_11_8_NEMA_RAS (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_11_8_PRU0_R30_3 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_11_8_GPIO2_5 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_7_4 (0x000000F0u) -#define SYSCFG_PINMUX6_PINMUX6_7_4_SHIFT (0x00000004u) -/*----PINMUX6_7_4 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_7_4_EMA_SDCKE (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_7_4_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_7_4_PRU0_R30_4 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_7_4_GPIO2_6 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX6_PINMUX6_3_0_SHIFT (0x00000000u) -/*----PINMUX6_3_0 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_3_0_EMA_CLK (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_3_0_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_3_0_PRU0_R30_5 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_3_0_GPIO2_7 (0x00000008u) - - -/* PINMUX7 */ - -#define SYSCFG_PINMUX7_PINMUX7_31_28 (0xF0000000u) -#define SYSCFG_PINMUX7_PINMUX7_31_28_SHIFT (0x0000001Cu) -/*----PINMUX7_31_28 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_31_28_EMA_WAIT0 (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_31_28_PRU0_R30_0 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_31_28_GPIO3_8 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_27_24 (0x0F000000u) -#define SYSCFG_PINMUX7_PINMUX7_27_24_SHIFT (0x00000018u) -/*----PINMUX7_27_24 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_27_24_NEMA_RNW (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_27_24_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_27_24_GPIO3_9 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_23_20 (0x00F00000u) -#define SYSCFG_PINMUX7_PINMUX7_23_20_SHIFT (0x00000014u) -/*----PINMUX7_23_20 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_23_20_NEMA_OE (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_23_20_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_23_20_GPIO3_10 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_19_16 (0x000F0000u) -#define SYSCFG_PINMUX7_PINMUX7_19_16_SHIFT (0x00000010u) -/*----PINMUX7_19_16 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_19_16_NEMA_WE (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_19_16_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_19_16_GPIO3_11 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_15_12 (0x0000F000u) -#define SYSCFG_PINMUX7_PINMUX7_15_12_SHIFT (0x0000000Cu) -/*----PINMUX7_15_12 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_15_12_NEMA_CS5 (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_15_12_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_15_12_GPIO3_12 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_11_8 (0x00000F00u) -#define SYSCFG_PINMUX7_PINMUX7_11_8_SHIFT (0x00000008u) -/*----PINMUX7_11_8 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_11_8_NEMA_CS4 (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_11_8_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_11_8_GPIO3_13 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_7_4 (0x000000F0u) -#define SYSCFG_PINMUX7_PINMUX7_7_4_SHIFT (0x00000004u) -/*----PINMUX7_7_4 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_7_4_NEMA_CS3 (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_7_4_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_7_4_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_7_4_GPIO3_14 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX7_PINMUX7_3_0_SHIFT (0x00000000u) -/*----PINMUX7_3_0 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_3_0_NEMA_CS2 (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_3_0_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_3_0_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_3_0_GPIO3_15 (0x00000008u) - - -/* PINMUX8 */ - -#define SYSCFG_PINMUX8_PINMUX8_31_28 (0xF0000000u) -#define SYSCFG_PINMUX8_PINMUX8_31_28_SHIFT (0x0000001Cu) -/*----PINMUX8_31_28 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_31_28_EMA_D8 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_31_28_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_31_28_GPIO3_0 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_27_24 (0x0F000000u) -#define SYSCFG_PINMUX8_PINMUX8_27_24_SHIFT (0x00000018u) -/*----PINMUX8_27_24 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_27_24_EMA_D9 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_27_24_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_27_24_GPIO3_1 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_23_20 (0x00F00000u) -#define SYSCFG_PINMUX8_PINMUX8_23_20_SHIFT (0x00000014u) -/*----PINMUX8_23_20 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_23_20_EMA_D10 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_23_20_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_23_20_GPIO3_2 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_19_16 (0x000F0000u) -#define SYSCFG_PINMUX8_PINMUX8_19_16_SHIFT (0x00000010u) -/*----PINMUX8_19_16 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_19_16_EMA_D11 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_19_16_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_19_16_GPIO3_3 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_15_12 (0x0000F000u) -#define SYSCFG_PINMUX8_PINMUX8_15_12_SHIFT (0x0000000Cu) -/*----PINMUX8_15_12 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_15_12_EMA_D12 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_15_12_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_15_12_GPIO3_4 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_11_8 (0x00000F00u) -#define SYSCFG_PINMUX8_PINMUX8_11_8_SHIFT (0x00000008u) -/*----PINMUX8_11_8 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_11_8_EMA_D13 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_11_8_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_11_8_GPIO3_5 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_7_4 (0x000000F0u) -#define SYSCFG_PINMUX8_PINMUX8_7_4_SHIFT (0x00000004u) -/*----PINMUX8_7_4 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_7_4_EMA_D14 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_7_4_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_7_4_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_7_4_GPIO3_6 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX8_PINMUX8_3_0_SHIFT (0x00000000u) -/*----PINMUX8_3_0 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_3_0_EMA_D15 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_3_0_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_3_0_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_3_0_GPIO3_7 (0x00000008u) - - -/* PINMUX9 */ - -#define SYSCFG_PINMUX9_PINMUX9_31_28 (0xF0000000u) -#define SYSCFG_PINMUX9_PINMUX9_31_28_SHIFT (0x0000001Cu) -/*----PINMUX9_31_28 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_31_28_EMA_D0 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_31_28_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_31_28_GPIO4_8 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_27_24 (0x0F000000u) -#define SYSCFG_PINMUX9_PINMUX9_27_24_SHIFT (0x00000018u) -/*----PINMUX9_27_24 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_27_24_EMA_D1 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_27_24_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_27_24_GPIO4_9 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_23_20 (0x00F00000u) -#define SYSCFG_PINMUX9_PINMUX9_23_20_SHIFT (0x00000014u) -/*----PINMUX9_23_20 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_23_20_EMA_D2 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_23_20_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_23_20_GPIO4_10 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_19_16 (0x000F0000u) -#define SYSCFG_PINMUX9_PINMUX9_19_16_SHIFT (0x00000010u) -/*----PINMUX9_19_16 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_19_16_EMA_D3 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_19_16_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_19_16_GPIO4_11 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_15_12 (0x0000F000u) -#define SYSCFG_PINMUX9_PINMUX9_15_12_SHIFT (0x0000000Cu) -/*----PINMUX9_15_12 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_15_12_EMA_D4 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_15_12_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_15_12_GPIO4_12 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_11_8 (0x00000F00u) -#define SYSCFG_PINMUX9_PINMUX9_11_8_SHIFT (0x00000008u) -/*----PINMUX9_11_8 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_11_8_EMA_D5 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_11_8_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_11_8_GPIO4_13 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_7_4 (0x000000F0u) -#define SYSCFG_PINMUX9_PINMUX9_7_4_SHIFT (0x00000004u) -/*----PINMUX9_7_4 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_7_4_EMA_D6 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_7_4_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_7_4_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_7_4_GPIO4_14 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX9_PINMUX9_3_0_SHIFT (0x00000000u) -/*----PINMUX9_3_0 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_3_0_EMA_D7 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_3_0_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_3_0_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_3_0_GPIO4_15 (0x00000008u) - - -/* PINMUX10 */ - -#define SYSCFG_PINMUX10_PINMUX10_31_28 (0xF0000000u) -#define SYSCFG_PINMUX10_PINMUX10_31_28_SHIFT (0x0000001Cu) -/*----PINMUX10_31_28 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_31_28_EMA_A16 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_31_28_MMCSD0_DAT5 (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_31_28_PRU1_R30_24 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_31_28_GPIO4_0 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_27_24 (0x0F000000u) -#define SYSCFG_PINMUX10_PINMUX10_27_24_SHIFT (0x00000018u) -/*----PINMUX10_27_24 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_27_24_EMA_A17 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_27_24_MMCSD0_DAT4 (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_27_24_PRU1_R30_25 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_27_24_GPIO4_1 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_23_20 (0x00F00000u) -#define SYSCFG_PINMUX10_PINMUX10_23_20_SHIFT (0x00000014u) -/*----PINMUX10_23_20 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_23_20_EMA_A18 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_23_20_MMCSD0_DAT3 (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_23_20_PRU1_R30_26 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_23_20_GPIO4_2 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_19_16 (0x000F0000u) -#define SYSCFG_PINMUX10_PINMUX10_19_16_SHIFT (0x00000010u) -/*----PINMUX10_19_16 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_19_16_EMA_A19 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_19_16_MMCSD0_DAT2 (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_19_16_PRU1_R30_27 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_19_16_GPIO4_3 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_15_12 (0x0000F000u) -#define SYSCFG_PINMUX10_PINMUX10_15_12_SHIFT (0x0000000Cu) -/*----PINMUX10_15_12 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_15_12_EMA_A20 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_15_12_MMCSD0_DAT1 (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_15_12_PRU1_R30_28 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_15_12_GPIO4_4 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_11_8 (0x00000F00u) -#define SYSCFG_PINMUX10_PINMUX10_11_8_SHIFT (0x00000008u) -/*----PINMUX10_11_8 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_11_8_EMA_A21 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_11_8_MMCSD0_DAT0 (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_11_8_PRU1_R30_29 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_11_8_GPIO4_5 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_7_4 (0x000000F0u) -#define SYSCFG_PINMUX10_PINMUX10_7_4_SHIFT (0x00000004u) -/*----PINMUX10_7_4 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_7_4_EMA_A22 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_7_4_MMCSD0_CMD (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_7_4_PRU1_R30_30 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_7_4_GPIO4_6 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX10_PINMUX10_3_0_SHIFT (0x00000000u) -/*----PINMUX10_3_0 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_3_0_EMA_A23 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_3_0_MMCSD0_CLK (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_3_0_PRU1_R30_31 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_3_0_GPIO4_7 (0x00000008u) - - -/* PINMUX11 */ - -#define SYSCFG_PINMUX11_PINMUX11_31_28 (0xF0000000u) -#define SYSCFG_PINMUX11_PINMUX11_31_28_SHIFT (0x0000001Cu) -/*----PINMUX11_31_28 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_31_28_EMA_A8 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_31_28_PRU1_R30_16 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_31_28_GPIO5_8 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_27_24 (0x0F000000u) -#define SYSCFG_PINMUX11_PINMUX11_27_24_SHIFT (0x00000018u) -/*----PINMUX11_27_24 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_27_24_EMA_A9 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_27_24_PRU1_R30_17 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_27_24_GPIO5_9 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_23_20 (0x00F00000u) -#define SYSCFG_PINMUX11_PINMUX11_23_20_SHIFT (0x00000014u) -/*----PINMUX11_23_20 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_23_20_EMA_A10 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_23_20_PRU1_R30_18 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_23_20_GPIO5_10 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_19_16 (0x000F0000u) -#define SYSCFG_PINMUX11_PINMUX11_19_16_SHIFT (0x00000010u) -/*----PINMUX11_19_16 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_19_16_EMA_A11 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_19_16_PRU1_R30_19 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_19_16_GPIO5_11 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_15_12 (0x0000F000u) -#define SYSCFG_PINMUX11_PINMUX11_15_12_SHIFT (0x0000000Cu) -/*----PINMUX11_15_12 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_15_12_EMA_A12 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_15_12_PRU1_R30_20 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_15_12_GPIO5_12 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_11_8 (0x00000F00u) -#define SYSCFG_PINMUX11_PINMUX11_11_8_SHIFT (0x00000008u) -/*----PINMUX11_11_8 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_11_8_EMA_A13 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_11_8_PRU0_R30_21 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_11_8_PRU1_R30_21 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_11_8_GPIO5_13 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_7_4 (0x000000F0u) -#define SYSCFG_PINMUX11_PINMUX11_7_4_SHIFT (0x00000004u) -/*----PINMUX11_7_4 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_7_4_EMA_A14 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_7_4_MMCSD0_DAT7 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_7_4_PRU1_R30_22 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_7_4_GPIO5_14 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX11_PINMUX11_3_0_SHIFT (0x00000000u) -/*----PINMUX11_3_0 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_3_0_EMA_A15 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_3_0_MMCSD0_DAT6 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_3_0_PRU1_R30_23 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_3_0_GPIO5_15 (0x00000008u) - - -/* PINMUX12 */ - -#define SYSCFG_PINMUX12_PINMUX12_31_28 (0xF0000000u) -#define SYSCFG_PINMUX12_PINMUX12_31_28_SHIFT (0x0000001Cu) -/*----PINMUX12_31_28 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_31_28_EMA_A0 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_31_28_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_31_28_GPIO5_0 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_27_24 (0x0F000000u) -#define SYSCFG_PINMUX12_PINMUX12_27_24_SHIFT (0x00000018u) -/*----PINMUX12_27_24 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_27_24_EMA_A1 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_27_24_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_27_24_GPIO5_1 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_23_20 (0x00F00000u) -#define SYSCFG_PINMUX12_PINMUX12_23_20_SHIFT (0x00000014u) -/*----PINMUX12_23_20 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_23_20_EMA_A2 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_23_20_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_23_20_GPIO5_2 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_19_16 (0x000F0000u) -#define SYSCFG_PINMUX12_PINMUX12_19_16_SHIFT (0x00000010u) -/*----PINMUX12_19_16 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_19_16_EMA_A3 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_19_16_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_19_16_GPIO5_3 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_15_12 (0x0000F000u) -#define SYSCFG_PINMUX12_PINMUX12_15_12_SHIFT (0x0000000Cu) -/*----PINMUX12_15_12 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_15_12_EMA_A4 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_15_12_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_15_12_GPIO5_4 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_11_8 (0x00000F00u) -#define SYSCFG_PINMUX12_PINMUX12_11_8_SHIFT (0x00000008u) -/*----PINMUX12_11_8 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_11_8_EMA_A5 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_11_8_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_11_8_GPIO5_5 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_7_4 (0x000000F0u) -#define SYSCFG_PINMUX12_PINMUX12_7_4_SHIFT (0x00000004u) -/*----PINMUX12_7_4 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_7_4_EMA_A6 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_7_4_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_7_4_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_7_4_GPIO5_6 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX12_PINMUX12_3_0_SHIFT (0x00000000u) -/*----PINMUX12_3_0 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_3_0_EMA_A7 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_3_0_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_3_0_PRU1_R30_15 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_3_0_GPIO5_7 (0x00000008u) - - -/* PINMUX13 */ - -#define SYSCFG_PINMUX13_PINMUX13_31_28 (0xF0000000u) -#define SYSCFG_PINMUX13_PINMUX13_31_28_SHIFT (0x0000001Cu) -/*----PINMUX13_31_28 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_31_28_PRU0_R30_26 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_31_28_UHPI_HRNW (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_31_28_CH1_WAIT (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_31_28_GPIO6_8 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_27_24 (0x0F000000u) -#define SYSCFG_PINMUX13_PINMUX13_27_24_SHIFT (0x00000018u) -/*----PINMUX13_27_24 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_27_24_PRU0_R30_27 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_27_24_UHPI_HHWIL (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_27_24_GPIO6_9 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_23_20 (0x00F00000u) -#define SYSCFG_PINMUX13_PINMUX13_23_20_SHIFT (0x00000014u) -/*----PINMUX13_23_20 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_23_20_PRU0_R30_28 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_23_20_UHPI_HCNTL1 (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_23_20_CH1_START (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_23_20_GPIO6_10 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_19_16 (0x000F0000u) -#define SYSCFG_PINMUX13_PINMUX13_19_16_SHIFT (0x00000010u) -/*----PINMUX13_19_16 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_19_16_PRU0_R30_29 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_19_16_UHPI_HCNTL0 (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_19_16_CH1_CLK (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_19_16_GPIO6_11 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_15_12 (0x0000F000u) -#define SYSCFG_PINMUX13_PINMUX13_15_12_SHIFT (0x0000000Cu) -/*----PINMUX13_15_12 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_15_12_PRU0_R30_30 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_15_12_NUHPI_HINT (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_15_12_PRU1_R30_11 (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_15_12_GPIO6_12 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_11_8 (0x00000F00u) -#define SYSCFG_PINMUX13_PINMUX13_11_8_SHIFT (0x00000008u) -/*----PINMUX13_11_8 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_11_8_PRU0_R30_31 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_11_8_NUHPI_HRDY (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_11_8_PRU1_R30_12 (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_11_8_GPIO6_13 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_7_4 (0x000000F0u) -#define SYSCFG_PINMUX13_PINMUX13_7_4_SHIFT (0x00000004u) -/*----PINMUX13_7_4 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_7_4_OBSCLK0 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_7_4_NUHPI_HDS2 (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_7_4_PRU1_R30_13 (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_7_4_GPIO6_14 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX13_PINMUX13_3_0_SHIFT (0x00000000u) -/*----PINMUX13_3_0 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_3_0_NRESETOUT (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_3_0_NUHPI_HAS (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_3_0_PRU1_R30_14 (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_3_0_GPIO6_15 (0x00000008u) - - -/* PINMUX14 */ - -#define SYSCFG_PINMUX14_PINMUX14_31_28 (0xF0000000u) -#define SYSCFG_PINMUX14_PINMUX14_31_28_SHIFT (0x0000001Cu) -/*----PINMUX14_31_28 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_31_28_DIN2 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_31_28_UHPI_HD10 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_31_28_UPP_D10 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_31_28_RMII_RXER (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_27_24 (0x0F000000u) -#define SYSCFG_PINMUX14_PINMUX14_27_24_SHIFT (0x00000018u) -/*----PINMUX14_27_24 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_27_24_DIN3 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_27_24_UHPI_HD11 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_27_24_UPP_D11 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_27_24_RMII_RXD0 (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_23_20 (0x00F00000u) -#define SYSCFG_PINMUX14_PINMUX14_23_20_SHIFT (0x00000014u) -/*----PINMUX14_23_20 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_23_20_DIN4 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_23_20_UHPI_HD12 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_23_20_UPP_D12 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_23_20_RMII_RXD1 (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_19_16 (0x000F0000u) -#define SYSCFG_PINMUX14_PINMUX14_19_16_SHIFT (0x00000010u) -/*----PINMUX14_19_16 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_19_16_DIN5 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_19_16_UHPI_HD13 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_19_16_UPP_D13 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_19_16_RMII_TXEN (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_15_12 (0x0000F000u) -#define SYSCFG_PINMUX14_PINMUX14_15_12_SHIFT (0x0000000Cu) -/*----PINMUX14_15_12 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_15_12_DIN6 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_15_12_UHPI_HD14 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_15_12_UPP_D14 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_15_12_RMII_TXD0 (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_11_8 (0x00000F00u) -#define SYSCFG_PINMUX14_PINMUX14_11_8_SHIFT (0x00000008u) -/*----PINMUX14_11_8 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_11_8_DIN7 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_11_8_UHPI_HD15 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_11_8_UPP_D15 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_11_8_RMII_TXD1 (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_7_4 (0x000000F0u) -#define SYSCFG_PINMUX14_PINMUX14_7_4_SHIFT (0x00000004u) -/*----PINMUX14_7_4 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_7_4_CLKIN1 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_7_4_NUHPI_HDS1 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_7_4_PRU1_R30_9 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_7_4_GPIO6_6 (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX14_PINMUX14_3_0_SHIFT (0x00000000u) -/*----PINMUX14_3_0 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_3_0_CLKIN0 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_3_0_NUHPI_HCS (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_3_0_PRU1_R30_10 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_3_0_GPIO6_7 (0x00000008u) - - -/* PINMUX15 */ - -#define SYSCFG_PINMUX15_PINMUX15_31_28 (0xF0000000u) -#define SYSCFG_PINMUX15_PINMUX15_31_28_SHIFT (0x0000001Cu) -/*----PINMUX15_31_28 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_31_28_DIN10 (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_31_28_UHPI_HD2 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_31_28_UPP_D2 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_31_28_PRU0_R30_10 (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_27_24 (0x0F000000u) -#define SYSCFG_PINMUX15_PINMUX15_27_24_SHIFT (0x00000018u) -/*----PINMUX15_27_24 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_27_24_DIN11 (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_27_24_UHPI_HD3 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_27_24_UPP_D3 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_27_24_PRU0_R30_11 (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_23_20 (0x00F00000u) -#define SYSCFG_PINMUX15_PINMUX15_23_20_SHIFT (0x00000014u) -/*----PINMUX15_23_20 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_23_20_DIN12 (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_23_20_UHPI_HD4 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_23_20_UPP_D4 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_23_20_PRU0_R30_12 (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_19_16 (0x000F0000u) -#define SYSCFG_PINMUX15_PINMUX15_19_16_SHIFT (0x00000010u) -/*----PINMUX15_19_16 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_19_16_DIN13_FIELD (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_19_16_UHPI_HD5 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_19_16_UPP_D5 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_19_16_PRU0_R30_13 (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_15_12 (0x0000F000u) -#define SYSCFG_PINMUX15_PINMUX15_15_12_SHIFT (0x0000000Cu) -/*----PINMUX15_15_12 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_15_12_DIN14_HSYNC (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_15_12_UHPI_HD6 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_15_12_UPP_D6 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_15_12_PRU0_R30_14 (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_11_8 (0x00000F00u) -#define SYSCFG_PINMUX15_PINMUX15_11_8_SHIFT (0x00000008u) -/*----PINMUX15_11_8 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_11_8_DIN15_VSYNC (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_11_8_UHPI_HD7 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_11_8_UPP_D7 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_11_8_PRU0_R30_15 (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_7_4 (0x000000F0u) -#define SYSCFG_PINMUX15_PINMUX15_7_4_SHIFT (0x00000004u) -/*----PINMUX15_7_4 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_7_4_DIN0 (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_7_4_UHPI_HD8 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_7_4_UPP_D8 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_7_4_RMII_CRS_DV (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX15_PINMUX15_3_0_SHIFT (0x00000000u) -/*----PINMUX15_3_0 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_3_0_DIN1 (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_3_0_UHPI_HD9 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_3_0_UPP_D9 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_3_0_RMII_MHZ_50_CLK (0x00000008u) - - -/* PINMUX16 */ - -#define SYSCFG_PINMUX16_PINMUX16_31_28 (0xF0000000u) -#define SYSCFG_PINMUX16_PINMUX16_31_28_SHIFT (0x0000001Cu) -/*----PINMUX16_31_28 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_31_28_DOUT2 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_31_28_LCD_D2 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_31_28_UPP_XD10 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_31_28_GPIO7_10 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_27_24 (0x0F000000u) -#define SYSCFG_PINMUX16_PINMUX16_27_24_SHIFT (0x00000018u) -/*----PINMUX16_27_24 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_27_24_DOUT3 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_27_24_LCD_D3 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_27_24_UPP_XD11 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_27_24_GPIO7_11 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_23_20 (0x00F00000u) -#define SYSCFG_PINMUX16_PINMUX16_23_20_SHIFT (0x00000014u) -/*----PINMUX16_23_20 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_23_20_DOUT4 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_23_20_LCD_D4 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_23_20_UPP_XD12 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_23_20_GPIO7_12 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_19_16 (0x000F0000u) -#define SYSCFG_PINMUX16_PINMUX16_19_16_SHIFT (0x00000010u) -/*----PINMUX16_19_16 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_19_16_DOUT5 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_19_16_LCD_D5 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_19_16_UPP_XD13 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_19_16_GPIO7_13 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_15_12 (0x0000F000u) -#define SYSCFG_PINMUX16_PINMUX16_15_12_SHIFT (0x0000000Cu) -/*----PINMUX16_15_12 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_15_12_DOUT6 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_15_12_LCD_D6 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_15_12_UPP_XD14 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_15_12_GPIO7_14 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_11_8 (0x00000F00u) -#define SYSCFG_PINMUX16_PINMUX16_11_8_SHIFT (0x00000008u) -/*----PINMUX16_11_8 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_11_8_DOUT7 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_11_8_LCD_D7 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_11_8_UPP_XD15 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_11_8_GPIO7_15 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_7_4 (0x000000F0u) -#define SYSCFG_PINMUX16_PINMUX16_7_4_SHIFT (0x00000004u) -/*----PINMUX16_7_4 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_7_4_DIN8 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_7_4_UHPI_HD0 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_7_4_UPP_D0 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_7_4_GPIO6_5 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX16_PINMUX16_3_0_SHIFT (0x00000000u) -/*----PINMUX16_3_0 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_3_0_DIN9 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_3_0_UHPI_HD1 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_3_0_UPP_D1 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_3_0_PRU0_R30_9 (0x00000008u) - - -/* PINMUX17 */ - -#define SYSCFG_PINMUX17_PINMUX17_31_28 (0xF0000000u) -#define SYSCFG_PINMUX17_PINMUX17_31_28_SHIFT (0x0000001Cu) -/*----PINMUX17_31_28 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_31_28_DOUT10 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_31_28_LCD_D10 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_31_28_UPP_XD2 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_31_28_GPIO7_2 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_27_24 (0x0F000000u) -#define SYSCFG_PINMUX17_PINMUX17_27_24_SHIFT (0x00000018u) -/*----PINMUX17_27_24 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_27_24_DOUT11 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_27_24_LCD_D11 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_27_24_UPP_XD3 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_27_24_GPIO7_3 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_23_20 (0x00F00000u) -#define SYSCFG_PINMUX17_PINMUX17_23_20_SHIFT (0x00000014u) -/*----PINMUX17_23_20 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_23_20_DOUT12 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_23_20_LCD_D12 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_23_20_UPP_XD4 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_23_20_GPIO7_4 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_19_16 (0x000F0000u) -#define SYSCFG_PINMUX17_PINMUX17_19_16_SHIFT (0x00000010u) -/*----PINMUX17_19_16 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_19_16_DOUT13 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_19_16_LCD_D13 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_19_16_UPP_XD5 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_19_16_GPIO7_5 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_15_12 (0x0000F000u) -#define SYSCFG_PINMUX17_PINMUX17_15_12_SHIFT (0x0000000Cu) -/*----PINMUX17_15_12 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_15_12_DOUT14 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_15_12_LCD_D14 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_15_12_UPP_XD6 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_15_12_GPIO7_6 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_11_8 (0x00000F00u) -#define SYSCFG_PINMUX17_PINMUX17_11_8_SHIFT (0x00000008u) -/*----PINMUX17_11_8 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_11_8_DOUT15 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_11_8_LCD_D15 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_11_8_UPP_XD7 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_11_8_GPIO7_7 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_7_4 (0x000000F0u) -#define SYSCFG_PINMUX17_PINMUX17_7_4_SHIFT (0x00000004u) -/*----PINMUX17_7_4 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_7_4_DOUT0 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_7_4_LCD_D0 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_7_4_UPP_XD8 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_7_4_GPIO7_8 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX17_PINMUX17_3_0_SHIFT (0x00000000u) -/*----PINMUX17_3_0 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_3_0_DOUT1 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_3_0_LCD_D1 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_3_0_UPP_XD9 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_3_0_GPIO7_9 (0x00000008u) - - -/* PINMUX18 */ - -#define SYSCFG_PINMUX18_PINMUX18_31_28 (0xF0000000u) -#define SYSCFG_PINMUX18_PINMUX18_31_28_SHIFT (0x0000001Cu) -/*----PINMUX18_31_28 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_31_28_MMCSD1_DAT6 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_31_28_LCD_MCLK (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_31_28_PRU1_R30_6 (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_31_28_GPIO8_10 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_27_24 (0x0F000000u) -#define SYSCFG_PINMUX18_PINMUX18_27_24_SHIFT (0x00000018u) -/*----PINMUX18_27_24 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_27_24_MMCSD1_DAT7 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_27_24_LCD_PCLK (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_27_24_PRU1_R30_7 (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_27_24_GPIO8_11 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_23_20 (0x00F00000u) -#define SYSCFG_PINMUX18_PINMUX18_23_20_SHIFT (0x00000014u) -/*----PINMUX18_23_20 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_23_20_PRU0_R30_22 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_23_20_PRU1_R30_8 (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_23_20_CH0_WAIT (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_23_20_GPIO8_12 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_19_16 (0x000F0000u) -#define SYSCFG_PINMUX18_PINMUX18_19_16_SHIFT (0x00000010u) -/*----PINMUX18_19_16 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_19_16_PRU0_R30_23 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_19_16_MMCSD1_CMD (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_19_16_GPIO8_13 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_15_12 (0x0000F000u) -#define SYSCFG_PINMUX18_PINMUX18_15_12_SHIFT (0x0000000Cu) -/*----PINMUX18_15_12 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_15_12_PRU0_R30_24 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_15_12_MMCSD1_CLK (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_15_12_CH0_START (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_15_12_GPIO8_14 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_11_8 (0x00000F00u) -#define SYSCFG_PINMUX18_PINMUX18_11_8_SHIFT (0x00000008u) -/*----PINMUX18_11_8 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_11_8_PRU0_R30_25 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_11_8_MMCSD1_DAT0 (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_11_8_CH0_CLK (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_11_8_GPIO8_15 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_7_4 (0x000000F0u) -#define SYSCFG_PINMUX18_PINMUX18_7_4_SHIFT (0x00000004u) -/*----PINMUX18_7_4 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_7_4_DOUT8 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_7_4_LCD_D8 (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_7_4_UPP_XD0 (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_7_4_GPIO7_0 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX18_PINMUX18_3_0_SHIFT (0x00000000u) -/*----PINMUX18_3_0 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_3_0_DOUT9 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_3_0_LCD_D9 (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_3_0_UPP_XD1 (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_3_0_GPIO7_1 (0x00000008u) - - -/* PINMUX19 */ - -#define SYSCFG_PINMUX19_PINMUX19_31_28 (0xF0000000u) -#define SYSCFG_PINMUX19_PINMUX19_31_28_SHIFT (0x0000001Cu) -/*----PINMUX19_31_28 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_31_28_RTCK (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_31_28_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_31_28_GPIO8_0 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_27_24 (0x0F000000u) -#define SYSCFG_PINMUX19_PINMUX19_27_24_SHIFT (0x00000018u) -/*----PINMUX19_27_24 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_27_24_RESERVED1 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_27_24_NLCD_AC_ENB_CS (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_27_24_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_27_24_GPIO6_0 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_23_20 (0x00F00000u) -#define SYSCFG_PINMUX19_PINMUX19_23_20_SHIFT (0x00000014u) -/*----PINMUX19_23_20 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_23_20_CLKO3 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_23_20_PRU1_R30_0 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_23_20_GPIO6_1 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_19_16 (0x000F0000u) -#define SYSCFG_PINMUX19_PINMUX19_19_16_SHIFT (0x00000010u) -/*----PINMUX19_19_16 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_19_16_CLKIN3 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_19_16_MMCSD1_DAT1 (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_19_16_PRU1_R30_1 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_19_16_GPIO6_2 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_15_12 (0x0000F000u) -#define SYSCFG_PINMUX19_PINMUX19_15_12_SHIFT (0x0000000Cu) -/*----PINMUX19_15_12 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_15_12_CLKO2 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_15_12_MMCSD1_DAT2 (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_15_12_PRU1_R30_2 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_15_12_GPIO6_3 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_11_8 (0x00000F00u) -#define SYSCFG_PINMUX19_PINMUX19_11_8_SHIFT (0x00000008u) -/*----PINMUX19_11_8 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_11_8_CLKIN2 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_11_8_MMCSD1_DAT3 (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_11_8_PRU1_R30_3 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_11_8_GPIO6_4 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_7_4 (0x000000F0u) -#define SYSCFG_PINMUX19_PINMUX19_7_4_SHIFT (0x00000004u) -/*----PINMUX19_7_4 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_7_4_MMCSD1_DAT4 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_7_4_LCD_VSYNC (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_7_4_PRU1_R30_4 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_7_4_GPIO8_8 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX19_PINMUX19_3_0_SHIFT (0x00000000u) -/*----PINMUX19_3_0 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_3_0_MMCSD1_DAT5 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_3_0_LCD_HSYNC (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_3_0_PRU1_R30_5 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_3_0_GPIO8_9 (0x00000008u) - - -/* SUSPSRC */ - - -#define SYSCFG_SUSPSRC_TIMER64P_2SRC (0x20000000u) -#define SYSCFG_SUSPSRC_TIMER64P_2SRC_SHIFT (0x0000001Du) - -#define SYSCFG_SUSPSRC_TIMER64P_1SRC (0x10000000u) -#define SYSCFG_SUSPSRC_TIMER64P_1SRC_SHIFT (0x0000001Cu) - -#define SYSCFG_SUSPSRC_TIMER64P_0SRC (0x08000000u) -#define SYSCFG_SUSPSRC_TIMER64P_0SRC_SHIFT (0x0000001Bu) - - -#define SYSCFG_SUSPSRC_EPWM1SRC (0x01000000u) -#define SYSCFG_SUSPSRC_EPWM1SRC_SHIFT (0x00000018u) - -#define SYSCFG_SUSPSRC_EPWM0SRC (0x00800000u) -#define SYSCFG_SUSPSRC_EPWM0SRC_SHIFT (0x00000017u) - -#define SYSCFG_SUSPSRC_SPI1SRC (0x00400000u) -#define SYSCFG_SUSPSRC_SPI1SRC_SHIFT (0x00000016u) - -#define SYSCFG_SUSPSRC_SPI0SRC (0x00200000u) -#define SYSCFG_SUSPSRC_SPI0SRC_SHIFT (0x00000015u) - -#define SYSCFG_SUSPSRC_UART2SRC (0x00100000u) -#define SYSCFG_SUSPSRC_UART2SRC_SHIFT (0x00000014u) - -#define SYSCFG_SUSPSRC_UART1SRC (0x00080000u) -#define SYSCFG_SUSPSRC_UART1SRC_SHIFT (0x00000013u) - -#define SYSCFG_SUSPSRC_UART0SRC (0x00040000u) -#define SYSCFG_SUSPSRC_UART0SRC_SHIFT (0x00000012u) - -#define SYSCFG_SUSPSRC_I2C1SRC (0x00020000u) -#define SYSCFG_SUSPSRC_I2C1SRC_SHIFT (0x00000011u) - -#define SYSCFG_SUSPSRC_I2C0SRC (0x00010000u) -#define SYSCFG_SUSPSRC_I2C0SRC_SHIFT (0x00000010u) - - -#define SYSCFG_SUSPSRC_VPIFSRC (0x00004000u) -#define SYSCFG_SUSPSRC_VPIFSRC_SHIFT (0x0000000Eu) - -#define SYSCFG_SUSPSRC_SATASRC (0x00002000u) -#define SYSCFG_SUSPSRC_SATASRC_SHIFT (0x0000000Du) - -#define SYSCFG_SUSPSRC_HPISRC (0x00001000u) -#define SYSCFG_SUSPSRC_HPISRC_SHIFT (0x0000000Cu) - - -#define SYSCFG_SUSPSRC_USB0SRC (0x00000200u) -#define SYSCFG_SUSPSRC_USB0SRC_SHIFT (0x00000009u) - -#define SYSCFG_SUSPSRC_MCBSP1SRC (0x00000100u) -#define SYSCFG_SUSPSRC_MCBSP1SRC_SHIFT (0x00000008u) - -#define SYSCFG_SUSPSRC_MCBSP0SRC (0x00000080u) -#define SYSCFG_SUSPSRC_MCBSP0SRC_SHIFT (0x00000007u) - -#define SYSCFG_SUSPSRC_PRUSRC (0x00000040u) -#define SYSCFG_SUSPSRC_PRUSRC_SHIFT (0x00000006u) - -#define SYSCFG_SUSPSRC_EMACSRC (0x00000020u) -#define SYSCFG_SUSPSRC_EMACSRC_SHIFT (0x00000005u) - -#define SYSCFG_SUSPSRC_UPPSRC (0x00000010u) -#define SYSCFG_SUSPSRC_UPPSRC_SHIFT (0x00000004u) - -#define SYSCFG_SUSPSRC_TIMER64P_3SRC (0x00000008u) -#define SYSCFG_SUSPSRC_TIMER64P_3SRC_SHIFT (0x00000003u) - -#define SYSCFG_SUSPSRC_ECAP2SRC (0x00000004u) -#define SYSCFG_SUSPSRC_ECAP2SRC_SHIFT (0x00000002u) - -#define SYSCFG_SUSPSRC_ECAP1SRC (0x00000002u) -#define SYSCFG_SUSPSRC_ECAP1SRC_SHIFT (0x00000001u) - -#define SYSCFG_SUSPSRC_ECAP0SRC (0x00000001u) -#define SYSCFG_SUSPSRC_ECAP0SRC_SHIFT (0x00000000u) - - -/* CHIPSIG */ - - -#define SYSCFG_CHIPSIG_CHIPSIG4 (0x00000010u) -#define SYSCFG_CHIPSIG_CHIPSIG4_SHIFT (0x00000004u) - -#define SYSCFG_CHIPSIG_CHIPSIG3 (0x00000008u) -#define SYSCFG_CHIPSIG_CHIPSIG3_SHIFT (0x00000003u) - -#define SYSCFG_CHIPSIG_CHIPSIG2 (0x00000004u) -#define SYSCFG_CHIPSIG_CHIPSIG2_SHIFT (0x00000002u) - -#define SYSCFG_CHIPSIG_CHIPSIG1 (0x00000002u) -#define SYSCFG_CHIPSIG_CHIPSIG1_SHIFT (0x00000001u) - -#define SYSCFG_CHIPSIG_CHIPSIG0 (0x00000001u) -#define SYSCFG_CHIPSIG_CHIPSIG0_SHIFT (0x00000000u) - - -/* CHIPSIG_CLR */ - - -#define SYSCFG_CHIPSIG_CLR_CHIPSIG4 (0x00000010u) -#define SYSCFG_CHIPSIG_CLR_CHIPSIG4_SHIFT (0x00000004u) - -#define SYSCFG_CHIPSIG_CLR_CHIPSIG3 (0x00000008u) -#define SYSCFG_CHIPSIG_CLR_CHIPSIG3_SHIFT (0x00000003u) - -#define SYSCFG_CHIPSIG_CLR_CHIPSIG2 (0x00000004u) -#define SYSCFG_CHIPSIG_CLR_CHIPSIG2_SHIFT (0x00000002u) - -#define SYSCFG_CHIPSIG_CLR_CHIPSIG1 (0x00000002u) -#define SYSCFG_CHIPSIG_CLR_CHIPSIG1_SHIFT (0x00000001u) - -#define SYSCFG_CHIPSIG_CLR_CHIPSIG0 (0x00000001u) -#define SYSCFG_CHIPSIG_CLR_CHIPSIG0_SHIFT (0x00000000u) - - -/* CFGCHIP0 */ - -#define SYSCFG_CFGCHIP0_ARM_CLK_DIS0 (0x80000000u) -#define SYSCFG_CFGCHIP0_ARM_CLK_DIS0_SHIFT (0x0000001Fu) - -#define SYSCFG_CFGCHIP0_ARM_TAP_DIS0 (0x40000000u) -#define SYSCFG_CFGCHIP0_ARM_TAP_DIS0_SHIFT (0x0000001Eu) - - -#define SYSCFG_CFGCHIP0_PLL_MASTER_LOCK (0x00000010u) -#define SYSCFG_CFGCHIP0_PLL_MASTER_LOCK_SHIFT (0x00000004u) - -#define SYSCFG_CFGCHIP0_EDMA30TC1DBS (0x0000000Cu) -#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_SHIFT (0x00000002u) -/*----EDMA30TC1DBS Tokens----*/ -#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_16BYTE (0x00000000u) -#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_32BYTE (0x00000001u) -#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_64BYTE (0x00000002u) -#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_RESERVED (0x00000003u) - -#define SYSCFG_CFGCHIP0_EDMA30TC0DBS (0x00000003u) -#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_SHIFT (0x00000000u) -/*----EDMA30TC0DBS Tokens----*/ -#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_16BYTE (0x00000000u) -#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_32BYTE (0x00000001u) -#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_64BYTE (0x00000002u) -#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_RESERVED (0x00000003u) - - -/* CFGCHIP1 */ - -#define SYSCFG_CFGCHIP1_CAP2SRC (0xF8000000u) -#define SYSCFG_CFGCHIP1_CAP2SRC_SHIFT (0x0000001Bu) -/*----CAP2SRC Tokens----*/ -#define SYSCFG_CFGCHIP1_CAP2SRC_ECAP2 (0x00000000u) -#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP0_TXDMA (0x00000001u) -#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP0_RXDMA (0x00000002u) -#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP1_TXDMA (0x00000003u) -#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP1_RXDMA (0x00000004u) -#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP2_TXDMA (0x00000005u) -#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP2_RXDMA (0x00000006u) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C0_RXTHPLSEINT (0x00000007u) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C0_RXPLSEINT (0x00000008u) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C0_TXPLSEINT (0x00000009u) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C0_MISCINT (0x0000000au) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C1_RXTHPLSEINT (0x0000000bu) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C1_RXPLSEINT (0x0000000cu) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C1_TXPLSEINT (0x0000000du) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C1_MISCINT (0x0000000eu) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C2_RXTHPLSEINT (0x0000000fu) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C2_RXPLSEINT (0x00000010u) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C2_TXPLSEINT (0x00000011u) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C2_MISCINT (0x00000012u) - -#define SYSCFG_CFGCHIP1_CAP1SRC (0x07C00000u) -#define SYSCFG_CFGCHIP1_CAP1SRC_SHIFT (0x00000016u) -/*----CAP1SRC Tokens----*/ -#define SYSCFG_CFGCHIP1_CAP1SRC_ECAP1 (0x00000000u) -#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP0_TXDMA (0x00000001u) -#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP0_RXDMA (0x00000002u) -#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP1_TXDMA (0x00000003u) -#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP1_RXDMA (0x00000004u) -#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP2_TXDMA (0x00000005u) -#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP2_RXDMA (0x00000006u) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C0_RXTHPLSEINT (0x00000007u) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C0_RXPLSEINT (0x00000008u) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C0_TXPLSEINT (0x00000009u) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C0_MISCINT (0x0000000au) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C1_RXTHPLSEINT (0x0000000bu) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C1_RXPLSEINT (0x0000000cu) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C1_TXPLSEINT (0x0000000du) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C1_MISCINT (0x0000000eu) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C2_RXTHPLSEINT (0x0000000fu) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C2_RXPLSEINT (0x00000010u) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C2_TXPLSEINT (0x00000011u) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C2_MISCINT (0x00000012u) - -#define SYSCFG_CFGCHIP1_CAP0SRC (0x003E0000u) -#define SYSCFG_CFGCHIP1_CAP0SRC_SHIFT (0x00000011u) -/*----CAP0SRC Tokens----*/ -#define SYSCFG_CFGCHIP1_CAP0SRC_ECAP0 (0x00000000u) -#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP0_TXDMA (0x00000001u) -#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP0_RXDMA (0x00000002u) -#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP1_TXDMA (0x00000003u) -#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP1_RXDMA (0x00000004u) -#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP2_TXDMA (0x00000005u) -#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP2_RXDMA (0x00000006u) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C0_RXTHPLSEINT (0x00000007u) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C0_RXPLSEINT (0x00000008u) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C0_TXPLSEINT (0x00000009u) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C0_MISCINT (0x0000000au) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C1_RXTHPLSEINT (0x0000000bu) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C1_RXPLSEINT (0x0000000cu) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C1_TXPLSEINT (0x0000000du) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C1_MISCINT (0x0000000eu) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C2_RXTHPLSEINT (0x0000000fu) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C2_RXPLSEINT (0x00000010u) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C2_TXPLSEINT (0x00000011u) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C2_MISCINT (0x00000012u) - -#define SYSCFG_CFGCHIP1_HPIBYTEAD (0x00010000u) -#define SYSCFG_CFGCHIP1_HPIBYTEAD_SHIFT (0x00000010u) - -#define SYSCFG_CFGCHIP1_HPIENA (0x00008000u) -#define SYSCFG_CFGCHIP1_HPIENA_SHIFT (0x0000000Fu) - -#define SYSCFG_CFGCHIP1_EDMA31TC0DBS (0x00006000u) -#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_SHIFT (0x0000000Du) -/*----EDMA31TC0DBS Tokens----*/ -#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_16BYTE (0x00000000u) -#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_32BYTE (0x00000001u) -#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_64BYTE (0x00000002u) -#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_RESERVED (0x00000003u) - -#define SYSCFG_CFGCHIP1_TBCLKSYNC (0x00001000u) -#define SYSCFG_CFGCHIP1_TBCLKSYNC_SHIFT (0x0000000Cu) - - -#define SYSCFG_CFGCHIP1_AMUTESEL0 (0x0000000Fu) -#define SYSCFG_CFGCHIP1_AMUTESEL0_SHIFT (0x00000000u) -/*----AMUTESEL0 Tokens----*/ -#define SYSCFG_CFGCHIP1_AMUTESEL0_LOW (0x00000000u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B0 (0x00000001u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B1 (0x00000002u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B2 (0x00000003u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B3 (0x00000004u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B4 (0x00000005u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B5 (0x00000006u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B6 (0x00000007u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B7 (0x00000008u) - - -/* CFGCHIP2 */ - - -#define SYSCFG_CFGCHIP2_USB0PHYCLKGD (0x00020000u) -#define SYSCFG_CFGCHIP2_USB0PHYCLKGD_SHIFT (0x00000011u) - -#define SYSCFG_CFGCHIP2_USB0VBUSSENSE (0x00010000u) -#define SYSCFG_CFGCHIP2_USB0VBUSSENSE_SHIFT (0x00000010u) - -#define SYSCFG_CFGCHIP2_RESET (0x00008000u) -#define SYSCFG_CFGCHIP2_RESET_SHIFT (0x0000000Fu) - -#define SYSCFG_CFGCHIP2_USB0OTGMODE (0x00006000u) -#define SYSCFG_CFGCHIP2_USB0OTGMODE_SHIFT (0x0000000Du) -/*----USB0OTGMODE Tokens----*/ -#define SYSCFG_CFGCHIP2_USB0OTGMODE_PHY (0x00000000u) -#define SYSCFG_CFGCHIP2_USB0OTGMODE_USB_HOST (0x00000001u) -#define SYSCFG_CFGCHIP2_USB0OTGMODE_USB_DEVICE (0x00000002u) -#define SYSCFG_CFGCHIP2_USB0OTGMODE_USB_HOST_LOW (0x00000003u) - -#define SYSCFG_CFGCHIP2_USB1PHYCLKMUX (0x00001000u) -#define SYSCFG_CFGCHIP2_USB1PHYCLKMUX_SHIFT (0x0000000Cu) - -#define SYSCFG_CFGCHIP2_USB0PHYCLKMUX (0x00000800u) -#define SYSCFG_CFGCHIP2_USB0PHYCLKMUX_SHIFT (0x0000000Bu) - -#define SYSCFG_CFGCHIP2_USB0PHYPWDN (0x00000400u) -#define SYSCFG_CFGCHIP2_USB0PHYPWDN_SHIFT (0x0000000Au) - -#define SYSCFG_CFGCHIP2_USB0OTGPWRDN (0x00000200u) -#define SYSCFG_CFGCHIP2_USB0OTGPWRDN_SHIFT (0x00000009u) - -#define SYSCFG_CFGCHIP2_USB0DATPOL (0x00000100u) -#define SYSCFG_CFGCHIP2_USB0DATPOL_SHIFT (0x00000008u) - -#define SYSCFG_CFGCHIP2_USB1SUSPENDM (0x00000080u) -#define SYSCFG_CFGCHIP2_USB1SUSPENDM_SHIFT (0x00000007u) - -#define SYSCFG_CFGCHIP2_USB0PHY_PLLON (0x00000040u) -#define SYSCFG_CFGCHIP2_USB0PHY_PLLON_SHIFT (0x00000006u) - -#define SYSCFG_CFGCHIP2_USB0SESNDEN (0x00000020u) -#define SYSCFG_CFGCHIP2_USB0SESNDEN_SHIFT (0x00000005u) - -#define SYSCFG_CFGCHIP2_USB0VBDTCTEN (0x00000010u) -#define SYSCFG_CFGCHIP2_USB0VBDTCTEN_SHIFT (0x00000004u) - -#define SYSCFG_CFGCHIP2_USB0REF_FREQ (0x0000000Fu) -#define SYSCFG_CFGCHIP2_USB0REF_FREQ_SHIFT (0x00000000u) - - -/* CFGCHIP3 */ - - - -#define SYSCFG_CFGCHIP3_RMII_SEL (0x00000100u) -#define SYSCFG_CFGCHIP3_RMII_SEL_SHIFT (0x00000008u) - -#define SYSCFG_CFGCHIP3_UPP_TX_CLKSRC (0x00000040u) -#define SYSCFG_CFGCHIP3_UPP_TX_CLKSRC_SHIFT (0x00000006u) - -#define SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK (0x00000020u) -#define SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_SHIFT (0x00000005u) - -#define SYSCFG_CFGCHIP3_ASYNC3_CLKSRC (0x00000010u) -#define SYSCFG_CFGCHIP3_ASYNC3_CLKSRC_SHIFT (0x00000004u) - -#define SYSCFG_CFGCHIP3_PRUEVTSEL (0x00000008u) -#define SYSCFG_CFGCHIP3_PRUEVTSEL_SHIFT (0x00000003u) - -#define SYSCFG_CFGCHIP3_DIV4P5ENA (0x00000004u) -#define SYSCFG_CFGCHIP3_DIV4P5ENA_SHIFT (0x00000002u) - -#define SYSCFG_CFGCHIP3_EMA_CLKSRC (0x00000002u) -#define SYSCFG_CFGCHIP3_EMA_CLKSRC_SHIFT (0x00000001u) - -#define SYSCFG_CFGCHIP4_AMUTECLR0 (0x00000001u) -#define SYSCFG_CFGCHIP4_AMUTECLR0_SHIFT (0x00000000u) - -#ifdef __cplusplus -} -#endif - -#endif /* _HW_SYSCFG1_H_ */ diff --git a/lib/tiam1808/tiam1808/hw/hw_syscfg0_OMAPL138.h b/lib/tiam1808/tiam1808/hw/hw_syscfg0_OMAPL138.h deleted file mode 100644 index 8d5cab01e..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_syscfg0_OMAPL138.h +++ /dev/null @@ -1,2167 +0,0 @@ -/** - * \name hw_syscfg0_OMAPL138.h - * - * \brief Hardware definitions for OMAPL138 - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _HW_SYSCFG0_H_ -#define _HW_SYSCFG0_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define SYSCFG0_REVID (0x0) -#define SYSCFG0_DIEIDR0 (0x8) -#define SYSCFG0_DIEIDR1 (0xC) -#define SYSCFG0_DIEIDR2 (0x10) -#define SYSCFG0_DIEIDR3 (0x14) -#define SYSCFG0_DEVIDR0 (0x18) -#define SYSCFG0_BOOTCFG (0x20) -#define SYSCFG0_KICK0R (0x38) -#define SYSCFG0_KICK1R (0x3C) -#define SYSCFG0_HOST0CFG (0x40) -#define SYSCFG0_HOST1CFG (0x44) -#define SYSCFG0_IRAWSTAT (0xE0) -#define SYSCFG0_IENSTAT (0xE4) -#define SYSCFG0_IENSET (0xE8) -#define SYSCFG0_IENCLR (0xEC) -#define SYSCFG0_EOI (0xF0) -#define SYSCFG0_FLTADDRR (0xF4) -#define SYSCFG0_FLTSTAT (0xF8) -#define SYSCFG0_MSTPRI0 (0x110) -#define SYSCFG0_MSTPRI1 (0x114) -#define SYSCFG0_MSTPRI2 (0x118) -#define SYSCFG0_PINMUX(n) (0x120 + (n * 4)) -#define SYSCFG0_SUSPSRC (0x170) -#define SYSCFG0_CHIPSIG (0x174) -#define SYSCFG0_CHIPSIG_CLR (0x178) -#define SYSCFG0_CFGCHIP0 (0x17C) -#define SYSCFG0_CFGCHIP1 (0x180) -#define SYSCFG0_CFGCHIP2 (0x184) -#define SYSCFG0_CFGCHIP3 (0x188) -#define SYSCFG0_CFGCHIP4 (0x18C) - -/**************************************************************************\ -* Field Definition Macros -\**************************************************************************/ - -/* REVID */ - -#define SYSCFG_REVID_REVID (0xFFFFFFFFu) -#define SYSCFG_REVID_REVID_SHIFT (0x00000000u) - - -/* DIEIDR0 */ - -#define SYSCFG_DIEIDR0_DIEID0 (0xFFFFFFFFu) -#define SYSCFG_DIEIDR0_DIEID0_SHIFT (0x00000000u) - - -/* DIEIDR1 */ - -#define SYSCFG_DIEIDR1_DIEID1 (0xFFFFFFFFu) -#define SYSCFG_DIEIDR1_DIEID1_SHIFT (0x00000000u) - - -/* DIEIDR2 */ - -#define SYSCFG_DIEIDR2_DIEID2 (0xFFFFFFFFu) -#define SYSCFG_DIEIDR2_DIEID2_SHIFT (0x00000000u) - - -/* DIEIDR3 */ - -#define SYSCFG_DIEIDR3_DIEID3 (0xFFFFFFFFu) -#define SYSCFG_DIEIDR3_DIEID3_SHIFT (0x00000000u) - - -/* DEVIDR0 */ - -#define SYSCFG_DEVIDR0_DEVID0 (0xFFFFFFFFu) -#define SYSCFG_DEVIDR0_DEVID0_SHIFT (0x00000000u) - - -/* BOOTCFG */ - - -#define SYSCFG_BOOTCFG_SMARTRFLX (0x0FFF0000u) -#define SYSCFG_BOOTCFG_SMARTRFLX_SHIFT (0x00000010u) - -#define SYSCFG_BOOTCFG_BOOTMODE (0x0000FFFFu) -#define SYSCFG_BOOTCFG_BOOTMODE_SHIFT (0x00000000u) - - -/* CHIPREVIDR */ - - -#define SYSCFG_CHIPREVIDR_CHIPREVID (0x0000003Fu) -#define SYSCFG_CHIPREVIDR_CHIPREVID_SHIFT (0x00000000u) - - -/* KICK0R */ - -#define SYSCFG_KICK0R_KICK0 (0xFFFFFFFFu) -#define SYSCFG_KICK0R_KICK0_SHIFT (0x00000000u) - -/* Unlock/Lock code for KICK0 */ -#define SYSCFG_KICK0R_UNLOCK (0x83E70B13u) - - -/* KICK1R */ - -#define SYSCFG_KICK1R_KICK1 (0xFFFFFFFFu) -#define SYSCFG_KICK1R_KICK1_SHIFT (0x00000000u) - -/* Unlock/Lock code for KICK1 */ -#define SYSCFG_KICK1R_UNLOCK (0x95A4F1E0u) - -/* HOST0CFG */ - -#define SYSCFG_HOST0CFG_BOOTRDY (0x80000000u) -#define SYSCFG_HOST0CFG_BOOTRDY_SHIFT (0x0000001Fu) - - - -/* HOST1CFG */ - -#define SYSCFG_HOST1CFG_DSP_ISTP_RST_VAL (0x003FFFFFu) -#define SYSCFG_HOST1CFG_DSP_ISTP_RST_VAL_SHIFT (0x0000000Au) - - -/* IRAWSTAT */ - - -#define SYSCFG_IRAWSTAT_ADDRERR (0x00000002u) -#define SYSCFG_IRAWSTAT_ADDRERR_SHIFT (0x00000001u) - -#define SYSCFG_IRAWSTAT_PROTERR (0x00000001u) -#define SYSCFG_IRAWSTAT_PROTERR_SHIFT (0x00000000u) - - -/* IENSTAT */ - - -#define SYSCFG_IENSTAT_ADDRERR (0x00000002u) -#define SYSCFG_IENSTAT_ADDRERR_SHIFT (0x00000001u) - -#define SYSCFG_IENSTAT_PROTERR (0x00000001u) -#define SYSCFG_IENSTAT_PROTERR_SHIFT (0x00000000u) - - -/* IENSET */ - - -#define SYSCFG_IENSET_ADDRERR_EN (0x00000002u) -#define SYSCFG_IENSET_ADDRERR_EN_SHIFT (0x00000001u) - -#define SYSCFG_IENSET_PROTERR_EN (0x00000001u) -#define SYSCFG_IENSET_PROTERR_EN_SHIFT (0x00000000u) - - -/* IENCLR */ - - -#define SYSCFG_IENCLR_ADDRERR_CLR (0x00000002u) -#define SYSCFG_IENCLR_ADDRERR_CLR_SHIFT (0x00000001u) - -#define SYSCFG_IENCLR_PROTERR_CLR (0x00000001u) -#define SYSCFG_IENCLR_PROTERR_CLR_SHIFT (0x00000000u) - - -/* EOI */ - - -#define SYSCFG_EOI_EOIVECT (0x000000FFu) -#define SYSCFG_EOI_EOIVECT_SHIFT (0x00000000u) - - -/* FLTADDRR */ - -#define SYSCFG_FLTADDRR_FLTADDR (0xFFFFFFFFu) -#define SYSCFG_FLTADDRR_FLTADDR_SHIFT (0x00000000u) - - -/* FLTSTAT */ - -#define SYSCFG_FLTSTAT_ID (0xFF000000u) -#define SYSCFG_FLTSTAT_ID_SHIFT (0x00000018u) - -#define SYSCFG_FLTSTAT_MSTID (0x00FF0000u) -#define SYSCFG_FLTSTAT_MSTID_SHIFT (0x00000010u) - - -#define SYSCFG_FLTSTAT_PRIVID (0x00001E00u) -#define SYSCFG_FLTSTAT_PRIVID_SHIFT (0x00000009u) - - -#define SYSCFG_FLTSTAT_NOSECACC (0x00000080u) -#define SYSCFG_FLTSTAT_NOSECACC_SHIFT (0x00000007u) - - -#define SYSCFG_FLTSTAT_TYPE (0x0000003Fu) -#define SYSCFG_FLTSTAT_TYPE_SHIFT (0x00000000u) -/*----TYPE Tokens----*/ -#define SYSCFG_FLTSTAT_TYPE_NOFLT (0x00000000u) -#define SYSCFG_FLTSTAT_TYPE_USREXE (0x00000001u) -#define SYSCFG_FLTSTAT_TYPE_USRWR (0x00000002u) -#define SYSCFG_FLTSTAT_TYPE_USRRD (0x00000004u) -#define SYSCFG_FLTSTAT_TYPE_SPREXE (0x00000008u) -#define SYSCFG_FLTSTAT_TYPE_SPRWR (0x00000010u) -#define SYSCFG_FLTSTAT_TYPE_SPRRD (0x00000020u) - - -/* MSTPRI0 */ - - -#define SYSCFG_MSTPRI0_SATA (0x00700000u) -#define SYSCFG_MSTPRI0_SATA_SHIFT (0x00000014u) - - -#define SYSCFG_MSTPRI0_UPP (0x00070000u) -#define SYSCFG_MSTPRI0_UPP_SHIFT (0x00000010u) - - -#define SYSCFG_MSTPRI0_DSP_CFG (0x00007000u) -#define SYSCFG_MSTPRI0_DSP_CFG_SHIFT (0x0000000Cu) - - -#define SYSCFG_MSTPRI0_DSP_MDMA (0x00000700u) -#define SYSCFG_MSTPRI0_DSP_MDMA_SHIFT (0x00000008u) - - -#define SYSCFG_MSTPRI0_ARM_D (0x00000070u) -#define SYSCFG_MSTPRI0_ARM_D_SHIFT (0x00000004u) - - -#define SYSCFG_MSTPRI0_ARM_I (0x00000007u) -#define SYSCFG_MSTPRI0_ARM_I_SHIFT (0x00000000u) - - -/* MSTPRI1 */ - - -#define SYSCFG_MSTPRI1_VPIF_DMA_1 (0x70000000u) -#define SYSCFG_MSTPRI1_VPIF_DMA_1_SHIFT (0x0000001Cu) - - -#define SYSCFG_MSTPRI1_VPIF_DMA_0 (0x07000000u) -#define SYSCFG_MSTPRI1_VPIF_DMA_0_SHIFT (0x00000018u) - - -#define SYSCFG_MSTPRI1_EDMA31TC0 (0x00070000u) -#define SYSCFG_MSTPRI1_EDMA31TC0_SHIFT (0x00000010u) - - -#define SYSCFG_MSTPRI1_EDMA30TC1 (0x00007000u) -#define SYSCFG_MSTPRI1_EDMA30TC1_SHIFT (0x0000000Cu) - - -#define SYSCFG_MSTPRI1_EDMA30TC0 (0x00000700u) -#define SYSCFG_MSTPRI1_EDMA30TC0_SHIFT (0x00000008u) - - -#define SYSCFG_MSTPRI1_PRU1 (0x00000070u) -#define SYSCFG_MSTPRI1_PRU1_SHIFT (0x00000004u) - - -#define SYSCFG_MSTPRI1_PRU0 (0x00000007u) -#define SYSCFG_MSTPRI1_PRU0_SHIFT (0x00000000u) - - -/* MSTPRI2 */ - - -#define SYSCFG_MSTPRI2_LCDC (0x70000000u) -#define SYSCFG_MSTPRI2_LCDC_SHIFT (0x0000001Cu) - - -#define SYSCFG_MSTPRI2_USB1 (0x07000000u) -#define SYSCFG_MSTPRI2_USB1_SHIFT (0x00000018u) - - -#define SYSCFG_MSTPRI2_UHPI (0x00700000u) -#define SYSCFG_MSTPRI2_UHPI_SHIFT (0x00000014u) - - -#define SYSCFG_MSTPRI2_USB0CDMA (0x00007000u) -#define SYSCFG_MSTPRI2_USB0CDMA_SHIFT (0x0000000Cu) - - -#define SYSCFG_MSTPRI2_USB0CFG (0x00000700u) -#define SYSCFG_MSTPRI2_USB0CFG_SHIFT (0x00000008u) - - -#define SYSCFG_MSTPRI2_EMAC (0x00000007u) -#define SYSCFG_MSTPRI2_EMAC_SHIFT (0x00000000u) - - -/* PINMUX0 */ - -#define SYSCFG_PINMUX0_PINMUX0_31_28 (0xF0000000u) -#define SYSCFG_PINMUX0_PINMUX0_31_28_SHIFT (0x0000001Cu) -/*----PINMUX0_31_28 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_31_28_RESERVED1 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_31_28_ALARM (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_31_28_UART2_CTS (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_31_28_GPIO0_8 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_27_24 (0x0F000000u) -#define SYSCFG_PINMUX0_PINMUX0_27_24_SHIFT (0x00000018u) -/*----PINMUX0_27_24 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_27_24_AMUTE0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_27_24_PRU0_R30_16 (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_27_24_UART2_RTS (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_27_24_GPIO0_9 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_23_20 (0x00F00000u) -#define SYSCFG_PINMUX0_PINMUX0_23_20_SHIFT (0x00000014u) -/*----PINMUX0_23_20 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_23_20_AHCLKX0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_23_20_USB_REFCLKIN (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_23_20_UART1_CTS (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_23_20_GPIO0_10 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_19_16 (0x000F0000u) -#define SYSCFG_PINMUX0_PINMUX0_19_16_SHIFT (0x00000010u) -/*----PINMUX0_19_16 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_19_16_AHCLKR0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_19_16_PRU0_R30_18 (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_19_16_UART1_RTS (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_19_16_GPIO0_11 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_15_12 (0x0000F000u) -#define SYSCFG_PINMUX0_PINMUX0_15_12_SHIFT (0x0000000Cu) -/*----PINMUX0_15_12 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_15_12_AFSX0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_15_12_OBSERVE0_LOS (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_15_12_GPIO0_12 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_11_8 (0x00000F00u) -#define SYSCFG_PINMUX0_PINMUX0_11_8_SHIFT (0x00000008u) -/*----PINMUX0_11_8 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_11_8_AFSR0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_11_8_OBSERVE0_SYNC (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_11_8_GPIO0_13 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_7_4 (0x000000F0u) -#define SYSCFG_PINMUX0_PINMUX0_7_4_SHIFT (0x00000004u) -/*----PINMUX0_7_4 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_7_4_ACLKX0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_7_4_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_7_4_PRU0_R30_19 (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_7_4_GPIO0_14 (0x00000008u) - -#define SYSCFG_PINMUX0_PINMUX0_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX0_PINMUX0_3_0_SHIFT (0x00000000u) -/*----PINMUX0_3_0 Tokens----*/ -#define SYSCFG_PINMUX0_PINMUX0_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX0_PINMUX0_3_0_ACLKR0 (0x00000001u) -#define SYSCFG_PINMUX0_PINMUX0_3_0_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX0_PINMUX0_3_0_PRU0_R30_20 (0x00000004u) -#define SYSCFG_PINMUX0_PINMUX0_3_0_GPIO0_15 (0x00000008u) - - -/* PINMUX1 */ - -#define SYSCFG_PINMUX1_PINMUX1_31_28 (0xF0000000u) -#define SYSCFG_PINMUX1_PINMUX1_31_28_SHIFT (0x0000001Cu) -/*----PINMUX1_31_28 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_31_28_AXR0_8 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_31_28_CLKS1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_31_28_ECAP1 (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_31_28_GPIO0_0 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_27_24 (0x0F000000u) -#define SYSCFG_PINMUX1_PINMUX1_27_24_SHIFT (0x00000018u) -/*----PINMUX1_27_24 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_27_24_AXR0_9 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_27_24_DX1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_27_24_OBSERVE0_PHY_STATE2 (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_27_24_GPIO0_1 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_23_20 (0x00F00000u) -#define SYSCFG_PINMUX1_PINMUX1_23_20_SHIFT (0x00000014u) -/*----PINMUX1_23_20 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_23_20_AXR0_10 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_23_20_DR1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_23_20_OBSERVE0_PHY_STATE1 (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_23_20_GPIO0_2 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_19_16 (0x000F0000u) -#define SYSCFG_PINMUX1_PINMUX1_19_16_SHIFT (0x00000010u) -/*----PINMUX1_19_16 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_19_16_AXR0_11 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_19_16_FSX1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_19_16_OBSERVE0_PHY_STATE0 (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_19_16_GPIO0_3 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_15_12 (0x0000F000u) -#define SYSCFG_PINMUX1_PINMUX1_15_12_SHIFT (0x0000000Cu) -/*----PINMUX1_15_12 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_15_12_AXR0_12 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_15_12_FSR1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_15_12_OBSERVE0_PHY_READY (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_15_12_GPIO0_4 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_11_8 (0x00000F00u) -#define SYSCFG_PINMUX1_PINMUX1_11_8_SHIFT (0x00000008u) -/*----PINMUX1_11_8 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_11_8_AXR0_13 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_11_8_CLKX1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_11_8_OBSERVE0_COMINIT (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_11_8_GPIO0_5 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_7_4 (0x000000F0u) -#define SYSCFG_PINMUX1_PINMUX1_7_4_SHIFT (0x00000004u) -/*----PINMUX1_7_4 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_7_4_AXR0_14 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_7_4_CLKR1 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_7_4_OBSERVE0_COMWAKE (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_7_4_GPIO0_6 (0x00000008u) - -#define SYSCFG_PINMUX1_PINMUX1_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX1_PINMUX1_3_0_SHIFT (0x00000000u) -/*----PINMUX1_3_0 Tokens----*/ -#define SYSCFG_PINMUX1_PINMUX1_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX1_PINMUX1_3_0_AXR0_15 (0x00000001u) -#define SYSCFG_PINMUX1_PINMUX1_3_0_EPWM0TZ0 (0x00000002u) -#define SYSCFG_PINMUX1_PINMUX1_3_0_ECAP2 (0x00000004u) -#define SYSCFG_PINMUX1_PINMUX1_3_0_GPIO0_7 (0x00000008u) - - -/* PINMUX2 */ - -#define SYSCFG_PINMUX2_PINMUX2_31_28 (0xF0000000u) -#define SYSCFG_PINMUX2_PINMUX2_31_28_SHIFT (0x0000001Cu) -/*----PINMUX2_31_28 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_31_28_AXR0_0 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_31_28_ECAP0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_31_28_GPIO8_7 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_31_28_MII_TXD0 (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_27_24 (0x0F000000u) -#define SYSCFG_PINMUX2_PINMUX2_27_24_SHIFT (0x00000018u) -/*----PINMUX2_27_24 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_27_24_AXR0_1 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_27_24_DX0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_27_24_GPIO1_9 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_27_24_MII_TXD1 (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_23_20 (0x00F00000u) -#define SYSCFG_PINMUX2_PINMUX2_23_20_SHIFT (0x00000014u) -/*----PINMUX2_23_20 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_23_20_AXR0_2 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_23_20_DR0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_23_20_GPIO1_10 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_23_20_MII_TXD2 (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_19_16 (0x000F0000u) -#define SYSCFG_PINMUX2_PINMUX2_19_16_SHIFT (0x00000010u) -/*----PINMUX2_19_16 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_19_16_AXR0_3 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_19_16_FSX0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_19_16_GPIO1_11 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_19_16_MII_TXD3 (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_15_12 (0x0000F000u) -#define SYSCFG_PINMUX2_PINMUX2_15_12_SHIFT (0x0000000Cu) -/*----PINMUX2_15_12 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_15_12_AXR0_4 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_15_12_FSR0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_15_12_GPIO1_12 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_15_12_MII_COL (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_11_8 (0x00000F00u) -#define SYSCFG_PINMUX2_PINMUX2_11_8_SHIFT (0x00000008u) -/*----PINMUX2_11_8 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_11_8_AXR0_5 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_11_8_CLKX0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_11_8_GPIO1_13 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_11_8_MII_TXCLK (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_7_4 (0x000000F0u) -#define SYSCFG_PINMUX2_PINMUX2_7_4_SHIFT (0x00000004u) -/*----PINMUX2_7_4 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_7_4_AXR0_6 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_7_4_CLKR0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_7_4_GPIO1_14 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_7_4_MII_TXEN (0x00000008u) - -#define SYSCFG_PINMUX2_PINMUX2_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX2_PINMUX2_3_0_SHIFT (0x00000000u) -/*----PINMUX2_3_0 Tokens----*/ -#define SYSCFG_PINMUX2_PINMUX2_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX2_PINMUX2_3_0_AXR0_7 (0x00000001u) -#define SYSCFG_PINMUX2_PINMUX2_3_0_EPWM1TZ0 (0x00000002u) -#define SYSCFG_PINMUX2_PINMUX2_3_0_PRU0_R30_17 (0x00000004u) -#define SYSCFG_PINMUX2_PINMUX2_3_0_GPIO1_15 (0x00000008u) - - -/* PINMUX3 */ - -#define SYSCFG_PINMUX3_PINMUX3_31_28 (0xF0000000u) -#define SYSCFG_PINMUX3_PINMUX3_31_28_SHIFT (0x0000001Cu) -/*----PINMUX3_31_28 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_31_28_NSPI0_SCS2 (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_31_28_UART0_RTS (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_31_28_GPIO8_1 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_31_28_MII_RXD0 (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_27_24 (0x0F000000u) -#define SYSCFG_PINMUX3_PINMUX3_27_24_SHIFT (0x00000018u) -/*----PINMUX3_27_24 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_27_24_NSPI0_SCS3 (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_27_24_UART0_CTS (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_27_24_GPIO8_2 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_27_24_MII_RXD1 (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_23_20 (0x00F00000u) -#define SYSCFG_PINMUX3_PINMUX3_23_20_SHIFT (0x00000014u) -/*----PINMUX3_23_20 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_23_20_NSPI0_SCS4 (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_23_20_UART0_TXD (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_23_20_GPIO8_3 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_23_20_MII_RXD2 (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_19_16 (0x000F0000u) -#define SYSCFG_PINMUX3_PINMUX3_19_16_SHIFT (0x00000010u) -/*----PINMUX3_19_16 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_19_16_NSPI0_SCS5 (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_19_16_UART0_RXD (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_19_16_GPIO8_4 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_19_16_MII_RXD3 (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_15_12 (0x0000F000u) -#define SYSCFG_PINMUX3_PINMUX3_15_12_SHIFT (0x0000000Cu) -/*----PINMUX3_15_12 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_15_12_SPI0_SIMO0 (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_15_12_EPWMSYNCO (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_15_12_GPIO8_5 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_15_12_MII_CRS (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_11_8 (0x00000F00u) -#define SYSCFG_PINMUX3_PINMUX3_11_8_SHIFT (0x00000008u) -/*----PINMUX3_11_8 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_11_8_SPI0_SOMI0 (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_11_8_EPWMSYNCI (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_11_8_GPIO8_6 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_11_8_MII_RXER (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_7_4 (0x000000F0u) -#define SYSCFG_PINMUX3_PINMUX3_7_4_SHIFT (0x00000004u) -/*----PINMUX3_7_4 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_7_4_NSPI0_ENA (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_7_4_EPWM0B (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_7_4_PRU0_R30_6 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_7_4_MII_RXDV (0x00000008u) - -#define SYSCFG_PINMUX3_PINMUX3_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX3_PINMUX3_3_0_SHIFT (0x00000000u) -/*----PINMUX3_3_0 Tokens----*/ -#define SYSCFG_PINMUX3_PINMUX3_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX3_PINMUX3_3_0_SPI0_CLK (0x00000001u) -#define SYSCFG_PINMUX3_PINMUX3_3_0_EPWM0A (0x00000002u) -#define SYSCFG_PINMUX3_PINMUX3_3_0_GPIO1_8 (0x00000004u) -#define SYSCFG_PINMUX3_PINMUX3_3_0_MII_RXCLK (0x00000008u) - - -/* PINMUX4 */ - -#define SYSCFG_PINMUX4_PINMUX4_31_28 (0xF0000000u) -#define SYSCFG_PINMUX4_PINMUX4_31_28_SHIFT (0x0000001Cu) -/*----PINMUX4_31_28 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_31_28_NSPI1_SCS2 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_31_28_UART1_TXD (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_31_28_CP_POD (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_31_28_GPIO1_0 (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_27_24 (0x0F000000u) -#define SYSCFG_PINMUX4_PINMUX4_27_24_SHIFT (0x00000018u) -/*----PINMUX4_27_24 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_27_24_NSPI1_SCS3 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_27_24_UART1_RXD (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_27_24_LED (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_27_24_GPIO1_1 (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_23_20 (0x00F00000u) -#define SYSCFG_PINMUX4_PINMUX4_23_20_SHIFT (0x00000014u) -/*----PINMUX4_23_20 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_23_20_NSPI1_SCS4 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_23_20_UART2_TXD (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_23_20_I2C1_SDA (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_23_20_GPIO1_2 (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_19_16 (0x000F0000u) -#define SYSCFG_PINMUX4_PINMUX4_19_16_SHIFT (0x00000010u) -/*----PINMUX4_19_16 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_19_16_NSPI1_SCS5 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_19_16_UART2_RXD (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_19_16_I2C1_SCL (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_19_16_GPIO1_3 (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_15_12 (0x0000F000u) -#define SYSCFG_PINMUX4_PINMUX4_15_12_SHIFT (0x0000000Cu) -/*----PINMUX4_15_12 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_15_12_NSPI1_SCS6 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_15_12_I2C0_SDA (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_15_12_TM64P3_OUT12 (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_15_12_GPIO1_4 (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_11_8 (0x00000F00u) -#define SYSCFG_PINMUX4_PINMUX4_11_8_SHIFT (0x00000008u) -/*----PINMUX4_11_8 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_11_8_NSPI1_SCS7 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_11_8_I2C0_SCL (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_11_8_TM64P2_OUT12 (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_11_8_GPIO1_5 (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_7_4 (0x000000F0u) -#define SYSCFG_PINMUX4_PINMUX4_7_4_SHIFT (0x00000004u) -/*----PINMUX4_7_4 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_7_4_NSPI0_SCS0 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_7_4_TM64P1_OUT12 (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_7_4_GPIO1_6 (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_7_4_MDIO_D (0x00000008u) - -#define SYSCFG_PINMUX4_PINMUX4_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX4_PINMUX4_3_0_SHIFT (0x00000000u) -/*----PINMUX4_3_0 Tokens----*/ -#define SYSCFG_PINMUX4_PINMUX4_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX4_PINMUX4_3_0_NSPI0_SCS1 (0x00000001u) -#define SYSCFG_PINMUX4_PINMUX4_3_0_TM64P0_OUT12 (0x00000002u) -#define SYSCFG_PINMUX4_PINMUX4_3_0_GPIO1_7 (0x00000004u) -#define SYSCFG_PINMUX4_PINMUX4_3_0_MDIO_CLK (0x00000008u) - - -/* PINMUX5 */ - -#define SYSCFG_PINMUX5_PINMUX5_31_28 (0xF0000000u) -#define SYSCFG_PINMUX5_PINMUX5_31_28_SHIFT (0x0000001Cu) -/*----PINMUX5_31_28 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_31_28_EMA_BA0 (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_31_28_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_31_28_GPIO2_8 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_27_24 (0x0F000000u) -#define SYSCFG_PINMUX5_PINMUX5_27_24_SHIFT (0x00000018u) -/*----PINMUX5_27_24 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_27_24_EMA_BA1 (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_27_24_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_27_24_GPIO2_9 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_23_20 (0x00F00000u) -#define SYSCFG_PINMUX5_PINMUX5_23_20_SHIFT (0x00000014u) -/*----PINMUX5_23_20 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_23_20_SPI1_SIMO0 (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_23_20_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_23_20_GPIO2_10 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_19_16 (0x000F0000u) -#define SYSCFG_PINMUX5_PINMUX5_19_16_SHIFT (0x00000010u) -/*----PINMUX5_19_16 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_19_16_SPI1_SOMI0 (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_19_16_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_19_16_GPIO2_11 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_15_12 (0x0000F000u) -#define SYSCFG_PINMUX5_PINMUX5_15_12_SHIFT (0x0000000Cu) -/*----PINMUX5_15_12 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_15_12_NSPI1_ENA (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_15_12_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_15_12_GPIO2_12 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_11_8 (0x00000F00u) -#define SYSCFG_PINMUX5_PINMUX5_11_8_SHIFT (0x00000008u) -/*----PINMUX5_11_8 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_11_8_SPI1_CLK (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_11_8_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_11_8_GPIO2_13 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_7_4 (0x000000F0u) -#define SYSCFG_PINMUX5_PINMUX5_7_4_SHIFT (0x00000004u) -/*----PINMUX5_7_4 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_7_4_NSPI1_SCS0 (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_7_4_EPWM1B (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_7_4_PRU0_R30_7 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_7_4_GPIO2_14 (0x00000008u) - -#define SYSCFG_PINMUX5_PINMUX5_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX5_PINMUX5_3_0_SHIFT (0x00000000u) -/*----PINMUX5_3_0 Tokens----*/ -#define SYSCFG_PINMUX5_PINMUX5_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX5_PINMUX5_3_0_NSPI1_SCS1 (0x00000001u) -#define SYSCFG_PINMUX5_PINMUX5_3_0_EPWM1A (0x00000002u) -#define SYSCFG_PINMUX5_PINMUX5_3_0_PRU0_R30_8 (0x00000004u) -#define SYSCFG_PINMUX5_PINMUX5_3_0_GPIO2_15 (0x00000008u) - - -/* PINMUX6 */ - -#define SYSCFG_PINMUX6_PINMUX6_31_28 (0xF0000000u) -#define SYSCFG_PINMUX6_PINMUX6_31_28_SHIFT (0x0000001Cu) -/*----PINMUX6_31_28 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_31_28_NEMA_CS0 (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_31_28_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_31_28_GPIO2_0 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_27_24 (0x0F000000u) -#define SYSCFG_PINMUX6_PINMUX6_27_24_SHIFT (0x00000018u) -/*----PINMUX6_27_24 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_27_24_EMA_WAIT1 (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_27_24_PRU0_R30_1 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_27_24_GPIO2_1 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_23_20 (0x00F00000u) -#define SYSCFG_PINMUX6_PINMUX6_23_20_SHIFT (0x00000014u) -/*----PINMUX6_23_20 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_23_20_NEMA_WE_DQM1 (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_23_20_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_23_20_GPIO2_2 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_19_16 (0x000F0000u) -#define SYSCFG_PINMUX6_PINMUX6_19_16_SHIFT (0x00000010u) -/*----PINMUX6_19_16 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_19_16_NEMA_WE_DQM0 (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_19_16_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_19_16_GPIO2_3 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_15_12 (0x0000F000u) -#define SYSCFG_PINMUX6_PINMUX6_15_12_SHIFT (0x0000000Cu) -/*----PINMUX6_15_12 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_15_12_NEMA_CAS (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_15_12_PRU0_R30_2 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_15_12_GPIO2_4 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_11_8 (0x00000F00u) -#define SYSCFG_PINMUX6_PINMUX6_11_8_SHIFT (0x00000008u) -/*----PINMUX6_11_8 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_11_8_NEMA_RAS (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_11_8_PRU0_R30_3 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_11_8_GPIO2_5 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_7_4 (0x000000F0u) -#define SYSCFG_PINMUX6_PINMUX6_7_4_SHIFT (0x00000004u) -/*----PINMUX6_7_4 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_7_4_EMA_SDCKE (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_7_4_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_7_4_PRU0_R30_4 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_7_4_GPIO2_6 (0x00000008u) - -#define SYSCFG_PINMUX6_PINMUX6_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX6_PINMUX6_3_0_SHIFT (0x00000000u) -/*----PINMUX6_3_0 Tokens----*/ -#define SYSCFG_PINMUX6_PINMUX6_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX6_PINMUX6_3_0_EMA_CLK (0x00000001u) -#define SYSCFG_PINMUX6_PINMUX6_3_0_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX6_PINMUX6_3_0_PRU0_R30_5 (0x00000004u) -#define SYSCFG_PINMUX6_PINMUX6_3_0_GPIO2_7 (0x00000008u) - - -/* PINMUX7 */ - -#define SYSCFG_PINMUX7_PINMUX7_31_28 (0xF0000000u) -#define SYSCFG_PINMUX7_PINMUX7_31_28_SHIFT (0x0000001Cu) -/*----PINMUX7_31_28 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_31_28_EMA_WAIT0 (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_31_28_PRU0_R30_0 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_31_28_GPIO3_8 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_27_24 (0x0F000000u) -#define SYSCFG_PINMUX7_PINMUX7_27_24_SHIFT (0x00000018u) -/*----PINMUX7_27_24 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_27_24_NEMA_RNW (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_27_24_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_27_24_GPIO3_9 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_23_20 (0x00F00000u) -#define SYSCFG_PINMUX7_PINMUX7_23_20_SHIFT (0x00000014u) -/*----PINMUX7_23_20 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_23_20_NEMA_OE (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_23_20_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_23_20_GPIO3_10 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_19_16 (0x000F0000u) -#define SYSCFG_PINMUX7_PINMUX7_19_16_SHIFT (0x00000010u) -/*----PINMUX7_19_16 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_19_16_NEMA_WE (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_19_16_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_19_16_GPIO3_11 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_15_12 (0x0000F000u) -#define SYSCFG_PINMUX7_PINMUX7_15_12_SHIFT (0x0000000Cu) -/*----PINMUX7_15_12 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_15_12_NEMA_CS5 (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_15_12_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_15_12_GPIO3_12 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_11_8 (0x00000F00u) -#define SYSCFG_PINMUX7_PINMUX7_11_8_SHIFT (0x00000008u) -/*----PINMUX7_11_8 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_11_8_NEMA_CS4 (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_11_8_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_11_8_GPIO3_13 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_7_4 (0x000000F0u) -#define SYSCFG_PINMUX7_PINMUX7_7_4_SHIFT (0x00000004u) -/*----PINMUX7_7_4 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_7_4_NEMA_CS3 (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_7_4_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_7_4_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_7_4_GPIO3_14 (0x00000008u) - -#define SYSCFG_PINMUX7_PINMUX7_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX7_PINMUX7_3_0_SHIFT (0x00000000u) -/*----PINMUX7_3_0 Tokens----*/ -#define SYSCFG_PINMUX7_PINMUX7_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX7_PINMUX7_3_0_NEMA_CS2 (0x00000001u) -#define SYSCFG_PINMUX7_PINMUX7_3_0_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX7_PINMUX7_3_0_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX7_PINMUX7_3_0_GPIO3_15 (0x00000008u) - - -/* PINMUX8 */ - -#define SYSCFG_PINMUX8_PINMUX8_31_28 (0xF0000000u) -#define SYSCFG_PINMUX8_PINMUX8_31_28_SHIFT (0x0000001Cu) -/*----PINMUX8_31_28 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_31_28_EMA_D8 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_31_28_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_31_28_GPIO3_0 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_27_24 (0x0F000000u) -#define SYSCFG_PINMUX8_PINMUX8_27_24_SHIFT (0x00000018u) -/*----PINMUX8_27_24 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_27_24_EMA_D9 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_27_24_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_27_24_GPIO3_1 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_23_20 (0x00F00000u) -#define SYSCFG_PINMUX8_PINMUX8_23_20_SHIFT (0x00000014u) -/*----PINMUX8_23_20 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_23_20_EMA_D10 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_23_20_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_23_20_GPIO3_2 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_19_16 (0x000F0000u) -#define SYSCFG_PINMUX8_PINMUX8_19_16_SHIFT (0x00000010u) -/*----PINMUX8_19_16 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_19_16_EMA_D11 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_19_16_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_19_16_GPIO3_3 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_15_12 (0x0000F000u) -#define SYSCFG_PINMUX8_PINMUX8_15_12_SHIFT (0x0000000Cu) -/*----PINMUX8_15_12 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_15_12_EMA_D12 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_15_12_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_15_12_GPIO3_4 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_11_8 (0x00000F00u) -#define SYSCFG_PINMUX8_PINMUX8_11_8_SHIFT (0x00000008u) -/*----PINMUX8_11_8 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_11_8_EMA_D13 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_11_8_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_11_8_GPIO3_5 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_7_4 (0x000000F0u) -#define SYSCFG_PINMUX8_PINMUX8_7_4_SHIFT (0x00000004u) -/*----PINMUX8_7_4 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_7_4_EMA_D14 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_7_4_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_7_4_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_7_4_GPIO3_6 (0x00000008u) - -#define SYSCFG_PINMUX8_PINMUX8_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX8_PINMUX8_3_0_SHIFT (0x00000000u) -/*----PINMUX8_3_0 Tokens----*/ -#define SYSCFG_PINMUX8_PINMUX8_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX8_PINMUX8_3_0_EMA_D15 (0x00000001u) -#define SYSCFG_PINMUX8_PINMUX8_3_0_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX8_PINMUX8_3_0_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX8_PINMUX8_3_0_GPIO3_7 (0x00000008u) - - -/* PINMUX9 */ - -#define SYSCFG_PINMUX9_PINMUX9_31_28 (0xF0000000u) -#define SYSCFG_PINMUX9_PINMUX9_31_28_SHIFT (0x0000001Cu) -/*----PINMUX9_31_28 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_31_28_EMA_D0 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_31_28_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_31_28_GPIO4_8 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_27_24 (0x0F000000u) -#define SYSCFG_PINMUX9_PINMUX9_27_24_SHIFT (0x00000018u) -/*----PINMUX9_27_24 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_27_24_EMA_D1 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_27_24_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_27_24_GPIO4_9 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_23_20 (0x00F00000u) -#define SYSCFG_PINMUX9_PINMUX9_23_20_SHIFT (0x00000014u) -/*----PINMUX9_23_20 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_23_20_EMA_D2 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_23_20_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_23_20_GPIO4_10 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_19_16 (0x000F0000u) -#define SYSCFG_PINMUX9_PINMUX9_19_16_SHIFT (0x00000010u) -/*----PINMUX9_19_16 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_19_16_EMA_D3 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_19_16_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_19_16_GPIO4_11 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_15_12 (0x0000F000u) -#define SYSCFG_PINMUX9_PINMUX9_15_12_SHIFT (0x0000000Cu) -/*----PINMUX9_15_12 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_15_12_EMA_D4 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_15_12_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_15_12_GPIO4_12 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_11_8 (0x00000F00u) -#define SYSCFG_PINMUX9_PINMUX9_11_8_SHIFT (0x00000008u) -/*----PINMUX9_11_8 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_11_8_EMA_D5 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_11_8_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_11_8_GPIO4_13 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_7_4 (0x000000F0u) -#define SYSCFG_PINMUX9_PINMUX9_7_4_SHIFT (0x00000004u) -/*----PINMUX9_7_4 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_7_4_EMA_D6 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_7_4_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_7_4_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_7_4_GPIO4_14 (0x00000008u) - -#define SYSCFG_PINMUX9_PINMUX9_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX9_PINMUX9_3_0_SHIFT (0x00000000u) -/*----PINMUX9_3_0 Tokens----*/ -#define SYSCFG_PINMUX9_PINMUX9_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX9_PINMUX9_3_0_EMA_D7 (0x00000001u) -#define SYSCFG_PINMUX9_PINMUX9_3_0_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX9_PINMUX9_3_0_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX9_PINMUX9_3_0_GPIO4_15 (0x00000008u) - - -/* PINMUX10 */ - -#define SYSCFG_PINMUX10_PINMUX10_31_28 (0xF0000000u) -#define SYSCFG_PINMUX10_PINMUX10_31_28_SHIFT (0x0000001Cu) -/*----PINMUX10_31_28 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_31_28_EMA_A16 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_31_28_MMCSD0_DAT5 (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_31_28_PRU1_R30_24 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_31_28_GPIO4_0 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_27_24 (0x0F000000u) -#define SYSCFG_PINMUX10_PINMUX10_27_24_SHIFT (0x00000018u) -/*----PINMUX10_27_24 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_27_24_EMA_A17 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_27_24_MMCSD0_DAT4 (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_27_24_PRU1_R30_25 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_27_24_GPIO4_1 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_23_20 (0x00F00000u) -#define SYSCFG_PINMUX10_PINMUX10_23_20_SHIFT (0x00000014u) -/*----PINMUX10_23_20 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_23_20_EMA_A18 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_23_20_MMCSD0_DAT3 (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_23_20_PRU1_R30_26 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_23_20_GPIO4_2 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_19_16 (0x000F0000u) -#define SYSCFG_PINMUX10_PINMUX10_19_16_SHIFT (0x00000010u) -/*----PINMUX10_19_16 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_19_16_EMA_A19 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_19_16_MMCSD0_DAT2 (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_19_16_PRU1_R30_27 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_19_16_GPIO4_3 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_15_12 (0x0000F000u) -#define SYSCFG_PINMUX10_PINMUX10_15_12_SHIFT (0x0000000Cu) -/*----PINMUX10_15_12 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_15_12_EMA_A20 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_15_12_MMCSD0_DAT1 (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_15_12_PRU1_R30_28 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_15_12_GPIO4_4 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_11_8 (0x00000F00u) -#define SYSCFG_PINMUX10_PINMUX10_11_8_SHIFT (0x00000008u) -/*----PINMUX10_11_8 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_11_8_EMA_A21 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_11_8_MMCSD0_DAT0 (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_11_8_PRU1_R30_29 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_11_8_GPIO4_5 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_7_4 (0x000000F0u) -#define SYSCFG_PINMUX10_PINMUX10_7_4_SHIFT (0x00000004u) -/*----PINMUX10_7_4 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_7_4_EMA_A22 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_7_4_MMCSD0_CMD (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_7_4_PRU1_R30_30 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_7_4_GPIO4_6 (0x00000008u) - -#define SYSCFG_PINMUX10_PINMUX10_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX10_PINMUX10_3_0_SHIFT (0x00000000u) -/*----PINMUX10_3_0 Tokens----*/ -#define SYSCFG_PINMUX10_PINMUX10_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX10_PINMUX10_3_0_EMA_A23 (0x00000001u) -#define SYSCFG_PINMUX10_PINMUX10_3_0_MMCSD0_CLK (0x00000002u) -#define SYSCFG_PINMUX10_PINMUX10_3_0_PRU1_R30_31 (0x00000004u) -#define SYSCFG_PINMUX10_PINMUX10_3_0_GPIO4_7 (0x00000008u) - - -/* PINMUX11 */ - -#define SYSCFG_PINMUX11_PINMUX11_31_28 (0xF0000000u) -#define SYSCFG_PINMUX11_PINMUX11_31_28_SHIFT (0x0000001Cu) -/*----PINMUX11_31_28 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_31_28_EMA_A8 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_31_28_PRU1_R30_16 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_31_28_GPIO5_8 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_27_24 (0x0F000000u) -#define SYSCFG_PINMUX11_PINMUX11_27_24_SHIFT (0x00000018u) -/*----PINMUX11_27_24 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_27_24_EMA_A9 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_27_24_PRU1_R30_17 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_27_24_GPIO5_9 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_23_20 (0x00F00000u) -#define SYSCFG_PINMUX11_PINMUX11_23_20_SHIFT (0x00000014u) -/*----PINMUX11_23_20 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_23_20_EMA_A10 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_23_20_PRU1_R30_18 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_23_20_GPIO5_10 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_19_16 (0x000F0000u) -#define SYSCFG_PINMUX11_PINMUX11_19_16_SHIFT (0x00000010u) -/*----PINMUX11_19_16 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_19_16_EMA_A11 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_19_16_PRU1_R30_19 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_19_16_GPIO5_11 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_15_12 (0x0000F000u) -#define SYSCFG_PINMUX11_PINMUX11_15_12_SHIFT (0x0000000Cu) -/*----PINMUX11_15_12 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_15_12_EMA_A12 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_15_12_PRU1_R30_20 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_15_12_GPIO5_12 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_11_8 (0x00000F00u) -#define SYSCFG_PINMUX11_PINMUX11_11_8_SHIFT (0x00000008u) -/*----PINMUX11_11_8 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_11_8_EMA_A13 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_11_8_PRU0_R30_21 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_11_8_PRU1_R30_21 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_11_8_GPIO5_13 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_7_4 (0x000000F0u) -#define SYSCFG_PINMUX11_PINMUX11_7_4_SHIFT (0x00000004u) -/*----PINMUX11_7_4 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_7_4_EMA_A14 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_7_4_MMCSD0_DAT7 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_7_4_PRU1_R30_22 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_7_4_GPIO5_14 (0x00000008u) - -#define SYSCFG_PINMUX11_PINMUX11_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX11_PINMUX11_3_0_SHIFT (0x00000000u) -/*----PINMUX11_3_0 Tokens----*/ -#define SYSCFG_PINMUX11_PINMUX11_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX11_PINMUX11_3_0_EMA_A15 (0x00000001u) -#define SYSCFG_PINMUX11_PINMUX11_3_0_MMCSD0_DAT6 (0x00000002u) -#define SYSCFG_PINMUX11_PINMUX11_3_0_PRU1_R30_23 (0x00000004u) -#define SYSCFG_PINMUX11_PINMUX11_3_0_GPIO5_15 (0x00000008u) - - -/* PINMUX12 */ - -#define SYSCFG_PINMUX12_PINMUX12_31_28 (0xF0000000u) -#define SYSCFG_PINMUX12_PINMUX12_31_28_SHIFT (0x0000001Cu) -/*----PINMUX12_31_28 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_31_28_EMA_A0 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_31_28_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_31_28_GPIO5_0 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_27_24 (0x0F000000u) -#define SYSCFG_PINMUX12_PINMUX12_27_24_SHIFT (0x00000018u) -/*----PINMUX12_27_24 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_27_24_EMA_A1 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_27_24_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_27_24_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_27_24_GPIO5_1 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_23_20 (0x00F00000u) -#define SYSCFG_PINMUX12_PINMUX12_23_20_SHIFT (0x00000014u) -/*----PINMUX12_23_20 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_23_20_EMA_A2 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_23_20_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_23_20_GPIO5_2 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_19_16 (0x000F0000u) -#define SYSCFG_PINMUX12_PINMUX12_19_16_SHIFT (0x00000010u) -/*----PINMUX12_19_16 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_19_16_EMA_A3 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_19_16_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_19_16_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_19_16_GPIO5_3 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_15_12 (0x0000F000u) -#define SYSCFG_PINMUX12_PINMUX12_15_12_SHIFT (0x0000000Cu) -/*----PINMUX12_15_12 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_15_12_EMA_A4 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_15_12_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_15_12_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_15_12_GPIO5_4 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_11_8 (0x00000F00u) -#define SYSCFG_PINMUX12_PINMUX12_11_8_SHIFT (0x00000008u) -/*----PINMUX12_11_8 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_11_8_EMA_A5 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_11_8_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_11_8_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_11_8_GPIO5_5 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_7_4 (0x000000F0u) -#define SYSCFG_PINMUX12_PINMUX12_7_4_SHIFT (0x00000004u) -/*----PINMUX12_7_4 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_7_4_EMA_A6 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_7_4_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_7_4_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_7_4_GPIO5_6 (0x00000008u) - -#define SYSCFG_PINMUX12_PINMUX12_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX12_PINMUX12_3_0_SHIFT (0x00000000u) -/*----PINMUX12_3_0 Tokens----*/ -#define SYSCFG_PINMUX12_PINMUX12_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX12_PINMUX12_3_0_EMA_A7 (0x00000001u) -#define SYSCFG_PINMUX12_PINMUX12_3_0_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX12_PINMUX12_3_0_PRU1_R30_15 (0x00000004u) -#define SYSCFG_PINMUX12_PINMUX12_3_0_GPIO5_7 (0x00000008u) - - -/* PINMUX13 */ - -#define SYSCFG_PINMUX13_PINMUX13_31_28 (0xF0000000u) -#define SYSCFG_PINMUX13_PINMUX13_31_28_SHIFT (0x0000001Cu) -/*----PINMUX13_31_28 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_31_28_PRU0_R30_26 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_31_28_UHPI_HRNW (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_31_28_CH1_WAIT (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_31_28_GPIO6_8 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_27_24 (0x0F000000u) -#define SYSCFG_PINMUX13_PINMUX13_27_24_SHIFT (0x00000018u) -/*----PINMUX13_27_24 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_27_24_PRU0_R30_27 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_27_24_UHPI_HHWIL (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_27_24_GPIO6_9 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_23_20 (0x00F00000u) -#define SYSCFG_PINMUX13_PINMUX13_23_20_SHIFT (0x00000014u) -/*----PINMUX13_23_20 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_23_20_PRU0_R30_28 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_23_20_UHPI_HCNTL1 (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_23_20_CH1_START (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_23_20_GPIO6_10 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_19_16 (0x000F0000u) -#define SYSCFG_PINMUX13_PINMUX13_19_16_SHIFT (0x00000010u) -/*----PINMUX13_19_16 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_19_16_PRU0_R30_29 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_19_16_UHPI_HCNTL0 (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_19_16_CH1_CLK (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_19_16_GPIO6_11 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_15_12 (0x0000F000u) -#define SYSCFG_PINMUX13_PINMUX13_15_12_SHIFT (0x0000000Cu) -/*----PINMUX13_15_12 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_15_12_PRU0_R30_30 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_15_12_NUHPI_HINT (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_15_12_PRU1_R30_11 (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_15_12_GPIO6_12 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_11_8 (0x00000F00u) -#define SYSCFG_PINMUX13_PINMUX13_11_8_SHIFT (0x00000008u) -/*----PINMUX13_11_8 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_11_8_PRU0_R30_31 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_11_8_NUHPI_HRDY (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_11_8_PRU1_R30_12 (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_11_8_GPIO6_13 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_7_4 (0x000000F0u) -#define SYSCFG_PINMUX13_PINMUX13_7_4_SHIFT (0x00000004u) -/*----PINMUX13_7_4 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_7_4_OBSCLK0 (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_7_4_NUHPI_HDS2 (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_7_4_PRU1_R30_13 (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_7_4_GPIO6_14 (0x00000008u) - -#define SYSCFG_PINMUX13_PINMUX13_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX13_PINMUX13_3_0_SHIFT (0x00000000u) -/*----PINMUX13_3_0 Tokens----*/ -#define SYSCFG_PINMUX13_PINMUX13_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX13_PINMUX13_3_0_NRESETOUT (0x00000001u) -#define SYSCFG_PINMUX13_PINMUX13_3_0_NUHPI_HAS (0x00000002u) -#define SYSCFG_PINMUX13_PINMUX13_3_0_PRU1_R30_14 (0x00000004u) -#define SYSCFG_PINMUX13_PINMUX13_3_0_GPIO6_15 (0x00000008u) - - -/* PINMUX14 */ - -#define SYSCFG_PINMUX14_PINMUX14_31_28 (0xF0000000u) -#define SYSCFG_PINMUX14_PINMUX14_31_28_SHIFT (0x0000001Cu) -/*----PINMUX14_31_28 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_31_28_DIN2 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_31_28_UHPI_HD10 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_31_28_UPP_D10 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_31_28_RMII_RXER (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_27_24 (0x0F000000u) -#define SYSCFG_PINMUX14_PINMUX14_27_24_SHIFT (0x00000018u) -/*----PINMUX14_27_24 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_27_24_DIN3 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_27_24_UHPI_HD11 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_27_24_UPP_D11 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_27_24_RMII_RXD0 (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_23_20 (0x00F00000u) -#define SYSCFG_PINMUX14_PINMUX14_23_20_SHIFT (0x00000014u) -/*----PINMUX14_23_20 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_23_20_DIN4 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_23_20_UHPI_HD12 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_23_20_UPP_D12 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_23_20_RMII_RXD1 (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_19_16 (0x000F0000u) -#define SYSCFG_PINMUX14_PINMUX14_19_16_SHIFT (0x00000010u) -/*----PINMUX14_19_16 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_19_16_DIN5 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_19_16_UHPI_HD13 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_19_16_UPP_D13 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_19_16_RMII_TXEN (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_15_12 (0x0000F000u) -#define SYSCFG_PINMUX14_PINMUX14_15_12_SHIFT (0x0000000Cu) -/*----PINMUX14_15_12 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_15_12_DIN6 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_15_12_UHPI_HD14 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_15_12_UPP_D14 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_15_12_RMII_TXD0 (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_11_8 (0x00000F00u) -#define SYSCFG_PINMUX14_PINMUX14_11_8_SHIFT (0x00000008u) -/*----PINMUX14_11_8 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_11_8_DIN7 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_11_8_UHPI_HD15 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_11_8_UPP_D15 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_11_8_RMII_TXD1 (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_7_4 (0x000000F0u) -#define SYSCFG_PINMUX14_PINMUX14_7_4_SHIFT (0x00000004u) -/*----PINMUX14_7_4 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_7_4_CLKIN1 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_7_4_NUHPI_HDS1 (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_7_4_PRU1_R30_9 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_7_4_GPIO6_6 (0x00000008u) - -#define SYSCFG_PINMUX14_PINMUX14_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX14_PINMUX14_3_0_SHIFT (0x00000000u) -/*----PINMUX14_3_0 Tokens----*/ -#define SYSCFG_PINMUX14_PINMUX14_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX14_PINMUX14_3_0_CLKIN0 (0x00000001u) -#define SYSCFG_PINMUX14_PINMUX14_3_0_NUHPI_HCS (0x00000002u) -#define SYSCFG_PINMUX14_PINMUX14_3_0_PRU1_R30_10 (0x00000004u) -#define SYSCFG_PINMUX14_PINMUX14_3_0_GPIO6_7 (0x00000008u) - - -/* PINMUX15 */ - -#define SYSCFG_PINMUX15_PINMUX15_31_28 (0xF0000000u) -#define SYSCFG_PINMUX15_PINMUX15_31_28_SHIFT (0x0000001Cu) -/*----PINMUX15_31_28 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_31_28_DIN10 (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_31_28_UHPI_HD2 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_31_28_UPP_D2 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_31_28_PRU0_R30_10 (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_27_24 (0x0F000000u) -#define SYSCFG_PINMUX15_PINMUX15_27_24_SHIFT (0x00000018u) -/*----PINMUX15_27_24 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_27_24_DIN11 (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_27_24_UHPI_HD3 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_27_24_UPP_D3 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_27_24_PRU0_R30_11 (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_23_20 (0x00F00000u) -#define SYSCFG_PINMUX15_PINMUX15_23_20_SHIFT (0x00000014u) -/*----PINMUX15_23_20 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_23_20_DIN12 (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_23_20_UHPI_HD4 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_23_20_UPP_D4 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_23_20_PRU0_R30_12 (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_19_16 (0x000F0000u) -#define SYSCFG_PINMUX15_PINMUX15_19_16_SHIFT (0x00000010u) -/*----PINMUX15_19_16 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_19_16_DIN13_FIELD (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_19_16_UHPI_HD5 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_19_16_UPP_D5 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_19_16_PRU0_R30_13 (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_15_12 (0x0000F000u) -#define SYSCFG_PINMUX15_PINMUX15_15_12_SHIFT (0x0000000Cu) -/*----PINMUX15_15_12 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_15_12_DIN14_HSYNC (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_15_12_UHPI_HD6 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_15_12_UPP_D6 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_15_12_PRU0_R30_14 (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_11_8 (0x00000F00u) -#define SYSCFG_PINMUX15_PINMUX15_11_8_SHIFT (0x00000008u) -/*----PINMUX15_11_8 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_11_8_DIN15_VSYNC (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_11_8_UHPI_HD7 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_11_8_UPP_D7 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_11_8_PRU0_R30_15 (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_7_4 (0x000000F0u) -#define SYSCFG_PINMUX15_PINMUX15_7_4_SHIFT (0x00000004u) -/*----PINMUX15_7_4 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_7_4_DIN0 (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_7_4_UHPI_HD8 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_7_4_UPP_D8 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_7_4_RMII_CRS_DV (0x00000008u) - -#define SYSCFG_PINMUX15_PINMUX15_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX15_PINMUX15_3_0_SHIFT (0x00000000u) -/*----PINMUX15_3_0 Tokens----*/ -#define SYSCFG_PINMUX15_PINMUX15_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX15_PINMUX15_3_0_DIN1 (0x00000001u) -#define SYSCFG_PINMUX15_PINMUX15_3_0_UHPI_HD9 (0x00000002u) -#define SYSCFG_PINMUX15_PINMUX15_3_0_UPP_D9 (0x00000004u) -#define SYSCFG_PINMUX15_PINMUX15_3_0_RMII_MHZ_50_CLK (0x00000008u) - - -/* PINMUX16 */ - -#define SYSCFG_PINMUX16_PINMUX16_31_28 (0xF0000000u) -#define SYSCFG_PINMUX16_PINMUX16_31_28_SHIFT (0x0000001Cu) -/*----PINMUX16_31_28 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_31_28_DOUT2 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_31_28_LCD_D2 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_31_28_UPP_XD10 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_31_28_GPIO7_10 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_27_24 (0x0F000000u) -#define SYSCFG_PINMUX16_PINMUX16_27_24_SHIFT (0x00000018u) -/*----PINMUX16_27_24 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_27_24_DOUT3 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_27_24_LCD_D3 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_27_24_UPP_XD11 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_27_24_GPIO7_11 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_23_20 (0x00F00000u) -#define SYSCFG_PINMUX16_PINMUX16_23_20_SHIFT (0x00000014u) -/*----PINMUX16_23_20 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_23_20_DOUT4 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_23_20_LCD_D4 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_23_20_UPP_XD12 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_23_20_GPIO7_12 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_19_16 (0x000F0000u) -#define SYSCFG_PINMUX16_PINMUX16_19_16_SHIFT (0x00000010u) -/*----PINMUX16_19_16 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_19_16_DOUT5 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_19_16_LCD_D5 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_19_16_UPP_XD13 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_19_16_GPIO7_13 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_15_12 (0x0000F000u) -#define SYSCFG_PINMUX16_PINMUX16_15_12_SHIFT (0x0000000Cu) -/*----PINMUX16_15_12 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_15_12_DOUT6 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_15_12_LCD_D6 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_15_12_UPP_XD14 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_15_12_GPIO7_14 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_11_8 (0x00000F00u) -#define SYSCFG_PINMUX16_PINMUX16_11_8_SHIFT (0x00000008u) -/*----PINMUX16_11_8 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_11_8_DOUT7 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_11_8_LCD_D7 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_11_8_UPP_XD15 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_11_8_GPIO7_15 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_7_4 (0x000000F0u) -#define SYSCFG_PINMUX16_PINMUX16_7_4_SHIFT (0x00000004u) -/*----PINMUX16_7_4 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_7_4_DIN8 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_7_4_UHPI_HD0 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_7_4_UPP_D0 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_7_4_GPIO6_5 (0x00000008u) - -#define SYSCFG_PINMUX16_PINMUX16_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX16_PINMUX16_3_0_SHIFT (0x00000000u) -/*----PINMUX16_3_0 Tokens----*/ -#define SYSCFG_PINMUX16_PINMUX16_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX16_PINMUX16_3_0_DIN9 (0x00000001u) -#define SYSCFG_PINMUX16_PINMUX16_3_0_UHPI_HD1 (0x00000002u) -#define SYSCFG_PINMUX16_PINMUX16_3_0_UPP_D1 (0x00000004u) -#define SYSCFG_PINMUX16_PINMUX16_3_0_PRU0_R30_9 (0x00000008u) - - -/* PINMUX17 */ - -#define SYSCFG_PINMUX17_PINMUX17_31_28 (0xF0000000u) -#define SYSCFG_PINMUX17_PINMUX17_31_28_SHIFT (0x0000001Cu) -/*----PINMUX17_31_28 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_31_28_DOUT10 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_31_28_LCD_D10 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_31_28_UPP_XD2 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_31_28_GPIO7_2 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_27_24 (0x0F000000u) -#define SYSCFG_PINMUX17_PINMUX17_27_24_SHIFT (0x00000018u) -/*----PINMUX17_27_24 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_27_24_DOUT11 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_27_24_LCD_D11 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_27_24_UPP_XD3 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_27_24_GPIO7_3 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_23_20 (0x00F00000u) -#define SYSCFG_PINMUX17_PINMUX17_23_20_SHIFT (0x00000014u) -/*----PINMUX17_23_20 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_23_20_DOUT12 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_23_20_LCD_D12 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_23_20_UPP_XD4 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_23_20_GPIO7_4 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_19_16 (0x000F0000u) -#define SYSCFG_PINMUX17_PINMUX17_19_16_SHIFT (0x00000010u) -/*----PINMUX17_19_16 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_19_16_DOUT13 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_19_16_LCD_D13 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_19_16_UPP_XD5 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_19_16_GPIO7_5 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_15_12 (0x0000F000u) -#define SYSCFG_PINMUX17_PINMUX17_15_12_SHIFT (0x0000000Cu) -/*----PINMUX17_15_12 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_15_12_DOUT14 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_15_12_LCD_D14 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_15_12_UPP_XD6 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_15_12_GPIO7_6 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_11_8 (0x00000F00u) -#define SYSCFG_PINMUX17_PINMUX17_11_8_SHIFT (0x00000008u) -/*----PINMUX17_11_8 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_11_8_DOUT15 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_11_8_LCD_D15 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_11_8_UPP_XD7 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_11_8_GPIO7_7 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_7_4 (0x000000F0u) -#define SYSCFG_PINMUX17_PINMUX17_7_4_SHIFT (0x00000004u) -/*----PINMUX17_7_4 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_7_4_DOUT0 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_7_4_LCD_D0 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_7_4_UPP_XD8 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_7_4_GPIO7_8 (0x00000008u) - -#define SYSCFG_PINMUX17_PINMUX17_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX17_PINMUX17_3_0_SHIFT (0x00000000u) -/*----PINMUX17_3_0 Tokens----*/ -#define SYSCFG_PINMUX17_PINMUX17_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX17_PINMUX17_3_0_DOUT1 (0x00000001u) -#define SYSCFG_PINMUX17_PINMUX17_3_0_LCD_D1 (0x00000002u) -#define SYSCFG_PINMUX17_PINMUX17_3_0_UPP_XD9 (0x00000004u) -#define SYSCFG_PINMUX17_PINMUX17_3_0_GPIO7_9 (0x00000008u) - - -/* PINMUX18 */ - -#define SYSCFG_PINMUX18_PINMUX18_31_28 (0xF0000000u) -#define SYSCFG_PINMUX18_PINMUX18_31_28_SHIFT (0x0000001Cu) -/*----PINMUX18_31_28 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_31_28_MMCSD1_DAT6 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_31_28_LCD_MCLK (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_31_28_PRU1_R30_6 (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_31_28_GPIO8_10 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_27_24 (0x0F000000u) -#define SYSCFG_PINMUX18_PINMUX18_27_24_SHIFT (0x00000018u) -/*----PINMUX18_27_24 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_27_24_MMCSD1_DAT7 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_27_24_LCD_PCLK (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_27_24_PRU1_R30_7 (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_27_24_GPIO8_11 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_23_20 (0x00F00000u) -#define SYSCFG_PINMUX18_PINMUX18_23_20_SHIFT (0x00000014u) -/*----PINMUX18_23_20 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_23_20_PRU0_R30_22 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_23_20_PRU1_R30_8 (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_23_20_CH0_WAIT (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_23_20_GPIO8_12 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_19_16 (0x000F0000u) -#define SYSCFG_PINMUX18_PINMUX18_19_16_SHIFT (0x00000010u) -/*----PINMUX18_19_16 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_19_16_PRU0_R30_23 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_19_16_MMCSD1_CMD (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_19_16_GPIO8_13 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_15_12 (0x0000F000u) -#define SYSCFG_PINMUX18_PINMUX18_15_12_SHIFT (0x0000000Cu) -/*----PINMUX18_15_12 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_15_12_PRU0_R30_24 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_15_12_MMCSD1_CLK (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_15_12_CH0_START (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_15_12_GPIO8_14 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_11_8 (0x00000F00u) -#define SYSCFG_PINMUX18_PINMUX18_11_8_SHIFT (0x00000008u) -/*----PINMUX18_11_8 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_11_8_PRU0_R30_25 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_11_8_MMCSD1_DAT0 (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_11_8_CH0_CLK (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_11_8_GPIO8_15 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_7_4 (0x000000F0u) -#define SYSCFG_PINMUX18_PINMUX18_7_4_SHIFT (0x00000004u) -/*----PINMUX18_7_4 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_7_4_DOUT8 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_7_4_LCD_D8 (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_7_4_UPP_XD0 (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_7_4_GPIO7_0 (0x00000008u) - -#define SYSCFG_PINMUX18_PINMUX18_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX18_PINMUX18_3_0_SHIFT (0x00000000u) -/*----PINMUX18_3_0 Tokens----*/ -#define SYSCFG_PINMUX18_PINMUX18_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX18_PINMUX18_3_0_DOUT9 (0x00000001u) -#define SYSCFG_PINMUX18_PINMUX18_3_0_LCD_D9 (0x00000002u) -#define SYSCFG_PINMUX18_PINMUX18_3_0_UPP_XD1 (0x00000004u) -#define SYSCFG_PINMUX18_PINMUX18_3_0_GPIO7_1 (0x00000008u) - - -/* PINMUX19 */ - -#define SYSCFG_PINMUX19_PINMUX19_31_28 (0xF0000000u) -#define SYSCFG_PINMUX19_PINMUX19_31_28_SHIFT (0x0000001Cu) -/*----PINMUX19_31_28 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_31_28_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_31_28_RTCK (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_31_28_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_31_28_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_31_28_GPIO8_0 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_27_24 (0x0F000000u) -#define SYSCFG_PINMUX19_PINMUX19_27_24_SHIFT (0x00000018u) -/*----PINMUX19_27_24 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_27_24_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_27_24_RESERVED1 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_27_24_NLCD_AC_ENB_CS (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_27_24_RESERVED4 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_27_24_GPIO6_0 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_23_20 (0x00F00000u) -#define SYSCFG_PINMUX19_PINMUX19_23_20_SHIFT (0x00000014u) -/*----PINMUX19_23_20 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_23_20_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_23_20_CLKO3 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_23_20_RESERVED2 (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_23_20_PRU1_R30_0 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_23_20_GPIO6_1 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_19_16 (0x000F0000u) -#define SYSCFG_PINMUX19_PINMUX19_19_16_SHIFT (0x00000010u) -/*----PINMUX19_19_16 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_19_16_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_19_16_CLKIN3 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_19_16_MMCSD1_DAT1 (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_19_16_PRU1_R30_1 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_19_16_GPIO6_2 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_15_12 (0x0000F000u) -#define SYSCFG_PINMUX19_PINMUX19_15_12_SHIFT (0x0000000Cu) -/*----PINMUX19_15_12 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_15_12_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_15_12_CLKO2 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_15_12_MMCSD1_DAT2 (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_15_12_PRU1_R30_2 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_15_12_GPIO6_3 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_11_8 (0x00000F00u) -#define SYSCFG_PINMUX19_PINMUX19_11_8_SHIFT (0x00000008u) -/*----PINMUX19_11_8 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_11_8_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_11_8_CLKIN2 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_11_8_MMCSD1_DAT3 (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_11_8_PRU1_R30_3 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_11_8_GPIO6_4 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_7_4 (0x000000F0u) -#define SYSCFG_PINMUX19_PINMUX19_7_4_SHIFT (0x00000004u) -/*----PINMUX19_7_4 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_7_4_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_7_4_MMCSD1_DAT4 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_7_4_LCD_VSYNC (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_7_4_PRU1_R30_4 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_7_4_GPIO8_8 (0x00000008u) - -#define SYSCFG_PINMUX19_PINMUX19_3_0 (0x0000000Fu) -#define SYSCFG_PINMUX19_PINMUX19_3_0_SHIFT (0x00000000u) -/*----PINMUX19_3_0 Tokens----*/ -#define SYSCFG_PINMUX19_PINMUX19_3_0_DEFAULT (0x00000000u) -#define SYSCFG_PINMUX19_PINMUX19_3_0_MMCSD1_DAT5 (0x00000001u) -#define SYSCFG_PINMUX19_PINMUX19_3_0_LCD_HSYNC (0x00000002u) -#define SYSCFG_PINMUX19_PINMUX19_3_0_PRU1_R30_5 (0x00000004u) -#define SYSCFG_PINMUX19_PINMUX19_3_0_GPIO8_9 (0x00000008u) - - -/* SUSPSRC */ - - -#define SYSCFG_SUSPSRC_TIMER64P_2SRC (0x20000000u) -#define SYSCFG_SUSPSRC_TIMER64P_2SRC_SHIFT (0x0000001Du) - -#define SYSCFG_SUSPSRC_TIMER64P_1SRC (0x10000000u) -#define SYSCFG_SUSPSRC_TIMER64P_1SRC_SHIFT (0x0000001Cu) - -#define SYSCFG_SUSPSRC_TIMER64P_0SRC (0x08000000u) -#define SYSCFG_SUSPSRC_TIMER64P_0SRC_SHIFT (0x0000001Bu) - - -#define SYSCFG_SUSPSRC_EPWM1SRC (0x01000000u) -#define SYSCFG_SUSPSRC_EPWM1SRC_SHIFT (0x00000018u) - -#define SYSCFG_SUSPSRC_EPWM0SRC (0x00800000u) -#define SYSCFG_SUSPSRC_EPWM0SRC_SHIFT (0x00000017u) - -#define SYSCFG_SUSPSRC_SPI1SRC (0x00400000u) -#define SYSCFG_SUSPSRC_SPI1SRC_SHIFT (0x00000016u) - -#define SYSCFG_SUSPSRC_SPI0SRC (0x00200000u) -#define SYSCFG_SUSPSRC_SPI0SRC_SHIFT (0x00000015u) - -#define SYSCFG_SUSPSRC_UART2SRC (0x00100000u) -#define SYSCFG_SUSPSRC_UART2SRC_SHIFT (0x00000014u) - -#define SYSCFG_SUSPSRC_UART1SRC (0x00080000u) -#define SYSCFG_SUSPSRC_UART1SRC_SHIFT (0x00000013u) - -#define SYSCFG_SUSPSRC_UART0SRC (0x00040000u) -#define SYSCFG_SUSPSRC_UART0SRC_SHIFT (0x00000012u) - -#define SYSCFG_SUSPSRC_I2C1SRC (0x00020000u) -#define SYSCFG_SUSPSRC_I2C1SRC_SHIFT (0x00000011u) - -#define SYSCFG_SUSPSRC_I2C0SRC (0x00010000u) -#define SYSCFG_SUSPSRC_I2C0SRC_SHIFT (0x00000010u) - - -#define SYSCFG_SUSPSRC_VPIFSRC (0x00004000u) -#define SYSCFG_SUSPSRC_VPIFSRC_SHIFT (0x0000000Eu) - -#define SYSCFG_SUSPSRC_SATASRC (0x00002000u) -#define SYSCFG_SUSPSRC_SATASRC_SHIFT (0x0000000Du) - -#define SYSCFG_SUSPSRC_HPISRC (0x00001000u) -#define SYSCFG_SUSPSRC_HPISRC_SHIFT (0x0000000Cu) - - -#define SYSCFG_SUSPSRC_USB0SRC (0x00000200u) -#define SYSCFG_SUSPSRC_USB0SRC_SHIFT (0x00000009u) - -#define SYSCFG_SUSPSRC_MCBSP1SRC (0x00000100u) -#define SYSCFG_SUSPSRC_MCBSP1SRC_SHIFT (0x00000008u) - -#define SYSCFG_SUSPSRC_MCBSP0SRC (0x00000080u) -#define SYSCFG_SUSPSRC_MCBSP0SRC_SHIFT (0x00000007u) - -#define SYSCFG_SUSPSRC_PRUSRC (0x00000040u) -#define SYSCFG_SUSPSRC_PRUSRC_SHIFT (0x00000006u) - -#define SYSCFG_SUSPSRC_EMACSRC (0x00000020u) -#define SYSCFG_SUSPSRC_EMACSRC_SHIFT (0x00000005u) - -#define SYSCFG_SUSPSRC_UPPSRC (0x00000010u) -#define SYSCFG_SUSPSRC_UPPSRC_SHIFT (0x00000004u) - -#define SYSCFG_SUSPSRC_TIMER64P_3SRC (0x00000008u) -#define SYSCFG_SUSPSRC_TIMER64P_3SRC_SHIFT (0x00000003u) - -#define SYSCFG_SUSPSRC_ECAP2SRC (0x00000004u) -#define SYSCFG_SUSPSRC_ECAP2SRC_SHIFT (0x00000002u) - -#define SYSCFG_SUSPSRC_ECAP1SRC (0x00000002u) -#define SYSCFG_SUSPSRC_ECAP1SRC_SHIFT (0x00000001u) - -#define SYSCFG_SUSPSRC_ECAP0SRC (0x00000001u) -#define SYSCFG_SUSPSRC_ECAP0SRC_SHIFT (0x00000000u) - - -/* CHIPSIG */ - - -#define SYSCFG_CHIPSIG_CHIPSIG4 (0x00000010u) -#define SYSCFG_CHIPSIG_CHIPSIG4_SHIFT (0x00000004u) - -#define SYSCFG_CHIPSIG_CHIPSIG3 (0x00000008u) -#define SYSCFG_CHIPSIG_CHIPSIG3_SHIFT (0x00000003u) - -#define SYSCFG_CHIPSIG_CHIPSIG2 (0x00000004u) -#define SYSCFG_CHIPSIG_CHIPSIG2_SHIFT (0x00000002u) - -#define SYSCFG_CHIPSIG_CHIPSIG1 (0x00000002u) -#define SYSCFG_CHIPSIG_CHIPSIG1_SHIFT (0x00000001u) - -#define SYSCFG_CHIPSIG_CHIPSIG0 (0x00000001u) -#define SYSCFG_CHIPSIG_CHIPSIG0_SHIFT (0x00000000u) - - -/* CHIPSIG_CLR */ - - -#define SYSCFG_CHIPSIG_CLR_CHIPSIG4 (0x00000010u) -#define SYSCFG_CHIPSIG_CLR_CHIPSIG4_SHIFT (0x00000004u) - -#define SYSCFG_CHIPSIG_CLR_CHIPSIG3 (0x00000008u) -#define SYSCFG_CHIPSIG_CLR_CHIPSIG3_SHIFT (0x00000003u) - -#define SYSCFG_CHIPSIG_CLR_CHIPSIG2 (0x00000004u) -#define SYSCFG_CHIPSIG_CLR_CHIPSIG2_SHIFT (0x00000002u) - -#define SYSCFG_CHIPSIG_CLR_CHIPSIG1 (0x00000002u) -#define SYSCFG_CHIPSIG_CLR_CHIPSIG1_SHIFT (0x00000001u) - -#define SYSCFG_CHIPSIG_CLR_CHIPSIG0 (0x00000001u) -#define SYSCFG_CHIPSIG_CLR_CHIPSIG0_SHIFT (0x00000000u) - - -/* CFGCHIP0 */ - -#define SYSCFG_CFGCHIP0_ARM_CLK_DIS0 (0x80000000u) -#define SYSCFG_CFGCHIP0_ARM_CLK_DIS0_SHIFT (0x0000001Fu) - -#define SYSCFG_CFGCHIP0_ARM_TAP_DIS0 (0x40000000u) -#define SYSCFG_CFGCHIP0_ARM_TAP_DIS0_SHIFT (0x0000001Eu) - - -#define SYSCFG_CFGCHIP0_PLL_MASTER_LOCK (0x00000010u) -#define SYSCFG_CFGCHIP0_PLL_MASTER_LOCK_SHIFT (0x00000004u) - -#define SYSCFG_CFGCHIP0_EDMA30TC1DBS (0x0000000Cu) -#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_SHIFT (0x00000002u) -/*----EDMA30TC1DBS Tokens----*/ -#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_16BYTE (0x00000000u) -#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_32BYTE (0x00000001u) -#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_64BYTE (0x00000002u) -#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_RESERVED (0x00000003u) - -#define SYSCFG_CFGCHIP0_EDMA30TC0DBS (0x00000003u) -#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_SHIFT (0x00000000u) -/*----EDMA30TC0DBS Tokens----*/ -#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_16BYTE (0x00000000u) -#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_32BYTE (0x00000001u) -#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_64BYTE (0x00000002u) -#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_RESERVED (0x00000003u) - - -/* CFGCHIP1 */ - -#define SYSCFG_CFGCHIP1_CAP2SRC (0xF8000000u) -#define SYSCFG_CFGCHIP1_CAP2SRC_SHIFT (0x0000001Bu) -/*----CAP2SRC Tokens----*/ -#define SYSCFG_CFGCHIP1_CAP2SRC_ECAP2 (0x00000000u) -#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP0_TXDMA (0x00000001u) -#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP0_RXDMA (0x00000002u) -#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP1_TXDMA (0x00000003u) -#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP1_RXDMA (0x00000004u) -#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP2_TXDMA (0x00000005u) -#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP2_RXDMA (0x00000006u) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C0_RXTHPLSEINT (0x00000007u) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C0_RXPLSEINT (0x00000008u) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C0_TXPLSEINT (0x00000009u) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C0_MISCINT (0x0000000au) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C1_RXTHPLSEINT (0x0000000bu) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C1_RXPLSEINT (0x0000000cu) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C1_TXPLSEINT (0x0000000du) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C1_MISCINT (0x0000000eu) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C2_RXTHPLSEINT (0x0000000fu) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C2_RXPLSEINT (0x00000010u) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C2_TXPLSEINT (0x00000011u) -#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C2_MISCINT (0x00000012u) - -#define SYSCFG_CFGCHIP1_CAP1SRC (0x07C00000u) -#define SYSCFG_CFGCHIP1_CAP1SRC_SHIFT (0x00000016u) -/*----CAP1SRC Tokens----*/ -#define SYSCFG_CFGCHIP1_CAP1SRC_ECAP1 (0x00000000u) -#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP0_TXDMA (0x00000001u) -#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP0_RXDMA (0x00000002u) -#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP1_TXDMA (0x00000003u) -#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP1_RXDMA (0x00000004u) -#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP2_TXDMA (0x00000005u) -#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP2_RXDMA (0x00000006u) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C0_RXTHPLSEINT (0x00000007u) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C0_RXPLSEINT (0x00000008u) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C0_TXPLSEINT (0x00000009u) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C0_MISCINT (0x0000000au) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C1_RXTHPLSEINT (0x0000000bu) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C1_RXPLSEINT (0x0000000cu) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C1_TXPLSEINT (0x0000000du) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C1_MISCINT (0x0000000eu) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C2_RXTHPLSEINT (0x0000000fu) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C2_RXPLSEINT (0x00000010u) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C2_TXPLSEINT (0x00000011u) -#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C2_MISCINT (0x00000012u) - -#define SYSCFG_CFGCHIP1_CAP0SRC (0x003E0000u) -#define SYSCFG_CFGCHIP1_CAP0SRC_SHIFT (0x00000011u) -/*----CAP0SRC Tokens----*/ -#define SYSCFG_CFGCHIP1_CAP0SRC_ECAP0 (0x00000000u) -#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP0_TXDMA (0x00000001u) -#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP0_RXDMA (0x00000002u) -#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP1_TXDMA (0x00000003u) -#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP1_RXDMA (0x00000004u) -#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP2_TXDMA (0x00000005u) -#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP2_RXDMA (0x00000006u) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C0_RXTHPLSEINT (0x00000007u) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C0_RXPLSEINT (0x00000008u) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C0_TXPLSEINT (0x00000009u) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C0_MISCINT (0x0000000au) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C1_RXTHPLSEINT (0x0000000bu) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C1_RXPLSEINT (0x0000000cu) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C1_TXPLSEINT (0x0000000du) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C1_MISCINT (0x0000000eu) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C2_RXTHPLSEINT (0x0000000fu) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C2_RXPLSEINT (0x00000010u) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C2_TXPLSEINT (0x00000011u) -#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C2_MISCINT (0x00000012u) - -#define SYSCFG_CFGCHIP1_HPIBYTEAD (0x00010000u) -#define SYSCFG_CFGCHIP1_HPIBYTEAD_SHIFT (0x00000010u) - -#define SYSCFG_CFGCHIP1_HPIENA (0x00008000u) -#define SYSCFG_CFGCHIP1_HPIENA_SHIFT (0x0000000Fu) - -#define SYSCFG_CFGCHIP1_EDMA31TC0DBS (0x00006000u) -#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_SHIFT (0x0000000Du) -/*----EDMA31TC0DBS Tokens----*/ -#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_16BYTE (0x00000000u) -#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_32BYTE (0x00000001u) -#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_64BYTE (0x00000002u) -#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_RESERVED (0x00000003u) - -#define SYSCFG_CFGCHIP1_TBCLKSYNC (0x00001000u) -#define SYSCFG_CFGCHIP1_TBCLKSYNC_SHIFT (0x0000000Cu) - - -#define SYSCFG_CFGCHIP1_AMUTESEL0 (0x0000000Fu) -#define SYSCFG_CFGCHIP1_AMUTESEL0_SHIFT (0x00000000u) -/*----AMUTESEL0 Tokens----*/ -#define SYSCFG_CFGCHIP1_AMUTESEL0_LOW (0x00000000u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B0 (0x00000001u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B1 (0x00000002u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B2 (0x00000003u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B3 (0x00000004u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B4 (0x00000005u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B5 (0x00000006u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B6 (0x00000007u) -#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B7 (0x00000008u) - - -/* CFGCHIP2 */ - - -#define SYSCFG_CFGCHIP2_USB0PHYCLKGD (0x00020000u) -#define SYSCFG_CFGCHIP2_USB0PHYCLKGD_SHIFT (0x00000011u) - -#define SYSCFG_CFGCHIP2_USB0VBUSSENSE (0x00010000u) -#define SYSCFG_CFGCHIP2_USB0VBUSSENSE_SHIFT (0x00000010u) - -#define SYSCFG_CFGCHIP2_RESET (0x00008000u) -#define SYSCFG_CFGCHIP2_RESET_SHIFT (0x0000000Fu) - -#define SYSCFG_CFGCHIP2_USB0OTGMODE (0x00006000u) -#define SYSCFG_CFGCHIP2_USB0OTGMODE_SHIFT (0x0000000Du) -/*----USB0OTGMODE Tokens----*/ -#define SYSCFG_CFGCHIP2_USB0OTGMODE_PHY (0x00000000u) -#define SYSCFG_CFGCHIP2_USB0OTGMODE_USB_HOST (0x00000001u) -#define SYSCFG_CFGCHIP2_USB0OTGMODE_USB_DEVICE (0x00000002u) -#define SYSCFG_CFGCHIP2_USB0OTGMODE_USB_HOST_LOW (0x00000003u) - -#define SYSCFG_CFGCHIP2_USB1PHYCLKMUX (0x00001000u) -#define SYSCFG_CFGCHIP2_USB1PHYCLKMUX_SHIFT (0x0000000Cu) - -#define SYSCFG_CFGCHIP2_USB0PHYCLKMUX (0x00000800u) -#define SYSCFG_CFGCHIP2_USB0PHYCLKMUX_SHIFT (0x0000000Bu) - -#define SYSCFG_CFGCHIP2_USB0PHYPWDN (0x00000400u) -#define SYSCFG_CFGCHIP2_USB0PHYPWDN_SHIFT (0x0000000Au) - -#define SYSCFG_CFGCHIP2_USB0OTGPWRDN (0x00000200u) -#define SYSCFG_CFGCHIP2_USB0OTGPWRDN_SHIFT (0x00000009u) - -#define SYSCFG_CFGCHIP2_USB0DATPOL (0x00000100u) -#define SYSCFG_CFGCHIP2_USB0DATPOL_SHIFT (0x00000008u) - -#define SYSCFG_CFGCHIP2_USB1SUSPENDM (0x00000080u) -#define SYSCFG_CFGCHIP2_USB1SUSPENDM_SHIFT (0x00000007u) - -#define SYSCFG_CFGCHIP2_USB0PHY_PLLON (0x00000040u) -#define SYSCFG_CFGCHIP2_USB0PHY_PLLON_SHIFT (0x00000006u) - -#define SYSCFG_CFGCHIP2_USB0SESNDEN (0x00000020u) -#define SYSCFG_CFGCHIP2_USB0SESNDEN_SHIFT (0x00000005u) - -#define SYSCFG_CFGCHIP2_USB0VBDTCTEN (0x00000010u) -#define SYSCFG_CFGCHIP2_USB0VBDTCTEN_SHIFT (0x00000004u) - -#define SYSCFG_CFGCHIP2_USB0REF_FREQ (0x0000000Fu) -#define SYSCFG_CFGCHIP2_USB0REF_FREQ_SHIFT (0x00000000u) - - -/* CFGCHIP3 */ - - - -#define SYSCFG_CFGCHIP3_RMII_SEL (0x00000100u) -#define SYSCFG_CFGCHIP3_RMII_SEL_SHIFT (0x00000008u) - -#define SYSCFG_CFGCHIP3_UPP_TX_CLKSRC (0x00000040u) -#define SYSCFG_CFGCHIP3_UPP_TX_CLKSRC_SHIFT (0x00000006u) - -#define SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK (0x00000020u) -#define SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_SHIFT (0x00000005u) - -#define SYSCFG_CFGCHIP3_ASYNC3_CLKSRC (0x00000010u) -#define SYSCFG_CFGCHIP3_ASYNC3_CLKSRC_SHIFT (0x00000004u) - -#define SYSCFG_CFGCHIP3_PRUEVTSEL (0x00000008u) -#define SYSCFG_CFGCHIP3_PRUEVTSEL_SHIFT (0x00000003u) - -#define SYSCFG_CFGCHIP3_DIV4P5ENA (0x00000004u) -#define SYSCFG_CFGCHIP3_DIV4P5ENA_SHIFT (0x00000002u) - -#define SYSCFG_CFGCHIP3_EMA_CLKSRC (0x00000002u) -#define SYSCFG_CFGCHIP3_EMA_CLKSRC_SHIFT (0x00000001u) - -#define SYSCFG_CFGCHIP4_AMUTECLR0 (0x00000001u) -#define SYSCFG_CFGCHIP4_AMUTECLR0_SHIFT (0x00000000u) - -#ifdef __cplusplus -} -#endif - -#endif /* _HW_SYSCFG1_H_ */ diff --git a/lib/tiam1808/tiam1808/hw/hw_syscfg1_C6748.h b/lib/tiam1808/tiam1808/hw/hw_syscfg1_C6748.h deleted file mode 100644 index 3220982d3..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_syscfg1_C6748.h +++ /dev/null @@ -1,465 +0,0 @@ -/** - * \file hw_syscfg1_C6748.h - * - * \brief Hardware registers and fields for SYSCFG1 module - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _HW_SYSCFG1_H_ -#define _HW_SYSCFG1_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define SYSCFG1_VTPIO_CTL (0x0) -#define SYSCFG1_DDR_SLEW (0x4) -#define SYSCFG1_DEEPSLEEP (0x8) -#define SYSCFG1_PUPD_ENA (0xC) -#define SYSCFG1_PUPD_SEL (0x10) -#define SYSCFG1_RXACTIVE (0x14) -#define SYSCFG1_PWRDN (0x18) - -/****************************************************************************** -** FIELD DEFINITION MACROS -******************************************************************************/ - -/* VTPIO_CTL */ - - -#define SYSCFG1_VTPIO_CTL_VREFEN (0x00040000u) -#define SYSCFG1_VTPIO_CTL_VREFEN_SHIFT (0x00000012u) - -#define SYSCFG1_VTPIO_CTL_VREFTAP (0x00030000u) -#define SYSCFG1_VTPIO_CTL_VREFTAP_SHIFT (0x00000010u) -/*----VREFTAP Tokens----*/ -#define SYSCFG1_VTPIO_CTL_VREFTAP_50_0 (0x00000000u) -#define SYSCFG1_VTPIO_CTL_VREFTAP_47_5 (0x00000001u) -#define SYSCFG1_VTPIO_CTL_VREFTAP_52_5 (0x00000002u) - -#define SYSCFG1_VTPIO_CTL_READY (0x00008000u) -#define SYSCFG1_VTPIO_CTL_READY_SHIFT (0x0000000Fu) - -#define SYSCFG1_VTPIO_CTL_IOPWRDN (0x00004000u) -#define SYSCFG1_VTPIO_CTL_IOPWRDN_SHIFT (0x0000000Eu) - -#define SYSCFG1_VTPIO_CTL_CLKRZ (0x00002000u) -#define SYSCFG1_VTPIO_CTL_CLKRZ_SHIFT (0x0000000Du) - -#define SYSCFG1_VTPIO_CTL_FORCEDNP (0x00001000u) -#define SYSCFG1_VTPIO_CTL_FORCEDNP_SHIFT (0x0000000Cu) - -#define SYSCFG1_VTPIO_CTL_FORCEDNN (0x00000800u) -#define SYSCFG1_VTPIO_CTL_FORCEDNN_SHIFT (0x0000000Bu) - -#define SYSCFG1_VTPIO_CTL_FORCEUPP (0x00000400u) -#define SYSCFG1_VTPIO_CTL_FORCEUPP_SHIFT (0x0000000Au) - -#define SYSCFG1_VTPIO_CTL_FORCEUPN (0x00000200u) -#define SYSCFG1_VTPIO_CTL_FORCEUPN_SHIFT (0x00000009u) - -#define SYSCFG1_VTPIO_CTL_PWRSAVE (0x00000100u) -#define SYSCFG1_VTPIO_CTL_PWRSAVE_SHIFT (0x00000008u) - -#define SYSCFG1_VTPIO_CTL_LOCK (0x00000080u) -#define SYSCFG1_VTPIO_CTL_LOCK_SHIFT (0x00000007u) - -#define SYSCFG1_VTPIO_CTL_POWERDN (0x00000040u) -#define SYSCFG1_VTPIO_CTL_POWERDN_SHIFT (0x00000006u) - -#define SYSCFG1_VTPIO_CTL_D0 (0x00000020u) -#define SYSCFG1_VTPIO_CTL_D0_SHIFT (0x00000005u) - -#define SYSCFG1_VTPIO_CTL_D1 (0x00000010u) -#define SYSCFG1_VTPIO_CTL_D1_SHIFT (0x00000004u) - -#define SYSCFG1_VTPIO_CTL_D2 (0x00000008u) -#define SYSCFG1_VTPIO_CTL_D2_SHIFT (0x00000003u) - -#define SYSCFG1_VTPIO_CTL_F0 (0x00000004u) -#define SYSCFG1_VTPIO_CTL_F0_SHIFT (0x00000002u) - -#define SYSCFG1_VTPIO_CTL_F1 (0x00000002u) -#define SYSCFG1_VTPIO_CTL_F1_SHIFT (0x00000001u) - -#define SYSCFG1_VTPIO_CTL_F2 (0x00000001u) -#define SYSCFG1_VTPIO_CTL_F2_SHIFT (0x00000000u) - - -/* DDR_SLEW */ - - -#define SYSCFG1_DDR_SLEW_ODT_TERMON (0x00000C00u) -#define SYSCFG1_DDR_SLEW_ODT_TERMON_SHIFT (0x0000000Au) - -#define SYSCFG1_DDR_SLEW_ODT_TERMOFF (0x00000300u) -#define SYSCFG1_DDR_SLEW_ODT_TERMOFF_SHIFT (0x00000008u) - -#define SYSCFG1_DDR_SLEW_DDR_PDENA (0x00000020u) -#define SYSCFG1_DDR_SLEW_DDR_PDENA_SHIFT (0x00000005u) - -#define SYSCFG1_DDR_SLEW_CMOSEN (0x00000010u) -#define SYSCFG1_DDR_SLEW_CMOSEN_SHIFT (0x00000004u) - -#define SYSCFG1_DDR_SLEW_DDR_DATASLEW (0x0000000Cu) -#define SYSCFG1_DDR_SLEW_DDR_DATASLEW_SHIFT (0x00000002u) - -#define SYSCFG1_DDR_SLEW_DDR_CMDSLEW (0x00000003u) -#define SYSCFG1_DDR_SLEW_DDR_CMDSLEW_SHIFT (0x00000000u) - -/* DEEPSLEEP */ - -#define SYSCFG1_DEEPSLEEP_SLEEPENABLE (0x80000000u) -#define SYSCFG1_DEEPSLEEP_SLEEPENABLE_SHIFT (0x0000001Fu) - -#define SYSCFG1_DEEPSLEEP_SLEEPCOMPLETE (0x40000000u) -#define SYSCFG1_DEEPSLEEP_SLEEPCOMPLETE_SHIFT (0x0000001Eu) - -#define SYSCFG1_DEEPSLEEP_SLEEPCOUNT (0x0000FFFFu) -#define SYSCFG1_DEEPSLEEP_SLEEPCOUNT_SHIFT (0x00000000u) - - -/* PUPD_ENA */ - -#define SYSCFG1_PUPD_ENA_PUPDENA31 (0x80000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA31_SHIFT (0x0000001Fu) - -#define SYSCFG1_PUPD_ENA_PUPDENA30 (0x40000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA30_SHIFT (0x0000001Eu) - -#define SYSCFG1_PUPD_ENA_PUPDENA29 (0x20000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA29_SHIFT (0x0000001Du) - -#define SYSCFG1_PUPD_ENA_PUPDENA28 (0x10000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA28_SHIFT (0x0000001Cu) - -#define SYSCFG1_PUPD_ENA_PUPDENA27 (0x08000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA27_SHIFT (0x0000001Bu) - -#define SYSCFG1_PUPD_ENA_PUPDENA26 (0x04000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA26_SHIFT (0x0000001Au) - -#define SYSCFG1_PUPD_ENA_PUPDENA25 (0x02000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA25_SHIFT (0x00000019u) - -#define SYSCFG1_PUPD_ENA_PUPDENA24 (0x01000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA24_SHIFT (0x00000018u) - -#define SYSCFG1_PUPD_ENA_PUPDENA23 (0x00800000u) -#define SYSCFG1_PUPD_ENA_PUPDENA23_SHIFT (0x00000017u) - -#define SYSCFG1_PUPD_ENA_PUPDENA22 (0x00400000u) -#define SYSCFG1_PUPD_ENA_PUPDENA22_SHIFT (0x00000016u) - -#define SYSCFG1_PUPD_ENA_PUPDENA21 (0x00200000u) -#define SYSCFG1_PUPD_ENA_PUPDENA21_SHIFT (0x00000015u) - -#define SYSCFG1_PUPD_ENA_PUPDENA20 (0x00100000u) -#define SYSCFG1_PUPD_ENA_PUPDENA20_SHIFT (0x00000014u) - -#define SYSCFG1_PUPD_ENA_PUPDENA19 (0x00080000u) -#define SYSCFG1_PUPD_ENA_PUPDENA19_SHIFT (0x00000013u) - -#define SYSCFG1_PUPD_ENA_PUPDENA18 (0x00040000u) -#define SYSCFG1_PUPD_ENA_PUPDENA18_SHIFT (0x00000012u) - -#define SYSCFG1_PUPD_ENA_PUPDENA17 (0x00020000u) -#define SYSCFG1_PUPD_ENA_PUPDENA17_SHIFT (0x00000011u) - -#define SYSCFG1_PUPD_ENA_PUPDENA16 (0x00010000u) -#define SYSCFG1_PUPD_ENA_PUPDENA16_SHIFT (0x00000010u) - -#define SYSCFG1_PUPD_ENA_PUPDENA15 (0x00008000u) -#define SYSCFG1_PUPD_ENA_PUPDENA15_SHIFT (0x0000000Fu) - -#define SYSCFG1_PUPD_ENA_PUPDENA14 (0x00004000u) -#define SYSCFG1_PUPD_ENA_PUPDENA14_SHIFT (0x0000000Eu) - -#define SYSCFG1_PUPD_ENA_PUPDENA13 (0x00002000u) -#define SYSCFG1_PUPD_ENA_PUPDENA13_SHIFT (0x0000000Du) - -#define SYSCFG1_PUPD_ENA_PUPDENA12 (0x00001000u) -#define SYSCFG1_PUPD_ENA_PUPDENA12_SHIFT (0x0000000Cu) - -#define SYSCFG1_PUPD_ENA_PUPDENA11 (0x00000800u) -#define SYSCFG1_PUPD_ENA_PUPDENA11_SHIFT (0x0000000Bu) - -#define SYSCFG1_PUPD_ENA_PUPDENA10 (0x00000400u) -#define SYSCFG1_PUPD_ENA_PUPDENA10_SHIFT (0x0000000Au) - -#define SYSCFG1_PUPD_ENA_PUPDENA9 (0x00000200u) -#define SYSCFG1_PUPD_ENA_PUPDENA9_SHIFT (0x00000009u) - -#define SYSCFG1_PUPD_ENA_PUPDENA8 (0x00000100u) -#define SYSCFG1_PUPD_ENA_PUPDENA8_SHIFT (0x00000008u) - -#define SYSCFG1_PUPD_ENA_PUPDENA7 (0x00000080u) -#define SYSCFG1_PUPD_ENA_PUPDENA7_SHIFT (0x00000007u) - -#define SYSCFG1_PUPD_ENA_PUPDENA6 (0x00000040u) -#define SYSCFG1_PUPD_ENA_PUPDENA6_SHIFT (0x00000006u) - -#define SYSCFG1_PUPD_ENA_PUPDENA5 (0x00000020u) -#define SYSCFG1_PUPD_ENA_PUPDENA5_SHIFT (0x00000005u) - -#define SYSCFG1_PUPD_ENA_PUPDENA4 (0x00000010u) -#define SYSCFG1_PUPD_ENA_PUPDENA4_SHIFT (0x00000004u) - -#define SYSCFG1_PUPD_ENA_PUPDENA3 (0x00000008u) -#define SYSCFG1_PUPD_ENA_PUPDENA3_SHIFT (0x00000003u) - -#define SYSCFG1_PUPD_ENA_PUPDENA2 (0x00000004u) -#define SYSCFG1_PUPD_ENA_PUPDENA2_SHIFT (0x00000002u) - -#define SYSCFG1_PUPD_ENA_PUPDENA1 (0x00000002u) -#define SYSCFG1_PUPD_ENA_PUPDENA1_SHIFT (0x00000001u) - -#define SYSCFG1_PUPD_ENA_PUPDENA0 (0x00000001u) -#define SYSCFG1_PUPD_ENA_PUPDENA0_SHIFT (0x00000000u) - - -/* PUPD_SEL */ - -#define SYSCFG1_PUPD_SEL_PUPDSEL31 (0x80000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL31_SHIFT (0x0000001Fu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL30 (0x40000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL30_SHIFT (0x0000001Eu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL29 (0x20000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL29_SHIFT (0x0000001Du) - -#define SYSCFG1_PUPD_SEL_PUPDSEL28 (0x10000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL28_SHIFT (0x0000001Cu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL27 (0x08000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL27_SHIFT (0x0000001Bu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL26 (0x04000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL26_SHIFT (0x0000001Au) - -#define SYSCFG1_PUPD_SEL_PUPDSEL25 (0x02000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL25_SHIFT (0x00000019u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL24 (0x01000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL24_SHIFT (0x00000018u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL23 (0x00800000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL23_SHIFT (0x00000017u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL22 (0x00400000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL22_SHIFT (0x00000016u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL21 (0x00200000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL21_SHIFT (0x00000015u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL20 (0x00100000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL20_SHIFT (0x00000014u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL19 (0x00080000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL19_SHIFT (0x00000013u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL18 (0x00040000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL18_SHIFT (0x00000012u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL17 (0x00020000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL17_SHIFT (0x00000011u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL16 (0x00010000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL16_SHIFT (0x00000010u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL15 (0x00008000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL15_SHIFT (0x0000000Fu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL14 (0x00004000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL14_SHIFT (0x0000000Eu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL13 (0x00002000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL13_SHIFT (0x0000000Du) - -#define SYSCFG1_PUPD_SEL_PUPDSEL12 (0x00001000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL12_SHIFT (0x0000000Cu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL11 (0x00000800u) -#define SYSCFG1_PUPD_SEL_PUPDSEL11_SHIFT (0x0000000Bu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL10 (0x00000400u) -#define SYSCFG1_PUPD_SEL_PUPDSEL10_SHIFT (0x0000000Au) - -#define SYSCFG1_PUPD_SEL_PUPDSEL9 (0x00000200u) -#define SYSCFG1_PUPD_SEL_PUPDSEL9_SHIFT (0x00000009u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL8 (0x00000100u) -#define SYSCFG1_PUPD_SEL_PUPDSEL8_SHIFT (0x00000008u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL7 (0x00000080u) -#define SYSCFG1_PUPD_SEL_PUPDSEL7_SHIFT (0x00000007u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL6 (0x00000040u) -#define SYSCFG1_PUPD_SEL_PUPDSEL6_SHIFT (0x00000006u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL5 (0x00000020u) -#define SYSCFG1_PUPD_SEL_PUPDSEL5_SHIFT (0x00000005u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL4 (0x00000010u) -#define SYSCFG1_PUPD_SEL_PUPDSEL4_SHIFT (0x00000004u) -/*----PUPDSEL4 Tokens----*/ -#define SYSCFG1_PUPD_SEL_PUPDSEL4_PULLDOWN (0x00000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL4_PULLUP (0x00000001u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL3 (0x00000008u) -#define SYSCFG1_PUPD_SEL_PUPDSEL3_SHIFT (0x00000003u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL2 (0x00000004u) -#define SYSCFG1_PUPD_SEL_PUPDSEL2_SHIFT (0x00000002u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL1 (0x00000002u) -#define SYSCFG1_PUPD_SEL_PUPDSEL1_SHIFT (0x00000001u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL0 (0x00000001u) -#define SYSCFG1_PUPD_SEL_PUPDSEL0_SHIFT (0x00000000u) - - -/* RXACTIVE */ - -#define SYSCFG1_RXACTIVE_RXACTIVE31 (0x80000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE31_SHIFT (0x0000001Fu) - -#define SYSCFG1_RXACTIVE_RXACTIVE30 (0x40000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE30_SHIFT (0x0000001Eu) - -#define SYSCFG1_RXACTIVE_RXACTIVE29 (0x20000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE29_SHIFT (0x0000001Du) - -#define SYSCFG1_RXACTIVE_RXACTIVE28 (0x10000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE28_SHIFT (0x0000001Cu) - -#define SYSCFG1_RXACTIVE_RXACTIVE27 (0x08000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE27_SHIFT (0x0000001Bu) - -#define SYSCFG1_RXACTIVE_RXACTIVE26 (0x04000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE26_SHIFT (0x0000001Au) - -#define SYSCFG1_RXACTIVE_RXACTIVE25 (0x02000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE25_SHIFT (0x00000019u) - -#define SYSCFG1_RXACTIVE_RXACTIVE24 (0x01000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE24_SHIFT (0x00000018u) - -#define SYSCFG1_RXACTIVE_RXACTIVE23 (0x00800000u) -#define SYSCFG1_RXACTIVE_RXACTIVE23_SHIFT (0x00000017u) - -#define SYSCFG1_RXACTIVE_RXACTIVE22 (0x00400000u) -#define SYSCFG1_RXACTIVE_RXACTIVE22_SHIFT (0x00000016u) - -#define SYSCFG1_RXACTIVE_RXACTIVE21 (0x00200000u) -#define SYSCFG1_RXACTIVE_RXACTIVE21_SHIFT (0x00000015u) - -#define SYSCFG1_RXACTIVE_RXACTIVE20 (0x00100000u) -#define SYSCFG1_RXACTIVE_RXACTIVE20_SHIFT (0x00000014u) - -#define SYSCFG1_RXACTIVE_RXACTIVE19 (0x00080000u) -#define SYSCFG1_RXACTIVE_RXACTIVE19_SHIFT (0x00000013u) - -#define SYSCFG1_RXACTIVE_RXACTIVE18 (0x00040000u) -#define SYSCFG1_RXACTIVE_RXACTIVE18_SHIFT (0x00000012u) - -#define SYSCFG1_RXACTIVE_RXACTIVE17 (0x00020000u) -#define SYSCFG1_RXACTIVE_RXACTIVE17_SHIFT (0x00000011u) - -#define SYSCFG1_RXACTIVE_RXACTIVE16 (0x00010000u) -#define SYSCFG1_RXACTIVE_RXACTIVE16_SHIFT (0x00000010u) - -#define SYSCFG1_RXACTIVE_RXACTIVE15 (0x00008000u) -#define SYSCFG1_RXACTIVE_RXACTIVE15_SHIFT (0x0000000Fu) - -#define SYSCFG1_RXACTIVE_RXACTIVE14 (0x00004000u) -#define SYSCFG1_RXACTIVE_RXACTIVE14_SHIFT (0x0000000Eu) - -#define SYSCFG1_RXACTIVE_RXACTIVE13 (0x00002000u) -#define SYSCFG1_RXACTIVE_RXACTIVE13_SHIFT (0x0000000Du) - -#define SYSCFG1_RXACTIVE_RXACTIVE12 (0x00001000u) -#define SYSCFG1_RXACTIVE_RXACTIVE12_SHIFT (0x0000000Cu) - -#define SYSCFG1_RXACTIVE_RXACTIVE11 (0x00000800u) -#define SYSCFG1_RXACTIVE_RXACTIVE11_SHIFT (0x0000000Bu) - -#define SYSCFG1_RXACTIVE_RXACTIVE10 (0x00000400u) -#define SYSCFG1_RXACTIVE_RXACTIVE10_SHIFT (0x0000000Au) - -#define SYSCFG1_RXACTIVE_RXACTIVE9 (0x00000200u) -#define SYSCFG1_RXACTIVE_RXACTIVE9_SHIFT (0x00000009u) - -#define SYSCFG1_RXACTIVE_RXACTIVE8 (0x00000100u) -#define SYSCFG1_RXACTIVE_RXACTIVE8_SHIFT (0x00000008u) - -#define SYSCFG1_RXACTIVE_RXACTIVE7 (0x00000080u) -#define SYSCFG1_RXACTIVE_RXACTIVE7_SHIFT (0x00000007u) - -#define SYSCFG1_RXACTIVE_RXACTIVE6 (0x00000040u) -#define SYSCFG1_RXACTIVE_RXACTIVE6_SHIFT (0x00000006u) - -#define SYSCFG1_RXACTIVE_RXACTIVE5 (0x00000020u) -#define SYSCFG1_RXACTIVE_RXACTIVE5_SHIFT (0x00000005u) - -#define SYSCFG1_RXACTIVE_RXACTIVE4 (0x00000010u) -#define SYSCFG1_RXACTIVE_RXACTIVE4_SHIFT (0x00000004u) - -#define SYSCFG1_RXACTIVE_RXACTIVE3 (0x00000008u) -#define SYSCFG1_RXACTIVE_RXACTIVE3_SHIFT (0x00000003u) - -#define SYSCFG1_RXACTIVE_RXACTIVE2 (0x00000004u) -#define SYSCFG1_RXACTIVE_RXACTIVE2_SHIFT (0x00000002u) - -#define SYSCFG1_RXACTIVE_RXACTIVE1 (0x00000002u) -#define SYSCFG1_RXACTIVE_RXACTIVE1_SHIFT (0x00000001u) - -#define SYSCFG1_RXACTIVE_RXACTIVE0 (0x00000001u) -#define SYSCFG1_RXACTIVE_RXACTIVE0_SHIFT (0x00000000u) - -/* PWRDN */ - - -#define SYSCFG1_PWRDN_SATACLK_PWRDN (0x00000001u) -#define SYSCFG1_PWRDN_SATACLK_PWRDN_SHIFT (0x00000000u) - -#ifdef __cplusplus -} -#endif - -#endif /* _HW_SYSCFG1_H_ */ diff --git a/lib/tiam1808/tiam1808/hw/hw_syscfg1_OMAPL138.h b/lib/tiam1808/tiam1808/hw/hw_syscfg1_OMAPL138.h deleted file mode 100644 index 41bd25db8..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_syscfg1_OMAPL138.h +++ /dev/null @@ -1,465 +0,0 @@ -/** - * \name hw_syscfg1_OMAPL138.h - * - * \brief Hardware definitions for OMAPL138 - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _HW_SYSCFG1_H_ -#define _HW_SYSCFG1_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define SYSCFG1_VTPIO_CTL (0x0) -#define SYSCFG1_DDR_SLEW (0x4) -#define SYSCFG1_DEEPSLEEP (0x8) -#define SYSCFG1_PUPD_ENA (0xC) -#define SYSCFG1_PUPD_SEL (0x10) -#define SYSCFG1_RXACTIVE (0x14) -#define SYSCFG1_PWRDN (0x18) - -/**************************************************************************\ -* Field Definition Macros -\**************************************************************************/ - -/* VTPIO_CTL */ - - -#define SYSCFG1_VTPIO_CTL_VREFEN (0x00040000u) -#define SYSCFG1_VTPIO_CTL_VREFEN_SHIFT (0x00000012u) - -#define SYSCFG1_VTPIO_CTL_VREFTAP (0x00030000u) -#define SYSCFG1_VTPIO_CTL_VREFTAP_SHIFT (0x00000010u) -/*----VREFTAP Tokens----*/ -#define SYSCFG1_VTPIO_CTL_VREFTAP_50_0 (0x00000000u) -#define SYSCFG1_VTPIO_CTL_VREFTAP_47_5 (0x00000001u) -#define SYSCFG1_VTPIO_CTL_VREFTAP_52_5 (0x00000002u) - -#define SYSCFG1_VTPIO_CTL_READY (0x00008000u) -#define SYSCFG1_VTPIO_CTL_READY_SHIFT (0x0000000Fu) - -#define SYSCFG1_VTPIO_CTL_IOPWRDN (0x00004000u) -#define SYSCFG1_VTPIO_CTL_IOPWRDN_SHIFT (0x0000000Eu) - -#define SYSCFG1_VTPIO_CTL_CLKRZ (0x00002000u) -#define SYSCFG1_VTPIO_CTL_CLKRZ_SHIFT (0x0000000Du) - -#define SYSCFG1_VTPIO_CTL_FORCEDNP (0x00001000u) -#define SYSCFG1_VTPIO_CTL_FORCEDNP_SHIFT (0x0000000Cu) - -#define SYSCFG1_VTPIO_CTL_FORCEDNN (0x00000800u) -#define SYSCFG1_VTPIO_CTL_FORCEDNN_SHIFT (0x0000000Bu) - -#define SYSCFG1_VTPIO_CTL_FORCEUPP (0x00000400u) -#define SYSCFG1_VTPIO_CTL_FORCEUPP_SHIFT (0x0000000Au) - -#define SYSCFG1_VTPIO_CTL_FORCEUPN (0x00000200u) -#define SYSCFG1_VTPIO_CTL_FORCEUPN_SHIFT (0x00000009u) - -#define SYSCFG1_VTPIO_CTL_PWRSAVE (0x00000100u) -#define SYSCFG1_VTPIO_CTL_PWRSAVE_SHIFT (0x00000008u) - -#define SYSCFG1_VTPIO_CTL_LOCK (0x00000080u) -#define SYSCFG1_VTPIO_CTL_LOCK_SHIFT (0x00000007u) - -#define SYSCFG1_VTPIO_CTL_POWERDN (0x00000040u) -#define SYSCFG1_VTPIO_CTL_POWERDN_SHIFT (0x00000006u) - -#define SYSCFG1_VTPIO_CTL_D0 (0x00000020u) -#define SYSCFG1_VTPIO_CTL_D0_SHIFT (0x00000005u) - -#define SYSCFG1_VTPIO_CTL_D1 (0x00000010u) -#define SYSCFG1_VTPIO_CTL_D1_SHIFT (0x00000004u) - -#define SYSCFG1_VTPIO_CTL_D2 (0x00000008u) -#define SYSCFG1_VTPIO_CTL_D2_SHIFT (0x00000003u) - -#define SYSCFG1_VTPIO_CTL_F0 (0x00000004u) -#define SYSCFG1_VTPIO_CTL_F0_SHIFT (0x00000002u) - -#define SYSCFG1_VTPIO_CTL_F1 (0x00000002u) -#define SYSCFG1_VTPIO_CTL_F1_SHIFT (0x00000001u) - -#define SYSCFG1_VTPIO_CTL_F2 (0x00000001u) -#define SYSCFG1_VTPIO_CTL_F2_SHIFT (0x00000000u) - - -/* DDR_SLEW */ - - -#define SYSCFG1_DDR_SLEW_ODT_TERMON (0x00000C00u) -#define SYSCFG1_DDR_SLEW_ODT_TERMON_SHIFT (0x0000000Au) - -#define SYSCFG1_DDR_SLEW_ODT_TERMOFF (0x00000300u) -#define SYSCFG1_DDR_SLEW_ODT_TERMOFF_SHIFT (0x00000008u) - -#define SYSCFG1_DDR_SLEW_DDR_PDENA (0x00000020u) -#define SYSCFG1_DDR_SLEW_DDR_PDENA_SHIFT (0x00000005u) - -#define SYSCFG1_DDR_SLEW_CMOSEN (0x00000010u) -#define SYSCFG1_DDR_SLEW_CMOSEN_SHIFT (0x00000004u) - -#define SYSCFG1_DDR_SLEW_DDR_DATASLEW (0x0000000Cu) -#define SYSCFG1_DDR_SLEW_DDR_DATASLEW_SHIFT (0x00000002u) - -#define SYSCFG1_DDR_SLEW_DDR_CMDSLEW (0x00000003u) -#define SYSCFG1_DDR_SLEW_DDR_CMDSLEW_SHIFT (0x00000000u) - -/* DEEPSLEEP */ - -#define SYSCFG1_DEEPSLEEP_SLEEPENABLE (0x80000000u) -#define SYSCFG1_DEEPSLEEP_SLEEPENABLE_SHIFT (0x0000001Fu) - -#define SYSCFG1_DEEPSLEEP_SLEEPCOMPLETE (0x40000000u) -#define SYSCFG1_DEEPSLEEP_SLEEPCOMPLETE_SHIFT (0x0000001Eu) - -#define SYSCFG1_DEEPSLEEP_SLEEPCOUNT (0x0000FFFFu) -#define SYSCFG1_DEEPSLEEP_SLEEPCOUNT_SHIFT (0x00000000u) - - -/* PUPD_ENA */ - -#define SYSCFG1_PUPD_ENA_PUPDENA31 (0x80000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA31_SHIFT (0x0000001Fu) - -#define SYSCFG1_PUPD_ENA_PUPDENA30 (0x40000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA30_SHIFT (0x0000001Eu) - -#define SYSCFG1_PUPD_ENA_PUPDENA29 (0x20000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA29_SHIFT (0x0000001Du) - -#define SYSCFG1_PUPD_ENA_PUPDENA28 (0x10000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA28_SHIFT (0x0000001Cu) - -#define SYSCFG1_PUPD_ENA_PUPDENA27 (0x08000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA27_SHIFT (0x0000001Bu) - -#define SYSCFG1_PUPD_ENA_PUPDENA26 (0x04000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA26_SHIFT (0x0000001Au) - -#define SYSCFG1_PUPD_ENA_PUPDENA25 (0x02000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA25_SHIFT (0x00000019u) - -#define SYSCFG1_PUPD_ENA_PUPDENA24 (0x01000000u) -#define SYSCFG1_PUPD_ENA_PUPDENA24_SHIFT (0x00000018u) - -#define SYSCFG1_PUPD_ENA_PUPDENA23 (0x00800000u) -#define SYSCFG1_PUPD_ENA_PUPDENA23_SHIFT (0x00000017u) - -#define SYSCFG1_PUPD_ENA_PUPDENA22 (0x00400000u) -#define SYSCFG1_PUPD_ENA_PUPDENA22_SHIFT (0x00000016u) - -#define SYSCFG1_PUPD_ENA_PUPDENA21 (0x00200000u) -#define SYSCFG1_PUPD_ENA_PUPDENA21_SHIFT (0x00000015u) - -#define SYSCFG1_PUPD_ENA_PUPDENA20 (0x00100000u) -#define SYSCFG1_PUPD_ENA_PUPDENA20_SHIFT (0x00000014u) - -#define SYSCFG1_PUPD_ENA_PUPDENA19 (0x00080000u) -#define SYSCFG1_PUPD_ENA_PUPDENA19_SHIFT (0x00000013u) - -#define SYSCFG1_PUPD_ENA_PUPDENA18 (0x00040000u) -#define SYSCFG1_PUPD_ENA_PUPDENA18_SHIFT (0x00000012u) - -#define SYSCFG1_PUPD_ENA_PUPDENA17 (0x00020000u) -#define SYSCFG1_PUPD_ENA_PUPDENA17_SHIFT (0x00000011u) - -#define SYSCFG1_PUPD_ENA_PUPDENA16 (0x00010000u) -#define SYSCFG1_PUPD_ENA_PUPDENA16_SHIFT (0x00000010u) - -#define SYSCFG1_PUPD_ENA_PUPDENA15 (0x00008000u) -#define SYSCFG1_PUPD_ENA_PUPDENA15_SHIFT (0x0000000Fu) - -#define SYSCFG1_PUPD_ENA_PUPDENA14 (0x00004000u) -#define SYSCFG1_PUPD_ENA_PUPDENA14_SHIFT (0x0000000Eu) - -#define SYSCFG1_PUPD_ENA_PUPDENA13 (0x00002000u) -#define SYSCFG1_PUPD_ENA_PUPDENA13_SHIFT (0x0000000Du) - -#define SYSCFG1_PUPD_ENA_PUPDENA12 (0x00001000u) -#define SYSCFG1_PUPD_ENA_PUPDENA12_SHIFT (0x0000000Cu) - -#define SYSCFG1_PUPD_ENA_PUPDENA11 (0x00000800u) -#define SYSCFG1_PUPD_ENA_PUPDENA11_SHIFT (0x0000000Bu) - -#define SYSCFG1_PUPD_ENA_PUPDENA10 (0x00000400u) -#define SYSCFG1_PUPD_ENA_PUPDENA10_SHIFT (0x0000000Au) - -#define SYSCFG1_PUPD_ENA_PUPDENA9 (0x00000200u) -#define SYSCFG1_PUPD_ENA_PUPDENA9_SHIFT (0x00000009u) - -#define SYSCFG1_PUPD_ENA_PUPDENA8 (0x00000100u) -#define SYSCFG1_PUPD_ENA_PUPDENA8_SHIFT (0x00000008u) - -#define SYSCFG1_PUPD_ENA_PUPDENA7 (0x00000080u) -#define SYSCFG1_PUPD_ENA_PUPDENA7_SHIFT (0x00000007u) - -#define SYSCFG1_PUPD_ENA_PUPDENA6 (0x00000040u) -#define SYSCFG1_PUPD_ENA_PUPDENA6_SHIFT (0x00000006u) - -#define SYSCFG1_PUPD_ENA_PUPDENA5 (0x00000020u) -#define SYSCFG1_PUPD_ENA_PUPDENA5_SHIFT (0x00000005u) - -#define SYSCFG1_PUPD_ENA_PUPDENA4 (0x00000010u) -#define SYSCFG1_PUPD_ENA_PUPDENA4_SHIFT (0x00000004u) - -#define SYSCFG1_PUPD_ENA_PUPDENA3 (0x00000008u) -#define SYSCFG1_PUPD_ENA_PUPDENA3_SHIFT (0x00000003u) - -#define SYSCFG1_PUPD_ENA_PUPDENA2 (0x00000004u) -#define SYSCFG1_PUPD_ENA_PUPDENA2_SHIFT (0x00000002u) - -#define SYSCFG1_PUPD_ENA_PUPDENA1 (0x00000002u) -#define SYSCFG1_PUPD_ENA_PUPDENA1_SHIFT (0x00000001u) - -#define SYSCFG1_PUPD_ENA_PUPDENA0 (0x00000001u) -#define SYSCFG1_PUPD_ENA_PUPDENA0_SHIFT (0x00000000u) - - -/* PUPD_SEL */ - -#define SYSCFG1_PUPD_SEL_PUPDSEL31 (0x80000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL31_SHIFT (0x0000001Fu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL30 (0x40000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL30_SHIFT (0x0000001Eu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL29 (0x20000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL29_SHIFT (0x0000001Du) - -#define SYSCFG1_PUPD_SEL_PUPDSEL28 (0x10000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL28_SHIFT (0x0000001Cu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL27 (0x08000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL27_SHIFT (0x0000001Bu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL26 (0x04000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL26_SHIFT (0x0000001Au) - -#define SYSCFG1_PUPD_SEL_PUPDSEL25 (0x02000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL25_SHIFT (0x00000019u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL24 (0x01000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL24_SHIFT (0x00000018u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL23 (0x00800000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL23_SHIFT (0x00000017u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL22 (0x00400000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL22_SHIFT (0x00000016u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL21 (0x00200000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL21_SHIFT (0x00000015u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL20 (0x00100000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL20_SHIFT (0x00000014u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL19 (0x00080000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL19_SHIFT (0x00000013u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL18 (0x00040000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL18_SHIFT (0x00000012u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL17 (0x00020000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL17_SHIFT (0x00000011u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL16 (0x00010000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL16_SHIFT (0x00000010u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL15 (0x00008000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL15_SHIFT (0x0000000Fu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL14 (0x00004000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL14_SHIFT (0x0000000Eu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL13 (0x00002000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL13_SHIFT (0x0000000Du) - -#define SYSCFG1_PUPD_SEL_PUPDSEL12 (0x00001000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL12_SHIFT (0x0000000Cu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL11 (0x00000800u) -#define SYSCFG1_PUPD_SEL_PUPDSEL11_SHIFT (0x0000000Bu) - -#define SYSCFG1_PUPD_SEL_PUPDSEL10 (0x00000400u) -#define SYSCFG1_PUPD_SEL_PUPDSEL10_SHIFT (0x0000000Au) - -#define SYSCFG1_PUPD_SEL_PUPDSEL9 (0x00000200u) -#define SYSCFG1_PUPD_SEL_PUPDSEL9_SHIFT (0x00000009u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL8 (0x00000100u) -#define SYSCFG1_PUPD_SEL_PUPDSEL8_SHIFT (0x00000008u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL7 (0x00000080u) -#define SYSCFG1_PUPD_SEL_PUPDSEL7_SHIFT (0x00000007u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL6 (0x00000040u) -#define SYSCFG1_PUPD_SEL_PUPDSEL6_SHIFT (0x00000006u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL5 (0x00000020u) -#define SYSCFG1_PUPD_SEL_PUPDSEL5_SHIFT (0x00000005u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL4 (0x00000010u) -#define SYSCFG1_PUPD_SEL_PUPDSEL4_SHIFT (0x00000004u) -/*----PUPDSEL4 Tokens----*/ -#define SYSCFG1_PUPD_SEL_PUPDSEL4_PULLDOWN (0x00000000u) -#define SYSCFG1_PUPD_SEL_PUPDSEL4_PULLUP (0x00000001u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL3 (0x00000008u) -#define SYSCFG1_PUPD_SEL_PUPDSEL3_SHIFT (0x00000003u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL2 (0x00000004u) -#define SYSCFG1_PUPD_SEL_PUPDSEL2_SHIFT (0x00000002u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL1 (0x00000002u) -#define SYSCFG1_PUPD_SEL_PUPDSEL1_SHIFT (0x00000001u) - -#define SYSCFG1_PUPD_SEL_PUPDSEL0 (0x00000001u) -#define SYSCFG1_PUPD_SEL_PUPDSEL0_SHIFT (0x00000000u) - - -/* RXACTIVE */ - -#define SYSCFG1_RXACTIVE_RXACTIVE31 (0x80000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE31_SHIFT (0x0000001Fu) - -#define SYSCFG1_RXACTIVE_RXACTIVE30 (0x40000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE30_SHIFT (0x0000001Eu) - -#define SYSCFG1_RXACTIVE_RXACTIVE29 (0x20000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE29_SHIFT (0x0000001Du) - -#define SYSCFG1_RXACTIVE_RXACTIVE28 (0x10000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE28_SHIFT (0x0000001Cu) - -#define SYSCFG1_RXACTIVE_RXACTIVE27 (0x08000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE27_SHIFT (0x0000001Bu) - -#define SYSCFG1_RXACTIVE_RXACTIVE26 (0x04000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE26_SHIFT (0x0000001Au) - -#define SYSCFG1_RXACTIVE_RXACTIVE25 (0x02000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE25_SHIFT (0x00000019u) - -#define SYSCFG1_RXACTIVE_RXACTIVE24 (0x01000000u) -#define SYSCFG1_RXACTIVE_RXACTIVE24_SHIFT (0x00000018u) - -#define SYSCFG1_RXACTIVE_RXACTIVE23 (0x00800000u) -#define SYSCFG1_RXACTIVE_RXACTIVE23_SHIFT (0x00000017u) - -#define SYSCFG1_RXACTIVE_RXACTIVE22 (0x00400000u) -#define SYSCFG1_RXACTIVE_RXACTIVE22_SHIFT (0x00000016u) - -#define SYSCFG1_RXACTIVE_RXACTIVE21 (0x00200000u) -#define SYSCFG1_RXACTIVE_RXACTIVE21_SHIFT (0x00000015u) - -#define SYSCFG1_RXACTIVE_RXACTIVE20 (0x00100000u) -#define SYSCFG1_RXACTIVE_RXACTIVE20_SHIFT (0x00000014u) - -#define SYSCFG1_RXACTIVE_RXACTIVE19 (0x00080000u) -#define SYSCFG1_RXACTIVE_RXACTIVE19_SHIFT (0x00000013u) - -#define SYSCFG1_RXACTIVE_RXACTIVE18 (0x00040000u) -#define SYSCFG1_RXACTIVE_RXACTIVE18_SHIFT (0x00000012u) - -#define SYSCFG1_RXACTIVE_RXACTIVE17 (0x00020000u) -#define SYSCFG1_RXACTIVE_RXACTIVE17_SHIFT (0x00000011u) - -#define SYSCFG1_RXACTIVE_RXACTIVE16 (0x00010000u) -#define SYSCFG1_RXACTIVE_RXACTIVE16_SHIFT (0x00000010u) - -#define SYSCFG1_RXACTIVE_RXACTIVE15 (0x00008000u) -#define SYSCFG1_RXACTIVE_RXACTIVE15_SHIFT (0x0000000Fu) - -#define SYSCFG1_RXACTIVE_RXACTIVE14 (0x00004000u) -#define SYSCFG1_RXACTIVE_RXACTIVE14_SHIFT (0x0000000Eu) - -#define SYSCFG1_RXACTIVE_RXACTIVE13 (0x00002000u) -#define SYSCFG1_RXACTIVE_RXACTIVE13_SHIFT (0x0000000Du) - -#define SYSCFG1_RXACTIVE_RXACTIVE12 (0x00001000u) -#define SYSCFG1_RXACTIVE_RXACTIVE12_SHIFT (0x0000000Cu) - -#define SYSCFG1_RXACTIVE_RXACTIVE11 (0x00000800u) -#define SYSCFG1_RXACTIVE_RXACTIVE11_SHIFT (0x0000000Bu) - -#define SYSCFG1_RXACTIVE_RXACTIVE10 (0x00000400u) -#define SYSCFG1_RXACTIVE_RXACTIVE10_SHIFT (0x0000000Au) - -#define SYSCFG1_RXACTIVE_RXACTIVE9 (0x00000200u) -#define SYSCFG1_RXACTIVE_RXACTIVE9_SHIFT (0x00000009u) - -#define SYSCFG1_RXACTIVE_RXACTIVE8 (0x00000100u) -#define SYSCFG1_RXACTIVE_RXACTIVE8_SHIFT (0x00000008u) - -#define SYSCFG1_RXACTIVE_RXACTIVE7 (0x00000080u) -#define SYSCFG1_RXACTIVE_RXACTIVE7_SHIFT (0x00000007u) - -#define SYSCFG1_RXACTIVE_RXACTIVE6 (0x00000040u) -#define SYSCFG1_RXACTIVE_RXACTIVE6_SHIFT (0x00000006u) - -#define SYSCFG1_RXACTIVE_RXACTIVE5 (0x00000020u) -#define SYSCFG1_RXACTIVE_RXACTIVE5_SHIFT (0x00000005u) - -#define SYSCFG1_RXACTIVE_RXACTIVE4 (0x00000010u) -#define SYSCFG1_RXACTIVE_RXACTIVE4_SHIFT (0x00000004u) - -#define SYSCFG1_RXACTIVE_RXACTIVE3 (0x00000008u) -#define SYSCFG1_RXACTIVE_RXACTIVE3_SHIFT (0x00000003u) - -#define SYSCFG1_RXACTIVE_RXACTIVE2 (0x00000004u) -#define SYSCFG1_RXACTIVE_RXACTIVE2_SHIFT (0x00000002u) - -#define SYSCFG1_RXACTIVE_RXACTIVE1 (0x00000002u) -#define SYSCFG1_RXACTIVE_RXACTIVE1_SHIFT (0x00000001u) - -#define SYSCFG1_RXACTIVE_RXACTIVE0 (0x00000001u) -#define SYSCFG1_RXACTIVE_RXACTIVE0_SHIFT (0x00000000u) - -/* PWRDN */ - - -#define SYSCFG1_PWRDN_SATACLK_PWRDN (0x00000001u) -#define SYSCFG1_PWRDN_SATACLK_PWRDN_SHIFT (0x00000000u) - -#ifdef __cplusplus -} -#endif - -#endif /* _HW_SYSCFG1_H_ */ diff --git a/lib/tiam1808/tiam1808/hw/hw_tps65217.h b/lib/tiam1808/tiam1808/hw/hw_tps65217.h deleted file mode 100644 index 18f8db53f..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_tps65217.h +++ /dev/null @@ -1,109 +0,0 @@ - -/** - * @Component: PMIC - * - * @Filename: hw_tps65217.h - * - ============================================================================ */ -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef __TPS65217_H__ -#define __TPS65217_H__ - - -/* Address of TPS65217(pmic) over I2C0 */ -#define PMIC_TPS65217_I2C_SLAVE_ADDR (0x24) - - -/* Registers */ -#define CHIPID 0x00 -#define POWER_PATH 0x01 -#define INTERRUPT 0x02 -#define CHGCONFIG0 0x03 -#define CHGCONFIG1 0x04 -#define CHGCONFIG2 0x05 -#define CHGCONFIG3 0x06 -#define WLEDCTRL1 0x07 -#define WLEDCTRL2 0x08 -#define MUXCTRL 0x09 -#define STATUS 0x0A -#define PASSWORD 0x0B -#define PGOOD 0x0C -#define DEFPG 0x0D -#define DEFDCDC1 0x0E -#define DEFDCDC2 0x0F -#define DEFDCDC3 0x10 -#define DEFSLEW 0x11 -#define DEFLDO1 0x12 -#define DEFLDO2 0x13 -#define DEFLS1 0x14 -#define DEFLS2 0x15 -#define ENABLE 0x16 -#define DEFUVLO 0x18 -#define SEQ1 0x19 -#define SEQ2 0x1A -#define SEQ3 0x1B -#define SEQ4 0x1C -#define SEQ5 0x1D -#define SEQ6 0x1E - -#define PROT_LEVEL_NONE 0x00 -#define PROT_LEVEL_1 0x01 -#define PROT_LEVEL_2 0x02 - -#define PASSWORD_LOCK_FOR_WRITE 0x00 -#define PASSWORD_UNLOCK 0x7D - -#define DCDC_GO 0x80 - -#define MASK_ALL_BITS 0xFF - -#define USB_INPUT_CUR_LIMIT_MASK 0x03 -#define USB_INPUT_CUR_LIMIT_100MA 0x00 -#define USB_INPUT_CUR_LIMIT_500MA 0x01 -#define USB_INPUT_CUR_LIMIT_1300MA 0x02 -#define USB_INPUT_CUR_LIMIT_1800MA 0x03 - -#define DCDC_VOLT_SEL_1275MV 0x0F - -#define LDO_MASK 0x1F -#define LDO_VOLTAGE_OUT_3_3 0x1F - -#define PWR_SRC_USB_BITMASK 0x4 -#define PWR_SRC_AC_BITMASK 0x8 - -#endif - diff --git a/lib/tiam1808/tiam1808/hw/hw_tps65910.h b/lib/tiam1808/tiam1808/hw/hw_tps65910.h deleted file mode 100644 index c88a133aa..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_tps65910.h +++ /dev/null @@ -1,1097 +0,0 @@ - - -/** - * @Component: PMIC - * - * @Filename: hw_tps65910.h - * - ============================================================================ */ -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - - -#ifndef _TPS65910_H_ -#define _TPS65910_H_ - - -/***********************************************************************\ - * Register arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundle arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundles Definition -\***********************************************************************/ - - - -/*************************************************************************\ - * Registers Definition -\*************************************************************************/ - -/* Address of TPS65910A (PMIC - SR) over I2C0 */ -#define PMIC_SR_I2C_SLAVE_ADDR (0x12) - -#define PMIC_CNTL_I2C_SLAVE_ADDR (0x2D) - -#define SECONDS_REG (0x00) -#define MINUTES_REG (0x01) -#define HOURS_REG (0x02) -#define DAYS_REG (0x03) -#define MONTHS_REG (0x04) -#define YEARS_REG (0x05) -#define WEEKS_REG (0x06) -#define ALARM_SECONDS_REG (0x08) -#define ALARM_MINUTES_REG (0x09) -#define ALARM_HOURS_REG (0x0A) -#define ALARM_DAYS_REG RW (0x0B) -#define ALARM_MONTHS_REG (0x0C) -#define ALARM_YEARS_REG (0x0D) -#define RTC_CTRL_REG RW (0x10) -#define RTC_STATUS_REG (0x11) -#define RTC_INTERRUPTS_REG (0x12) -#define RTC_COMP_LSB_REG (0x13) -#define RTC_COMP_MSB_REG (0x14) -#define RTC_RES_PROG_REG (0x15) -#define RTC_RESET_STATUS_REG (0x16) -#define BCK1_REG (0x17) -#define BCK2_REG (0x18) -#define BCK3_REG (0x19) -#define BCK4_REG (0x1A) -#define BCK5_REG (0x1B) -#define PUADEN_REG (0x1C) -#define REF_REG (0x1D) -#define VRTC_REG (0x1E) -#define VIO_REG (0x20) -#define VDD1_REG (0x21) -#define VDD1_OP_REG (0x22) -#define VDD1_SR_REG (0x23) -#define VDD2_REG (0x24) -#define VDD2_OP_REG (0x25) -#define VDD2_SR_REG (0x26) -#define VDD3_REG (0x27) -#define VDIG1_REG (0x30) -#define VDIG2_REG (0x31) -#define VAUX1_REG (0x32) -#define VAUX2_REG (0x33) -#define VAUX33_REG (0x34) -#define VMMC_REG (0x35) -#define VPLL_REG (0x36) -#define VDAC_REG (0x37) -#define THERM_REG (0x38) -#define BBCH_REG (0x39) -#define DCDCCTRL_REG (0x3E) -#define DEVCTRL_REG (0x3F) -#define DEVCTRL2_REG (0x40) -#define SLEEP_KEEP_LDO_ON_REG (0x41) -#define SLEEP_KEEP_RES_ON_REG (0x42) -#define SLEEP_SET_LDO_OFF_REG (0x43) -#define SLEEP_SET_RES_OFF_REG (0x44) -#define EN1_LDO_ASS_REG (0x45) -#define EN1_SMPS_ASS_REG (0x46) -#define EN2_LDO_ASS_REG (0x47) -#define EN2_SMPS_ASS_REG (0x48) -#define EN3_LDO_ASS_REG (0x49) -#define SPARE_REG (0x4A) -#define INT_STS_REG (0x50) -#define INT_MSK_REG (0x51) -#define INT_STS2_REG (0x52) -#define INT_MSK2_REG (0x53) -#define GPIO0_REG (0x60) -#define JTAGVERNUM_REG (0x80) - -/**************************************************************************\ - * Field Definition Macros -\**************************************************************************/ - -/* SECONDS_REG */ -#define PMIC_SECONDS_REG_SEC0 (0x0Fu) -#define PMIC_SECONDS_REG_SEC0_SHIFT (0x00u) -#define PMIC_SECONDS_REG_SEC1 (0x70u) -#define PMIC_SECONDS_REG_SEC1_SHIFT (0x04u) - -/* MINUTES_REG */ -#define PMIC_MINUTES_REG_MIN0 (0x0Fu) -#define PMIC_MINUTES_REG_MIN0_SHIFT (0x00u) -#define PMIC_MINUTES_REG_MIN1 (0x70u) -#define PMIC_MINUTES_REG_MIN1_SHIFT (0x04u) - -/* HOURS_REG */ -#define PMIC_HOURS_REG_HOUR0 (0x0Fu) -#define PMIC_HOURS_REG_HOUR0_SHIFT (0x00u) -#define PMIC_HOURS_REG_HOUR1 (0x30u) -#define PMIC_HOURS_REG_HOUR1_SHIFT (0x04u) -#define PMIC_HOURS_REG_PM_NAM (0x80u) -#define PMIC_HOURS_REG_PM_NAM_SHIFT (0x07u) -#define PMIC_HOURS_REG_PM_NAM_AM (0x0u) -#define PMIC_HOURS_REG_PM_NAM_PM (0x1u) - -/* DAYS_REG */ -#define PMIC_DAYS_REG_DAY0 (0x0Fu) -#define PMIC_DAYS_REG_DAY0_SHIFT (0x00u) -#define PMIC_DAYS_REG_DAY1 (0x30u) -#define PMIC_DAYS_REG_DAY1_SHIFT (0x04u) - -/* MONTHS_REG */ -#define PMIC_MONTHS_REG_MONTH0 (0x0Fu) -#define PMIC_MONTHS_REG_MONTH0_SHIFT (0x00u) -#define PMIC_MONTHS_REG_MONTH1 (0x10u) -#define PMIC_MONTHS_REG_MONTH1_SHIFT (0x04u) - -/* YEARS_REG */ -#define PMIC_YEARS_REG_YEAR0 (0x0Fu) -#define PMIC_YEARS_REG_YEAR0_SHIFT (0x00u) -#define PMIC_YEARS_REG_YEAR1 (0xF0u) -#define PMIC_YEARS_REG_YEAR1_SHIFT (0x04u) - -/* WEEKS_REG */ -#define PMIC_WEEKS_REG_WEEK (0x07u) -#define PMIC_WEEKS_REG_WEEK_SHIFT (0x00u) - -/* ALARM_SECONDS_REG */ -#define PMIC_ALARM_SECONDS_REGALARM_SEC0 (0x0Fu) -#define PMIC_ALARM_SECONDS_REGALARM_SEC0_SHIFT (0x00u) -#define PMIC_ALARM_SECONDS_REGALARM_SEC1 (0x70u) -#define PMIC_ALARM_SECONDS_REGALARM_SEC1_SHIFT (0x04u) - -/* ALARM_MINUTES_REG */ -#define PMIC_ALARM_MINUTES_REG_ALARM_MIN0 (0x0Fu) -#define PMIC_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT (0x00u) -#define PMIC_ALARM_MINUTES_REG_ALARM_MIN1 (0x70u) -#define PMIC_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT (0x04u) - -/* ALARM_HOURS_REG */ -#define PMIC_ALARM_HOURS_REG_ALARM_HOUR0 (0x0Fu) -#define PMIC_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT (0x00u) -#define PMIC_ALARM_HOURS_REG_ALARM_HOUR1 (0x30u) -#define PMIC_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT (0x04u) -#define PMIC_ALARM_HOURS_REG_ALARM_PM_NAM (0x80u) -#define PMIC_ALARM_HOURS_REG_ALARM_PM_NAM_AM (0x0u) -#define PMIC_ALARM_HOURS_REG_ALARM_PM_NAM_PM (0x1u) - -/* ALARM_DAYS_REG */ -#define PMIC_ALARM_DAYS_REG_ALARM_DAY0 (0x0Fu) -#define PMIC_ALARM_DAYS_REG_ALARM_DAY0_SHIFT (0x00u) -#define PMIC_ALARM_DAYS_REG_ALARM_DAY1 (0x30u) -#define PMIC_ALARM_DAYS_REG_ALARM_DAY1_SHIFT (0x04u) - -/* ALARM_MONTHS_REG */ -#define PMIC_ALARM_MONTHS_REG_ALARM_MONTH0 (0x0Fu) -#define PMIC_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT (0x00u) -#define PMIC_ALARM_MONTHS_REG_ALARM_MONTH1 (0x10u) -#define PMIC_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT (0x04u) - -/* ALARM_YEARS_REG */ -#define PMIC_ALARM_YEARS_REG_ALARM_YEAR0 (0x0Fu) -#define PMIC_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT (0x00u) -#define PMIC_ALARM_YEARS_REG_ALARM_YEAR1 (0xF0u) -#define PMIC_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT (0x04u) - -/* RTC_CTRL_REG */ -#define PMIC_RTC_CTRL_REG_STOP_RTC (0x01u) -#define PMIC_RTC_CTRL_REG_STOP_RTC_SHIFT (0x00u) -#define PMIC_RTC_CTRL_REG_STOP_RTC_FROZEN (0x0u) -#define PMIC_RTC_CTRL_REG_STOP_RTC_RUNNING (0x1u) - -#define PMIC_RTC_CTRL_REG_ROUND_30S (0x02u) -#define PMIC_RTC_CTRL_REG_ROUND_30S_SHIFT (0x01u) -#define PMIC_RTC_CTRL_REG_ROUND_30S_NO_ROUND_30S (0x0u) -#define PMIC_RTC_CTRL_REG_ROUND_30S_ROUND_30S (0x1u) - -#define PMIC_RTC_CTRL_REG_AUTO_COMP (0x04u) -#define PMIC_RTC_CTRL_REG_AUTO_COMP_SHIFT (0x02u) -#define PMIC_RTC_CTRL_REG_AUTO_COMP_NO_AUTO_COMP (0x0u) -#define PMIC_RTC_CTRL_REG_AUTO_COMP_AUTO_COMP (0x1u) - -#define PMIC_RTC_CTRL_REG_MODE_12_24 (0x08u) -#define PMIC_RTC_CTRL_REG_MODE_12_24_SHIFT (0x03u) -#define PMIC_RTC_CTRL_REG_MODE_12_24_MODE_24 (0x0u) -#define PMIC_RTC_CTRL_REG_MODE_12_24_MODE_12 (0x1u) - -#define PMIC_RTC_CTRL_REG_TEST_MODE (0x10u) -#define PMIC_RTC_CTRL_REG_TEST_MODE_SHIFT (0x04u) -#define PMIC_RTC_CTRL_REG_TEST_MODE_FUNC_MODE (0x0u) -#define PMIC_RTC_CTRL_REG_TEST_MODE_TEST_MODE (0x1u) - -#define PMIC_RTC_CTRL_REG_SET_32_COUNTER (0x20u) -#define PMIC_RTC_CTRL_REG_SET_32_COUNTER_SHIFT (0x05u) -#define PMIC_RTC_CTRL_REG_SET_32_COUNTER_NO_ACTION (0x0u) -#define PMIC_RTC_CTRL_REG_SET_32_COUNTER_SET_COMP (0x1u) - -#define PMIC_RTC_CTRL_REG_GET_TIME (0x40u) -#define PMIC_RTC_CTRL_REG_GET_TIME_SHIFT (0x06u) -#define PMIC_RTC_CTRL_REG_GET_TIME_RESET (0x0u) -#define PMIC_RTC_CTRL_REG_GET_TIME_ASSERT (0x1u) - -#define PMIC_RTC_CTRL_REG_RTC_V_OPT (0x80u) -#define PMIC_RTC_CTRL_REG_RTC_V_OPT_SHIFT (0x07u) -#define PMIC_RTC_CTRL_REG_RTC_V_OPT_DYN_REG (0x0u) -#define PMIC_RTC_CTRL_REG_RTC_V_OPT_SHDW_REG (0x1u) - -/* RTC_STATUS_REG */ -#define PMIC_RTC_STATUS_REG_RUN (0x02u) -#define PMIC_RTC_STATUS_REG_RUN_SHIFT (0x01u) -#define PMIC_RTC_STATUS_REG_RUN_FROZEN (0x0u) -#define PMIC_RTC_STATUS_REG_RUN_RUNNING (0x1u) - -#define PMIC_RTC_STATUS_REG_EVENT_1S (0x04u) -#define PMIC_RTC_STATUS_REG_EVENT_1S_SHIFT (0x02u) - -#define PMIC_RTC_STATUS_REG_EVENT_1M (0x08u) -#define PMIC_RTC_STATUS_REG_EVENT_1M_SHIFT (0x03u) - -#define PMIC_RTC_STATUS_REG_EVENT_1H (0x10u) -#define PMIC_RTC_STATUS_REG_EVENT_1H_SHIFT (0x04u) - -#define PMIC_RTC_STATUS_REG_EVENT_1D (0x20u) -#define PMIC_RTC_STATUS_REG_EVENT_1D_SHIFT (0x05u) - -#define PMIC_RTC_STATUS_REG_ALARM (0x40u) -#define PMIC_RTC_STATUS_REG_ALARM_SHIFT (0x06u) - -#define PMIC_RTC_STATUS_REG_POWER_UP (0x80u) -#define PMIC_RTC_STATUS_REG_POWER_UP_SHIFT (0x07u) - -/* RTC_INTERRUPTS_REG */ -#define PMIC_RTC_INTERRUPTS_REG_EVERY (0x0Fu) -#define PMIC_RTC_INTERRUPTS_REG_EVERY_SHFT (0x00u) -#define PMIC_RTC_INTERRUPTS_REG_EVERY_SEC (0x0u) -#define PMIC_RTC_INTERRUPTS_REG_EVERY_MIN (0x1u) -#define PMIC_RTC_INTERRUPTS_REG_EVERY_HR (0x2u) -#define PMIC_RTC_INTERRUPTS_REG_EVERY_DAY (0x3u) - -/* RTC_COMP_LSB_REG */ -#define PMIC_RTC_COMP_LSB_REG_RTC_COMP_LSB (0xFFu) -#define PMIC_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT (0x00u) - -/* RTC_COMP_MSB_REG */ -#define PMIC_RTC_COMP_MSB_REG_RTC_COMP_MSB (0xFFu) -#define PMIC_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT (0x00u) - -/* RTC_RES_PROG_REG */ -#define PMIC_RTC_RES_PROG_REG_SW_RES_PROG (0x3Fu) -#define PMIC_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT (0x00u) - -/* RTC_RESET_STATUS_REG */ -#define PMIC_RTC_RESET_STATUS_REG_RESET_STATUS (0x01u) -#define PMIC_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT (0x00u) - -/* BCK1_REG */ -#define PMIC_BCK1_REG_BCKUP (0xFFu) -#define PMIC_BCK1_REG_BCKUP_SHIFT (0x00u) - -/* BCK2_REG */ -#define PMIC_BCK2_REG_BCKUP (0xFFu) -#define PMIC_BCK2_REG_BCKUP_SHIFT (0x00u) - -/* BCK3_REG */ -#define PMIC_BCK3_REG_BCKUP (0xFFu) -#define PMIC_BCK3_REG_BCKUP_SHIFT (0x00u) - -/* BCK4_REG */ -#define PMIC_BCK4_REG_BCKUP (0xFFu) -#define PMIC_BCK4_REG_BCKUP_SHIFT (0x00u) - -/* BCK5_REG */ -#define PMIC_BCK5_REG_BCKUP (0xFFu) -#define PMIC_BCK5_REG_BCKUP_SHIFT (0x00u) - -/* PUADEN_REG */ -#define PMIC_PUADEN_REG_BOOT0P (0x01u) -#define PMIC_PUADEN_REG_BOOT0P_SHIFT (0x00u) -#define PMIC_PUADEN_REG_BOOT0P_ENABLED (0x1u) -#define PMIC_PUADEN_REG_BOOT0P_DISABLED (0x0u) - -#define PMIC_PUADEN_REG_BOOT1P (0x02u) -#define PMIC_PUADEN_REG_BOOT1P_SHIFT (0x01u) -#define PMIC_PUADEN_REG_BOOT1P_ENABLED (0x1u) -#define PMIC_PUADEN_REG_BOOT1P_DISABLED (0x0u) - -#define PMIC_PUADEN_REG_PWRHOLDP (0x04u) -#define PMIC_PUADEN_REG_PWRHOLDP_SHIFT (0x02u) -#define PMIC_PUADEN_REG_PWRHOLDP_ENABLED (0x1u) -#define PMIC_PUADEN_REG_PWRHOLDP_DISABLED (0x0u) - -#define PMIC_PUADEN_REG_SLEEPP (0x08u) -#define PMIC_PUADEN_REG_SLEEPP_SHIFT (0x03u) -#define PMIC_PUADEN_REG_SLEEPP_ENABLED (0x1u) -#define PMIC_PUADEN_REG_SLEEPP_DISABLED (0x0u) - -#define PMIC_PUADEN_REG_PWRONP (0x10u) -#define PMIC_PUADEN_REG_PWRONP_SHIFT (0x04u) -#define PMIC_PUADEN_REG_PWRONP_ENABLED (0x1u) -#define PMIC_PUADEN_REG_PWRONP_DISABLED (0x0u) - -#define PMIC_PUADEN_REG_I2CSRP (0x20u) -#define PMIC_PUADEN_REG_I2CSRP_SHIFT (0x05u) -#define PMIC_PUADEN_REG_I2CSRP_ENABLED (0x1u) -#define PMIC_PUADEN_REG_I2CSRP_DISABLED (0x0u) - -#define PMIC_PUADEN_REG_I2CCTLP (0x40u) -#define PMIC_PUADEN_REG_I2CCTLP_SHIFT (0x06u) -#define PMIC_PUADEN_REG_I2CCTLP_ENABLED (0x1u) -#define PMIC_PUADEN_REG_I2CCTLP_DISABLED (0x0u) - -#define PMIC_PUADEN_REG_EN3P (0x80u) -#define PMIC_PUADEN_REG_EN3P_SHIFT (0x07u) -#define PMIC_PUADEN_REG_EN3P_ENABLED (0x1u) -#define PMIC_PUADEN_REG_EN3P_DISABLED (0x0u) - -/* REF_REG */ -#define PMIC_REF_REG_ST (0x03u) -#define PMIC_REF_REG_ST_SHIFT (0x00u) -#define PMIC_REF_REG_ST_OFF (0x0u) -#define PMIC_REF_REG_ST_ON_HI_POW (0x1u) -#define PMIC_REF_REG_ST_RSVD (0x2u) -#define PMIC_REF_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_REF_REG_VMBCH_SEL (0x0Cu) -#define PMIC_REF_REG_VMBCH_SEL_SHIFT (0x02u) -#define PMIC_REF_REG_VMBCH_SEL_BYPASS (0x0u) -#define PMIC_REF_REG_VMBCH_SEL_2_8_V (0x1u) -#define PMIC_REF_REG_VMBCH_SEL_2_9_V (0x2u) -#define PMIC_REF_REG_VMBCH_SEL_3_0_V (0x3u) - -/* VRTC_REG */ -#define PMIC_VRTC_REG_ST (0x03u) -#define PMIC_VRTC_REG_ST_SHIFT (0x00u) -#define PMIC_VRTC_REG_ST_RSVD (0x0u) -#define PMIC_VRTC_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VRTC_REG_ST_RSVD_1 (0x2u) -#define PMIC_VRTC_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VRTC_REG_VRTC_OFFMASK (0x08u) -#define PMIC_VRTC_REG_VRTC_OFFMASK_SHIFT (0x03u) -#define PMIC_VRTC_REG_VRTC_OFFMASK_FULL_LOAD (0x1u) -#define PMIC_VRTC_REG_VRTC_OFFMASK_LOW_POW (0x0u) - -/* VIO_REG */ -#define PMIC_VIO_REG_ST (0x03u) -#define PMIC_VIO_REG_ST_SHIFT (0x00u) -#define PMIC_VIO_REG_ST_OFF (0x0u) -#define PMIC_VIO_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VIO_REG_ST_OFF_1 (0x2u) -#define PMIC_VIO_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VIO_REG_SEL (0x0Cu) -#define PMIC_VIO_REG_SEL_SHIFT (0x02u) -#define PMIC_VIO_REG_SEL_1_5_V (0x0u) -#define PMIC_VIO_REG_SEL_1_8_V (0x1u) -#define PMIC_VIO_REG_SEL_2_5_V (0x2u) -#define PMIC_VIO_REG_SEL_3_3_V (0x3u) - -#define PMIC_VIO_REG_ILMAX (0xC0u) -#define PMIC_VIO_REG_ILMAX_SHIFT (0x06u) -#define PMIC_VIO_REG_ILMAX_0_5_A (0x0u) -#define PMIC_VIO_REG_ILMAX_1_0_A_1 (0x1u) -#define PMIC_VIO_REG_ILMAX_1_0_A_2 (0x2u) -#define PMIC_VIO_REG_ILMAX_1_0_A_3 (0x3u) - -/* VDD1_REG */ -#define PMIC_VDD1_REG_ST (0x03u) -#define PMIC_VDD1_REG_ST_SHIFT (0x00u) -#define PMIC_VDD1_REG_ST_OFF (0x0u) -#define PMIC_VDD1_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VDD1_REG_ST_OFF1 (0x2u) -#define PMIC_VDD1_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VDD1_REG_TSTEP (0x1Cu) -#define PMIC_VDD1_REG_TSTEP_SHIFT (0x02u) -#define PMIC_VDD1_REG_TSTEP_0 (0x0u) -#define PMIC_VDD1_REG_TSTEP_12_5 (0x1u) -#define PMIC_VDD1_REG_TSTEP_9_4 (0x2u) -#define PMIC_VDD1_REG_TSTEP_7_5 (0x3u) -#define PMIC_VDD1_REG_TSTEP_6_25 (0x4u) -#define PMIC_VDD1_REG_TSTEP_4_7 (0x5u) -#define PMIC_VDD1_REG_TSTEP_3_12 (0x6u) -#define PMIC_VDD1_REG_TSTEP_2_5 (0x7u) - -#define PMIC_VDD1_REG_ILMAX (0x20u) -#define PMIC_VDD1_REG_ILMAX_SHIFT (0x05u) -#define PMIC_VDD1_REG_ILMAX_1_0_A (0x0u) -#define PMIC_VDD1_REG_ILMAX_1_5_A (0x1u) - -#define PMIC_VDD1_REG_VGAIN_SEL (0xC0u) -#define PMIC_VDD1_REG_VGAIN_SEL_SHIFT (0x06u) -#define PMIC_VDD1_REG_VGAIN_SEL_X1 (0x0u) -#define PMIC_VDD1_REG_VGAIN_SEL_X1_1 (0x1u) -#define PMIC_VDD1_REG_VGAIN_SEL_X2 (0x2u) -#define PMIC_VDD1_REG_VGAIN_SEL_X3 (0x3u) - -/* VDD1_OP_REG */ -#define PMIC_VDD1_OP_REG_SEL (0x7Fu) -#define PMIC_VDD1_OP_REG_SEL_SHIFT (0x00u) - -#define PMIC_VDD1_OP_REG_CMD (0x80u) -#define PMIC_VDD1_OP_REG_CMD_SHIFT (0x07u) -#define PMIC_VDD1_OP_REG_CMD_OP (0x0u) -#define PMIC_VDD1_OP_REG_CMD_SR (0x1u) - -/* VDD1_SR_REG */ -#define PMIC_VDD1_SR_REG_SEL (0x7Fu) -#define PMIC_VDD1_SR_REG_SEL_SHIFT (0x00u) - -/* VDD2_REG */ -#define PMIC_VDD2_REG_ST (0x03u) -#define PMIC_VDD2_REG_ST_SHIFT (0x00u) -#define PMIC_VDD2_REG_ST_OFF (0x0u) -#define PMIC_VDD2_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VDD2_REG_ST_OFF_1 (0x2u) -#define PMIC_VDD2_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VDD2_REG_TSTEP (0x1Cu) -#define PMIC_VDD2_REG_TSTEP_SHIFT (0x02u) -#define PMIC_VDD2_REG_TSTEP_0 (0x0u) -#define PMIC_VDD2_REG_TSTEP_12_5 (0x1u) -#define PMIC_VDD2_REG_TSTEP_9_4 (0x2u) -#define PMIC_VDD2_REG_TSTEP_7_5 (0x3u) -#define PMIC_VDD2_REG_TSTEP_6_25 (0x4u) -#define PMIC_VDD2_REG_TSTEP_4_7 (0x5u) -#define PMIC_VDD2_REG_TSTEP_3_12 (0x6u) -#define PMIC_VDD2_REG_TSTEP_2_5 (0x7u) - -#define PMIC_VDD2_REG_ILMAX (0x20u) -#define PMIC_VDD2_REG_ILMAX_SHIFT (0x05u) -#define PMIC_VDD2_REG_ILMAX_1_0_A (0x0u) -#define PMIC_VDD2_REG_ILMAX_1_5_A (0x1u) - -#define PMIC_VDD2_REG_VGAIN_SEL (0xC0u) -#define PMIC_VDD2_REG_VGAIN_SEL_SHIFT (0x06u) -#define PMIC_VDD2_REG_VGAIN_SEL_X1 (0x0u) -#define PMIC_VDD2_REG_VGAIN_SEL_X1_0 (0x1u) -#define PMIC_VDD2_REG_VGAIN_SEL_X3 (0x2u) -#define PMIC_VDD2_REG_VGAIN_SEL_X4 (0x3u) - -/* VDD2_OP_REG */ -#define PMIC_VDD2_OP_REG_SEL (0x7Fu) -#define PMIC_VDD2_OP_REG_SEL_SHIFT (0x00u) - -#define PMIC_VDD2_OP_REG_CMD (0x80u) -#define PMIC_VDD2_OP_REG_CMD_SHIFT (0x07u) -#define PMIC_VDD2_OP_REG_CMD_OP (0x0u) -#define PMIC_VDD2_OP_REG_CMD_SR (0x1u) - -/* VDD2_SR_REG */ -#define PMIC_VDD2_SR_REG_SEL (0x7Fu) -#define PMIC_VDD2_SR_REG_SEL_SHIFT (0x00u) - -/* VDD3_REG */ -#define PMIC_VDD3_REG_ST (0x03u) -#define PMIC_VDD3_REG_ST_SHIFT (0x00u) -#define PMIC_VDD3_REG_ST_OFF (0x0u) -#define PMIC_VDD3_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VDD3_REG_ST_OFF_1 (0x2u) -#define PMIC_VDD3_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VDD3_REG_CKINEN (0x04u) -#define PMIC_VDD3_REG_CKINEN_SHIFT (0x02u) - -/* VDIG1_REG */ -#define PMIC_VDIG1_REG_ST (0x03u) -#define PMIC_VDIG1_REG_ST_SHIFT (0x00u) -#define PMIC_VDIG1_REG_ST_OFF (0x0u) -#define PMIC_VDIG1_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VDIG1_REG_ST_OFF_1 (0x2u) -#define PMIC_VDIG1_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VDIG1_REG_SEL (0x0Cu) -#define PMIC_VDIG1_REG_SEL_SHIFT (0x02u) -#define PMIC_VDIG1_REG_SEL_1_2_V (0x0u) -#define PMIC_VDIG1_REG_SEL_1_5_V (0x1u) -#define PMIC_VDIG1_REG_SEL_1_8_V (0x2u) -#define PMIC_VDIG1_REG_SEL_2_7_v (0x3u) - -/* VDIG2_REG */ -#define PMIC_VDIG2_REG_ST (0x03u) -#define PMIC_VDIG2_REG_ST_SHIFT (0x00u) -#define PMIC_VDIG2_REG_ST_OFF (0x0u) -#define PMIC_VDIG2_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VDIG2_REG_ST_OFF_1 (0x2u) -#define PMIC_VDIG2_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VDIG2_REG_SEL (0x0Cu) -#define PMIC_VDIG2_REG_SEL_SHIFT (0x02u) -#define PMIC_VDIG2_REG_SEL_1_0_V (0x0u) -#define PMIC_VDIG2_REG_SEL_1_1_V (0x1u) -#define PMIC_VDIG2_REG_SEL_1_2_V (0x2u) -#define PMIC_VDIG2_REG_SEL_1_8_v (0x3u) - -/* VAUX1_REG */ -#define PMIC_VAUX1_REG_ST (0x03u) -#define PMIC_VAUX1_REG_ST_SHIFT (0x00u) -#define PMIC_VAUX1_REG_ST_OFF (0x0u) -#define PMIC_VAUX1_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VAUX1_REG_ST_OFF_1 (0x2u) -#define PMIC_VAUX1_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VAUX1_REG_SEL (0x0Cu) -#define PMIC_VAUX1_REG_SEL_SHIFT (0x00u) -#define PMIC_VAUX1_REG_SEL_1_8_V (0x0u) -#define PMIC_VAUX1_REG_SEL_2_5_V (0x1u) -#define PMIC_VAUX1_REG_SEL_2_8_V (0x2u) -#define PMIC_VAUX1_REG_SEL_2_85_V (0x3u) - -/* VAUX2_REG */ -#define PMIC_VAUX2_REG_ST (0x03u) -#define PMIC_VAUX2_REG_ST_SHIFT (0x00u) -#define PMIC_VAUX2_REG_ST_OFF (0x0u) -#define PMIC_VAUX2_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VAUX2_REG_ST_OFF_1 (0x2u) -#define PMIC_VAUX2_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VAUX2_REG_SEL (0x0Cu) -#define PMIC_VAUX2_REG_SEL_SHIFT (0x00u) -#define PMIC_VAUX2_REG_SEL_1_8_V (0x0u) -#define PMIC_VAUX2_REG_SEL_2_8_V (0x1u) -#define PMIC_VAUX2_REG_SEL_2_9_V (0x2u) -#define PMIC_VAUX2_REG_SEL_3_3_V (0x3u) - -/* VAUX33_REG */ -#define PMIC_VAUX33_REG_ST (0x03u) -#define PMIC_VAUX33_REG_ST_SHIFT (0x00u) -#define PMIC_VAUX33_REG_ST_OFF (0x0u) -#define PMIC_VAUX33_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VAUX33_REG_ST_OFF_1 (0x2u) -#define PMIC_VAUX33_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VAUX33_REG_SEL (0x0Cu) -#define PMIC_VAUX33_REG_SEL_SHIFT (0x00u) -#define PMIC_VAUX33_REG_SEL_1_8_V (0x0u) -#define PMIC_VAUX33_REG_SEL_2_0_V (0x1u) -#define PMIC_VAUX33_REG_SEL_2_8_V (0x2u) -#define PMIC_VAUX33_REG_SEL_3_3_V (0x3u) - -/* VMMC_REG */ -#define PMIC_VMMC_REG_ST (0x03u) -#define PMIC_VMMC_REG_ST_SHIFT (0x00u) -#define PMIC_VMMC_REG_ST_OFF (0x0u) -#define PMIC_VMMC_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VMMC_REG_ST_OFF_1 (0x2u) -#define PMIC_VMMC_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VMMC_REG_SEL (0x0Cu) -#define PMIC_VMMC_REG_SEL_SHIFT (0x00u) -#define PMIC_VMMC_REG_SEL_1_8_V (0x0u) -#define PMIC_VMMC_REG_SEL_2_8_V (0x1u) -#define PMIC_VMMC_REG_SEL_3_0_V (0x2u) -#define PMIC_VMMC_REG_SEL_3_3_V (0x3u) - -/* VPLL_REG */ -#define PMIC_VPLL_REG_ST (0x03u) -#define PMIC_VPLL_REG_ST_SHIFT (0x00u) -#define PMIC_VPLL_REG_ST_OFF (0x0u) -#define PMIC_VPLL_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VPLL_REG_ST_OFF_1 (0x2u) -#define PMIC_VPLL_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VPLL_REG_SEL (0x0Cu) -#define PMIC_VPLL_REG_SEL_SHIFT (0x00u) -#define PMIC_VPLL_REG_SEL_1_0_V (0x0u) -#define PMIC_VPLL_REG_SEL_1_1_V (0x1u) -#define PMIC_VPLL_REG_SEL_1_8_V (0x2u) -#define PMIC_VPLL_REG_SEL_2_5_V (0x3u) - -/* VDAC_REG */ -#define PMIC_VDAC_REG_ST (0x03u) -#define PMIC_VDAC_REG_ST_SHIFT (0x00u) -#define PMIC_VDAC_REG_ST_OFF (0x0u) -#define PMIC_VDAC_REG_ST_ON_HI_POW (0x1u) -#define PMIC_VDAC_REG_ST_OFF_1 (0x2u) -#define PMIC_VDAC_REG_ST_ON_LOW_POW (0x3u) - -#define PMIC_VDAC_REG_SEL (0x0Cu) -#define PMIC_VDAC_REG_SEL_SHIFT (0x00u) -#define PMIC_VDAC_REG_SEL_1_8_V (0x0u) -#define PMIC_VDAC_REG_SEL_2_6_V (0x1u) -#define PMIC_VDAC_REG_SEL_2_8_V (0x2u) -#define PMIC_VDAC_REG_SEL_2_85_V (0x3u) - -/* Therm_REG */ -#define PMIC_THERM_REG_THERM_STATE (0x01u) -#define PMIC_THERM_REG_THERM_STATE_SHIFT (0x00u) -#define PMIC_THERM_REG_THERM_STATE_DISABLE (0x0u) -#define PMIC_THERM_REG_THERM_STATE_ENABLE (0x1u) - -#define PMIC_THERM_REG_THERM_HDSEL (0xC0u) -#define PMIC_THERM_REG_THERM_HDSEL_SHIFT (0x02u) -#define PMIC_THERM_REG_THERM_HDSEL_LOW (0x0u) -#define PMIC_THERM_REG_THERM_HDSEL_HIGH (0x3u) - -#define PMIC_THERM_REG_THERM_TS (0x10u) -#define PMIC_THERM_REG_THERM_TS_SHIFT (0x04u) -#define PMIC_THERM_REG_THERM_TS_TSH_REACHED (0x0u) -#define PMIC_THERM_REG_THERM_TS_TSH_NOT_REACHED (0x1u) - -#define PMIC_THERM_REG_THERM_HD (0x20u) -#define PMIC_THERM_REG_THERM_HD_SHIFT (0x05u) -#define PMIC_THERM_REG_THERM_HD_TSH_REACHED (0x0u) -#define PMIC_THERM_REG_THERM_HD_TSH_NOT_REACHED (0x1u) - -/* BBCH_REG */ -#define PMIC_BBCH_REG_BBCHEN (0x01u) -#define PMIC_BBCH_REG_BBCHEN_SHIFT (0x00u) - -#define PMIC_BBCH_REG_BBSEL (0x06u) -#define PMIC_BBCH_REG_BBSEL_SHIFT (0x01u) - -/* DCDCCTRL_REG */ -#define PMIC_DCDCCTRL_REG_DCDCCKSYNC (0x03u) -#define PMIC_DCDCCTRL_REG_DCDCCKSYNC_SHIFT (0x00u) -#define PMIC_DCDCCTRL_REG_DCDCCKSYNC_NO_SYNC (0x0u) -#define PMIC_DCDCCTRL_REG_DCDCCKSYNC_SYNC_WITH_PHASE_SHIFT (0x1u) -#define PMIC_DCDCCTRL_REG_DCDCCKSYNC_NO_SYNCH (0x2u) -#define PMIC_DCDCCTRL_REG_DCDCCKSYNC_SYNC (0x3u) - -#define PMIC_DCDCCTRL_REG_DCDCCKEXT (0x04u) -#define PMIC_DCDCCTRL_REG_DCDCCKEXT_SHIFT (0x02u) -#define PMIC_DCDCCTRL_REG_DCDCCKEXT_GPIO (0x0u) -#define PMIC_DCDCCTRL_REG_DCDCCKEXT_EXT_CLK (0x1u) - -#define PMIC_DCDCCTRL_REG_VIO_PSKIP (0x08u) -#define PMIC_DCDCCTRL_REG_VIO_PSKIP_SHIFT (0x03u) - -#define PMIC_DCDCCTRL_REG_VDD1_PSKIP (0x10u) -#define PMIC_DCDCCTRL_REG_VDD1_PSKIP_SHIFT (0x04u) - -#define PMIC_DCDCCTRL_REG_VDD2_PSKIP (0x20u) -#define PMIC_DCDCCTRL_REG_VDD2_PSKIP_SHIFT (0x05u) - -/* DEVCTRL_REG */ -#define PMIC_DEVCTRL_REG_DEV_OFF (0x01u) -#define PMIC_DEVCTRL_REG_DEV_OFF_SHIFT (0x00u) -#define PMIC_DEVCTRL_REG_DEV_OFF_TO_OFF (0x1u) - -#define PMIC_DEVCTRL_REG_DEV_SLP (0x02u) -#define PMIC_DEVCTRL_REG_DEV_SLP_SHIFT (0x01u) -#define PMIC_DEVCTRL_REG_DEV_SLP_SLEEP_TO_ACTIVE (0x0u) -#define PMIC_DEVCTRL_REG_DEV_SLP_TO_SLEEP (0x1u) - -#define PMIC_DEVCTRL_REG_DEV_ON (0x04u) -#define PMIC_DEVCTRL_REG_DEV_ON_SHIFT (0x02u) -#define PMIC_DEVCTRL_REG_DEV_ON_MAINTAIN (0x1u) - -#define PMIC_DEVCTRL_REG_DEV_OFF_RST (0x08u) -#define PMIC_DEVCTRL_REG_DEV_OFF_RST_SHIFT (0x03u) -#define PMIC_DEVCTRL_REG_DEV_OFF_RST_TO_OFF (0x1u) - -#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL (0x10u) -#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SHIFT (0x04u) -#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0u) -#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1u) - -#define PMIC_DEVCTRL_REG_CK32K_CTRL (0x20u) -#define PMIC_DEVCTRL_REG_CK32K_CTRL_SHIFT (0x05u) -#define PMIC_DEVCTRL_REG_CK32K_CTRL_X_OSC (0x0u) -#define PMIC_DEVCTRL_REG_CK32K_CTRL_RC_OSC (0x1u) - -#define PMIC_DEVCTRL_REG_RTC_PWDN (0x40u) -#define PMIC_DEVCTRL_REG_RTC_PWDN_SHIFT (0x06u) -#define PMIC_DEVCTRL_REG_RTC_PWDN_DIS_RTC (0x1u) - -/* DEVCTRL2_REG */ -#define PMIC_DEVCTRL2_REG_IT_POL (0x01u) -#define PMIC_DEVCTRL2_REG_IT_POL_SHIFT (0x00u) -#define PMIC_DEVCTRL2_REG_IT_POL_ACTIVE_LOW (0x0u) -#define PMIC_DEVCTRL2_REG_IT_POL_ACTIVE_HIGH (0x1u) - -#define PMIC_DEVCTRL2_REG_PWRON_LP_RST (0x02u) -#define PMIC_DEVCTRL2_REG_PWRON_LP_RST_SHIFT (0x01u) -#define PMIC_DEVCTRL2_REG_PWRON_LP_RST_ALLOW_RST (0x1u) - -#define PMIC_DEVCTRL2_REG_PWRON_LP_OFF (0x04u) -#define PMIC_DEVCTRL2_REG_PWRON_LP_OFF_SHIFT (0x02u) -#define PMIC_DEVCTRL2_REG_PWRON_LP_OFF_TURN_OFF (0x1u) - -#define PMIC_DEVCTRL2_REG_SLEEPSIG_POL (0x08u) -#define PMIC_DEVCTRL2_REG_SLEEPSIG_POL_SHIFT (0x03u) -#define PMIC_DEVCTRL2_REG_SLEEPSIG_POL_LOW (0x0u) -#define PMIC_DEVCTRL2_REG_SLEEPSIG_POL_HIGH (0x1u) - -#define PMIC_DEVCTRL2_REG_TSLOT_LENGTH (0x30u) -#define PMIC_DEVCTRL2_REG_TSLOT_LENGTH_SHIFT (0x04u) -#define PMIC_DEVCTRL2_REG_TSLOT_LENGTH_0_us (0x0u) -#define PMIC_DEVCTRL2_REG_TSLOT_LENGTH_200_us (0x1u) -#define PMIC_DEVCTRL2_REG_TSLOT_LENGTH_500_us (0x2u) -#define PMIC_DEVCTRL2_REG_TSLOT_LENGTH_2000_us (0x3u) - -/* SLEEP_KEEP_LDO_ON_REG */ -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VMMC_KEEPON (0x01u) -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VMMC_KEEPON_SHIFT (0x00u) - -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VDIG1_KEEPON (0x02u) -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VDIG1_KEEPON_SHIFT (0x01u) - -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VDIG2_KEEPON (0x04u) -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VDIG2_KEEPON_SHIFT (0x02u) - -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VAUX1_KEEPON (0x08u) -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VAUX1_KEEPON_SHIFT (0x03u) - -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VAUX2_KEEPON (0x10u) -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VAUX2_KEEPON_SHIFT (0x04u) - -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VAUX33_KEEPON (0x20u) -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VAUX33_KEEPON_SHIFT (0x05u) - -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VPLL_KEEPON (0x40u) -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VPLL_KEEPON_SHIFT (0x06u) - -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VDAC_KEEPON (0x80u) -#define PMIC_SLEEP_KEEP_LDO_ON_REG_VDAC_KEEPON_SHIFT (0x07u) - -/* SLEEP_KEEP_RES_ON_REG */ -#define PMIC_SLEEP_KEEP_RES_ON_REG_VIO_KEEPON (0x01u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VIO_KEEPON_SHIFT (0x00u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VIO_KEEPON_SET (0x0u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VIO_KEEPON_MAINT (0x1u) - -#define PMIC_SLEEP_KEEP_RES_ON_REG_VDD1_KEEPON (0x02u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VDD1_KEEPON_SHIFT (0x01u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VDD1_KEEPON_SET (0x0u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VDD1_KEEPON_MAINT (0x1u) - -#define PMIC_SLEEP_KEEP_RES_ON_REG_VDD2_KEEPON (0x04u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VDD2_KEEPON_SHIFT (0x02u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VDD2_KEEPON_SET (0x0u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VDD2_KEEPON_MAINT (0x1u) - -#define PMIC_SLEEP_KEEP_RES_ON_REG_VDD3_KEEPON (0x08u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VDD3_KEEPON_SHIFT (0x03u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VDD3_KEEPON_SET (0x0u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VDD3_KEEPON_MAINT (0x1u) - -#define PMIC_SLEEP_KEEP_RES_ON_REG_I2CHS_KEEPON (0x10u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_I2CHS_KEEPON_SHIFT (0x04u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_I2CHS_KEEPON_OFF (0x0u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_I2CHS_KEEPON_MAINT (0x1u) - -#define PMIC_SLEEP_KEEP_RES_ON_REG_VRTC_KEEPON (0x20u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VRTC_KEEPON_SHIFT (0x05u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VRTC_KEEPON_SET (0x0u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_VRTC_KEEPON_MAINT (0x1u) - -#define PMIC_SLEEP_KEEP_RES_ON_REG_CLKOUT32K_KEEPON (0x40u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_CLKOUT32K_KEEPON_SHIFT (0x06u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_CLKOUT32K_KEEPON_SET (0x0u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_CLKOUT32K_KEEPON_MAINT (0x1u) - -#define PMIC_SLEEP_KEEP_RES_ON_REG_THERM_KEEPON (0x80u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_THERM_KEEPON_SHIFT (0x07u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_THERM_KEEPON_OFF (0x0u) -#define PMIC_SLEEP_KEEP_RES_ON_REG_THERM_KEEPON_MAINT (0x1u) - -/* SLEEP_SET_LDO_OFF_REG */ -#define PMIC_SLEEP_SET_LDO_OFF_REG_VMMC_SETOFF (0x01u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VMMC_SETOFF_SHIFT (0x00u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VMMC_SETOFF_OFF (0x1u) - -#define PMIC_SLEEP_SET_LDO_OFF_REG_VDIG1_SETOFF (0x02u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VDIG1_SETOFF_SHIFT (0x01u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VDIG1_SETOFF_OFF (0x1u) - -#define PMIC_SLEEP_SET_LDO_OFF_REG_VDIG2_SETOFF (0x04u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VDIG2_SETOFF_SHIFT (0x02u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VDIG2_SETOFF_OFF (0x1u) - -#define PMIC_SLEEP_SET_LDO_OFF_REG_VAUX1_SETOFF (0x08u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VAUX1_SETOFF_SHIFT (0x03u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VAUX1_SETOFF_OFF (0x1u) - -#define PMIC_SLEEP_SET_LDO_OFF_REG_VAUX2_SETOFF (0x10u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VAUX2_SETOFF_SHIFT (0x04u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VAUX2_SETOFF_OFF (0x1u) - -#define PMIC_SLEEP_SET_LDO_OFF_REG_VAUX33_SETOFF (0x20u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VAUX33_SETOFF_SHIFT (0x05u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VAUX33_SETOFF_OFF (0x1u) - -#define PMIC_SLEEP_SET_LDO_OFF_REG_VPLL_SETOFF (0x40u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VPLL_SETOFF_SHIFT (0x06u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VPLL_SETOFF_OFF (0x1u) - -#define PMIC_SLEEP_SET_LDO_OFF_REG_VDAC_SETOFF (0x80u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VDAC_SETOFF_SHIFT (0x07u) -#define PMIC_SLEEP_SET_LDO_OFF_REG_VDAC_SETOFF_OFF (0x1u) - -/* SLEEP_SET_RES_OFF_REG */ -#define PMIC_SLEEP_SET_RES_OFF_REG_VIO_SETOFF (0x01u) -#define PMIC_SLEEP_SET_RES_OFF_REG_VIO_SETOFF_SHIFT (0x00u) -#define PMIC_SLEEP_SET_RES_OFF_REG_VIO_SETOFF_OFF (0x1u) - -#define PMIC_SLEEP_SET_RES_OFF_REG_VDD1_SETOFF (0x02u) -#define PMIC_SLEEP_SET_RES_OFF_REG_VDD1_SETOFF_SHIFT (0x01u) -#define PMIC_SLEEP_SET_RES_OFF_REG_VDD1_SETOFF_OFF (0x1u) - -#define PMIC_SLEEP_SET_RES_OFF_REG_VDD2_SETOFF (0x04u) -#define PMIC_SLEEP_SET_RES_OFF_REG_VDD2_SETOFF_SHIFT (0x02u) -#define PMIC_SLEEP_SET_RES_OFF_REG_VDD2_SETOFF_OFF (0x1u) - -#define PMIC_SLEEP_SET_RES_OFF_REG_VDD3_SETOFF (0x08u) -#define PMIC_SLEEP_SET_RES_OFF_REG_VDD3_SETOFF_SHIFT (0x03u) -#define PMIC_SLEEP_SET_RES_OFF_REG_VDD3_SETOFF_OFF (0x1u) - -#define PMIC_SLEEP_SET_RES_OFF_REG_SPARE_SETOFF (0x10u) -#define PMIC_SLEEP_SET_RES_OFF_REG_SPARE_SETOFF_SHIFT (0x04u) -#define PMIC_SLEEP_SET_RES_OFF_REG_SPARE_SETOFF_OFF (0x1u) - -#define PMIC_SLEEP_SET_RES_OFF_REG_RSVD - -#define PMIC_SLEEP_SET_RES_OFF_REG_DEFAULT_VOLT (0x80u) -#define PMIC_SLEEP_SET_RES_OFF_REG_DEFAULT_VOLT_SHIFT (0x07u) -#define PMIC_SLEEP_SET_RES_OFF_REG_DEFAULT_VOLT_PRG (0x0u) -#define PMIC_SLEEP_SET_RES_OFF_REG_DEFAULT_VOLT_DEF (0x1u) - -/* EN1_LDO_ASS_REG */ -#define PMIC_EN1_LDO_ASS_REG_VMMC_EN1 (0x01u) -#define PMIC_EN1_LDO_ASS_REG_VMMC_EN1_SHIFT (0x00u) - -#define PMIC_EN1_LDO_ASS_REG_VDIG1_EN1 (0x02u) -#define PMIC_EN1_LDO_ASS_REG_VDIG1_EN1_SHIFT (0x01u) - -#define PMIC_EN1_LDO_ASS_REG_VDIG2_EN1 (0x04u) -#define PMIC_EN1_LDO_ASS_REG_VDIG2_EN1_SHIFT (0x02u) - -#define PMIC_EN1_LDO_ASS_REG_VAUX1_EN1 (0x08u) -#define PMIC_EN1_LDO_ASS_REG_VAUX1_EN1_SHIFT (0x03u) - -#define PMIC_EN1_LDO_ASS_REG_VAUX2_EN1 (0x10u) -#define PMIC_EN1_LDO_ASS_REG_VAUX2_EN1_SHIFT (0x04u) - -#define PMIC_EN1_LDO_ASS_REG_VAUX33_EN1 (0x20u) -#define PMIC_EN1_LDO_ASS_REG_VAUX33_EN1_SHIFT (0x05u) - -#define PMIC_EN1_LDO_ASS_REG_VPLL_EN1 (0x40u) -#define PMIC_EN1_LDO_ASS_REG_VPLL_EN1_SHIFT (0x06u) - -#define PMIC_EN1_LDO_ASS_REG_VDAC_EN1 (0x80u) -#define PMIC_EN1_LDO_ASS_REG_VDAC_EN1_SHIFT (0x07u) - -/* EN1_SMPS_ASS_REG */ -#define PMIC_EN1_SMPS_ASS_REG_VIO_EN1 (0x01u) -#define PMIC_EN1_SMPS_ASS_REG_VIO_EN1_SHIFT (0x00u) -#define PMIC_EN1_SMPS_ASS_REG_VIO_EN1_SCLSR_EN1 (0x0u) -#define PMIC_EN1_SMPS_ASS_REG_VIO_EN1_NO_EFFECT (0x1u) - -#define PMIC_EN1_SMPS_ASS_REG_VDD1_EN1 (0x02u) -#define PMIC_EN1_SMPS_ASS_REG_VDD1_EN1_SHIFT (0x01u) -#define PMIC_EN1_SMPS_ASS_REG_VIO_EN1_SCLSR_EN1 (0x0u) -#define PMIC_EN1_SMPS_ASS_REG_VIO_EN1_NO_EFFECT (0x1u) - -#define PMIC_EN1_SMPS_ASS_REG_VDD2_EN1 (0x04u) -#define PMIC_EN1_SMPS_ASS_REG_VDD2_EN1_SHIFT (0x02u) -#define PMIC_EN1_SMPS_ASS_REG_VIO_EN1_SCLSR_EN1 (0x0u) -#define PMIC_EN1_SMPS_ASS_REG_VIO_EN1_NO_EFFECT (0x1u) - -#define PMIC_EN1_SMPS_ASS_REG_VDD3_EN1 (0x08u) -#define PMIC_EN1_SMPS_ASS_REG_VDD3_EN1_SHIFT (0x03u) -#define PMIC_EN1_SMPS_ASS_REG_VIO_EN1_SCLSR_EN1 (0x0u) -#define PMIC_EN1_SMPS_ASS_REG_VIO_EN1_NO_EFFECT (0x1u) - -#define PMIC_EN1_SMPS_ASS_REG_SPARE_EN1 (0x10u) -#define PMIC_EN1_SMPS_ASS_REG_SPARE_EN1_SHIFT (0x04u) - -/* EN2_LDO_ASS_REG */ -#define PMIC_EN2_LDO_ASS_REG_VMMC_EN2 (0x01u) -#define PMIC_EN2_LDO_ASS_REG_VMMC_EN2_SHIFT (0x00u) - -#define PMIC_EN2_LDO_ASS_REG_VDIG1_EN2 (0x02u) -#define PMIC_EN2_LDO_ASS_REG_VDIG1_EN2_SHIFT (0x01u) - -#define PMIC_EN2_LDO_ASS_REG_VDIG2_EN2 (0x04u) -#define PMIC_EN2_LDO_ASS_REG_VDIG2_EN2_SHIFT (0x02u) - -#define PMIC_EN2_LDO_ASS_REG_VAUX1_EN2 (0x08u) -#define PMIC_EN2_LDO_ASS_REG_VAUX1_EN2_SHIFT (0x03u) - -#define PMIC_EN2_LDO_ASS_REG_VAUX2_EN2 (0x10u) -#define PMIC_EN2_LDO_ASS_REG_VAUX2_EN2_SHIFT (0x04u) - -#define PMIC_EN2_LDO_ASS_REG_VAUX33_EN2 (0x20u) -#define PMIC_EN2_LDO_ASS_REG_VAUX33_EN2_SHIFT (0x05u) - -#define PMIC_EN2_LDO_ASS_REG_VPLL_EN2 (0x40u) -#define PMIC_EN2_LDO_ASS_REG_VPLL_EN2_SHIFT (0x06u) - -#define PMIC_EN2_LDO_ASS_REG_VDAC_EN2 (0x80u) -#define PMIC_EN2_LDO_ASS_REG_VDAC_EN2_SHIFT (0x07u) - -/* EN2_SMPS_ASS_REG */ -#define PMIC_EN2_SMPS_ASS_REG_VIO_EN2 (0x01u) -#define PMIC_EN2_SMPS_ASS_REG_VIO_EN2_SHIFT (0x00u) -#define PMIC_EN2_SMPS_ASS_REG_VIO_EN2_REG (0x0u) -#define PMIC_EN2_SMPS_ASS_REG_VIO_EN2_SCLSR_EN2 (0x1u) - -#define PMIC_EN2_SMPS_ASS_REG_VDD1_EN2 (0x02u) -#define PMIC_EN2_SMPS_ASS_REG_VDD1_EN2_SHIFT (0x01u) -#define PMIC_EN2_SMPS_ASS_REG_VDD1_EN2_REG (0x0u) -#define PMIC_EN2_SMPS_ASS_REG_VDD1_EN2_SR_OP (0x1u) - -#define PMIC_EN2_SMPS_ASS_REG_VDD2_EN2 (0x04u) -#define PMIC_EN2_SMPS_ASS_REG_VDD2_EN2_SHIFT (0x02u) -#define PMIC_EN2_SMPS_ASS_REG_VDD2_EN2_REG (0x0u) -#define PMIC_EN2_SMPS_ASS_REG_VDD2_EN2_SR_OP (0x1u) - -#define PMIC_EN2_SMPS_ASS_REG_VDD3_EN2 (0x08u) -#define PMIC_EN2_SMPS_ASS_REG_VDD3_EN2_SHIFT (0x03u) -#define PMIC_EN2_SMPS_ASS_REG_VDD3_EN2_REG (0x0u) -#define PMIC_EN2_SMPS_ASS_REG_VDD3_EN2_SDASR_EN2 (0x1u) - -/* EN3_LDO_ASS_REG */ -#define PMIC_EN3_LDO_ASS_REG_VMMC_EN3 (0x01u) -#define PMIC_EN3_LDO_ASS_REG_VMMC_EN3_SHIFT (0x00u) - -#define PMIC_EN3_LDO_ASS_REG_VDIG1_EN3 (0x02u) -#define PMIC_EN3_LDO_ASS_REG_VDIG1_EN3_SHIFT (0x01u) - -#define PMIC_EN3_LDO_ASS_REG_VDIG2_EN3 (0x04u) -#define PMIC_EN3_LDO_ASS_REG_VDIG2_EN3_SHIFT (0x02u) - -#define PMIC_EN3_LDO_ASS_REG_VAUX1_EN3 (0x08u) -#define PMIC_EN3_LDO_ASS_REG_VAUX1_EN3_SHIFT (0x03u) - -#define PMIC_EN3_LDO_ASS_REG_VAUX2_EN3 (0x10u) -#define PMIC_EN3_LDO_ASS_REG_VAUX2_EN3_SHIFT (0x04u) - -#define PMIC_EN3_LDO_ASS_REG_VAUX33_EN3 (0x20u) -#define PMIC_EN3_LDO_ASS_REG_VAUX33_EN3_SHIFT (0x05u) - -#define PMIC_EN3_LDO_ASS_REG_VPLL_EN3 (0x40u) -#define PMIC_EN3_LDO_ASS_REG_VPLL_EN3_SHIFT (0x06u) - -#define PMIC_EN3_LDO_ASS_REG_VDAC_EN3 (0x80u) -#define PMIC_EN3_LDO_ASS_REG_VDAC_EN3_SHIFT (0x07u) - -/* SPARE_REG */ -#define PMIC_SPARE_REG (0xFFu) -#define PMIC_SPARE_REG_SHIFT (0x00u) - -/* INT_STS_REG */ -#define PMIC_INT_STS_REG_VMBDCH_IT (0x01u) -#define PMIC_INT_STS_REG_VMBDCH_IT_SHIFT (0x00u) - -#define PMIC_INT_STS_REG_VMBHI_IT (0x02u) -#define PMIC_INT_STS_REG_VMBHI_IT_SHIFT (0x01u) - -#define PMIC_INT_STS_REG_PWRON_IT (0x04u) -#define PMIC_INT_STS_REG_PWRON_IT_SHIFT (0x02u) - -#define PMIC_INT_STS_REG_PWRON_LP_IT (0x08u) -#define PMIC_INT_STS_REG_PWRON_LP_IT_SHIFT (0x03u) - -#define PMIC_INT_STS_REG_PWRHOLD_IT (0x10u) -#define PMIC_INT_STS_REG_PWRHOLD_IT_SHIFT (0x04u) - -#define PMIC_INT_STS_REG_HOTDIE_IT (0x20u) -#define PMIC_INT_STS_REG_HOTDIE_IT_SHIFT (0x05u) - -#define PMIC_INT_STS_REG_RTC_ALARM_IT (0x40u) -#define PMIC_INT_STS_REG_RTC_ALARM_IT_SHIFT (0x06u) - -#define PMIC_INT_STS_REG_RTC_PERIOD_IT (0x80u) -#define PMIC_INT_STS_REG_RTC_PERIOD_IT_SHIFT (0x07u) - -/* INT_MSK_REG */ -#define PMIC_INT_MSK_REG_VMBDCH_IT_MSK (0x01u) -#define PMIC_INT_MSK_REG_VMBDCH_IT_MSK_SHIFT (0x00u) - -#define PMIC_INT_MSK_REG_VMBHI_IT_MSK (0x02u) -#define PMIC_INT_MSK_REG_VMBHI_IT_MSK_SHIFT (0x01u) - -#define PMIC_INT_MSK_REG_PWRON_IT_MSK (0x04u) -#define PMIC_INT_MSK_REG_PWRON_IT_MSK_SHIFT (0x02u) - -#define PMIC_INT_MSK_REG_PWRON_LP_IT_MSK (0x08u) -#define PMIC_INT_MSK_REG_PWRON_LP_IT_MSK_SHIFT (0x03u) - -#define PMIC_INT_MSK_REG_PWRHOLD_IT_MSK (0x10u) -#define PMIC_INT_MSK_REG_PWRHOLD_IT_MSK_SHIFT (0x04u) - -#define PMIC_INT_MSK_REG_HOTDIE_IT_MSK (0x20u) -#define PMIC_INT_MSK_REG_HOTDIE_IT_MSK_SHIFT (0x05u) - -#define PMIC_INT_MSK_REG_RTC_ALARM_IT_MSK (0x40u) -#define PMIC_INT_MSK_REG_RTC_ALARM_IT_MSK_SHIFT (0x06u) - -#define PMIC_INT_MSK_REG_RTC_PERIOD_IT_MSK (0x80u) -#define PMIC_INT_MSK_REG_RTC_PERIOD_IT_MSK_SHIFT (0x07u) - -/* INT_STS2_REG */ -#define PMIC_INT_STS2_REG_GPIO0_R_IT (0x01u) -#define PMIC_INT_STS2_REG_GPIO0_R_IT_SHIFT (0x00u) - -#define PMIC_INT_STS2_REG_GPIO0_F_IT (0x02u) -#define PMIC_INT_STS2_REG_GPIO0_F_IT_SHIFT (0x01u) - -/* INT_MSK2_REG */ -#define PMIC_INT_MSK2_REG_GPIO0_R_IT_MSK (0x01u) -#define PMIC_INT_MSK2_REG_GPIO0_R_IT_MSK_SHIFT (0x00u) - -#define PMIC_INT_MSK2_REG_GPIO0_F_IT_MSK (0x02u) -#define PMIC_INT_MSK2_REG_GPIO0_F_IT_MSK_SHIFT (0x01u) - -/* GPIO0_REG */ -#define PMIC_GPIO0_REG_GPIO_SET (0x01u) -#define PMIC_GPIO0_REG_GPIO_SET_SHIFT (0x00u) - -#define PMIC_GPIO0_REG_GPIO_STS (0x02u) -#define PMIC_GPIO0_REG_GPIO_STS_SHIFT (0x01u) - -#define PMIC_GPIO0_REG_GPIO_CFG (0x04u) -#define PMIC_GPIO0_REG_GPIO_CFG_SHIFT (0x02u) -#define PMIC_GPIO0_REG_GPIO_CFG_INPUT (0x0u) -#define PMIC_GPIO0_REG_GPIO_CFG_OUTPUT (0x1u) - -#define PMIC_GPIO0_REG_GPIO_PUEN (0x08u) -#define PMIC_GPIO0_REG_GPIO_PUEN_SHIFT (0x03u) -#define PMIC_GPIO0_REG_GPIO_PUEN_PULL_UP_DIS (0x0u) -#define PMIC_GPIO0_REG_GPIO_PUEN_PULL_UP_EN (0x1u) - -#define PMIC_GPIO0_REG_GPIO_DEB (0x10u) -#define PMIC_GPIO0_REG_GPIO_DEB_SHIFT (0x04u) -#define PMIC_GPIO0_REG_GPIO_DEB_91_5_US (0x0u) -#define PMIC_GPIO0_REG_GPIO_DEB_150_MS (0x1u) - -/* JTAGVERNUM_REG */ -#define PMIC_JTAGVERNUM_REG_VERNUM (0x0Fu) -#define PMIC_JTAGVERNUM_REG_VERNUM_SHIFT (0x00u) - -#endif - - diff --git a/lib/tiam1808/tiam1808/hw/hw_uart_irda_cir.h b/lib/tiam1808/tiam1808/hw/hw_uart_irda_cir.h deleted file mode 100644 index 091df4d10..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_uart_irda_cir.h +++ /dev/null @@ -1,1006 +0,0 @@ - - -/** - * @Component: UART - * - * @Filename: hw_uart_irda_cir.h - * - ============================================================================ */ -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - - -#ifndef _HW_UART_H_ -#define _HW_UART_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***********************************************************************\ - * Register arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundle arrays Definition -\***********************************************************************/ - - -/***********************************************************************\ - * Bundles Definition -\***********************************************************************/ - - - -/*************************************************************************\ - * Registers Definition -\*************************************************************************/ - -#define UART_DLL (0x0) -#define UART_RHR (0x0) -#define UART_THR (0x0) -#define UART_DLH (0x4) -#define UART_IER (0x4) -#define UART_EFR (0x8) -#define UART_FCR (0x8) -#define UART_IIR (0x8) -#define UART_LCR (0xC) -#define UART_MCR (0x10) -#define UART_XON1_ADDR1 (0x10) -#define UART_LSR (0x14) -#define UART_XON2_ADDR2 (0x14) -#define UART_MSR (0x18) -#define UART_TCR (0x18) -#define UART_XOFF1 (0x18) -#define UART_SPR (0x1C) -#define UART_TLR (0x1C) -#define UART_XOFF2 (0x1C) -#define UART_MDR1 (0x20) -#define UART_MDR2 (0x24) -#define UART_SFLSR (0x28) -#define UART_TXFLL (0x28) -#define UART_RESUME (0x2C) -#define UART_TXFLH (0x2C) -#define UART_RXFLL (0x30) -#define UART_SFREGL (0x30) -#define UART_RXFLH (0x34) -#define UART_SFREGH (0x34) -#define UART_BLR (0x38) -#define UART_UASR (0x38) -#define UART_ACREG (0x3C) -#define UART_SCR (0x40) -#define UART_SSR (0x44) -#define UART_EBLR (0x48) -#define UART_MVR (0x50) -#define UART_SYSC (0x54) -#define UART_SYSS (0x58) -#define UART_WER (0x5C) -#define UART_CFPS (0x60) - -/**************************************************************************\ - * Field Definition Macros -\**************************************************************************/ - -/* DLL */ -#define UART_DLL_CLOCK_LSB (0x000000FFu) -#define UART_DLL_CLOCK_LSB_SHIFT (0x00000000u) - - -/* RHR */ -#define UART_RHR_RHR (0x000000FFu) -#define UART_RHR_RHR_SHIFT (0x00000000u) - - -/* THR */ -#define UART_THR_THR (0x000000FFu) -#define UART_THR_THR_SHIFT (0x00000000u) - - -/* DLH */ -#define UART_DLH_CLOCK_MSB (0x0000003Fu) -#define UART_DLH_CLOCK_MSB_SHIFT (0x00000000u) - -/* IER */ - -/* IER - UART Register */ -#define UART_IER_CTS_IT (0x00000080u) -#define UART_IER_CTS_IT_SHIFT (0x00000007u) -#define UART_IER_CTS_IT_DISABLE (0x0u) -#define UART_IER_CTS_IT_ENABLE (0x1u) - -#define UART_IER_RTS_IT (0x00000040u) -#define UART_IER_RTS_IT_SHIFT (0x00000006u) -#define UART_IER_RTS_IT_DISABLE (0x0u) -#define UART_IER_RTS_IT_ENABLE (0x1u) - -#define UART_IER_XOFF_IT (0x00000020u) -#define UART_IER_XOFF_IT_SHIFT (0x00000005u) -#define UART_IER_XOFF_IT_DISABLE (0x0u) -#define UART_IER_XOFF_IT_ENABLE (0x1u) - -#define UART_IER_SLEEP_MODE_IT (0x00000010u) -#define UART_IER_SLEEP_MODE_IT_SHIFT (0x00000004u) -#define UART_IER_SLEEP_MODE_IT_DISABLE (0x0u) -#define UART_IER_SLEEP_MODE_IT_ENABLE (0x1u) - -#define UART_IER_MODEM_STS_IT (0x00000008u) -#define UART_IER_MODEM_STS_IT_SHIFT (0x00000003u) -#define UART_IER_MODEM_STS_IT_DISABLE (0x0u) -#define UART_IER_MODEM_STS_IT_ENABLE (0x1u) - -#define UART_IER_LINE_STS_IT (0x00000004u) -#define UART_IER_LINE_STS_IT_SHIFT (0x00000002u) -#define UART_IER_LINE_STS_IT_DISABLE (0x0u) -#define UART_IER_LINE_STS_IT_ENABLE (0x1u) - -#define UART_IER_THR_IT (0x00000002u) -#define UART_IER_THR_IT_SHIFT (0x00000001u) -#define UART_IER_THR_IT_DISABLE (0x0u) -#define UART_IER_THR_IT_ENABLE (0x1u) - -#define UART_IER_RHR_IT (0x00000001u) -#define UART_IER_RHR_IT_SHIFT (0x00000000u) -#define UART_IER_RHR_IT_DISABLE (0x0u) -#define UART_IER_RHR_IT_ENABLE (0x1u) - -/* IER - IrDA Register */ -#define UART_IER_IRDA_EOF_IT (0x00000080u) -#define UART_IER_IRDA_EOF_IT_SHIFT (0x00000007u) -#define UART_IER_IRDA_EOF_IT_DISABLE (0x0u) -#define UART_IER_IRDA_EOF_IT_ENABLE (0x1u) - -#define UART_IER_IRDA_LINE_STS_IT (0x00000040u) -#define UART_IER_IRDA_LINE_STS_IT_SHIFT (0x00000006u) -#define UART_IER_IRDA_LINE_STS_IT_DISABLE (0x0u) -#define UART_IER_IRDA_LINE_STS_IT_ENABLE (0x1u) - -#define UART_IER_IRDA_TX_STATUS_IT (0x00000020u) -#define UART_IER_IRDA_TX_STATUS_IT_SHIFT (0x00000005u) -#define UART_IER_IRDA_TX_STATUS_IT_DISABLE (0x0u) -#define UART_IER_IRDA_TX_STATUS_IT_ENABLE (0x1u) - -#define UART_IER_IRDA_STS_FIFO_TRIG_IT (0x00000010u) -#define UART_IER_IRDA_STS_FIFO_TRIG_IT_SHIFT (0x00000004u) -#define UART_IER_IRDA_STS_FIFO_TRIG_IT_DISABLE (0x0u) -#define UART_IER_IRDA_STS_FIFO_TRIG_IT_ENABLE (0x0u) - -#define UART_IER_IRDA_RX_OVERRUN_IT (0x00000008u) -#define UART_IER_IRDA_RX_OVERRUN_IT_SHIFT (0x00000003u) -#define UART_IER_IRDA_RX_OVERRUN_IT_DISABLE (0x0u) -#define UART_IER_IRDA_RX_OVERRUN_IT_ENABLE (0x1u) - -#define UART_IER_IRDA_LAST_RX_BYTE_IT (0x00000004u) -#define UART_IER_IRDA_LAST_RX_BYTE_IT_SHIFT (0x00000002u) -#define UART_IER_IRDA_LAST_RX_BYTE_IT_DISABLE (0x0u) -#define UART_IER_IRDA_LAST_RX_BYTE_IT_ENABLE (0x1u) - -#define UART_IER_IRDA_THR_IT (0x00000002u) -#define UART_IER_IRDA_THR_IT_SHIFT (0x00000001u) -#define UART_IER_IRDA_THR_IT_DISABLE (0x0u) -#define UART_IER_IRDA_THR_IT_ENABLE (0x1u) - -#define UART_IER_IRDA_RHR_IT (0x00000001u) -#define UART_IER_IRDA_RHR_IT_SHIFT (0x00000000u) -#define UART_IER_IRDA_RHR_IT_DISABLE (0x0u) -#define UART_IER_IRDA_RHR_IT_ENABLE (0x1u) - -/* IER - CIR Register */ -#define UART_IER_CIR_TX_STATUS_IT (0x00000020u) -#define UART_IER_CIR_TX_STATUS_IT_SHIFT (0x00000005u) -#define UART_IER_CIR_TX_STATUS_IT_DISABLE (0x0u) -#define UART_IER_CIR_TX_STATUS_IT_ENABLE (0x1u) - -#define UART_IER_CIR_RX_OVERRUN_IT (0x00000008u) -#define UART_IER_CIR_RX_OVERRUN_IT_SHIFT (0x00000003u) -#define UART_IER_CIR_RX_OVERRUN_IT_DISABLE (0x0u) -#define UART_IER_CIR_RX_OVERRUN_IT_ENABLE (0x1u) - -#define UART_IER_CIR_RX_STOP_IT (0x00000004u) -#define UART_IER_CIR_RX_STOP_IT_SHIFT (0x00000002u) -#define UART_IER_CIR_RX_STOP_IT_DISABLE (0x0u) -#define UART_IER_CIR_RX_STOP_IT_ENABLE (0x1u) - -#define UART_IER_CIR_THR_IT (0x00000002u) -#define UART_IER_CIR_THR_IT_SHIFT (0x00000001u) -#define UART_IER_CIR_THR_IT_DISABLE (0x0u) -#define UART_IER_CIR_THR_IT_ENABLE (0x1u) - -#define UART_IER_CIR_RHR_IT (0x00000001u) -#define UART_IER_CIR_RHR_IT_SHIFT (0x00000000u) -#define UART_IER_CIR_RHR_IT_DISABLE (0x0u) -#define UART_IER_CIR_RHR_IT_ENABLE (0x1u) - -/* EFR */ -#define UART_EFR_AUTO_CTS_EN (0x00000080u) -#define UART_EFR_AUTO_CTS_EN_SHIFT (0x00000007u) -#define UART_EFR_AUTO_CTS_EN_ENABLE (0x1u) -#define UART_EFR_AUTO_CTS_EN_NORMAL (0x0u) - -#define UART_EFR_AUTO_RTS_EN (0x00000040u) -#define UART_EFR_AUTO_RTS_EN_SHIFT (0x00000006u) -#define UART_EFR_AUTO_RTS_EN_ENABLE (0x1u) -#define UART_EFR_AUTO_RTS_EN_NORMAL (0x0u) - -#define UART_EFR_ENHANCED_EN (0x00000010u) -#define UART_EFR_ENHANCED_EN_SHIFT (0x00000004u) -#define UART_EFR_ENHANCED_EN_DISABLE (0x0u) -#define UART_EFR_ENHANCED_EN_ENABLE (0x1u) - -#define UART_EFR_SPECIAL_CHAR_DETECT (0x00000020u) -#define UART_EFR_SPECIAL_CHAR_DETECT_SHIFT (0x00000005u) -#define UART_EFR_SPECIAL_CHAR_DETECT_ENABLE (0x1u) -#define UART_EFR_SPECIAL_CHAR_DETECT_NORMAL (0x0u) - -#define UART_EFR_SW_FLOW_CONTROL (0x0000000Fu) -#define UART_EFR_SW_FLOW_CONTROL_SHIFT (0x00000000u) - -#define UART_EFR_SW_FLOW_CONTROL_RX (0x00000003u) -#define UART_EFR_SW_FLOW_CONTROL_RX_SHIFT (0x00000000u) -#define UART_EFR_SW_FLOW_CONTROL_RX_NONE (0x0u) -#define UART_EFR_SW_FLOW_CONTROL_RX_XONOFF1 (0x2u) -#define UART_EFR_SW_FLOW_CONTROL_RX_XONOFF1AND2 (0x3u) -#define UART_EFR_SW_FLOW_CONTROL_RX_XONOFF2 (0x1u) - -#define UART_EFR_SW_FLOW_CONTROL_TX (0x0000000Cu) -#define UART_EFR_SW_FLOW_CONTROL_TX_SHIFT (0x00000002u) -#define UART_EFR_SW_FLOW_CONTROL_TX_NONE (0x0u) -#define UART_EFR_SW_FLOW_CONTROL_TX_XONOFF1 (0x2u) -#define UART_EFR_SW_FLOW_CONTROL_TX_XONOFF1AND2 (0x3u) -#define UART_EFR_SW_FLOW_CONTROL_TX_XONOFF2 (0x1u) - - -/* FCR */ -#define UART_FCR_DMA_MODE (0x00000008u) -#define UART_FCR_DMA_MODE_SHIFT (0x00000003u) -#define UART_FCR_DMA_MODE_MODE0 (0x0u) -#define UART_FCR_DMA_MODE_MODE1 (0x1u) - -#define UART_FCR_FIFO_EN (0x00000001u) -#define UART_FCR_FIFO_EN_SHIFT (0x00000000u) -#define UART_FCR_FIFO_EN_DISABLE (0x0u) -#define UART_FCR_FIFO_EN_ENABLE (0x1u) - -#define UART_FCR_RX_FIFO_CLEAR (0x00000002u) -#define UART_FCR_RX_FIFO_CLEAR_SHIFT (0x00000001u) -#define UART_FCR_RX_FIFO_CLEAR_CLEAR (0x1u) - -#define UART_FCR_RX_FIFO_TRIG (0x000000C0u) -#define UART_FCR_RX_FIFO_TRIG_SHIFT (0x00000006u) -#define UART_FCR_RX_FIFO_TRIG_16CHAR (0x1u) -#define UART_FCR_RX_FIFO_TRIG_56CHAR (0x2u) -#define UART_FCR_RX_FIFO_TRIG_60CHAR (0x3u) -#define UART_FCR_RX_FIFO_TRIG_8CHAR (0x0u) - -#define UART_FCR_TX_FIFO_CLEAR (0x00000004u) -#define UART_FCR_TX_FIFO_CLEAR_SHIFT (0x00000002u) -#define UART_FCR_TX_FIFO_CLEAR_CLEAR (0x1u) - -#define UART_FCR_TX_FIFO_TRIG (0x00000030u) -#define UART_FCR_TX_FIFO_TRIG_SHIFT (0x00000004u) -#define UART_FCR_TX_FIFO_TRIG_8SPACES (0x0u) -#define UART_FCR_TX_FIFO_TRIG_16SPACES (0x1u) -#define UART_FCR_TX_FIFO_TRIG_32SPACES (0x2u) -#define UART_FCR_TX_FIFO_TRIG_56SPACES (0x3u) - -/* IIR */ - -/* IIR - UART Register. */ -#define UART_IIR_FCR_MIRROR (0x000000C0u) -#define UART_IIR_FCR_MIRROR_SHIFT (0x00000006u) - -#define UART_IIR_IT_TYPE (0x0000003Eu) -#define UART_IIR_IT_TYPE_SHIFT (0x00000001u) -#define UART_IIR_IT_TYPE_MODEMINT (0x0u) -#define UART_IIR_IT_TYPE_RHRINT (0x2u) -#define UART_IIR_IT_TYPE_RXSTATUSERROR (0x3u) -#define UART_IIR_IT_TYPE_RXTIMEOUT (0x6u) -#define UART_IIR_IT_TYPE_STATECHANGE (0x10u) -#define UART_IIR_IT_TYPE_THRINT (0x1u) -#define UART_IIR_IT_TYPE_XOFF (0x8u) - -#define UART_IIR_IT_PENDING (0x00000001u) -#define UART_IIR_IT_PENDING_SHIFT (0x00000000u) -#define UART_IIR_IT_PENDING_NO (0x1u) -#define UART_IIR_IT_PENDING_YES (0x0u) - -/* IIR - IrDA Register. */ -#define UART_IIR_IRDA_EOF_IT (0x00000080u) -#define UART_IIR_IRDA_EOF_IT_SHIFT (0x00000007u) -#define UART_IIR_IRDA_EOF_IT_ACTIVE (0x1u) -#define UART_IIR_IRDA_EOF_IT_INACTIVE (0x0u) - -#define UART_IIR_IRDA_LINE_STS_IT (0x00000040u) -#define UART_IIR_IRDA_LINE_STS_IT_SHIFT (0x00000006u) -#define UART_IIR_IRDA_LINE_STS_IT_ACTIVE (0x1u) -#define UART_IIR_IRDA_LINE_STS_IT_INACTIVE (0x0u) - -#define UART_IIR_IRDA_TX_STATUS_IT (0x00000020u) -#define UART_IIR_IRDA_TX_STATUS_IT_SHIFT (0x00000005u) -#define UART_IIR_IRDA_TX_STATUS_IT_ACTIVE (0x1u) -#define UART_IIR_IRDA_TX_STATUS_IT_INACTIVE (0x0u) - -#define UART_IIR_IRDA_STS_FIFO_IT (0x00000010u) -#define UART_IIR_IRDA_STS_FIFO_IT_SHIFT (0x00000004u) -#define UART_IIR_IRDA_STS_FIFO_IT_ACTIVE (0x1u) -#define UART_IIR_IRDA_STS_FIFO_IT_INACTIVE (0x0u) - -#define UART_IIR_IRDA_RX_OE_IT (0x00000008u) -#define UART_IIR_IRDA_RX_OE_IT_SHIFT (0x00000003u) -#define UART_IIR_IRDA_RX_OE_IT_ACTIVE (0x1u) -#define UART_IIR_IRDA_RX_OE_IT_INACTIVE (0x0u) - -#define UART_IIR_IRDA_RX_FIFO_LAST_BYTE_IT (0x00000004u) -#define UART_IIR_IRDA_RX_FIFO_LAST_BYTE_IT_SHIFT (0x00000002u) -#define UART_IIR_IRDA_RX_FIFO_LAST_BYTE_IT_ACTIVE (0x1u) -#define UART_IIR_IRDA_RX_FIFO_LAST_BYTE_IT_INACTIVE (0x0u) - -#define UART_IIR_IRDA_THR_IT (0x00000002u) -#define UART_IIR_IRDA_THR_IT_SHIFT (0x00000001u) -#define UART_IIR_IRDA_THR_IT_ACTIVE (0x1u) -#define UART_IIR_IRDA_THR_IT_INACTIVE (0x0u) - -#define UART_IIR_IRDA_RHR_IT (0x00000001u) -#define UART_IIR_IRDA_RHR_IT_SHIFT (0x00000000u) -#define UART_IIR_IRDA_RHR_IT_ACTIVE (0x1u) -#define UART_IIR_IRDA_RHR_IT_INACTIVE (0x0u) - -/* IIR - CIR Register. */ -#define UART_IIR_CIR_TX_STATUS_IT (0x00000020u) -#define UART_IIR_CIR_TX_STATUS_IT_SHIFT (0x00000005u) -#define UART_IIR_CIR_TX_STATUS_IT_ACTIVE (0x1u) -#define UART_IIR_CIR_TX_STATUS_IT_INACTIVE (0x0u) - -#define UART_IIR_CIR_RX_OE_IT (0x00000008u) -#define UART_IIR_CIR_RX_OE_IT_SHIFT (0x00000003u) -#define UART_IIR_CIR_RX_OE_IT_ACTIVE (0x1u) -#define UART_IIR_CIR_RX_OE_IT_INACTIVE (0x0u) - -#define UART_IIR_CIR_RX_STOP_IT (0x00000004u) -#define UART_IIR_CIR_RX_STOP_IT_SHIFT (0x00000002u) -#define UART_IIR_CIR_RX_STOP_IT_ACTIVE (0x1u) -#define UART_IIR_CIR_RX_STOP_IT_INACTIVE (0x0u) - -#define UART_IIR_CIR_THR_IT (0x00000002u) -#define UART_IIR_CIR_THR_IT_SHIFT (0x00000001u) -#define UART_IIR_CIR_THR_IT_ACTIVE (0x1u) -#define UART_IIR_CIR_THR_IT_INACTIVE (0x0u) - -#define UART_IIR_CIR_RHR_IT (0x00000001u) -#define UART_IIR_CIR_RHR_IT_SHIFT (0x00000000u) -#define UART_IIR_CIR_RHR_IT_ACTIVE (0x1u) -#define UART_IIR_CIR_RHR_IT_INACTIVE (0x0u) - -/* LCR */ -#define UART_LCR_BREAK_EN (0x00000040u) -#define UART_LCR_BREAK_EN_SHIFT (0x00000006u) -#define UART_LCR_BREAK_EN_FORCE (0x1u) -#define UART_LCR_BREAK_EN_NORMAL (0x0u) - -#define UART_LCR_CHAR_LENGTH (0x00000003u) -#define UART_LCR_CHAR_LENGTH_SHIFT (0x00000000u) -#define UART_LCR_CHAR_LENGTH_5BIT (0x0u) -#define UART_LCR_CHAR_LENGTH_6BIT (0x1u) -#define UART_LCR_CHAR_LENGTH_7BIT (0x2u) -#define UART_LCR_CHAR_LENGTH_8BIT (0x3u) - -#define UART_LCR_DIV_EN (0x00000080u) -#define UART_LCR_DIV_EN_SHIFT (0x00000007u) -#define UART_LCR_DIV_EN_DIVISOR (0x1u) -#define UART_LCR_DIV_EN_NORMAL (0x0u) - -#define UART_LCR_NB_STOP (0x00000004u) -#define UART_LCR_NB_STOP_SHIFT (0x00000002u) -#define UART_LCR_NB_STOP_1BIT (0x0u) -#define UART_LCR_NB_STOP_1P5BIT (0x1u) -#define UART_LCR_NB_STOP_2BIT (0x1u) - -#define UART_LCR_PARITY_EN (0x00000008u) -#define UART_LCR_PARITY_EN_SHIFT (0x00000003u) -#define UART_LCR_PARITY_EN_DISABLE (0x0u) -#define UART_LCR_PARITY_EN_ENABLE (0x1u) - -#define UART_LCR_PARITY_TYPE1 (0x00000010u) -#define UART_LCR_PARITY_TYPE1_SHIFT (0x00000004u) -#define UART_LCR_PARITY_TYPE1_EVEN (0x1u) -#define UART_LCR_PARITY_TYPE1_ODD (0x0u) - -#define UART_LCR_PARITY_TYPE2 (0x00000020u) -#define UART_LCR_PARITY_TYPE2_SHIFT (0x00000005u) -#define UART_LCR_PARITY_TYPE2_FORCE (0x1u) -#define UART_LCR_PARITY_TYPE2_NORMAL (0x0u) - - -/* MCR */ -#define UART_MCR_CD_STS_CH (0x00000008u) -#define UART_MCR_CD_STS_CH_SHIFT (0x00000003u) -#define UART_MCR_CD_STS_CH_FORCEHIGH (0x0u) -#define UART_MCR_CD_STS_CH_FORCELOW (0x1u) - -#define UART_MCR_DTR (0x00000001u) -#define UART_MCR_DTR_SHIFT (0x00000000u) -#define UART_MCR_DTR_FORCEHIGH (0x0u) -#define UART_MCR_DTR_FORCELOW (0x1u) - -#define UART_MCR_LOOPBACK_EN (0x00000010u) -#define UART_MCR_LOOPBACK_EN_SHIFT (0x00000004u) -#define UART_MCR_LOOPBACK_EN_LOOPBACK (0x1u) -#define UART_MCR_LOOPBACK_EN_NORMAL (0x0u) - -#define UART_MCR_RI_STS_CH (0x00000004u) -#define UART_MCR_RI_STS_CH_SHIFT (0x00000002u) -#define UART_MCR_RI_STS_CH_FORCEHIGH (0x0u) -#define UART_MCR_RI_STS_CH_FORCELOW (0x1u) - -#define UART_MCR_RTS (0x00000002u) -#define UART_MCR_RTS_SHIFT (0x00000001u) -#define UART_MCR_RTS_FORCEHIGH (0x0u) -#define UART_MCR_RTS_FORCELOW (0x1u) - -#define UART_MCR_TCR_TLR (0x00000040u) -#define UART_MCR_TCR_TLR_SHIFT (0x00000006u) -#define UART_MCR_TCR_TLR_ENABLE (0x1u) - -#define UART_MCR_XON_EN (0x00000020u) -#define UART_MCR_XON_EN_SHIFT (0x00000005u) -#define UART_MCR_XON_EN_DISABLE (0x0u) -#define UART_MCR_XON_EN_ENABLE (0x1u) - - -/* XON1_ADDR1 */ -#define UART_XON1_ADDR1_XON1_WORD1 (0x000000FFu) -#define UART_XON1_ADDR1_XON1_WORD1_SHIFT (0x00000000u) - -/* LSR */ - -/* LSR - UART Register */ -#define UART_LSR_RX_FIFO_STS (0x00000080u) -#define UART_LSR_RX_FIFO_STS_SHIFT (0x00000007u) -#define UART_LSR_RX_FIFO_STS_ERROR (0x1u) -#define UART_LSR_RX_FIFO_STS_NORMAL (0x0u) - -#define UART_LSR_TX_SR_E (0x00000040u) -#define UART_LSR_TX_SR_E_SHIFT (0x00000006u) -#define UART_LSR_TX_SR_E_EMPTY (0x1u) -#define UART_LSR_TX_SR_E_NOTEMPTY (0x0u) - -#define UART_LSR_TX_FIFO_E (0x00000020u) -#define UART_LSR_TX_FIFO_E_SHIFT (0x00000005u) -#define UART_LSR_TX_FIFO_E_EMPTY (0x1u) -#define UART_LSR_TX_FIFO_E_NOTEMPTY (0x0u) - -#define UART_LSR_RX_BI (0x00000010u) -#define UART_LSR_RX_BI_SHIFT (0x00000004u) -#define UART_LSR_RX_BI_BREAK (0x1u) -#define UART_LSR_RX_BI_NONE (0x0u) - -#define UART_LSR_RX_FE (0x00000008u) -#define UART_LSR_RX_FE_SHIFT (0x00000003u) -#define UART_LSR_RX_FE_ERROR (0x1u) -#define UART_LSR_RX_FE_NONE (0x0u) - -#define UART_LSR_RX_PE (0x00000004u) -#define UART_LSR_RX_PE_SHIFT (0x00000002u) -#define UART_LSR_RX_PE_ERROR (0x1u) -#define UART_LSR_RX_PE_NONE (0x0u) - -#define UART_LSR_RX_OE (0x00000002u) -#define UART_LSR_RX_OE_SHIFT (0x00000001u) -#define UART_LSR_RX_OE_ERROR (0x1u) -#define UART_LSR_RX_OE_NONE (0x0u) - -#define UART_LSR_RX_FIFO_E (0x00000001u) -#define UART_LSR_RX_FIFO_E_SHIFT (0x00000000u) -#define UART_LSR_RX_FIFO_E_EMPTY (0x0u) -#define UART_LSR_RX_FIFO_E_NOTEMPTY (0x1u) - -/* LSR - IrDA Register */ -#define UART_LSR_THR_EMPTY (0x00000080u) -#define UART_LSR_THR_EMPTY_SHIFT (0x00000007u) -#define UART_LSR_THR_EMPTY_EMPTY (0x1u) -#define UART_LSR_THR_EMPTY_NOTEMPTY (0x0u) - -#define UART_LSR_STS_FIFO_FULL (0x00000040u) -#define UART_LSR_STS_FIFO_FULL_SHIFT (0x00000006u) -#define UART_LSR_STS_FIFO_FULL_FULL (0x1u) -#define UART_LSR_STS_FIFO_FULL_NOTFULL (0x0u) - -#define UART_LSR_RX_LAST_BYTE (0x00000020u) -#define UART_LSR_RX_LAST_BYTE_SHIFT (0x00000005u) -#define UART_LSR_RX_LAST_BYTE_NO (0x0u) -#define UART_LSR_RX_LAST_BYTE_YES (0x1u) - -#define UART_LSR_FRAME_TOO_LONG (0x00000010u) -#define UART_LSR_FRAME_TOO_LONG_SHIFT (0x00000004u) -#define UART_LSR_FRAME_TOO_LONG_ERROR (0x1u) -#define UART_LSR_FRAME_TOO_LONG_NONE (0x0u) - -#define UART_LSR_ABORT (0x00000008u) -#define UART_LSR_ABORT_SHIFT (0x00000003u) -#define UART_LSR_ABORT_ERROR (0x1u) -#define UART_LSR_ABORT_NONE (0x0u) - -#define UART_LSR_CRC (0x00000004u) -#define UART_LSR_CRC_SHIFT (0x00000002u) -#define UART_LSR_CRC_ERROR (0x1u) -#define UART_LSR_CRC_NONE (0x0u) - -#define UART_LSR_STS_FIFO_E (0x00000002u) -#define UART_LSR_STS_FIFO_E_SHIFT (0x00000001u) -#define UART_LSR_STS_FIFO_E_EMPTY (0x1u) -#define UART_LSR_STS_FIFO_E_NOTEMPTY (0x0u) - -#define UART_LSR_IRDA_RX_FIFO_E (0x00000001u) -#define UART_LSR_IRDA_RX_FIFO_E_SHIFT (0x00000000u) -#define UART_LSR_IRDA_RX_FIFO_E_EMPTY (0x1u) -#define UART_LSR_IRDA_RX_FIFO_E_NOTEMPTY (0x0u) - -/* LSR - CIR Register */ -#define UART_LSR_CIR_THR_EMPTY (0x00000080u) -#define UART_LSR_CIR_THR_EMPTY_SHIFT (0x00000007u) -#define UART_LSR_CIR_THR_EMPTY_EMPTY (0x1u) -#define UART_LSR_CIR_THR_EMPTY_NOTEMPTY (0x0u) - -#define UART_LSR_CIR_RX_STOP (0x00000020u) -#define UART_LSR_RX_STOP_SHIFT (0x00000005u) -#define UART_LSR_RX_STOP_COMPLETE (0x1u) -#define UART_LSR_RX_STOP_ONGOING (0x0u) - -#define UART_LSR_CIR_RX_FIFO_E (0x00000001u) -#define UART_LSR_CIR_RX_FIFO_E_SHIFT (0x00000000u) -#define UART_LSR_CIR_RX_FIFO_E_EMPTY (0x1u) -#define UART_LSR_CIR_RX_FIFO_E_NOTEMPTY (0x0u) - -/* XON2_ADDR2 */ -#define UART_XON2_ADDR2_XON2_WORD2 (0x000000FFu) -#define UART_XON2_ADDR2_XON2_WORD2_SHIFT (0x00000000u) - - -/* MSR */ -#define UART_MSR_CTS_STS (0x00000001u) -#define UART_MSR_CTS_STS_SHIFT (0x00000000u) -#define UART_MSR_CTS_STS_CHANGED (0x1u) - -#define UART_MSR_DCD_STS (0x00000008u) -#define UART_MSR_DCD_STS_SHIFT (0x00000003u) -#define UART_MSR_DCD_STS_CHANGED (0x1u) - -#define UART_MSR_DSR_STS (0x00000002u) -#define UART_MSR_DSR_STS_SHIFT (0x00000001u) -#define UART_MSR_DSR_STS_CHANGED (0x1u) - -#define UART_MSR_NCD_STS (0x00000080u) -#define UART_MSR_NCD_STS_SHIFT (0x00000007u) - -#define UART_MSR_NCTS_STS (0x00000010u) -#define UART_MSR_NCTS_STS_SHIFT (0x00000004u) - -#define UART_MSR_NDSR_STS (0x00000020u) -#define UART_MSR_NDSR_STS_SHIFT (0x00000005u) - -#define UART_MSR_NRI_STS (0x00000040u) -#define UART_MSR_NRI_STS_SHIFT (0x00000006u) - -#define UART_MSR_RI_STS (0x00000004u) -#define UART_MSR_RI_STS_SHIFT (0x00000002u) -#define UART_MSR_RI_STS_CHANGED (0x1u) - - -/* TCR */ -#define UART_TCR_RX_FIFO_TRIG_HALT (0x0000000Fu) -#define UART_TCR_RX_FIFO_TRIG_HALT_SHIFT (0x00000000u) - -#define UART_TCR_RX_FIFO_TRIG_START (0x000000F0u) -#define UART_TCR_RX_FIFO_TRIG_START_SHIFT (0x00000004u) - - -/* XOFF1 */ -#define UART_XOFF1_WORD1 (0x000000FFu) -#define UART_XOFF1_WORD1_SHIFT (0x00000000u) - - -/* SPR */ -#define UART_SPR_SPR_WORD (0x000000FFu) -#define UART_SPR_SPR_WORD_SHIFT (0x00000000u) - - -/* TLR */ -#define UART_TLR_RX_FIFO_TRIG_DMA (0x000000F0u) -#define UART_TLR_RX_FIFO_TRIG_DMA_SHIFT (0x00000004u) - -#define UART_TLR_TX_FIFO_TRIG_DMA (0x0000000Fu) -#define UART_TLR_TX_FIFO_TRIG_DMA_SHIFT (0x00000000u) - - -/* XOFF2 */ -#define UART_XOFF2_WORD2 (0x000000FFu) -#define UART_XOFF2_WORD2_SHIFT (0x00000000u) - - -/* MDR1 */ -#define UART_MDR1_FRAME_END_MODE (0x00000080u) -#define UART_MDR1_FRAME_END_MODE_SHIFT (0x00000007u) -#define UART_MDR1_FRAME_END_MODE_EOT (0x1u) -#define UART_MDR1_FRAME_END_MODE_LENGTH (0x0u) - -#define UART_MDR1_IR_SLEEP (0x00000008u) -#define UART_MDR1_IR_SLEEP_SHIFT (0x00000003u) -#define UART_MDR1_IR_SLEEP_DISABLED (0x0u) -#define UART_MDR1_IR_SLEEP_ENABLED (0x1u) - -#define UART_MDR1_MODE_SELECT (0x00000007u) -#define UART_MDR1_MODE_SELECT_SHIFT (0x00000000u) -#define UART_MDR1_MODE_SELECT_CIR (0x6u) -#define UART_MDR1_MODE_SELECT_DISABLED (0x7u) -#define UART_MDR1_MODE_SELECT_FIR (0x5u) -#define UART_MDR1_MODE_SELECT_MIR (0x4u) -#define UART_MDR1_MODE_SELECT_SIR (0x1u) -#define UART_MDR1_MODE_SELECT_UART13X (0x3u) -#define UART_MDR1_MODE_SELECT_UART16X (0x0u) -#define UART_MDR1_MODE_SELECT_UART16XAUTO (0x2u) - -#define UART_MDR1_SCT (0x00000020u) -#define UART_MDR1_SCT_SHIFT (0x00000005u) -#define UART_MDR1_SCT_ACREG_SCTX (0x1u) -#define UART_MDR1_SCT_IMMEDIATE (0x0u) - -#define UART_MDR1_SET_TXIR (0x00000010u) -#define UART_MDR1_SET_TXIR_SHIFT (0x00000004u) -#define UART_MDR1_SET_TXIR_FORCEHIGH (0x1u) -#define UART_MDR1_SET_TXIR_FORCELOW (0x0u) - -#define UART_MDR1_SIP_MODE (0x00000040u) -#define UART_MDR1_SIP_MODE_SHIFT (0x00000006u) -#define UART_MDR1_SIP_MODE_AUTO (0x1u) -#define UART_MDR1_SIP_MODE_MANUAL (0x0u) - - -/* MDR2 */ -#define UART_MDR2_CIR_PULSE_MODE (0x00000030u) -#define UART_MDR2_CIR_PULSE_MODE_SHIFT (0x00000004u) -#define UART_MDR2_CIR_PULSE_MODE_WIDTH3 (0x0u) -#define UART_MDR2_CIR_PULSE_MODE_WIDTH4 (0x1u) -#define UART_MDR2_CIR_PULSE_MODE_WIDTH5 (0x2u) -#define UART_MDR2_CIR_PULSE_MODE_WIDTH6 (0x3u) - -#define UART_MDR2_IRRXINVERT (0x00000040u) -#define UART_MDR2_IRRXINVERT_SHIFT (0x00000006u) -#define UART_MDR2_IRRXINVERT_INVERT (0x0u) -#define UART_MDR2_IRRXINVERT_NOINVERT (0x1u) - -#define UART_MDR2_IRTX_UNDERRUN (0x00000001u) -#define UART_MDR2_IRTX_UNDERRUN_SHIFT (0x00000000u) -#define UART_MDR2_IRTX_UNDERRUN_ERROR (0x1u) -#define UART_MDR2_IRTX_UNDERRUN_NONE (0x0u) - -#define UART_MDR2_SET_TXIR_ALT (0x00000080u) -#define UART_MDR2_SET_TXIR_ALT_SHIFT (0x00000007u) -#define UART_MDR2_SET_TXIR_ALT_ALT (0x1u) -#define UART_MDR2_SET_TXIR_ALT_NORMAL (0x0u) - -#define UART_MDR2_STS_FIFO_TRIG (0x00000006u) -#define UART_MDR2_STS_FIFO_TRIG_SHIFT (0x00000001u) -#define UART_MDR2_STS_FIFO_TRIG_1ENTRY (0x0u) -#define UART_MDR2_STS_FIFO_TRIG_4ENTRIES (0x1u) -#define UART_MDR2_STS_FIFO_TRIG_7ENTRIES (0x2u) -#define UART_MDR2_STS_FIFO_TRIG_8ENTRIES (0x3u) - -#define UART_MDR2_UART_PULSE (0x00000008u) -#define UART_MDR2_UART_PULSE_SHIFT (0x00000003u) -#define UART_MDR2_UART_PULSE_NORMAL (0x0u) -#define UART_MDR2_UART_PULSE_SHAPING (0x1u) - - -/* SFLSR */ -#define UART_SFLSR_ABORT_DETECT (0x00000004u) -#define UART_SFLSR_ABORT_DETECT_SHIFT (0x00000002u) -#define UART_SFLSR_ABORT_DETECT_TRUE (0x1u) - -#define UART_SFLSR_CRC_ERROR (0x00000002u) -#define UART_SFLSR_CRC_ERROR_SHIFT (0x00000001u) -#define UART_SFLSR_CRC_ERROR_TRUE (0x1u) - -#define UART_SFLSR_FRAME_TOO_LONG_ERROR (0x00000008u) -#define UART_SFLSR_FRAME_TOO_LONG_ERROR_SHIFT (0x00000003u) -#define UART_SFLSR_FRAME_TOO_LONG_ERROR_TRUE (0x1u) - -#define UART_SFLSR_OE_ERROR (0x00000010u) -#define UART_SFLSR_OE_ERROR_SHIFT (0x00000004u) -#define UART_SFLSR_OE_ERROR_TRUE (0x1u) - - -/* TXFLL */ -#define UART_TXFLL_TXFLL (0x000000FFu) -#define UART_TXFLL_TXFLL_SHIFT (0x00000000u) - - -/* RESUME */ -#define UART_RESUME_RESUME (0x000000FFu) -#define UART_RESUME_RESUME_SHIFT (0x00000000u) - - -/* TXFLH */ -#define UART_TXFLH_TXFLH (0x0000001Fu) -#define UART_TXFLH_TXFLH_SHIFT (0x00000000u) - - -/* RXFLL */ -#define UART_RXFLL_RXFLL (0x000000FFu) -#define UART_RXFLL_RXFLL_SHIFT (0x00000000u) - - -/* SFREGL */ -#define UART_SFREGL_SFREGL (0x000000FFu) -#define UART_SFREGL_SFREGL_SHIFT (0x00000000u) - - -/* RXFLH */ -#define UART_RXFLH_RXFLH (0x0000000Fu) -#define UART_RXFLH_RXFLH_SHIFT (0x00000000u) - - -/* SFREGH */ -#define UART_SFREGH_SFREGH (0x0000000Fu) -#define UART_SFREGH_SFREGH_SHIFT (0x00000000u) - - -/* BLR */ -#define UART_BLR_STS_FIFO_RESET (0x00000080u) -#define UART_BLR_STS_FIFO_RESET_SHIFT (0x00000007u) - -#define UART_BLR_XBOF_TYPE (0x00000040u) -#define UART_BLR_XBOF_TYPE_SHIFT (0x00000006u) -#define UART_BLR_XBOF_TYPE_0XC0 (0x1u) -#define UART_BLR_XBOF_TYPE_0XFF (0x0u) - - -/* UASR */ -#define UART_UASR_BIT_BY_CHAR (0x00000020u) -#define UART_UASR_BIT_BY_CHAR_SHIFT (0x00000005u) -#define UART_UASR_BIT_BY_CHAR_7BITS (0x0u) -#define UART_UASR_BIT_BY_CHAR_8BITS (0x1u) - -#define UART_UASR_PARITY_TYPE (0x000000C0u) -#define UART_UASR_PARITY_TYPE_SHIFT (0x00000006u) -#define UART_UASR_PARITY_TYPE_EVEN (0x2u) -#define UART_UASR_PARITY_TYPE_NONE (0x0u) -#define UART_UASR_PARITY_TYPE_ODD (0x3u) -#define UART_UASR_PARITY_TYPE_SPACE (0x1u) - -#define UART_UASR_SPEED (0x0000001Fu) -#define UART_UASR_SPEED_SHIFT (0x00000000u) -#define UART_UASR_SPEED_115200 (0x1u) -#define UART_UASR_SPEED_1200 (0xAu) -#define UART_UASR_SPEED_14400 (0x6u) -#define UART_UASR_SPEED_19200 (0x5u) -#define UART_UASR_SPEED_2400 (0x9u) -#define UART_UASR_SPEED_28800 (0x4u) -#define UART_UASR_SPEED_38400 (0x3u) -#define UART_UASR_SPEED_4800 (0x8u) -#define UART_UASR_SPEED_57600 (0x2u) -#define UART_UASR_SPEED_9600 (0x7u) -#define UART_UASR_SPEED_NONE (0x0u) - - -/* ACREG */ -#define UART_ACREG_ABORT_EN (0x00000002u) -#define UART_ACREG_ABORT_EN_SHIFT (0x00000001u) -#define UART_ACREG_ABORT_EN_SET (0x2u) - -#define UART_ACREG_DIS_IR_RX (0x00000020u) -#define UART_ACREG_DIS_IR_RX_SHIFT (0x00000005u) -#define UART_ACREG_DIS_IR_RX_DISABLE (0x1u) -#define UART_ACREG_DIS_IR_RX_NORMAL (0x0u) - -#define UART_ACREG_DIS_TX_UNDERRUN (0x00000010u) -#define UART_ACREG_DIS_TX_UNDERRUN_SHIFT (0x00000004u) -#define UART_ACREG_DIS_TX_UNDERRUN_DISABLED (0x1u) -#define UART_ACREG_DIS_TX_UNDERRUN_NORMAL (0x0u) - -#define UART_ACREG_EOT_EN (0x00000001u) -#define UART_ACREG_EOT_EN_SHIFT (0x00000000u) -#define UART_ACREG_EOT_EN_SET (0x1u) - -#define UART_ACREG_PULSE_TYPE (0x00000080u) -#define UART_ACREG_PULSE_TYPE_SHIFT (0x00000007u) -#define UART_ACREG_PULSE_TYPE_0P1875PW (0x0u) -#define UART_ACREG_PULSE_TYPE_1P6US (0x1u) - -#define UART_ACREG_SCTX_EN (0x00000004u) -#define UART_ACREG_SCTX_EN_SHIFT (0x00000002u) -#define UART_ACREG_SCTX_EN_SET (0x4u) - -#define UART_ACREG_SD_MOD (0x00000040u) -#define UART_ACREG_SD_MOD_SHIFT (0x00000006u) -#define UART_ACREG_SD_MOD_HIGH (0x0u) -#define UART_ACREG_SD_MOD_LOW (0x1u) - -#define UART_ACREG_SEND_SIP (0x00000008u) -#define UART_ACREG_SEND_SIP_SHIFT (0x00000003u) -#define UART_ACREG_SEND_SIP_SET (0x1u) - - -/* SCR */ -#define UART_SCR_DMA_MODE_2 (0x00000006u) -#define UART_SCR_DMA_MODE_2_SHIFT (0x00000001u) -#define UART_SCR_DMA_MODE_2_MODE0 (0x0u) -#define UART_SCR_DMA_MODE_2_MODE1 (0x1u) -#define UART_SCR_DMA_MODE_2_MODE2 (0x2u) -#define UART_SCR_DMA_MODE_2_MODE3 (0x3u) - -#define UART_SCR_DMA_MODE_CTL (0x00000001u) -#define UART_SCR_DMA_MODE_CTL_SHIFT (0x00000000u) -#define UART_SCR_DMA_MODE_CTL_FCR (0x0u) -#define UART_SCR_DMA_MODE_CTL_SCR (0x1u) - -#define UART_SCR_DSR_IT (0x00000020u) -#define UART_SCR_DSR_IT_SHIFT (0x00000005u) -#define UART_SCR_DSR_IT_DISABLE (0x0u) -#define UART_SCR_DSR_IT_ENABLE (0x1u) - -#define UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE (0x00000010u) -#define UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_SHIFT (0x00000004u) -#define UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_DISABLE (0x0u) -#define UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_ENABLE (0x1u) - -#define UART_SCR_RX_TRIG_GRANU1 (0x00000080u) -#define UART_SCR_RX_TRIG_GRANU1_SHIFT (0x00000007u) -#define UART_SCR_RX_TRIG_GRANU1_DISABLE (0x0u) -#define UART_SCR_RX_TRIG_GRANU1_ENABLE (0x1u) - -#define UART_SCR_TX_EMPTY_CTL_IT (0x00000008u) -#define UART_SCR_TX_EMPTY_CTL_IT_SHIFT (0x00000003u) -#define UART_SCR_TX_EMPTY_CTL_IT_EMPTY (0x1u) -#define UART_SCR_TX_EMPTY_CTL_IT_NORMAL (0x0u) - -#define UART_SCR_TX_TRIG_GRANU1 (0x00000040u) -#define UART_SCR_TX_TRIG_GRANU1_SHIFT (0x00000006u) -#define UART_SCR_TX_TRIG_GRANU1_DISABLE (0x0u) -#define UART_SCR_TX_TRIG_GRANU1_ENABLE (0x1u) - - -/* SSR */ -#define UART_SSR_DMA_COUNTER_RST (0x00000004u) -#define UART_SSR_DMA_COUNTER_RST_SHIFT (0x00000002u) -#define UART_SSR_DMA_COUNTER_RST_MODE0 (0x0u) -#define UART_SSR_DMA_COUNTER_RST_MODE1 (0x1u) - -#define UART_SSR_RX_CTS_DSR_WAKE_UP_STS (0x00000002u) -#define UART_SSR_RX_CTS_DSR_WAKE_UP_STS_SHIFT (0x00000001u) -#define UART_SSR_RX_CTS_DSR_WAKE_UP_STS_DETECTED (0x1u) -#define UART_SSR_RX_CTS_DSR_WAKE_UP_STS_NONE (0x0u) - -#define UART_SSR_TX_FIFO_FULL (0x00000001u) -#define UART_SSR_TX_FIFO_FULL_SHIFT (0x00000000u) -#define UART_SSR_TX_FIFO_FULL_FULL (0x1u) -#define UART_SSR_TX_FIFO_FULL_NOTFULL (0x0u) - - -/* EBLR */ -#define UART_EBLR_EBLR (0x000000FFu) -#define UART_EBLR_EBLR_SHIFT (0x00000000u) - - -/* MVR */ -#define UART_MVR_MAJORREV (0x000000F0u) -#define UART_MVR_MAJORREV_SHIFT (0x00000004u) - -#define UART_MVR_MINORREV (0x0000000Fu) -#define UART_MVR_MINORREV_SHIFT (0x00000000u) - -/* SYSC */ -#define UART_SYSC_AUTOIDLE (0x00000001u) -#define UART_SYSC_AUTOIDLE_SHIFT (0x00000000u) -#define UART_SYSC_AUTOIDLE_DISABLE (0x0u) -#define UART_SYSC_AUTOIDLE_ENABLE (0x1u) - -#define UART_SYSC_ENAWAKEUP (0x00000004u) -#define UART_SYSC_ENAWAKEUP_SHIFT (0x00000002u) -#define UART_SYSC_ENAWAKEUP_DISABLE (0x0u) -#define UART_SYSC_ENAWAKEUP_ENABLE (0x1u) - -#define UART_SYSC_IDLEMODE (0x00000018u) -#define UART_SYSC_IDLEMODE_SHIFT (0x00000003u) -#define UART_SYSC_IDLEMODE_FORCE (0x0u) -#define UART_SYSC_IDLEMODE_NOIDLE (0x1u) -#define UART_SYSC_IDLEMODE_SMART (0x2u) -#define UART_SYSC_IDLEMODE_WAKEUP (0x3u) - -#define UART_SYSC_SOFTRESET (0x00000002u) -#define UART_SYSC_SOFTRESET_SHIFT (0x00000001u) -#define UART_SYSC_SOFTRESET_DONE (0x0u) -#define UART_SYSC_SOFTRESET_INITIATE (0x1u) - - -/* SYSS */ -#define UART_SYSS_RESETDONE (0x00000001u) -#define UART_SYSS_RESETDONE_SHIFT (0x00000000u) -#define UART_SYSS_RESETDONE_DONE (0x1u) -#define UART_SYSS_RESETDONE_ONGOING (0x0u) - - -/* WER */ -#define UART_WER_EVENT_0_CTS_ACTIVITY (0x00000001u) -#define UART_WER_EVENT_0_CTS_ACTIVITY_SHIFT (0x00000000u) -#define UART_WER_EVENT_0_CTS_ACTIVITY_DISABLE (0x0u) -#define UART_WER_EVENT_0_CTS_ACTIVITY_ENABLE (0x1u) - -#define UART_WER_EVENT_1_DSR_ACTIVITY (0x00000002u) -#define UART_WER_EVENT_1_DSR_ACTIVITY_SHIFT (0x00000001u) -#define UART_WER_EVENT_1_DSR_ACTIVITY_DISABLE (0x0u) -#define UART_WER_EVENT_1_DSR_ACTIVITY_ENABLE (0x1u) - -#define UART_WER_EVENT_2_RI_ACTIVITY (0x00000004u) -#define UART_WER_EVENT_2_RI_ACTIVITY_SHIFT (0x00000002u) -#define UART_WER_EVENT_2_RI_ACTIVITY_DISABLE (0x0u) -#define UART_WER_EVENT_2_RI_ACTIVITY_ENABLE (0x1u) - -#define UART_WER_EVENT_3_DCD_CD_ACTIVITY (0x00000008u) -#define UART_WER_EVENT_3_DCD_CD_ACTIVITY_SHIFT (0x00000003u) -#define UART_WER_EVENT_3_DCD_CD_ACTIVITY_DISABLE (0x0u) -#define UART_WER_EVENT_3_DCD_CD_ACTIVITY_ENABLE (0x1u) - -#define UART_WER_EVENT_4_RX_ACTIVITY (0x00000010u) -#define UART_WER_EVENT_4_RX_ACTIVITY_SHIFT (0x00000004u) -#define UART_WER_EVENT_4_RX_ACTIVITY_DISABLE (0x0u) -#define UART_WER_EVENT_4_RX_ACTIVITY_ENABLE (0x1u) - -#define UART_WER_EVENT_5_RHR_INTERRUPT (0x00000020u) -#define UART_WER_EVENT_5_RHR_INTERRUPT_SHIFT (0x00000005u) -#define UART_WER_EVENT_5_RHR_INTERRUPT_DISABLE (0x0u) -#define UART_WER_EVENT_5_RHR_INTERRUPT_ENABLE (0x1u) - -#define UART_WER_EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT (0x00000040u) -#define UART_WER_EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_SHIFT (0x00000006u) -#define UART_WER_EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_DISABLE (0x0u) -#define UART_WER_EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_ENABLE (0x1u) - -#define UART_WER_EVENT_7_TX_WAKEUP_EN (0x00000080u) -#define UART_WER_EVENT_7_TX_WAKEUP_EN_SHIFT (0x00000007u) -#define UART_WER_EVENT_7_TX_WAKEUP_EN_DISABLE (0x0u) -#define UART_WER_EVENT_7_TX_WAKEUP_EN_ENABLE (0x1u) - - -/* CFPS */ -#define UART_CFPS_CFPS (0x000000FFu) -#define UART_CFPS_CFPS_SHIFT (0x00000000u) - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/lib/tiam1808/tiam1808/hw/hw_usbOtg_AM335x.h b/lib/tiam1808/tiam1808/hw/hw_usbOtg_AM335x.h deleted file mode 100644 index afdab60d1..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_usbOtg_AM335x.h +++ /dev/null @@ -1,140 +0,0 @@ -/** ============================================================================ - * \file hw_usbOtg.h - * - * \brief This file contains the offset of USB OTG registers - * - * ============================================================================ - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -//***************************************************************************** -// -// hw_usbOtg.h - Macros for use in accessing the USB registers. -// -//***************************************************************************** -#ifndef __HW_USBOTG_H__ -#define __HW_USBOTG_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are defines for the Univeral Serial Bus OTG register offsets. -// -//***************************************************************************** - -// -//USB subsystem base address -// -#define USBSS_BASE 0x47400000 -// -//USB0 base address -// -#define USB_0_OTGBASE 0x47401000 -// -//USB1 base address -// -#define USB_1_OTGBASE 0x47401800 - -// -//USB subsystem register offsets -// -#define USBSS_IRQ_EOI 0x20 -#define USBSS_IRQ_STATUS_RAW 0x24 -#define USBSS_IRQ_STATUS 0x28 -#define USBSS_IRQ_ENABLE_SET 0x2C -#define USBSS_IRQ_ENABLE_CLR 0x30 - -// -//USB0 offset register offsets -// -#define USB_0_REVISION 0x00 -#define USB_0_CTRL 0x14 -#define USB_0_STAT 0x18 -#define USB_0_IRQ_MERGED_STATUS 0x20 -#define USB_0_IRQ_EOI 0x24 -#define USB_0_IRQ_STATUS_RAW_0 0x28 -#define USB_0_IRQ_STATUS_RAW_1 0x2C -#define USB_0_IRQ_STATUS_0 0x30 -#define USB_0_IRQ_STATUS_1 0x34 -#define USB_0_IRQ_ENABLE_SET_0 0x38 -#define USB_0_IRQ_ENABLE_SET_1 0x3C -#define USB_0_IRQ_ENABLE_CLR_0 0x40 -#define USB_0_IRQ_ENABLE_CLR_1 0x44 - -#define USB_0_TX_MODE 0x70 -#define USB_0_RX_MODE 0x74 - -#define USB_0_GEN_RNDIS_SIZE_EP1 0x80 -#define USB_0_GEN_RNDIS_SIZE_EP2 0x84 -#define USB_0_GEN_RNDIS_SIZE_EP3 0x88 -#define USB_0_GEN_RNDIS_SIZE_EP4 0x8C -#define USB_0_GEN_RNDIS_SIZE_EP5 0x90 -#define USB_0_GEN_RNDIS_SIZE_EP6 0x94 -#define USB_0_GEN_RNDIS_SIZE_EP7 0x98 -#define USB_0_GEN_RNDIS_SIZE_EP8 0x9C -#define USB_0_GEN_RNDIS_SIZE_EP9 0xA0 -#define USB_0_GEN_RNDIS_SIZE_EP10 0xA4 -#define USB_0_GEN_RNDIS_SIZE_EP11 0xA8 -#define USB_0_GEN_RNDIS_SIZE_EP12 0xAC -#define USB_0_GEN_RNDIS_SIZE_EP13 0xB0 -#define USB_0_GEN_RNDIS_SIZE_EP14 0xB4 -#define USB_0_GEN_RNDIS_SIZE_EP15 0xB8 - -#define USB_0_AUTO_REQ 0xD0 -#define USB_0_SRP_FIX_TIME 0xD4 -#define USB_0_TEARDOWN 0xD8 -#define USB_0_THRESHOLD_XDMA_IDLE 0xDC -#define USB_0_PHY_UTMI 0xE0 -#define USB_0_MGC_UTMI_LOOPBACK 0xE4 -#define USB_0_MODE 0xE8 - -#ifdef __cplusplus -} -#endif - -#endif // __HW_USBOTG_H__ - diff --git a/lib/tiam1808/tiam1808/hw/hw_usbOtg_C6748.h b/lib/tiam1808/tiam1808/hw/hw_usbOtg_C6748.h deleted file mode 100644 index 648560909..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_usbOtg_C6748.h +++ /dev/null @@ -1,83 +0,0 @@ -/** - * \file hw_usbOtg_OMAPL138.h - * - * \brief This file contains the offset of USB OTG registers - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef __HW_USBOTG_H__ -#define __HW_USBOTG_H__ - -/* If building with a C++ compiler, make all of the definitions in this header - * have a C binding. */ -#ifdef __cplusplus -extern "C" -{ -#endif - -/* The following are defines for the Univeral Serial Bus OTG register offsets. */ - -#define USB_0_OTGBASE SOC_USB_0_OTG_BASE - -#define USB_0_REVISION 0x00 -#define USB_0_CTRL 0x04 -#define USB_0_STAT 0x08 -#define USB_0_EMULATION 0x08 -#define USB_0_MODE 0x10 -#define USB_0_AUTOREQ 0x14 -#define USB_0_SRP_FIX_TIME 0x18 -#define USB_0_TEARDOWN 0x1c -#define USB_0_INTR_SRC 0x20 -#define USB_0_INTR_SRC_SET 0x24 -#define USB_0_INTR_SRC_CLEAR 0x28 -#define USB_0_INTR_MASK 0x2c -#define USB_0_INTR_MASK_SET 0x30 -#define USB_0_INTR_MASK_CLEAR 0x34 -#define USB_0_INTR_SRC_MASKED 0x38 -#define USB_0_END_OF_INTR 0x3c - -#define USB_0_GEN_RNDIS_SIZE_EP1 0x50 -#define USB_0_GEN_RNDIS_SIZE_EP2 0x54 -#define USB_0_GEN_RNDIS_SIZE_EP3 0x58 -#define USB_0_GEN_RNDIS_SIZE_EP4 0x5C -#define USB_0_GENR_INTR 0x22 - -#ifdef __cplusplus -} -#endif - -#endif /* __HW_USBOTG_H__ */ diff --git a/lib/tiam1808/tiam1808/hw/hw_usbOtg_C6A811x.h b/lib/tiam1808/tiam1808/hw/hw_usbOtg_C6A811x.h deleted file mode 100644 index 52346f1ad..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_usbOtg_C6A811x.h +++ /dev/null @@ -1,139 +0,0 @@ -/** ============================================================================ - * \file hw_usbOtg_C6A811x.h - * - * \brief This file contains the offset of USB OTG registers - * - * ============================================================================ - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -//***************************************************************************** -// -// hw_usbOtg.h - Macros for use in accessing the USB registers. -// -//***************************************************************************** -#ifndef __HW_USBOTG_H__ -#define __HW_USBOTG_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are defines for the Univeral Serial Bus OTG register offsets. -// -//***************************************************************************** - -// -//USB subsystem base address -// -#define USBSS_BASE 0x47400000 -// -//USB0 base address -// -#define USB_0_OTGBASE 0x47401000 -// -//USB1 base address -// -#define USB_1_OTGBASE 0x47401800 - -// -//USB subsystem register offsets -// -#define USBSS_IRQ_EOI 0x20 -#define USBSS_IRQ_STATUS_RAW 0x24 -#define USBSS_IRQ_STATUS 0x28 -#define USBSS_IRQ_ENABLE_SET 0x2C -#define USBSS_IRQ_ENABLE_CLR 0x30 - -// -//USB0 offset register offsets -// -#define USB_0_REVISION 0x00 -#define USB_0_CTRL 0x14 -#define USB_0_STAT 0x18 -#define USB_0_IRQ_MERGED_STATUS 0x20 -#define USB_0_IRQ_EOI 0x24 -#define USB_0_IRQ_STATUS_RAW_0 0x28 -#define USB_0_IRQ_STATUS_RAW_1 0x2C -#define USB_0_IRQ_STATUS_0 0x30 -#define USB_0_IRQ_STATUS_1 0x34 -#define USB_0_IRQ_ENABLE_SET_0 0x38 -#define USB_0_IRQ_ENABLE_SET_1 0x3C -#define USB_0_IRQ_ENABLE_CLR_0 0x40 -#define USB_0_IRQ_ENABLE_CLR_1 0x44 - -#define USB_0_TX_MODE 0x70 -#define USB_0_RX_MODE 0x74 - -#define USB_0_GEN_RNDIS_SIZE_EP1 0x80 -#define USB_0_GEN_RNDIS_SIZE_EP2 0x84 -#define USB_0_GEN_RNDIS_SIZE_EP3 0x88 -#define USB_0_GEN_RNDIS_SIZE_EP4 0x8C -#define USB_0_GEN_RNDIS_SIZE_EP5 0x90 -#define USB_0_GEN_RNDIS_SIZE_EP6 0x94 -#define USB_0_GEN_RNDIS_SIZE_EP7 0x98 -#define USB_0_GEN_RNDIS_SIZE_EP8 0x9C -#define USB_0_GEN_RNDIS_SIZE_EP9 0xA0 -#define USB_0_GEN_RNDIS_SIZE_EP10 0xA4 -#define USB_0_GEN_RNDIS_SIZE_EP11 0xA8 -#define USB_0_GEN_RNDIS_SIZE_EP12 0xAC -#define USB_0_GEN_RNDIS_SIZE_EP13 0xB0 -#define USB_0_GEN_RNDIS_SIZE_EP14 0xB4 -#define USB_0_GEN_RNDIS_SIZE_EP15 0xB8 - -#define USB_0_AUTO_REQ 0xD0 -#define USB_0_SRP_FIX_TIME 0xD4 -#define USB_0_TEARDOWN 0xD8 -#define USB_0_THRESHOLD_XDMA_IDLE 0xDC -#define USB_0_PHY_UTMI 0xE0 -#define USB_0_MGC_UTMI_LOOPBACK 0xE4 -#define USB_0_MODE 0xE8 - -#ifdef __cplusplus -} -#endif - -#endif // __HW_USBOTG_H__ diff --git a/lib/tiam1808/tiam1808/hw/hw_usbOtg_OMAPL138.h b/lib/tiam1808/tiam1808/hw/hw_usbOtg_OMAPL138.h deleted file mode 100644 index 648560909..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_usbOtg_OMAPL138.h +++ /dev/null @@ -1,83 +0,0 @@ -/** - * \file hw_usbOtg_OMAPL138.h - * - * \brief This file contains the offset of USB OTG registers - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef __HW_USBOTG_H__ -#define __HW_USBOTG_H__ - -/* If building with a C++ compiler, make all of the definitions in this header - * have a C binding. */ -#ifdef __cplusplus -extern "C" -{ -#endif - -/* The following are defines for the Univeral Serial Bus OTG register offsets. */ - -#define USB_0_OTGBASE SOC_USB_0_OTG_BASE - -#define USB_0_REVISION 0x00 -#define USB_0_CTRL 0x04 -#define USB_0_STAT 0x08 -#define USB_0_EMULATION 0x08 -#define USB_0_MODE 0x10 -#define USB_0_AUTOREQ 0x14 -#define USB_0_SRP_FIX_TIME 0x18 -#define USB_0_TEARDOWN 0x1c -#define USB_0_INTR_SRC 0x20 -#define USB_0_INTR_SRC_SET 0x24 -#define USB_0_INTR_SRC_CLEAR 0x28 -#define USB_0_INTR_MASK 0x2c -#define USB_0_INTR_MASK_SET 0x30 -#define USB_0_INTR_MASK_CLEAR 0x34 -#define USB_0_INTR_SRC_MASKED 0x38 -#define USB_0_END_OF_INTR 0x3c - -#define USB_0_GEN_RNDIS_SIZE_EP1 0x50 -#define USB_0_GEN_RNDIS_SIZE_EP2 0x54 -#define USB_0_GEN_RNDIS_SIZE_EP3 0x58 -#define USB_0_GEN_RNDIS_SIZE_EP4 0x5C -#define USB_0_GENR_INTR 0x22 - -#ifdef __cplusplus -} -#endif - -#endif /* __HW_USBOTG_H__ */ diff --git a/lib/tiam1808/tiam1808/hw/hw_usbphyGS70.h b/lib/tiam1808/tiam1808/hw/hw_usbphyGS70.h deleted file mode 100644 index 4b69d3d1e..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_usbphyGS70.h +++ /dev/null @@ -1,79 +0,0 @@ -/** ============================================================================ - * \file hw_usbphyGS70.h - * - * \brief This file contains the bit field values to use with the USB phy register - * - * ============================================================================ - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef __HW_USBPHY_GS70_H__ -#define __HW_USBPHY_GS70_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -/****************************************************************************** -** PHY REGISTER ADDRESS -*******************************************************************************/ -#define CFGCHIP2_USBPHYCTRL 0x44E10620 - - -/****************************************************************************** -** BIT FIELDS TO USE WITH PHY REGISTER -*******************************************************************************/ -#define USBPHY_CM_PWRDN (1 << 0) -#define USBPHY_OTG_PWRDN (1 << 1) -#define USBPHY_OTGVDET_EN (1 << 19) -#define USBPHY_OTGSESSEND_EN (1 << 20) - -void UsbPhyOn(void); -void UsbPhyOff(void); - -#ifdef __cplusplus -} -#endif - -#endif // __HW_USBPHY_GS70_H__ diff --git a/lib/tiam1808/tiam1808/hw/hw_vpif.h b/lib/tiam1808/tiam1808/hw/hw_vpif.h deleted file mode 100644 index 911f2414b..000000000 --- a/lib/tiam1808/tiam1808/hw/hw_vpif.h +++ /dev/null @@ -1,944 +0,0 @@ -/** - * \file hw_vpif.h - * - * \brief Hardware registers and fields for VPIF module - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _HW_VPIF_H_ -#define _HW_VPIF_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - - -#define REVID (0x0) -#define C0CTRL (0x4) -#define C1CTRL (0x8) -#define C2CTRL (0xC) -#define C3CTRL (0x10) -#define ERRSTAT (0x14) -#define INTEN (0x20) -#define INTSET (0x24) -#define INTCLR (0x28) -#define INTSTAT (0x2C) -#define INTSTATCLR (0x30) -#define EMUCTRL (0x34) -#define REQSIZE (0x38) -/* Channel 0 */ -#define C0TLUMA (0x40) -#define C0BLUMA (0x44) -#define C0TCHROMA (0x48) -#define C0BCHROMA (0x4C) -#define C0THANC (0x50) -#define C0BHANC (0x54) -#define C0TVANC (0x58) -#define C0BVANC (0x5C) -#define C0IMGOFFSET (0x64) -#define C0HANCOFFSET (0x68) -#define C0HCFG (0x6C) -#define C0VCFG0 (0x70) -#define C0VCFG1 (0x74) -#define C0VCFG2 (0x78) -#define C0VSIZE (0x7C) -/* Channel 1 */ -#define C1TLUMA (0x80) -#define C1BLUMA (0x84) -#define C1TCHROMA (0x88) -#define C1BCHROMA (0x8C) -#define C1THANC (0x90) -#define C1BHANC (0x94) -#define C1TVANC (0x98) -#define C1BVANC (0x9C) -#define C1IMGOFFSET (0xA4) -#define C1HANCOFFSET (0xA8) -#define C1HCFG (0xAC) -#define C1VCFG0 (0xB0) -#define C1VCFG1 (0xB4) -#define C1VCFG2 (0xB8) -#define C1VSIZE (0xBC) -/* Channel 2 */ -#define C2TLUMA (0xC0) -#define C2BLUMA (0xC4) -#define C2TCHROMA (0xC8) -#define C2BCHROMA (0xCC) -#define C2THANC (0xD0) -#define C2BHANC (0xD4) -#define C2TVANC (0xD8) -#define C2BVANC (0xDC) -#define C2IMGOFFSET (0xE4) -#define C2HANCOFFSET (0xE8) -#define C2HCFG (0xEC) -#define C2VCFG0 (0xF0) -#define C2VCFG1 (0xF4) -#define C2VCFG2 (0xF8) -#define C2VSIZE (0xFC) -#define C2THANCPOS (0x100) -#define C2THANCSIZE (0x104) -#define C2BHANCPOS (0x108) -#define C2BHANCSIZE (0x10C) -#define C2TVANCPOS (0x110) -#define C2TVANCSIZE (0x114) -#define C2BVANCPOS (0x118) -#define C2BVANCSIZE (0x11C) -/* Channel 3 */ -#define C3TLUMA (0x140) -#define C3BLUMA (0x144) -#define C3TCHROMA (0x148) -#define C3BCHROMA (0x14C) -#define C3THANC (0x150) -#define C3BHANC (0x154) -#define C3TVANC (0x158) -#define C3BVANC (0x15C) -#define C3IMGOFFSET (0x164) -#define C3HANCOFFSET (0x168) -#define C3HCFG (0x16C) -#define C3VCFG0 (0x170) -#define C3VCFG1 (0x174) -#define C3VCFG2 (0x178) -#define C3VSIZE (0x17C) -#define C3THANCPOS (0x180) -#define C3THANCSIZE (0x184) -#define C3BHANCPOS (0x188) -#define C3BHANCSIZE (0x18C) -#define C3TVANCPOS (0x190) -#define C3TVANCSIZE (0x194) -#define C3BVANCPOS (0x198) -#define C3BVANCSIZE (0x19C) - -/**************************************************************************\ -* Field Definition Macros -\**************************************************************************/ - -/* REVID */ - -#define VPIF_REVID_REV (0xFFFFFFFFu) -#define VPIF_REVID_REV_SHIFT (0x00000000u) - -/* C0CTRL */ - -#define VPIF_C0CTRL_CLKEDGE (0x80000000u) -#define VPIF_C0CTRL_CLKEDGE_SHIFT (0x0000001Fu) - -#define VPIF_C0CTRL_DATAWIDTH (0x30000000u) -#define VPIF_C0CTRL_DATAWIDTH_SHIFT (0x0000001Cu) -/*-----DATAWIDTH Tokens-----*/ -#define VPIF_C0CTRL_DATAWIDTH_EIGHT_BPS (0x00000000u) -#define VPIF_C0CTRL_DATAWIDTH_TEN_BPS (0x00000001u) -#define VPIF_C0CTRL_DATAWIDTH_TWELVE_BPS (0x00000002u) - -#define VPIF_C0CTRL_INTLINE (0x0FFF0000u) -#define VPIF_C0CTRL_INTLINE_SHIFT (0x00000010u) - -#define VPIF_C0CTRL_FIDINV (0x00008000u) -#define VPIF_C0CTRL_FIDINV_SHIFT (0x0000000Fu) - -#define VPIF_C0CTRL_VVINV (0x00004000u) -#define VPIF_C0CTRL_VVINV_SHIFT (0x0000000Eu) - -#define VPIF_C0CTRL_HVINV (0x00002000u) -#define VPIF_C0CTRL_HVINV_SHIFT (0x0000000Du) - -#define VPIF_C0CTRL_FIELDFRAME (0x00001000u) -#define VPIF_C0CTRL_FIELDFRAME_SHIFT (0x0000000Cu) - -#define VPIF_C0CTRL_INTRPROG (0x00000400u) -#define VPIF_C0CTRL_INTRPROG_SHIFT (0x0000000Au) - -#define VPIF_C0CTRL_VANC (0x00000200u) -#define VPIF_C0CTRL_VANC_SHIFT (0x00000009u) - -#define VPIF_C0CTRL_HANC (0x00000100u) -#define VPIF_C0CTRL_HANC_SHIFT (0x00000008u) - -#define VPIF_C0CTRL_INTFRAME (0x000000C0u) -#define VPIF_C0CTRL_INTFRAME_SHIFT (0x00000006u) -/*-----INTFRAME Tokens-----*/ -#define VPIF_C0CTRL_INTFRAME_TOP (0x00000000u) -#define VPIF_C0CTRL_INTFRAME_BOTTOM (0x00000001u) -#define VPIF_C0CTRL_INTFRAME_TOP_BOTTOM (0x00000002u) - -#define VPIF_C0CTRL_FID (0x00000020u) -#define VPIF_C0CTRL_FID_SHIFT (0x00000005u) - -#define VPIF_C0CTRL_YCMUX (0x00000008u) -#define VPIF_C0CTRL_YCMUX_SHIFT (0x00000003u) - -#define VPIF_C0CTRL_CAPMODE (0x00000004u) -#define VPIF_C0CTRL_CAPMODE_SHIFT (0x00000002u) - -#define VPIF_C0CTRL_CHANEN (0x00000001u) -#define VPIF_C0CTRL_CHANEN_SHIFT (0x00000000u) - -/* C1CTRL */ - -#define VPIF_C1CTRL_CLKEDGE (0x80000000u) -#define VPIF_C1CTRL_CLKEDGE_SHIFT (0x0000001Fu) - -#define VPIF_C1CTRL_INTRPROG (0x00000400u) -#define VPIF_C1CTRL_INTRPROG_SHIFT (0x0000000Au) - -#define VPIF_C1CTRL_VANC (0x00000200u) -#define VPIF_C1CTRL_VANC_SHIFT (0x00000009u) - -#define VPIF_C1CTRL_HANC (0x00000100u) -#define VPIF_C1CTRL_HANC_SHIFT (0x00000008u) - -#define VPIF_C1CTRL_INTFRAME (0x000000C0u) -#define VPIF_C1CTRL_INTFRAME_SHIFT (0x00000006u) -/*-----INTFRAME Tokens-----*/ -#define VPIF_C1CTRL_INTFRAME_TOP (0x00000000u) -#define VPIF_C1CTRL_INTFRAME_BOTTOM (0x00000001u) -#define VPIF_C1CTRL_INTFRAME_TOP_BOTTOM (0x00000002u) - -#define VPIF_C1CTRL_FID (0x00000020u) -#define VPIF_C1CTRL_FID_SHIFT (0x00000005u) - -#define VPIF_C1CTRL_YCMUX (0x00000008u) -#define VPIF_C1CTRL_YCMUX_SHIFT (0x00000003u) - -#define VPIF_C1CTRL_CAPMODE (0x00000004u) -#define VPIF_C1CTRL_CAPMODE_SHIFT (0x00000002u) - -#define VPIF_C1CTRL_CHANEN (0x00000001u) -#define VPIF_C1CTRL_CHANEN_SHIFT (0x00000000u) - -/* C2CTRL */ - -#define VPIF_C2CTRL_CLKEDGE (0x80000000u) -#define VPIF_C2CTRL_CLKEDGE_SHIFT (0x0000001Fu) - -#define VPIF_C2CTRL_CLIPANC (0x00004000u) -#define VPIF_C2CTRL_CLIPANC_SHIFT (0x0000000Eu) - -#define VPIF_C2CTRL_CLIPVID (0x00002000u) -#define VPIF_C2CTRL_CLIPVID_SHIFT (0x0000000Du) - -#define VPIF_C2CTRL_FIELDFRAME (0x00001000u) -#define VPIF_C2CTRL_FIELDFRAME_SHIFT (0x0000000Cu) - -#define VPIF_C2CTRL_INTRPROG (0x00000800u) -#define VPIF_C2CTRL_INTRPROG_SHIFT (0x0000000Bu) - -#define VPIF_C2CTRL_PIXEL (0x00000400u) -#define VPIF_C2CTRL_PIXEL_SHIFT (0x0000000Au) - -#define VPIF_C2CTRL_VANC (0x00000200u) -#define VPIF_C2CTRL_VANC_SHIFT (0x00000009u) - -#define VPIF_C2CTRL_HANC (0x00000100u) -#define VPIF_C2CTRL_HANC_SHIFT (0x00000008u) - -#define VPIF_C2CTRL_INTFRAME (0x000000C0u) -#define VPIF_C2CTRL_INTFRAME_SHIFT (0x00000006u) -/*-----INTFRAME Tokens-----*/ -#define VPIF_C2CTRL_INTFRAME_TOP (0x00000000u) -#define VPIF_C2CTRL_INTFRAME_BOTTOM (0x00000001u) -#define VPIF_C2CTRL_INTFRAME_TOP_BOTTOM (0x00000002u) - -#define VPIF_C2CTRL_FID (0x00000020u) -#define VPIF_C2CTRL_FID_SHIFT (0x00000005u) - -#define VPIF_C2CTRL_YCMUX (0x00000008u) -#define VPIF_C2CTRL_YCMUX_SHIFT (0x00000003u) - -#define VPIF_C2CTRL_CLKEN (0x00000002u) -#define VPIF_C2CTRL_CLKEN_SHIFT (0x00000001u) - -#define VPIF_C2CTRL_CHANEN (0x00000001u) -#define VPIF_C2CTRL_CHANEN_SHIFT (0x00000000u) - -/* C3CTRL */ - -#define VPIF_C3CTRL_CLKEDGE (0x80000000u) -#define VPIF_C3CTRL_CLKEDGE_SHIFT (0x0000001Fu) - -#define VPIF_C3CTRL_CLIPANC (0x00004000u) -#define VPIF_C3CTRL_CLIPANC_SHIFT (0x0000000Eu) - -#define VPIF_C3CTRL_CLIPVID (0x00002000u) -#define VPIF_C3CTRL_CLIPVID_SHIFT (0x0000000Du) - -#define VPIF_C3CTRL_INTRPROG (0x00000800u) -#define VPIF_C3CTRL_INTRPROG_SHIFT (0x0000000Bu) - -#define VPIF_C3CTRL_PIXEL (0x00000400u) -#define VPIF_C3CTRL_PIXEL_SHIFT (0x0000000Au) - -#define VPIF_C3CTRL_VANC (0x00000200u) -#define VPIF_C3CTRL_VANC_SHIFT (0x00000009u) - -#define VPIF_C3CTRL_HANC (0x00000100u) -#define VPIF_C3CTRL_HANC_SHIFT (0x00000008u) - -#define VPIF_C3CTRL_INTFRAME (0x000000C0u) -#define VPIF_C3CTRL_INTFRAME_SHIFT (0x00000006u) -/*-----INTFRAME Tokens-----*/ -#define VPIF_C3CTRL_INTFRAME_TOP (0x00000000u) -#define VPIF_C3CTRL_INTFRAME_BOTTOM (0x00000001u) -#define VPIF_C3CTRL_INTFRAME_TOP_BOTTOM (0x00000002u) - -#define VPIF_C3CTRL_FID (0x00000020u) -#define VPIF_C3CTRL_FID_SHIFT (0x00000005u) - -#define VPIF_C3CTRL_YCMUX (0x00000008u) -#define VPIF_C3CTRL_YCMUX_SHIFT (0x00000003u) - -#define VPIF_C3CTRL_CLKEN (0x00000002u) -#define VPIF_C3CTRL_CLKEN_SHIFT (0x00000001u) - -#define VPIF_C3CTRL_CHANEN (0x00000001u) -#define VPIF_C3CTRL_CHANEN_SHIFT (0x00000000u) - -/* ERRSTAT */ - -#define VPIF_ERRSTAT_UNDERFLOW3 (0x00000080u) -#define VPIF_ERRSTAT_UNDERFLOW3_SHIFT (0x00000007u) - -#define VPIF_ERRSTAT_UNDERFLOW2 (0x00000040u) -#define VPIF_ERRSTAT_UNDERFLOW2_SHIFT (0x00000006u) - -#define VPIF_ERRSTAT_OVERFLOW1 (0x00000020u) -#define VPIF_ERRSTAT_OVERFLOW1_SHIFT (0x00000005u) - -#define VPIF_ERRSTAT_OVERFLOW0 (0x00000010u) -#define VPIF_ERRSTAT_OVERFLOW0_SHIFT (0x00000004u) - -#define VPIF_ERRSTAT_SYNCDISTERR1 (0x00000008u) -#define VPIF_ERRSTAT_SYNCDISTERR1_SHIFT (0x00000003u) - -#define VPIF_ERRSTAT_SYNCDISTERR0 (0x00000004u) -#define VPIF_ERRSTAT_SYNCDISTERR0_SHIFT (0x00000002u) - -#define VPIF_ERRSTAT_BITERR1 (0x00000002u) -#define VPIF_ERRSTAT_BITERR1_SHIFT (0x00000001u) - -#define VPIF_ERRSTAT_BITERR0 (0x00000001u) -#define VPIF_ERRSTAT_BITERR0_SHIFT (0x00000000u) - -/* INTEN */ - -#define VPIF_INTEN_ERROR (0x00000010u) -#define VPIF_INTEN_ERROR_SHIFT (0x00000004u) - -#define VPIF_INTEN_FRAME3 (0x00000008u) -#define VPIF_INTEN_FRAME3_SHIFT (0x00000003u) - -#define VPIF_INTEN_FRAME2 (0x00000004u) -#define VPIF_INTEN_FRAME2_SHIFT (0x00000002u) - -#define VPIF_INTEN_FRAME1 (0x00000002u) -#define VPIF_INTEN_FRAME1_SHIFT (0x00000001u) - -#define VPIF_INTEN_FRAME0 (0x00000001u) -#define VPIF_INTEN_FRAME0_SHIFT (0x00000000u) - -/* INTSET */ - -#define VPIF_INTSET_ERROR (0x00000010u) -#define VPIF_INTSET_ERROR_SHIFT (0x00000004u) - -#define VPIF_INTSET_FRAME3 (0x00000008u) -#define VPIF_INTSET_FRAME3_SHIFT (0x00000003u) - -#define VPIF_INTSET_FRAME2 (0x00000004u) -#define VPIF_INTSET_FRAME2_SHIFT (0x00000002u) - -#define VPIF_INTSET_FRAME1 (0x00000002u) -#define VPIF_INTSET_FRAME1_SHIFT (0x00000001u) - -#define VPIF_INTSET_FRAME0 (0x00000001u) -#define VPIF_INTSET_FRAME0_SHIFT (0x00000000u) - -/* INTCLR */ - -#define VPIF_INTCLR_ERROR (0x00000010u) -#define VPIF_INTCLR_ERROR_SHIFT (0x00000004u) - -#define VPIF_INTCLR_FRAME3 (0x00000008u) -#define VPIF_INTCLR_FRAME3_SHIFT (0x00000003u) - -#define VPIF_INTCLR_FRAME2 (0x00000004u) -#define VPIF_INTCLR_FRAME2_SHIFT (0x00000002u) - -#define VPIF_INTCLR_FRAME1 (0x00000002u) -#define VPIF_INTCLR_FRAME1_SHIFT (0x00000001u) - -#define VPIF_INTCLR_FRAME0 (0x00000001u) -#define VPIF_INTCLR_FRAME0_SHIFT (0x00000000u) - -/* INTSTAT */ - -#define VPIF_INTSTAT_ERROR (0x00000010u) -#define VPIF_INTSTAT_ERROR_SHIFT (0x00000004u) - -#define VPIF_INTSTAT_FRAME3 (0x00000008u) -#define VPIF_INTSTAT_FRAME3_SHIFT (0x00000003u) - -#define VPIF_INTSTAT_FRAME2 (0x00000004u) -#define VPIF_INTSTAT_FRAME2_SHIFT (0x00000002u) - -#define VPIF_INTSTAT_FRAME1 (0x00000002u) -#define VPIF_INTSTAT_FRAME1_SHIFT (0x00000001u) - -#define VPIF_INTSTAT_FRAME0 (0x00000001u) -#define VPIF_INTSTAT_FRAME0_SHIFT (0x00000000u) - -/* INTSTATCLR */ - -#define VPIF_INTSTATCLR_ERROR (0x00000010u) -#define VPIF_INTSTATCLR_ERROR_SHIFT (0x00000004u) - -#define VPIF_INTSTATCLR_FRAME3 (0x00000008u) -#define VPIF_INTSTATCLR_FRAME3_SHIFT (0x00000003u) - -#define VPIF_INTSTATCLR_FRAME2 (0x00000004u) -#define VPIF_INTSTATCLR_FRAME2_SHIFT (0x00000002u) - -#define VPIF_INTSTATCLR_FRAME1 (0x00000002u) -#define VPIF_INTSTATCLR_FRAME1_SHIFT (0x00000001u) - -#define VPIF_INTSTATCLR_FRAME0 (0x00000001u) -#define VPIF_INTSTATCLR_FRAME0_SHIFT (0x00000000u) - -/* EMUCTRL */ - -#define VPIF_EMUCTRL_FREE (0x00000001u) -#define VPIF_EMUCTRL_FREE_SHIFT (0x00000000u) - -/* REQSIZE */ - -#define VPIF_REQSIZE_BYTES (0x000001FFu) -#define VPIF_REQSIZE_BYTES_SHIFT (0x00000000u) -/*-----BYTES Tokens-----*/ -#define VPIF_REQSIZE_BYTES_THIRTY_TWO (0x00000020u) -#define VPIF_REQSIZE_BYTES_SIXTY_FOUR (0x00000040u) -#define VPIF_REQSIZE_BYTES_ONE_TWENTY_EIGHT (0x00000080u) -#define VPIF_REQSIZE_BYTES_TWO_FIFTY_SIX (0x00000100u) - -/* Channel 0 */ - -/* C0TLUMA */ - -#define VPIF_C0TLUMA_C0TLUMA (0xFFFFFFFFu) -#define VPIF_C0TLUMA_C0TLUMA_SHIFT (0x00000000u) - -/* C0BLUMA */ - -#define VPIF_C0BLUMA_C0BLUMA (0xFFFFFFFFu) -#define VPIF_C0BLUMA_C0BLUMA_SHIFT (0x00000000u) - -/* C0TCHROMA */ - -#define VPIF_C0TCHROMA_C0TCHROMA (0xFFFFFFFFu) -#define VPIF_C0TCHROMA_C0TCHROMA_SHIFT (0x00000000u) - -/* C0BCHROMA */ - -#define VPIF_C0BCHROMA_C0BCHROMA (0xFFFFFFFFu) -#define VPIF_C0BCHROMA_C0BCHROMA_SHIFT (0x00000000u) - -/* C0THANC */ - -#define VPIF_C0THANC_C0THANC (0xFFFFFFFFu) -#define VPIF_C0THANC_C0THANC_SHIFT (0x00000000u) - -/* C0BHANC */ - -#define VPIF_C0BHANC_C0BHANC (0xFFFFFFFFu) -#define VPIF_C0BHANC_C0BHANC_SHIFT (0x00000000u) - -/* C0TVANC */ - -#define VPIF_C0TVANC_C0TVANC (0xFFFFFFFFu) -#define VPIF_C0TVANC_C0TVANC_SHIFT (0x00000000u) - -/* C0BVANC */ - -#define VPIF_C0BVANC_C0BVANC (0xFFFFFFFFu) -#define VPIF_C0BVANC_C0BVANC_SHIFT (0x00000000u) - -/* C0IMGOFFSET */ - -#define VPIF_C0IMGOFFSET_C0IMGOFFSET (0xFFFFFFFFu) -#define VPIF_C0IMGOFFSET_C0IMGOFFSET_SHIFT (0x00000000u) - -/* C0HANCOFFSET */ - -#define VPIF_C0HANCOFFSET_C0HANCOFFSET (0xFFFFFFFFu) -#define VPIF_C0HANCOFFSET_C0HANCOFFSET_SHIFT (0x00000000u) - -/* C0HCFG */ - -#define VPIF_C0HCFG_EAV2SAV (0x1FFF0000u) -#define VPIF_C0HCFG_EAV2SAV_SHIFT (0x00000010u) - -#define VPIF_C0HCFG_SAV2EAV (0x00001FFFu) -#define VPIF_C0HCFG_SAV2EAV_SHIFT (0x00000000u) - -/* C0VCFG0 */ - -#define VPIF_C0VCFG0_L1 (0x0FFF0000u) -#define VPIF_C0VCFG0_L1_SHIFT (0x00000010u) - -#define VPIF_C0VCFG0_L3 (0x00000FFFu) -#define VPIF_C0VCFG0_L3_SHIFT (0x00000000u) - -/* C0VCFG1 */ - -#define VPIF_C0VCFG1_L5 (0x0FFF0000u) -#define VPIF_C0VCFG1_L5_SHIFT (0x00000010u) - -#define VPIF_C0VCFG1_L7 (0x00000FFFu) -#define VPIF_C0VCFG1_L7_SHIFT (0x00000000u) - -/* C0VCFG2 */ - -#define VPIF_C0VCFG2_L9 (0x0FFF0000u) -#define VPIF_C0VCFG2_L9_SHIFT (0x00000010u) - -#define VPIF_C0VCFG2_L11 (0x00000FFFu) -#define VPIF_C0VCFG2_L11_SHIFT (0x00000000u) - -/* C0VSIZE */ - -#define VPIF_C0VSIZE_VSIZE (0x00000FFFu) -#define VPIF_C0VSIZE_VSIZE_SHIFT (0x00000000u) - -/* Channel 1 */ - -/* C1TLUMA */ - -#define VPIF_C1TLUMA_C1TLUMA (0xFFFFFFFFu) -#define VPIF_C1TLUMA_C1TLUMA_SHIFT (0x00000000u) - -/* C1BLUMA */ - -#define VPIF_C1BLUMA_C1BLUMA (0xFFFFFFFFu) -#define VPIF_C1BLUMA_C1BLUMA_SHIFT (0x00000000u) - -/* C1TCHROMA */ - -#define VPIF_C1TCHROMA_C1TCHROMA (0xFFFFFFFFu) -#define VPIF_C1TCHROMA_C1TCHROMA_SHIFT (0x00000000u) - -/* C1BCHROMA */ - -#define VPIF_C1BCHROMA_C1BCHROMA (0xFFFFFFFFu) -#define VPIF_C1BCHROMA_C1BCHROMA_SHIFT (0x00000000u) - -/* C1THANC */ - -#define VPIF_C1THANC_C1THANC (0xFFFFFFFFu) -#define VPIF_C1THANC_C1THANC_SHIFT (0x00000000u) - -/* C1BHANC */ - -#define VPIF_C1BHANC_C1BHANC (0xFFFFFFFFu) -#define VPIF_C1BHANC_C1BHANC_SHIFT (0x00000000u) - -/* C1TVANC */ - -#define VPIF_C1TVANC_C1TVANC (0xFFFFFFFFu) -#define VPIF_C1TVANC_C1TVANC_SHIFT (0x00000000u) - -/* C1BVANC */ - -#define VPIF_C1BVANC_C1BVANC (0xFFFFFFFFu) -#define VPIF_C1BVANC_C1BVANC_SHIFT (0x00000000u) - -/* C1IMGOFFSET */ - -#define VPIF_C1IMGOFFSET_C1IMGOFFSET (0xFFFFFFFFu) -#define VPIF_C1IMGOFFSET_C1IMGOFFSET_SHIFT (0x00000000u) - -/* C1HANCOFFSET */ - -#define VPIF_C1HANCOFFSET_C1HANCOFFSET (0xFFFFFFFFu) -#define VPIF_C1HANCOFFSET_C1HANCOFFSET_SHIFT (0x00000000u) - -/* C1HCFG */ - -#define VPIF_C1HCFG_EAV2SAV (0x1FFF0000u) -#define VPIF_C1HCFG_EAV2SAV_SHIFT (0x00000010u) - -#define VPIF_C1HCFG_SAV2EAV (0x00001FFFu) -#define VPIF_C1HCFG_SAV2EAV_SHIFT (0x00000000u) - -/* C1VCFG0 */ - -#define VPIF_C1VCFG0_L1 (0x0FFF0000u) -#define VPIF_C1VCFG0_L1_SHIFT (0x00000010u) - -#define VPIF_C1VCFG0_L3 (0x00000FFFu) -#define VPIF_C1VCFG0_L3_SHIFT (0x00000000u) - -/* C1VCFG1 */ - -#define VPIF_C1VCFG1_L5 (0x0FFF0000u) -#define VPIF_C1VCFG1_L5_SHIFT (0x00000010u) - -#define VPIF_C1VCFG1_L7 (0x00000FFFu) -#define VPIF_C1VCFG1_L7_SHIFT (0x00000000u) - -/* C1VCFG2 */ - -#define VPIF_C1VCFG2_L9 (0x0FFF0000u) -#define VPIF_C1VCFG2_L9_SHIFT (0x00000010u) - -#define VPIF_C1VCFG2_L11 (0x00000FFFu) -#define VPIF_C1VCFG2_L11_SHIFT (0x00000000u) - -/* C1VSIZE */ - -#define VPIF_C1VSIZE_VSIZE (0x00000FFFu) -#define VPIF_C1VSIZE_VSIZE_SHIFT (0x00000000u) - -/* Channel 2 */ - -/* C2TLUMA */ - -#define VPIF_C2TLUMA_C2TLUMA (0xFFFFFFFFu) -#define VPIF_C2TLUMA_C2TLUMA_SHIFT (0x00000000u) - -/* C2BLUMA */ - -#define VPIF_C2BLUMA_C2BLUMA (0xFFFFFFFFu) -#define VPIF_C2BLUMA_C2BLUMA_SHIFT (0x00000000u) - -/* C2TCHROMA */ - -#define VPIF_C2TCHROMA_C2TCHROMA (0xFFFFFFFFu) -#define VPIF_C2TCHROMA_C2TCHROMA_SHIFT (0x00000000u) - -/* C2BCHROMA */ - -#define VPIF_C2BCHROMA_C2BCHROMA (0xFFFFFFFFu) -#define VPIF_C2BCHROMA_C2BCHROMA_SHIFT (0x00000000u) - -/* C2THANC */ - -#define VPIF_C2THANC_C2THANC (0xFFFFFFFFu) -#define VPIF_C2THANC_C2THANC_SHIFT (0x00000000u) - -/* C2BHANC */ - -#define VPIF_C2BHANC_C2BHANC (0xFFFFFFFFu) -#define VPIF_C2BHANC_C2BHANC_SHIFT (0x00000000u) - -/* C2TVANC */ - -#define VPIF_C2TVANC_C2TVANC (0xFFFFFFFFu) -#define VPIF_C2TVANC_C2TVANC_SHIFT (0x00000000u) - -/* C2BVANC */ - -#define VPIF_C2BVANC_C2BVANC (0xFFFFFFFFu) -#define VPIF_C2BVANC_C2BVANC_SHIFT (0x00000000u) - -/* C2IMGOFFSET */ - -#define VPIF_C2IMGOFFSET_C2IMGOFFSET (0xFFFFFFFFu) -#define VPIF_C2IMGOFFSET_C2IMGOFFSET_SHIFT (0x00000000u) - -/* C2HANCOFFSET */ - -#define VPIF_C2HANCOFFSET_C2HANCOFFSET (0xFFFFFFFFu) -#define VPIF_C2HANCOFFSET_C2HANCOFFSET_SHIFT (0x00000000u) - -/* C2HCFG */ - -#define VPIF_C2HCFG_EAV2SAV (0x07FF0000u) -#define VPIF_C2HCFG_EAV2SAV_SHIFT (0x00000010u) - -#define VPIF_C2HCFG_SAV2EAV (0x000007FFu) -#define VPIF_C2HCFG_SAV2EAV_SHIFT (0x00000000u) - -/* C2VCFG0 */ - -#define VPIF_C2VCFG0_L1 (0x07FF0000u) -#define VPIF_C2VCFG0_L1_SHIFT (0x00000010u) - -#define VPIF_C2VCFG0_L3 (0x000007FFu) -#define VPIF_C2VCFG0_L3_SHIFT (0x00000000u) - -/* C2VCFG1 */ - -#define VPIF_C2VCFG1_L5 (0x07FF0000u) -#define VPIF_C2VCFG1_L5_SHIFT (0x00000010u) - -#define VPIF_C2VCFG1_L7 (0x000007FFu) -#define VPIF_C2VCFG1_L7_SHIFT (0x00000000u) - -/* C2VCFG2 */ - -#define VPIF_C2VCFG2_L9 (0x07FF0000u) -#define VPIF_C2VCFG2_L9_SHIFT (0x00000010u) - -#define VPIF_C2VCFG2_L11 (0x000007FFu) -#define VPIF_C2VCFG2_L11_SHIFT (0x00000000u) - -/* C2VSIZE */ - -#define VPIF_C2VSIZE_VSIZE (0x000007FFu) -#define VPIF_C2VSIZE_VSIZE_SHIFT (0x00000000u) - -/* C2THANCPOS */ - -#define VPIF_C2THANCPOS_VPOS (0x07FF0000u) -#define VPIF_C2THANCPOS_VPOS_SHIFT (0x00000010u) - -#define VPIF_C2THANCPOS_HPOS (0x000007FFu) -#define VPIF_C2THANCPOS_HPOS_SHIFT (0x00000000u) - -/* C2THANCSIZE */ - -#define VPIF_C2THANCSIZE_VSIZE (0x07FF0000u) -#define VPIF_C2THANCSIZE_VSIZE_SHIFT (0x00000010u) - -#define VPIF_C2THANCSIZE_HSIZE (0x000007FFu) -#define VPIF_C2THANCSIZE_HSIZE_SHIFT (0x00000000u) - -/* C2BHANCPOS */ - -#define VPIF_C2BHANCPOS_VPOS (0x07FF0000u) -#define VPIF_C2BHANCPOS_VPOS_SHIFT (0x00000010u) - -#define VPIF_C2BHANCPOS_HPOS (0x000007FFu) -#define VPIF_C2BHANCPOS_HPOS_SHIFT (0x00000000u) - -/* C2BHANCSIZE */ - -#define VPIF_C2BHANCSIZE_VSIZE (0x07FF0000u) -#define VPIF_C2BHANCSIZE_VSIZE_SHIFT (0x00000010u) - -#define VPIF_C2BHANCSIZE_HSIZE (0x000007FFu) -#define VPIF_C2BHANCSIZE_HSIZE_SHIFT (0x00000000u) - -/* C2TVANCPOS */ - -#define VPIF_C2TVANCPOS_VPOS (0x07FF0000u) -#define VPIF_C2TVANCPOS_VPOS_SHIFT (0x00000010u) - -#define VPIF_C2TVANCPOS_HPOS (0x000007FFu) -#define VPIF_C2TVANCPOS_HPOS_SHIFT (0x00000000u) - -/* C2TVANCSIZE */ - -#define VPIF_C2TVANCSIZE_VSIZE (0x07FF0000u) -#define VPIF_C2TVANCSIZE_VSIZE_SHIFT (0x00000010u) - -#define VPIF_C2TVANCSIZE_HSIZE (0x000007FFu) -#define VPIF_C2TVANCSIZE_HSIZE_SHIFT (0x00000000u) - -/* C2BVANCPOS */ - -#define VPIF_C2BVANCPOS_VPOS (0x07FF0000u) -#define VPIF_C2BVANCPOS_VPOS_SHIFT (0x00000010u) - -#define VPIF_C2BVANCPOS_HPOS (0x000007FFu) -#define VPIF_C2BVANCPOS_HPOS_SHIFT (0x00000000u) - -/* C2BVANCSIZE */ - -#define VPIF_C2BVANCSIZE_VSIZE (0x07FF0000u) -#define VPIF_C2BVANCSIZE_VSIZE_SHIFT (0x00000010u) - -#define VPIF_C2BVANCSIZE_HSIZE (0x000007FFu) -#define VPIF_C2BVANCSIZE_HSIZE_SHIFT (0x00000000u) - -/* Channel 3 */ - -/* C3TLUMA */ - -#define VPIF_C3TLUMA_C3TLUMA (0xFFFFFFFFu) -#define VPIF_C3TLUMA_C3TLUMA_SHIFT (0x00000000u) - -/* C3BLUMA */ - -#define VPIF_C3BLUMA_C3BLUMA (0xFFFFFFFFu) -#define VPIF_C3BLUMA_C3BLUMA_SHIFT (0x00000000u) - -/* C3TCHROMA */ - -#define VPIF_C3TCHROMA_C3TCHROMA (0xFFFFFFFFu) -#define VPIF_C3TCHROMA_C3TCHROMA_SHIFT (0x00000000u) - -/* C3BCHROMA */ - -#define VPIF_C3BCHROMA_C3BCHROMA (0xFFFFFFFFu) -#define VPIF_C3BCHROMA_C3BCHROMA_SHIFT (0x00000000u) - -/* C3THANC */ - -#define VPIF_C3THANC_C3THANC (0xFFFFFFFFu) -#define VPIF_C3THANC_C3THANC_SHIFT (0x00000000u) - -/* C3BHANC */ - -#define VPIF_C3BHANC_C3BHANC (0xFFFFFFFFu) -#define VPIF_C3BHANC_C3BHANC_SHIFT (0x00000000u) - -/* C3TVANC */ - -#define VPIF_C3TVANC_C3TVANC (0xFFFFFFFFu) -#define VPIF_C3TVANC_C3TVANC_SHIFT (0x00000000u) - -/* C3BVANC */ - -#define VPIF_C3BVANC_C3BVANC (0xFFFFFFFFu) -#define VPIF_C3BVANC_C3BVANC_SHIFT (0x00000000u) - -/* C3IMGOFFSET */ - -#define VPIF_C3IMGOFFSET_C3IMGOFFSET (0xFFFFFFFFu) -#define VPIF_C3IMGOFFSET_C3IMGOFFSET_SHIFT (0x00000000u) - -/* C3HANCOFFSET */ - -#define VPIF_C3HANCOFFSET_C3HANCOFFSET (0xFFFFFFFFu) -#define VPIF_C3HANCOFFSET_C3HANCOFFSET_SHIFT (0x00000000u) - -/* C3HCFG */ - -#define VPIF_C3HCFG_EAV2SAV (0x07FF0000u) -#define VPIF_C3HCFG_EAV2SAV_SHIFT (0x00000010u) - -#define VPIF_C3HCFG_SAV2EAV (0x000007FFu) -#define VPIF_C3HCFG_SAV2EAV_SHIFT (0x00000000u) - -/* C3VCFG0 */ - -#define VPIF_C3VCFG0_L1 (0x07FF0000u) -#define VPIF_C3VCFG0_L1_SHIFT (0x00000010u) - -#define VPIF_C3VCFG0_L3 (0x000007FFu) -#define VPIF_C3VCFG0_L3_SHIFT (0x00000000u) - -/* C3VCFG1 */ - -#define VPIF_C3VCFG1_L5 (0x07FF0000u) -#define VPIF_C3VCFG1_L5_SHIFT (0x00000010u) - -#define VPIF_C3VCFG1_L7 (0x000007FFu) -#define VPIF_C3VCFG1_L7_SHIFT (0x00000000u) - -/* C3VCFG2 */ - -#define VPIF_C3VCFG2_L9 (0x07FF0000u) -#define VPIF_C3VCFG2_L9_SHIFT (0x00000010u) - -#define VPIF_C3VCFG2_L11 (0x000007FFu) -#define VPIF_C3VCFG2_L11_SHIFT (0x00000000u) - -/* C3VSIZE */ - -#define VPIF_C3VSIZE_VSIZE (0x000007FFu) -#define VPIF_C3VSIZE_VSIZE_SHIFT (0x00000000u) - -/* C3THANCPOS */ - -#define VPIF_C3THANCPOS_VPOS (0x07FF0000u) -#define VPIF_C3THANCPOS_VPOS_SHIFT (0x00000010u) - -#define VPIF_C3THANCPOS_HPOS (0x000007FFu) -#define VPIF_C3THANCPOS_HPOS_SHIFT (0x00000000u) - -/* C3THANCSIZE */ - -#define VPIF_C3THANCSIZE_VSIZE (0x07FF0000u) -#define VPIF_C3THANCSIZE_VSIZE_SHIFT (0x00000010u) - -#define VPIF_C3THANCSIZE_HSIZE (0x000007FFu) -#define VPIF_C3THANCSIZE_HSIZE_SHIFT (0x00000000u) - -/* C3BHANCPOS */ - -#define VPIF_C3BHANCPOS_VPOS (0x07FF0000u) -#define VPIF_C3BHANCPOS_VPOS_SHIFT (0x00000010u) - -#define VPIF_C3BHANCPOS_HPOS (0x000007FFu) -#define VPIF_C3BHANCPOS_HPOS_SHIFT (0x00000000u) - -/* C3BHANCSIZE */ - -#define VPIF_C3BHANCSIZE_VSIZE (0x07FF0000u) -#define VPIF_C3BHANCSIZE_VSIZE_SHIFT (0x00000010u) - -#define VPIF_C3BHANCSIZE_HSIZE (0x000007FFu) -#define VPIF_C3BHANCSIZE_HSIZE_SHIFT (0x00000000u) - -/* C3TVANCPOS */ - -#define VPIF_C3TVANCPOS_VPOS (0x07FF0000u) -#define VPIF_C3TVANCPOS_VPOS_SHIFT (0x00000010u) - -#define VPIF_C3TVANCPOS_HPOS (0x000007FFu) -#define VPIF_C3TVANCPOS_HPOS_SHIFT (0x00000000u) - -/* C3TVANCSIZE */ - -#define VPIF_C3TVANCSIZE_VSIZE (0x07FF0000u) -#define VPIF_C3TVANCSIZE_VSIZE_SHIFT (0x00000010u) - -#define VPIF_C3TVANCSIZE_HSIZE (0x000007FFu) -#define VPIF_C3TVANCSIZE_HSIZE_SHIFT (0x00000000u) - -/* C3BVANCPOS */ - -#define VPIF_C3BVANCPOS_VPOS (0x07FF0000u) -#define VPIF_C3BVANCPOS_VPOS_SHIFT (0x00000010u) - -#define VPIF_C3BVANCPOS_HPOS (0x000007FFu) -#define VPIF_C3BVANCPOS_HPOS_SHIFT (0x00000000u) - -/* C3BVANCSIZE */ - -#define VPIF_C3BVANCSIZE_VSIZE (0x07FF0000u) -#define VPIF_C3BVANCSIZE_VSIZE_SHIFT (0x00000010u) - -#define VPIF_C3BVANCSIZE_HSIZE (0x000007FFu) -#define VPIF_C3BVANCSIZE_HSIZE_SHIFT (0x00000000u) - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/tiam1808/tiam1808/hw/soc_AM335x.h b/lib/tiam1808/tiam1808/hw/soc_AM335x.h deleted file mode 100644 index 44ec207e3..000000000 --- a/lib/tiam1808/tiam1808/hw/soc_AM335x.h +++ /dev/null @@ -1,200 +0,0 @@ -/** ============================================================================ - * \file soc_AM33XX.h - * - * \brief This file contains the peripheral information for AM33XX SoC - * - * ============================================================================ - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _SOC_AM33XX_H_ -#define _SOC_AM33XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief Base address of AINTC memory mapped registers */ -#define SOC_AINTC_REGS (0x48200000) - -/** @brief Base addresses of UART memory mapped registers */ -#define SOC_UART_0_REGS (0x44E09000) -#define SOC_UART_1_REGS (0x48022000) -#define SOC_UART_2_REGS (0x48024000) -#define SOC_UART_3_REGS (0x481A6000) -#define SOC_UART_4_REGS (0x481A8000) -#define SOC_UART_5_REGS (0x481AA000) - -/** @brief Base addresses of USB memory mapped registers */ -#define SOC_USB_0_BASE (0x47401400) -#define SOC_USB_1_BASE (0x47401C00) -/** @brief Base addresses of SPI memory mapped registers */ -#define SOC_SPI_0_REGS (0x48030000) -#define SOC_SPI_1_REGS (0x481A0000) - -/** @brief Base addresses of GPIO memory mapped registers */ -#define SOC_GPIO_0_REGS (0x44E07000) -#define SOC_GPIO_1_REGS (0x4804C000) -#define SOC_GPIO_2_REGS (0x481AC000) -#define SOC_GPIO_3_REGS (0x481AE000) - -/** @brief Base addresses of DMTIMER memory mapped registers */ -#define SOC_DMTIMER_0_REGS (0x44E05000) -#define SOC_DMTIMER_1_REGS (0x44E31000) -#define SOC_DMTIMER_2_REGS (0x48040000) -#define SOC_DMTIMER_3_REGS (0x48042000) -#define SOC_DMTIMER_4_REGS (0x48044000) -#define SOC_DMTIMER_5_REGS (0x48046000) -#define SOC_DMTIMER_6_REGS (0x48048000) -#define SOC_DMTIMER_7_REGS (0x4804A000) - -/** @brief Base address of MMC memory mapped registers */ -#define SOC_MMCHS_0_REGS (0x48060000) -#define SOC_MMCHS_1_REGS (0x481D8000) -#define SOC_MMCHS_2_REGS (0x47810000) - -/** @brief Base address of GPMC memory mapped registers */ -#define SOC_GPMC_0_REGS (0x50000000) - -/** @brief Base address of GPMC memory mapped registers */ -#define SOC_ELM_0_REGS (0x48080000) - -/** @brief Base address of I2C memory mapped registers */ -#define SOC_I2C_0_REGS (0x44E0B000) -#define SOC_I2C_1_REGS (0x4802A000) -#define SOC_I2C_2_REGS (0x4819C000) - -/** @brief Base address of WDT memory mapped registers */ -#define SOC_WDT_0_REGS (0x44E33000) -#define SOC_WDT_1_REGS (0x44E35000) - -/** @brief Base address of WDT memory mapped registers */ -#define SOC_CPSW_SS_REGS (0x4A100000) -#define SOC_CPSW_MDIO_REGS (0x4A101000) -#define SOC_CPSW_WR_REGS (0x4A101200) -#define SOC_CPSW_CPDMA_REGS (0x4A100800) -#define SOC_CPSW_ALE_REGS (0x4A100D00) -#define SOC_CPSW_STAT_REGS (0x4A100900) -#define SOC_CPSW_PORT_0_REGS (0x4A100100) -#define SOC_CPSW_PORT_1_REGS (0x4A100200) -#define SOC_CPSW_SLIVER_1_REGS (0x4A100D80) -#define SOC_CPSW_PORT_2_REGS (0x4A100300) -#define SOC_CPSW_SLIVER_2_REGS (0x4A100DC0) -#define SOC_CPSW_CPPI_RAM_REGS (0x4A102000) - -/** @brief Base address of McASP memory mapped registers */ -#define SOC_MCASP_1_CTRL_REGS (0x4803C000) -#define SOC_MCASP_1_FIFO_REGS (SOC_MCASP_1_CTRL_REGS + 0x1000) -#define SOC_MCASP_1_DATA_REGS (0x46400000) - -/** @brief Base address of EMIF memory mapped registers */ -#define SOC_EMIF_0_REGS (0x4C000000) - -/** @brief Base addresses of RTC memory mapped registers */ -#define SOC_RTC_0_REGS (0x44E3E000) - -/** @brief Base addresses of PRCM memory mapped registers */ -#define SOC_PRCM_REGS (0x44E00000) -#define SOC_CM_PER_REGS (SOC_PRCM_REGS + 0) -#define SOC_CM_WKUP_REGS (SOC_PRCM_REGS + 0x400) -#define SOC_CM_DPLL_REGS (SOC_PRCM_REGS + 0x500) -#define SOC_CM_MPU_REGS (SOC_PRCM_REGS + 0x600) -#define SOC_CM_DEVICE_REGS (SOC_PRCM_REGS + 0x700) -#define SOC_CM_RTC_REGS (SOC_PRCM_REGS + 0x800) -#define SOC_CM_GFX_REGS (SOC_PRCM_REGS + 0x900) -#define SOC_CM_CEFUSE_REGS (SOC_PRCM_REGS + 0xA00) -#define SOC_OCP_SOCKET_RAM_REGS (SOC_PRCM_REGS + 0xB00) -#define SOC_PRM_PER_REGS (SOC_PRCM_REGS + 0xC00) -#define SOC_PRM_WKUP_REGS (SOC_PRCM_REGS + 0xD00) -#define SOC_PRM_MPU_REGS (SOC_PRCM_REGS + 0xE00) -#define SOC_PRM_DEVICE_REGS (SOC_PRCM_REGS + 0xF00) -#define SOC_PRM_RTC_REGS (SOC_PRCM_REGS + 0x1000) -#define SOC_PRM_GFX_REGS (SOC_PRCM_REGS + 0x1100) -#define SOC_PRM_CEFUSE_REGS (SOC_PRCM_REGS + 0x1200) - -/** @brief Base address of control module memory mapped registers */ -#define SOC_CONTROL_REGS (0x44E10000) - - -/** @brief Base address of Channel controller memory mapped registers */ -#define SOC_EDMA30CC_0_REGS (0x49000000) - -/** @brief Base address of DCAN module memory mapped registers */ -#define SOC_DCAN_0_REGS (0x481CC000) -#define SOC_DCAN_1_REGS (0x481D0000) - -/******************************************************************************\ -* Parameterizable Configuration:- These are fed directly from the RTL -* parameters for the given SOC -\******************************************************************************/ -#define TPCC_MUX(n) 0xF90 + ((n) * 4) - - -#define SOC_LCDC_0_REGS 0x4830E000 - -#define SOC_ADC_TSC_0_REGS 0x44E0D000 - -/** @brief Base addresses of PWMSS memory mapped registers. */ - -#define SOC_PWMSS0_REGS (0x48300000) -#define SOC_PWMSS1_REGS (0x48302000) -#define SOC_PWMSS2_REGS (0x48304000) - -#define SOC_ECAP_REGS (0x00000100) -#define SOC_EQEP_REGS (0x00000180) -#define SOC_EPWM_REGS (0x00000200) - -#define SOC_ECAP_0_REGS (SOC_PWMSS0_REGS + SOC_ECAP_REGS) -#define SOC_ECAP_1_REGS (SOC_PWMSS1_REGS + SOC_ECAP_REGS) -#define SOC_ECAP_2_REGS (SOC_PWMSS2_REGS + SOC_ECAP_REGS) - -#define SOC_EQEP_0_REGS (SOC_PWMSS0_REGS + SOC_EQEP_REGS) -#define SOC_EQEP_1_REGS (SOC_PWMSS1_REGS + SOC_EQEP_REGS) -#define SOC_EQEP_2_REGS (SOC_PWMSS2_REGS + SOC_EQEP_REGS) - -#define SOC_EPWM_0_REGS (SOC_PWMSS0_REGS + SOC_EPWM_REGS) -#define SOC_EPWM_1_REGS (SOC_PWMSS1_REGS + SOC_EPWM_REGS) -#define SOC_EPWM_2_REGS (SOC_PWMSS2_REGS + SOC_EPWM_REGS) - - -#define SOC_EPWM_MODULE_FREQ 100 - -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_AM33XX_H_ */ diff --git a/lib/tiam1808/tiam1808/hw/soc_C6748.h b/lib/tiam1808/tiam1808/hw/soc_C6748.h deleted file mode 100644 index 010233c95..000000000 --- a/lib/tiam1808/tiam1808/hw/soc_C6748.h +++ /dev/null @@ -1,595 +0,0 @@ -/** - * \file soc_C6748.h - * - * \brief This file contains the peripheral information for C6748 SOC - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _SOC_C6748_H_ -#define _SOC_C6748_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/****************************************************************************** -** PERIPHERAL INSTANCE COUNT -******************************************************************************/ - -/** \brief Number of UPP instances */ -#define SOC_UPP_PER_CNT 1 - -/** \brief Number of UHPI instances */ -#define SOC_HPI_PER_CNT 1 - -/** \brief Number of McASP instances */ -#define SOC_MCASP_PER_CNT 1 - -/** \brief Number of TIMER instances */ -#define SOC_TMR_PER_CNT 4 - -/** \brief Number of PSC instances */ -#define SOC_PSC_PER_CNT 2 - -/** \brief Number of UART instances */ -#define SOC_UART_PER_CNT 3 - -/** \brief Number of SPI instances */ -#define SOC_SPI_PER_CNT 2 - -/** \brief Number of I2C instances */ -#define SOC_I2C_PER_CNT 2 - -/** \brief Number of PLL instances */ -#define SOC_PLLC_PER_CNT 2 - -/** \brief Number of MMCSD instances */ -#define SOC_MMCSD_PER_CNT 2 - -/** \brief Number of LCDC instances */ -#define SOC_LCDC_PER_CNT 1 - -/** \brief Number of Mcbsp instances */ -#define SOC_MCBSP_PER_CNT 2 - -/** \brief Number of EDMA3 CC instances */ -#define SOC_EDMA3CC_CNT 2 - -/** \brief Number of EDMA3 TC instances */ -#define SOC_EDMA3TC_CNT 3 - -/** \brief Number of EMIFA instances */ -#define SOC_EMIFA_PER_CNT 1 - -/** \brief Number of EMIFB instances */ -#define SOC_EMIFB_PER_CNT 1 - -/** \brief Number of EMAC instances */ -#define SOC_EMAC_PER_CNT 1 - -/** \brief Number of MDIO instances */ -#define SOC_MDIO_PER_CNT 1 - -/** \brief Number of EHRPWM instances */ -#define SOC_EHRPWM_PER_CNT 2 - -/** \brief Number of ECAP instances */ -#define SOC_ECAP_PER_CNT 3 - -/** \brief Number of CPGMAC instances */ -#define SOC_CPGMACSSR_PER_CNT 1 - -/** \brief Number of CPPI instances */ -#define SOC_CPPI_PER_CNT 1 - -/** \brief Number of USB instances */ -#define SOC_USB_PER_CNT 2 - -/** \brief Number of VPIF instances */ -#define SOC_VPIF_PER_CNT 1 - -/** \brief Number of INTC instances */ -#define SOC_INTC_PER_CNT 1 - -/** \brief Number of AINTC instances */ -#define SOC_AINTC_PER_CNT 1 - -/** \brief Number of SATA instances */ -#define SOC_SATA_PER_CNT 1 - -/** \brief Number of RTC instances */ -#define SOC_RTC_PER_CNT 1 - -/** \brief Number of GPIO instances */ -#define SOC_GPIO_PER_CNT 1 - -/** \brief Number of SYSCFG instances */ -#define SOC_SYSCFG_PER_CNT 2 -/****************************************************************************** -** PERIPHERAL INSTANCE DEFINITIONS -******************************************************************************/ - -/** \brief Peripheral Instances of UHPI instances */ -#define SOC_HPI (0) - -/** \brief Peripheral Instances of McASP instances */ -#define SOC_MCASP_0 (0) - -/** \brief Peripheral Instance of EDMA CC instances */ -#define SOC_EDMA3CC_0 (0) -#define SOC_EDMA3CC_1 (1) - -/** \brief Peripheral Instance of EDMA TC instances */ -#define SOC_EDMA3TC_0 (0) -#define SOC_EDMA3TC_1 (1) - -/** \brief Peripheral Instance of Timer 64 instances */ -#define SOC_TMR_0 (0) -#define SOC_TMR_1 (1) -#define SOC_TMR_2 (2) -#define SOC_TMR_3 (3) - -/** \brief Peripheral Instances of PSC instances */ -#define SOC_PSC_0 (0) -#define SOC_PSC_1 (1) - -/** \brief Peripheral Instances of UART instances */ -#define SOC_UART_0 (0) -#define SOC_UART_1 (1) -#define SOC_UART_2 (2) - -/** \brief Peripheral Instances of SPI instances */ -#define SOC_SPI_0 (0) -#define SOC_SPI_1 (1) - -/** \brief Peripheral Instances of I2C instances */ -#define SOC_I2C_0 (0) -#define SOC_I2C_1 (1) - -/** \brief Peripheral Instances of MMCSD instances */ -#define SOC_MMCSD_0 (0) -#define SOC_MMCSD_1 (1) - -/** \brief Peripheral Instances of LCDC instances */ -#define SOC_LCDC (0) - -/** \brief Instance number of PLL controller */ -#define SOC_PLLC_0 (0) -#define SOC_PLLC_1 (1) - -/** \brief Peripheral Instance of EMIFA instances */ -#define SOC_EMIFA (0) - -/** \brief Peripheral Instance of EMAC instances */ -#define SOC_EMAC (0) - -/** \brief Peripheral Instance of MDIO instances */ -#define SOC_MDIO (0) - -/** \brief Peripheral Instance of EHRPWM instances */ -#define SOC_EHRPWM_0 (0) -#define SOC_EHRPWM_1 (1) - -/** \brief Peripheral Instance of ECAP instances */ -#define SOC_ECAP_0 (0) -#define SOC_ECAP_1 (1) -#define SOC_ECAP_2 (2) - -/** \brief Peripheral Instance of USB instances */ -#define SOC_USB_0 (0) -#define SOC_USB_1 (1) - -/** \brief Peripheral Instance of PRU CORE instances */ -#define SOC_PRUCORE_0 (0) -#define SOC_PRUCORE_1 (1) - -/** \brief Peripheral Instance of PRUINTC instances */ -#define SOC_PRUINTC (0) - -/** \brief Peripheral Instances of VPIF instances */ -#define SOC_VPIF (0) - -/** \brief Peripheral Instance of INTC instances */ -#define SOC_INTC (0) - -/** \brief Peripheral Instance of AINTC instances */ -#define SOC_AINTC (0) - -/** \brief Peripheral Instance of RTC instances */ -#define SOC_RTC (0) - -/** \brief Peripheral Instance of GPIO instances */ -#define SOC_GPIO (0) -/** \brief GPIO pin and bank information */ -#define SOC_GPIO_NUM_PINS (144) -#define SOC_GPIO_NUM_BANKS ((SOC_GPIO_NUM_PINS + 15)/16) - -/** \brief Peripheral Instance of ECTL instances */ -#define SOC_ECTL (0) - -/** \brief Peripheral Instance of SYSCFG instances */ -#define SOC_SYSCFG (2) - -/****************************************************************************** -** PERIPHERAL BASE ADDRESS -******************************************************************************/ - -/** \brief Base address of INTC memory mapped registers */ -#define SOC_INTC_0_REGS (0x01800000) - -/** \brief Base address of PDC memory mapped registers */ -#define SOC_PWRDWN_PDC_REGS (0x01810000) - -/** \brief Base address of SYS - Security ID register */ -#define SOC_SYS_0_SECURITY_ID_REGS (0x01811000) - -/** \brief Base address of SYS - Revision ID register */ -#define SOC_SYS_0_REV_ID_REGS (0x01812000) - -/** \brief IDMA Module memory mapped address */ -#define SOC_IDMA_0_REGS (0x01820000) - -/** \brief EMC Module memory mapped address */ -#define SOC_EMC_0_REGS (0x01820000) - -/** \brief Cache Module memory mapped address */ -#define SOC_CACHE_0_REGS (0x01840000) - -/** \brief Base address of Channel controller memory mapped registers */ -#define SOC_EDMA30CC_0_REGS (0x01C00000) - -/** \brief Base address of Transfer controller memory mapped registers */ -#define SOC_EDMA30TC_0_REGS (0x01C08000) -#define SOC_EDMA30TC_1_REGS (0x01C08400) - -/** \brief Base address of PSC memory mapped registers */ -#define SOC_PSC_0_REGS (0x01C10000) - -/** \brief PLL controller instance o module address */ -#define SOC_PLLC_0_REGS (0x01C11000) - -/** \brief Base address of DEV memory mapped registers */ -#define SOC_SYSCFG_0_REGS (0x01C14000) - -/** \brief Base address of TIMER memory mapped registers */ -#define SOC_TMR_0_REGS (0x01C20000) -#define SOC_TMR_1_REGS (0x01C21000) - -/** \brief Base address of I2C memory mapped registers */ -#define SOC_I2C_0_REGS (0x01C22000) - -/** \brief Base address of RTC memory */ -#define SOC_RTC_0_REGS (0x01C23000) - -/** \brief Base address of MMCSD memory mapped registers */ -#define SOC_MMCSD_0_REGS (0x01C40000) - -/** \brief Base address of SPI memory mapped registers */ -#define SOC_SPI_0_REGS (0x01C41000) - -/** \brief Base address of UART memory mapped registers */ -#define SOC_UART_0_REGS (0x01C42000) - -/** \brief Base address of McASP memory mapped registers */ -#define SOC_MCASP_0_CTRL_REGS (0x01D00000) -#define SOC_MCASP_0_FIFO_REGS (0x01D01000) -#define SOC_MCASP_0_DATA_REGS (0x01D02000) - -/** \brief Base address of UART memory mapped registers */ -#define SOC_UART_1_REGS (0x01D0C000) -#define SOC_UART_2_REGS (0x01D0D000) - -/** \brief Base address of McBSP memory mapped registers */ -#define SOC_MCBSP_0_CTRL_REGS (0x01D10000) -#define SOC_MCBSP_0_FIFO_REGS (0x01D10800) -#define SOC_MCBSP_0_DATA_REGS (0x01F10000) - -/** \brief Base address of McASP memory mapped registers */ -#define SOC_MCBSP_1_CTRL_REGS (0x01D11000) -#define SOC_MCBSP_1_FIFO_REGS (0x01D11800) -#define SOC_MCBSP_1_DATA_REGS (0x01F11000) - -#define SOC_MPU_0_REGS (0x01E14000) -#define SOC_MPU_1_REGS (0x01E15000) - -/** \brief Base address of USB memory */ -#define SOC_USB_0_REGS (0x01E00000) -#define SOC_USB_1_REGS (0x01E25000) - -/** \brief Base address of HPI memory mapped registers */ -#define SOC_HPI_0_REGS (0x01E10000) - -/** \brief Base address of LCDC memory mapped registers */ -#define SOC_LCDC_0_REGS (0x01E13000) - -/** \brief Base address of UPP memory mapped registers */ -#define SOC_UPP_0_REGS (0x01E16000) - -/** \brief Base address of VPIF memory mapped registers */ -#define SOC_VPIF_0_REGS (0x01E17000) - -/** \brief Base address of SATA memory mapped registers */ -#define SOC_SATA_0_REGS (0x01E18000) - -/** \brief PLL controller instance 1 module address */ -#define SOC_PLLC_1_REGS (0X01E1A000) - -/** \brief Base address of MMCSD memory mapped registers */ -#define SOC_MMCSD_1_REGS (0x01E1B000) - -/** \brief Base address of EMAC memory */ -#define SOC_EMAC_DSC_CTRL_MOD_RAM (0x01E20000) -#define SOC_EMAC_DSC_CTRL_MOD_REG (0x01E22000) -#define SOC_EMAC_DSC_CONTROL_REG (0x01E23000) -#define SOC_MDIO_0_REGS (0x01E24000) - -/** \brief Base address of PRU Core Regsiters */ -#define SOC_PRUCORE_0_REGS (0x01C37000) -#define SOC_PRUCORE_1_REGS (0x01C37800) - -/** \brief Base address of PRU Interrupt Controller Registers */ -#define SOC_PRUINTC_0_REGS (0x01C34000) - -/** \brief Base address of MUSB memmory mapped Registers */ -#define SOC_USB_0_BASE (0x01E00400) - -/** \brief Base address of OTG memmory mapped Registers */ -#define SOC_USB_0_OTG_BASE (0x01E00000) - -/** \brief USB 0 Phy regsister( CFGCHIP2 register) address */ -#define SOC_USB_0_PHY_REGS (0x01C14184) - -/** \brief Base address of GPIO memory mapped registers */ -#define SOC_GPIO_0_REGS (0x01E26000) - -/** \brief Base address of PSC memory mapped registers */ -#define SOC_PSC_1_REGS (0x01E27000) - -/** \brief Base address of I2C memory mapped registers */ -#define SOC_I2C_1_REGS (0x01E28000) - -/** \brief Base address of syscfg registers */ -#define SOC_SYSCFG_1_REGS (0x01E2C000) - -/** \brief Base address of Channel controller memory mapped registers */ -#define SOC_EDMA31CC_0_REGS (0x01E30000) - -/** \brief Base address of Transfer controller memory mapped registers */ -#define SOC_EDMA31TC_0_REGS (0x01E38000) - -/** \brief Base address of EPWM memory mapped registers */ -#define SOC_EHRPWM_0_REGS (0x01F00000) -#define SOC_EHRPWM_1_REGS (0x01F02000) - -/** \brief Base address of EPWM memory mapped registers */ -#define SOC_HRPWM_0_REGS (0x01F01000) -#define SOC_HRPWM_1_REGS (0x01F03000) - -/** \brief Base address of ECAP memory mapped registers */ -#define SOC_ECAP_0_REGS (0x01F06000) -#define SOC_ECAP_1_REGS (0x01F07000) -#define SOC_ECAP_2_REGS (0x01F08000) - -/** \brief Base address of TIMER memory mapped registers */ -#define SOC_TMR_2_REGS (0x01F0C000) -#define SOC_TMR_3_REGS (0x01F0D000) - -/** \brief Base address of SPI memory mapped registers */ -#define SOC_SPI_1_REGS (0x01F0E000) - -/** \brief Base address of EMIFA memory mapped registers */ -#define SOC_EMIFA_0_REGS (0x68000000) - -/** \brief Base address of EMIFA_CS0 memory */ -#define SOC_EMIFA_CS0_ADDR (0x40000000) - -/** \brief Base address of EMIFA_CS2 memory */ -#define SOC_EMIFA_CS2_ADDR (0x60000000) - -/** \brief Base address of EMIFA_CS3 memory */ -#define SOC_EMIFA_CS3_ADDR (0x62000000) - -/** \brief Base address of EMIFA_CS4 memory */ -#define SOC_EMIFA_CS4_ADDR (0x64000000) - -/** \brief Base address of EMIFA_CS5 memory */ -#define SOC_EMIFA_CS5_ADDR (0x66000000) - -/** \brief Base address of DDR memory mapped registers */ -#define SOC_DDR2_0_CTRL_REGS (0xB0000000) -#define SOC_DDR2_0_DATA_REGS (0xC0000000) - -/** \brief Base address of AINTC memory mapped registers */ -#define SOC_AINTC_0_REGS (0xFFFEE000) - -/** \brief Base address of UMC Memory protection registers */ -#define SOC_MEMPROT_L2_REGS (0x00800000) - -/** \brief Base address of PMC memory Protection registers */ -#define SOC_MEMPROT_L1P_REGS (0x00E00000) - -/** \brief Base address of DMC memory protection registers */ -#define SOC_MEMPROT_L1D_REGS (0x00F00000) - -/****************************************************************************** -** EDMA RELATED DEFINITIONS -******************************************************************************/ - -/* Parameterizable Configuration: These are fed directly from the RTL - * parameters for the given SOC */ - -#define SOC_EDMA3_NUM_DMACH 32 -#define SOC_EDMA3_NUM_QDMACH 8 -#define SOC_EDMA3_NUM_PARAMSETS 128 -#define SOC_EDMA3_NUM_EVQUE 2 -#define SOC_EDMA3_CHMAPEXIST 0 -#define SOC_EDMA3_NUM_REGIONS 4 -#define SOC_EDMA3_MEMPROTECT 0 - -/****************************************************************************** -** CHANNEL INSTANCE COUNT -******************************************************************************/ -#define SOC_EDMA3_CHA_CNT (SOC_EDMA3_NUM_DMACH + \ - SOC_EDMA3_NUM_QDMACH) - - -/* QDMA channels */ -#define SOC_EDMA3_QCHA_BASE SOC_EDMA3_NUM_DMACH /* QDMA Channel Base */ -#define SOC_EDMA3_QCHA_0 (SOC_EDMA3_QCHA_BASE + 0) /* QDMA Channel 0 */ -#define SOC_EDMA3_QCHA_1 (SOC_EDMA3_QCHA_BASE + 1) /* QDMA Channel 1 */ -#define SOC_EDMA3_QCHA_2 (SOC_EDMA3_QCHA_BASE + 2) /* QDMA Channel 2 */ -#define SOC_EDMA3_QCHA_3 (SOC_EDMA3_QCHA_BASE + 3) /* QDMA Channel 3 */ -#define SOC_EDMA3_QCHA_4 (SOC_EDMA3_QCHA_BASE + 4) /* QDMA Channel 4 */ -#define SOC_EDMA3_QCHA_5 (SOC_EDMA3_QCHA_BASE + 5) /* QDMA Channel 5 */ -#define SOC_EDMA3_QCHA_6 (SOC_EDMA3_QCHA_BASE + 6) /* QDMA Channel 6 */ -#define SOC_EDMA3_QCHA_7 (SOC_EDMA3_QCHA_BASE + 7) /* QDMA Channel 7 */ - - -/* Enumerations for EDMA Controlleres */ -#define SOC_EDMACC_ANY -1 /* Any instance of EDMACC module*/ -#define SOC_EDMACC_0 0 /* EDMACC Instance 0 */ - - -/* Enumerations for EDMA Event Queues */ -#define SOC_EDMA3_QUE_0 0 /* Queue 0 */ -#define SOC_EDMA3_QUE_1 1 /* Queue 1 */ - -/* Enumerations for EDMA Transfer Controllers - * - * There are 2 Transfer Controllers. Typically a one to one mapping exists - * between Event Queues and Transfer Controllers. */ -#define SOC_EDMATC_ANY -1 /* Any instance of EDMATC */ -#define SOC_EDMATC_0 0 /* EDMATC Instance 0 */ -#define SOC_EDMATC_1 1 /* EDMATC Instance 1 */ - - -#define SOC_EDMA3_REGION_GLOBAL (-1) -#define SOC_EDMA3_REGION_0 0 -#define SOC_EDMA3_REGION_1 1 -#define SOC_EDMA3_REGION_2 2 -#define SOC_EDMA3_REGION_3 3 - - -/****************************************************************************** -** DAT RELATED DEFINITIONS -******************************************************************************/ - -/* Parameterizable Configuration:- These are fed directly from the RTL - * parameters for the given SOC */ - - /****************************************************************************** -** CHANNEL INSTANCE COUNT -******************************************************************************/ -/** \brief Number of Generic Channel instances */ - - -/** \brief Enumerations for EDMA channels - * - * There are 8 QDMA channels - - */ - -#define SOC_DAT_QCHA_0 0 /**< QDMA Channel 0 */ -#define SOC_DAT_QCHA_1 1 /**< QDMA Channel 1 */ -#define SOC_DAT_QCHA_2 2 /**< QDMA Channel 2 */ -#define SOC_DAT_QCHA_3 3 /**< QDMA Channel 3 */ -#define SOC_DAT_QCHA_4 4 /**< QDMA Channel 4 */ -#define SOC_DAT_QCHA_5 5 /**< QDMA Channel 5 */ -#define SOC_DAT_QCHA_6 6 /**< QDMA Channel 6 */ -#define SOC_DAT_QCHA_7 7 /**< QDMA Channel 7 */ - -/** \brief Enumerations for EDMA Event Queues -* -* There are two Event Queues. Q0 is the highest priority and Q1 is the least -* priority -* -*/ -#define SOC_DAT_PRI_DEFAULT 0 /* Queue 0 is default */ -#define SOC_DAT_PRI_0 0 /* Queue 0 */ -#define SOC_DAT_PRI_1 1 /* Queue 1 */ - -/** \brief Enumeration for EDMA Regions -* -* -*/ - -#define SOC_DAT_REGION_GLOBAL (-1) /* Global Region */ -#define SOC_DAT_REGION_0 0 /* EDMA Region 0 */ -#define SOC_DAT_REGION_1 1 /* EDMA Region 1 */ -#define SOC_DAT_REGION_2 2 /* EDMA Region 2 */ -#define SOC_DAT_REGION_3 3 /* EDMA Region 3 */ - -/** \brief Enumeration for peripheral frequencies -* -* -*/ - -#define SOC_SYSCLK_1_FREQ (300000000) -#define SOC_SYSCLK_2_FREQ (SOC_SYSCLK_1_FREQ/2) -#define SOC_SYSCLK_3_FREQ (SOC_SYSCLK_1_FREQ/3) -#define SOC_SYSCLK_4_FREQ (SOC_SYSCLK_1_FREQ/4) - -#define SOC_ASYNC_2_FREQ (24000000) - -/** I2C */ -#define SOC_I2C_0_MODULE_FREQ (SOC_ASYNC_2_FREQ) -#define SOC_I2C_1_MODULE_FREQ (SOC_SYSCLK_4_FREQ) - -/** MCBSP */ -#define SOC_MCBSP_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ) -#define SOC_MCBSP_1_MODULE_FREQ (SOC_SYSCLK_2_FREQ) - -/** LCDC */ -#define SOC_LCDC_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ) - -/** SPI */ -#define SOC_SPI_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ) -#define SOC_SPI_1_MODULE_FREQ (SOC_SYSCLK_2_FREQ) - -/** UART */ -#define SOC_UART_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ) -#define SOC_UART_1_MODULE_FREQ (SOC_SYSCLK_2_FREQ) -#define SOC_UART_2_MODULE_FREQ (SOC_SYSCLK_2_FREQ) - -/** EHRPWM */ -#define SOC_EHRPWM_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ) -#define SOC_EHRPWM_1_MODULE_FREQ (SOC_SYSCLK_2_FREQ) - -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_C6748_H_ */ diff --git a/lib/tiam1808/tiam1808/hw/soc_C6A811x.h b/lib/tiam1808/tiam1808/hw/soc_C6A811x.h deleted file mode 100644 index 521d89546..000000000 --- a/lib/tiam1808/tiam1808/hw/soc_C6A811x.h +++ /dev/null @@ -1,246 +0,0 @@ -/** - * \file soc_C6A811x.h - * - * \brief This file contains the peripheral information for C6A811x SoC - * - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _SOC_C6A811X_H_ -#define _SOC_C6A811X_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief Base address of AINTC memory mapped registers */ -#define SOC_AINTC_REGS (0x48200000) - -/** @brief Base addresses of UART memory mapped registers */ -#define SOC_UART_0_REGS (0x48020000) -#define SOC_UART_1_REGS (0x48022000) -#define SOC_UART_2_REGS (0x48024000) -#define SOC_UART_3_REGS (0x481A6000) -#define SOC_UART_4_REGS (0x481A8000) -#define SOC_UART_5_REGS (0x481AA000) -#define SOC_UART_6_REGS (0x48440000) -#define SOC_UART_7_REGS (0x48442000) - -/** @brief Base addresses of USB memory mapped registers */ -#define SOC_USB_0_BASE (0x47401400) -#define SOC_USB_1_BASE (0x47401C00) - -/** @brief Base addresses of SPI memory mapped registers */ -#define SOC_SPI_0_REGS (0x48030000) -#define SOC_SPI_1_REGS (0x481A0000) -#define SOC_SPI_2_REGS (0x481A2000) -#define SOC_SPI_3_REGS (0x481A4000) - -/** @brief Base addresses of GPIO memory mapped registers */ -#define SOC_GPIO_0_REGS (0x48032000) -#define SOC_GPIO_1_REGS (0x4804C000) -#define SOC_GPIO_2_REGS (0x481AC000) -#define SOC_GPIO_3_REGS (0x481AE000) -#define SOC_GPIO_4_REGS (0x48420000) -#define SOC_GPIO_5_REGS (0x48422000) - -/** @brief Base addresses of DMTIMER memory mapped registers */ -#define SOC_DMTIMER_0_REGS (0x4802C000) -#define SOC_DMTIMER_1_REGS (0x4802E000) -#define SOC_DMTIMER_2_REGS (0x48040000) -#define SOC_DMTIMER_3_REGS (0x48042000) -#define SOC_DMTIMER_4_REGS (0x48044000) -#define SOC_DMTIMER_5_REGS (0x48046000) -#define SOC_DMTIMER_6_REGS (0x48048000) -#define SOC_DMTIMER_7_REGS (0x4804A000) -#define SOC_DMTIMER_8_REGS (0x481C1000) - -/** @brief Base address of MMC memory mapped registers */ -#define SOC_MMCHS_0_REGS (0x48060000) -#define SOC_MMCHS_1_REGS (0x481D8000) -#define SOC_MMCHS_2_REGS (0x47810000) - -/** @brief Base address of GPMC memory mapped registers */ -#define SOC_GPMC_0_REGS (0x50000000) - -/** @brief Base address of GPMC memory mapped registers */ -#define SOC_ELM_0_REGS (0x48080000) - -/** @brief Base address of I2C memory mapped registers */ -#define SOC_I2C_0_REGS (0x48028000) -#define SOC_I2C_1_REGS (0x4802A000) -#define SOC_I2C_2_REGS (0x4819C000) -#define SOC_I2C_3_REGS (0x4819E000) - -/** @brief Base address of WDT memory mapped registers */ -#define SOC_WDT_0_REGS (0x481C7000) - -/** @brief Base address of EMAC SW memory mapped registers */ -#define SOC_CPSW_SS_REGS (0x4A100000) -#define SOC_CPSW_PORT_0_REGS (0x4A100100) -#define SOC_CPSW_PORT_1_REGS (0x4A100200) -#define SOC_CPSW_PORT_2_REGS (0x4A100300) -#define SOC_CPSW_CPDMA_REGS (0x4A100800) -#define SOC_CPSW_STAT_REGS (0x4A100900) -#define SOC_CPSW_CPTS_REGS (0x4A100C00) -#define SOC_CPSW_ALE_REGS (0x4A100D00) -#define SOC_CPSW_SLIVER_1_REGS (0x4A100D80) -#define SOC_CPSW_SLIVER_2_REGS (0x4A100DC0) -#define SOC_CPSW_MDIO_REGS (0x4A101000) -#define SOC_CPSW_WR_REGS (0x4A101200) -#define SOC_CPSW_CPPI_RAM_REGS (0x4A102000) - -/** @brief Base address of McASP memory mapped registers */ -#define SOC_MCASP_0_CTRL_REGS (0x48038000) -#define SOC_MCASP_0_FIFO_REGS (SOC_MCASP_0_CTRL_REGS + 0x1000) -#define SOC_MCASP_0_DATA_REGS (0x46000000) -#define SOC_MCASP_1_CTRL_REGS (0x4803C000) -#define SOC_MCASP_1_FIFO_REGS (SOC_MCASP_1_CTRL_REGS + 0x1000) -#define SOC_MCASP_1_DATA_REGS (0x46400000) -#define SOC_MCASP_2_CTRL_REGS (0x48050000) -#define SOC_MCASP_2_FIFO_REGS (SOC_MCASP_2_CTRL_REGS + 0x1000) -#define SOC_MCASP_2_DATA_REGS (0x46800000) -#define SOC_MCASP_3_CTRL_REGS (0x4A1A2000) -#define SOC_MCASP_3_FIFO_REGS (SOC_MCASP_3_CTRL_REGS + 0x1000) -#define SOC_MCASP_3_DATA_REGS (0x4A1A5000) -#define SOC_MCASP_4_CTRL_REGS (0x4A1A8000) -#define SOC_MCASP_4_FIFO_REGS (SOC_MCASP_4_CTRL_REGS + 0x1000) -#define SOC_MCASP_4_DATA_REGS (0x4A1AB000) -#define SOC_MCASP_5_CTRL_REGS (0x4A1AE000) -#define SOC_MCASP_5_FIFO_REGS (SOC_MCASP_5_CTRL_REGS + 0x1000) -#define SOC_MCASP_5_DATA_REGS (0x4A1B1000) - -/** @brief Base address of McBSP memory mapped registers */ -#define SOC_MCBSP_0_CTRL_REGS (0x47000000) - -/** @brief Base address of EMIF memory mapped registers */ -#define SOC_EMIF_0_REGS (0x4C000000) -#define SOC_EMIF_1_REGS (0x4D000000) - -/** @brief Base addresses of RTC memory mapped registers */ -#define SOC_RTC_0_REGS (0x44E3E000) - -/** @brief Base addresses of PRCM memory mapped registers */ -#define SOC_PRCM_REGS (0x48180000) -#define SOC_PRM_DEVICE_REGS (SOC_PRCM_REGS + 0x0) -#define SOC_CM_DEVICE_REGS (SOC_PRCM_REGS + 0x100) -#define SOC_OCP_SOCKET_PRM_REGS (SOC_PRCM_REGS + 0x200) -#define SOC_CM_DPLL_REGS (SOC_PRCM_REGS + 0x300) -#define SOC_CM_ACTIVE_REGS (SOC_PRCM_REGS + 0x400) -#define SOC_CM_DEFAULT_REGS (SOC_PRCM_REGS + 0x500) -/* note: removed HDICP, ISP */ -#define SOC_CM_DSS_REGS (SOC_PRCM_REGS + 0x800) -#define SOC_CM_SGX_REGS (SOC_PRCM_REGS + 0x900) -#define SOC_PRM_ACTIVE_REGS (SOC_PRCM_REGS + 0xA00) -#define SOC_PRM_DEFAULT_REGS (SOC_PRCM_REGS + 0xB00) -/* note: removed HDICP, ISP */ -#define SOC_PRM_DSS_REGS (SOC_PRCM_REGS + 0xE00) -#define SOC_PRM_SGX_REGS (SOC_PRCM_REGS + 0xF00) -#define SOC_CM_ALWON_REGS (SOC_PRCM_REGS + 0x1400) -#define SOC_PRM_ALWON_REGS (SOC_PRCM_REGS + 0x1800) - -/** @brief Base addresses of PLLSS memory mapped registers */ -#define SOC_PLLSS_REGS (0x481C5000) - -/** @brief Base address of control module memory mapped registers */ -#define SOC_CONTROL_REGS (0x48140000) - -/** @brief Base address of Channel controller memory mapped registers */ -#define SOC_EDMA30CC_0_REGS (0x49000000) -#define SOC_EDMA30TC_0_REGS (0x49800000) -#define SOC_EDMA30TC_1_REGS (0x49900000) -#define SOC_EDMA30TC_2_REGS (0x49A00000) -#define SOC_EDMA30TC_3_REGS (0x49B00000) - - -/** @brief Base address of DCAN module memory mapped registers */ -#define SOC_DCAN_0_REGS (0x481CC000) -#define SOC_DCAN_1_REGS (0x481D0000) - -/** @brief Base address of PCIe module memory mapped port and registers */ -#define SOC_PCIE_0_PORT (0x20000000) -#define SOC_PCIE_0_REGS (0x51000000) - -/******************************************************************************\ -* Parameterizable Configuration:- These are fed directly from the RTL -* parameters for the given SOC -\******************************************************************************/ -#define TPCC_MUX(n) 0xF90 + ((n) * 4) - -#define SOC_ADC_TSC_0_REGS (0x48450000) - -/** @brief Base addresses of PWMSS memory mapped registers. */ - -#define SOC_PWMSS0_REGS (0x48302000) -#define SOC_PWMSS1_REGS (0x48304000) -#define SOC_PWMSS2_REGS (0x48306000) - -#define SOC_ECAP_REGS (0x00000100) -#define SOC_EQEP_REGS (0x00000180) -#define SOC_EPWM_REGS (0x00000200) - -#define SOC_ECAP_0_REGS (SOC_PWMSS0_REGS + SOC_ECAP_REGS) -#define SOC_ECAP_1_REGS (SOC_PWMSS1_REGS + SOC_ECAP_REGS) -#define SOC_ECAP_2_REGS (SOC_PWMSS2_REGS + SOC_ECAP_REGS) - -#define SOC_EQEP_0_REGS (SOC_PWMSS0_REGS + SOC_EQEP_REGS) -#define SOC_EQEP_1_REGS (SOC_PWMSS1_REGS + SOC_EQEP_REGS) -#define SOC_EQEP_2_REGS (SOC_PWMSS2_REGS + SOC_EQEP_REGS) - -#define SOC_EPWM_0_REGS (SOC_PWMSS0_REGS + SOC_EPWM_REGS) -#define SOC_EPWM_1_REGS (SOC_PWMSS1_REGS + SOC_EPWM_REGS) -#define SOC_EPWM_2_REGS (SOC_PWMSS2_REGS + SOC_EPWM_REGS) - -#define SOC_PWM0_SUB_SYS_CLOCK_CONFIG_REGS 0x48302008 -#define SOC_PWM0_SUB_SYS_CLOCK_STATUS_REGS 0x4830200C -#define SOC_PWM0_SUB_SYS_SYS_CONFIG_REGS 0x48302004 - -#define SOC_PWM1_SUB_SYS_CLOCK_CONFIG_REGS 0x48304008 -#define SOC_PWM1_SUB_SYS_CLOCK_STATUS_REGS 0x4830400C -#define SOC_PWM1_SUB_SYS_SYS_CONFIG_REGS 0x48304004 - -#define SOC_PWM2_SUB_SYS_CLOCK_CONFIG_REGS 0x48306008 -#define SOC_PWM2_SUB_SYS_CLOCK_STATUS_REGS 0x4830600C -#define SOC_PWM2_SUB_SYS_SYS_CONFIG_REGS 0x48306004 - -#define SOC_EPWM_MODULE_FREQ 100 - -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_C6A811X_H_ */ diff --git a/lib/tiam1808/tiam1808/hw/soc_OMAPL138.h b/lib/tiam1808/tiam1808/hw/soc_OMAPL138.h deleted file mode 100644 index a12362056..000000000 --- a/lib/tiam1808/tiam1808/hw/soc_OMAPL138.h +++ /dev/null @@ -1,595 +0,0 @@ -/** - * \file soc_OMAPL138.h - * - * \brief This file contains the peripheral information for OMAPL138 SOC - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _SOC_OMAPL138_H_ -#define _SOC_OMAPL138_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/****************************************************************************** -** PERIPHERAL INSTANCE COUNT -******************************************************************************/ - -/** \brief Number of UPP instances */ -#define SOC_UPP_PER_CNT 1 - -/** \brief Number of UHPI instances */ -#define SOC_HPI_PER_CNT 1 - -/** \brief Number of McASP instances */ -#define SOC_MCASP_PER_CNT 1 - -/** \brief Number of TIMER instances */ -#define SOC_TMR_PER_CNT 4 - -/** \brief Number of PSC instances */ -#define SOC_PSC_PER_CNT 2 - -/** \brief Number of UART instances */ -#define SOC_UART_PER_CNT 3 - -/** \brief Number of SPI instances */ -#define SOC_SPI_PER_CNT 2 - -/** \brief Number of I2C instances */ -#define SOC_I2C_PER_CNT 2 - -/** \brief Number of PLL instances */ -#define SOC_PLLC_PER_CNT 2 - -/** \brief Number of MMCSD instances */ -#define SOC_MMCSD_PER_CNT 2 - -/** \brief Number of LCDC instances */ -#define SOC_LCDC_PER_CNT 1 - -/** \brief Number of Mcbsp instances */ -#define SOC_MCBSP_PER_CNT 2 - -/** \brief Number of EDMA3 CC instances */ -#define SOC_EDMA3CC_CNT 2 - -/** \brief Number of EDMA3 TC instances */ -#define SOC_EDMA3TC_CNT 3 - -/** \brief Number of EMIFA instances */ -#define SOC_EMIFA_PER_CNT 1 - -/** \brief Number of EMIFB instances */ -#define SOC_EMIFB_PER_CNT 1 - -/** \brief Number of EMAC instances */ -#define SOC_EMAC_PER_CNT 1 - -/** \brief Number of MDIO instances */ -#define SOC_MDIO_PER_CNT 1 - -/** \brief Number of EHRPWM instances */ -#define SOC_EHRPWM_PER_CNT 2 - -/** \brief Number of ECAP instances */ -#define SOC_ECAP_PER_CNT 3 - -/** \brief Number of CPGMAC instances */ -#define SOC_CPGMACSSR_PER_CNT 1 - -/** \brief Number of CPPI instances */ -#define SOC_CPPI_PER_CNT 1 - -/** \brief Number of USB instances */ -#define SOC_USB_PER_CNT 2 - -/** \brief Number of VPIF instances */ -#define SOC_VPIF_PER_CNT 1 - -/** \brief Number of INTC instances */ -#define SOC_INTC_PER_CNT 1 - -/** \brief Number of AINTC instances */ -#define SOC_AINTC_PER_CNT 1 - -/** \brief Number of SATA instances */ -#define SOC_SATA_PER_CNT 1 - -/** \brief Number of RTC instances */ -#define SOC_RTC_PER_CNT 1 - -/** \brief Number of GPIO instances */ -#define SOC_GPIO_PER_CNT 1 - -/** \brief Number of SYSCFG instances */ -#define SOC_SYSCFG_PER_CNT 2 -/****************************************************************************** -** PERIPHERAL INSTANCE DEFINITIONS -******************************************************************************/ - -/** \brief Peripheral Instances of UHPI instances */ -#define SOC_HPI (0) - -/** \brief Peripheral Instances of McASP instances */ -#define SOC_MCASP_0 (0) - -/** \brief Peripheral Instance of EDMA CC instances */ -#define SOC_EDMA3CC_0 (0) -#define SOC_EDMA3CC_1 (1) - -/** \brief Peripheral Instance of EDMA TC instances */ -#define SOC_EDMA3TC_0 (0) -#define SOC_EDMA3TC_1 (1) - -/** \brief Peripheral Instance of Timer 64 instances */ -#define SOC_TMR_0 (0) -#define SOC_TMR_1 (1) -#define SOC_TMR_2 (2) -#define SOC_TMR_3 (3) - -/** \brief Peripheral Instances of PSC instances */ -#define SOC_PSC_0 (0) -#define SOC_PSC_1 (1) - -/** \brief Peripheral Instances of UART instances */ -#define SOC_UART_0 (0) -#define SOC_UART_1 (1) -#define SOC_UART_2 (2) - -/** \brief Peripheral Instances of SPI instances */ -#define SOC_SPI_0 (0) -#define SOC_SPI_1 (1) - -/** \brief Peripheral Instances of I2C instances */ -#define SOC_I2C_0 (0) -#define SOC_I2C_1 (1) - -/** \brief Peripheral Instances of MMCSD instances */ -#define SOC_MMCSD_0 (0) -#define SOC_MMCSD_1 (1) - -/** \brief Peripheral Instances of LCDC instances */ -#define SOC_LCDC (0) - -/** \brief Instance number of PLL controller */ -#define SOC_PLLC_0 (0) -#define SOC_PLLC_1 (1) - -/** \brief Peripheral Instance of EMIFA instances */ -#define SOC_EMIFA (0) - -/** \brief Peripheral Instance of EMAC instances */ -#define SOC_EMAC (0) - -/** \brief Peripheral Instance of MDIO instances */ -#define SOC_MDIO (0) - -/** \brief Peripheral Instance of EHRPWM instances */ -#define SOC_EHRPWM_0 (0) -#define SOC_EHRPWM_1 (1) - -/** \brief Peripheral Instance of ECAP instances */ -#define SOC_ECAP_0 (0) -#define SOC_ECAP_1 (1) -#define SOC_ECAP_2 (2) - -/** \brief Peripheral Instance of USB instances */ -#define SOC_USB_0 (0) -#define SOC_USB_1 (1) - -/** \brief Peripheral Instance of PRU CORE instances */ -#define SOC_PRUCORE_0 (0) -#define SOC_PRUCORE_1 (1) - -/** \brief Peripheral Instance of PRUINTC instances */ -#define SOC_PRUINTC (0) - -/** \brief Peripheral Instances of VPIF instances */ -#define SOC_VPIF (0) - -/** \brief Peripheral Instance of INTC instances */ -#define SOC_INTC (0) - -/** \brief Peripheral Instance of AINTC instances */ -#define SOC_AINTC (0) - -/** \brief Peripheral Instance of RTC instances */ -#define SOC_RTC (0) - -/** \brief Peripheral Instance of GPIO instances */ -#define SOC_GPIO (0) -/** \brief GPIO pin and bank information */ -#define SOC_GPIO_NUM_PINS (144) -#define SOC_GPIO_NUM_BANKS ((SOC_GPIO_NUM_PINS + 15)/16) - -/** \brief Peripheral Instance of ECTL instances */ -#define SOC_ECTL (0) - -/** \brief Peripheral Instance of SYSCFG instances */ -#define SOC_SYSCFG (2) - -/****************************************************************************** -** PERIPHERAL BASE ADDRESS -******************************************************************************/ - -/** \brief Base address of INTC memory mapped registers */ -#define SOC_INTC_0_REGS (0x01800000) - -/** \brief Base address of PDC memory mapped registers */ -#define SOC_PWRDWN_PDC_REGS (0x01810000) - -/** \brief Base address of SYS - Security ID register */ -#define SOC_SYS_0_SECURITY_ID_REGS (0x01811000) - -/** \brief Base address of SYS - Revision ID register */ -#define SOC_SYS_0_REV_ID_REGS (0x01812000) - -/** \brief IDMA Module memory mapped address */ -#define SOC_IDMA_0_REGS (0x01820000) - -/** \brief EMC Module memory mapped address */ -#define SOC_EMC_0_REGS (0x01820000) - -/** \brief Cache Module memory mapped address */ -#define SOC_CACHE_0_REGS (0x01840000) - -/** \brief Base address of Channel controller memory mapped registers */ -#define SOC_EDMA30CC_0_REGS (0x01C00000) - -/** \brief Base address of Transfer controller memory mapped registers */ -#define SOC_EDMA30TC_0_REGS (0x01C08000) -#define SOC_EDMA30TC_1_REGS (0x01C08400) - -/** \brief Base address of PSC memory mapped registers */ -#define SOC_PSC_0_REGS (0x01C10000) - -/** \brief PLL controller instance o module address */ -#define SOC_PLLC_0_REGS (0x01C11000) - -/** \brief Base address of DEV memory mapped registers */ -#define SOC_SYSCFG_0_REGS (0x01C14000) - -/** \brief Base address of TIMER memory mapped registers */ -#define SOC_TMR_0_REGS (0x01C20000) -#define SOC_TMR_1_REGS (0x01C21000) - -/** \brief Base address of I2C memory mapped registers */ -#define SOC_I2C_0_REGS (0x01C22000) - -/** \brief Base address of RTC memory */ -#define SOC_RTC_0_REGS (0x01C23000) - -/** \brief Base address of MMCSD memory mapped registers */ -#define SOC_MMCSD_0_REGS (0x01C40000) - -/** \brief Base address of SPI memory mapped registers */ -#define SOC_SPI_0_REGS (0x01C41000) - -/** \brief Base address of UART memory mapped registers */ -#define SOC_UART_0_REGS (0x01C42000) - -/** \brief Base address of McASP memory mapped registers */ -#define SOC_MCASP_0_CTRL_REGS (0x01D00000) -#define SOC_MCASP_0_FIFO_REGS (0x01D01000) -#define SOC_MCASP_0_DATA_REGS (0x01D02000) - -/** \brief Base address of UART memory mapped registers */ -#define SOC_UART_1_REGS (0x01D0C000) -#define SOC_UART_2_REGS (0x01D0D000) - -/** \brief Base address of McBSP memory mapped registers */ -#define SOC_MCBSP_0_CTRL_REGS (0x01D10000) -#define SOC_MCBSP_0_FIFO_REGS (0x01D10800) -#define SOC_MCBSP_0_DATA_REGS (0x01F10000) - -/** \brief Base address of McASP memory mapped registers */ -#define SOC_MCBSP_1_CTRL_REGS (0x01D11000) -#define SOC_MCBSP_1_FIFO_REGS (0x01D11800) -#define SOC_MCBSP_1_DATA_REGS (0x01F11000) - -#define SOC_MPU_0_REGS (0x01E14000) -#define SOC_MPU_1_REGS (0x01E15000) - -/** \brief Base address of USB memory */ -#define SOC_USB_0_REGS (0x01E00000) -#define SOC_USB_1_REGS (0x01E25000) - -/** \brief Base address of HPI memory mapped registers */ -#define SOC_HPI_0_REGS (0x01E10000) - -/** \brief Base address of LCDC memory mapped registers */ -#define SOC_LCDC_0_REGS (0x01E13000) - -/** \brief Base address of UPP memory mapped registers */ -#define SOC_UPP_0_REGS (0x01E16000) - -/** \brief Base address of VPIF memory mapped registers */ -#define SOC_VPIF_0_REGS (0x01E17000) - -/** \brief Base address of SATA memory mapped registers */ -#define SOC_SATA_0_REGS (0x01E18000) - -/** \brief PLL controller instance 1 module address */ -#define SOC_PLLC_1_REGS (0X01E1A000) - -/** \brief Base address of MMCSD memory mapped registers */ -#define SOC_MMCSD_1_REGS (0x01E1B000) - -/** \brief Base address of EMAC memory */ -#define SOC_EMAC_DSC_CTRL_MOD_RAM (0x01E20000) -#define SOC_EMAC_DSC_CTRL_MOD_REG (0x01E22000) -#define SOC_EMAC_DSC_CONTROL_REG (0x01E23000) -#define SOC_MDIO_0_REGS (0x01E24000) - -/** \brief Base address of PRU Core Regsiters */ -#define SOC_PRUCORE_0_REGS (0x01C37000) -#define SOC_PRUCORE_1_REGS (0x01C37800) - -/** \brief Base address of PRU Interrupt Controller Registers */ -#define SOC_PRUINTC_0_REGS (0x01C34000) - -/** \brief Base address of MUSB memmory mapped Registers */ -#define SOC_USB_0_BASE (0x01E00400) - -/** \brief Base address of OTG memmory mapped Registers */ -#define SOC_USB_0_OTG_BASE (0x01E00000) - -/** \brief USB 0 Phy regsister( CFGCHIP2 register) address */ -#define SOC_USB_0_PHY_REGS (0x01C14184) - -/** \brief Base address of GPIO memory mapped registers */ -#define SOC_GPIO_0_REGS (0x01E26000) - -/** \brief Base address of PSC memory mapped registers */ -#define SOC_PSC_1_REGS (0x01E27000) - -/** \brief Base address of I2C memory mapped registers */ -#define SOC_I2C_1_REGS (0x01E28000) - -/** \brief Base address of syscfg registers */ -#define SOC_SYSCFG_1_REGS (0x01E2C000) - -/** \brief Base address of Channel controller memory mapped registers */ -#define SOC_EDMA31CC_0_REGS (0x01E30000) - -/** \brief Base address of Transfer controller memory mapped registers */ -#define SOC_EDMA31TC_0_REGS (0x01E38000) - -/** \brief Base address of EPWM memory mapped registers */ -#define SOC_EHRPWM_0_REGS (0x01F00000) -#define SOC_EHRPWM_1_REGS (0x01F02000) - -/** \brief Base address of EPWM memory mapped registers */ -#define SOC_HRPWM_0_REGS (0x01F01000) -#define SOC_HRPWM_1_REGS (0x01F03000) - -/** \brief Base address of ECAP memory mapped registers */ -#define SOC_ECAP_0_REGS (0x01F06000) -#define SOC_ECAP_1_REGS (0x01F07000) -#define SOC_ECAP_2_REGS (0x01F08000) - -/** \brief Base address of TIMER memory mapped registers */ -#define SOC_TMR_2_REGS (0x01F0C000) -#define SOC_TMR_3_REGS (0x01F0D000) - -/** \brief Base address of SPI memory mapped registers */ -#define SOC_SPI_1_REGS (0x01F0E000) - -/** \brief Base address of EMIFA memory mapped registers */ -#define SOC_EMIFA_0_REGS (0x68000000) - -/** \brief Base address of EMIFA_CS0 memory */ -#define SOC_EMIFA_CS0_ADDR (0x40000000) - -/** \brief Base address of EMIFA_CS2 memory */ -#define SOC_EMIFA_CS2_ADDR (0x60000000) - -/** \brief Base address of EMIFA_CS3 memory */ -#define SOC_EMIFA_CS3_ADDR (0x62000000) - -/** \brief Base address of EMIFA_CS4 memory */ -#define SOC_EMIFA_CS4_ADDR (0x64000000) - -/** \brief Base address of EMIFA_CS5 memory */ -#define SOC_EMIFA_CS5_ADDR (0x66000000) - -/** \brief Base address of DDR memory mapped registers */ -#define SOC_DDR2_0_CTRL_REGS (0xB0000000) -#define SOC_DDR2_0_DATA_REGS (0xC0000000) - -/** \brief Base address of AINTC memory mapped registers */ -#define SOC_AINTC_0_REGS (0xFFFEE000) - -/** \brief Base address of UMC Memory protection registers */ -#define SOC_MEMPROT_L2_REGS (0x00800000) - -/** \brief Base address of PMC memory Protection registers */ -#define SOC_MEMPROT_L1P_REGS (0x00E00000) - -/** \brief Base address of DMC memory protection registers */ -#define SOC_MEMPROT_L1D_REGS (0x00F00000) - -/****************************************************************************** -** EDMA RELATED DEFINITIONS -******************************************************************************/ - -/* Parameterizable Configuration: These are fed directly from the RTL - * parameters for the given SOC */ - -#define SOC_EDMA3_NUM_DMACH 32 -#define SOC_EDMA3_NUM_QDMACH 8 -#define SOC_EDMA3_NUM_PARAMSETS 128 -#define SOC_EDMA3_NUM_EVQUE 2 -#define SOC_EDMA3_CHMAPEXIST 0 -#define SOC_EDMA3_NUM_REGIONS 4 -#define SOC_EDMA3_MEMPROTECT 0 - -/****************************************************************************** -** CHANNEL INSTANCE COUNT -******************************************************************************/ -#define SOC_EDMA3_CHA_CNT (SOC_EDMA3_NUM_DMACH + \ - SOC_EDMA3_NUM_QDMACH) - - -/* QDMA channels */ -#define SOC_EDMA3_QCHA_BASE SOC_EDMA3_NUM_DMACH /* QDMA Channel Base */ -#define SOC_EDMA3_QCHA_0 (SOC_EDMA3_QCHA_BASE + 0) /* QDMA Channel 0 */ -#define SOC_EDMA3_QCHA_1 (SOC_EDMA3_QCHA_BASE + 1) /* QDMA Channel 1 */ -#define SOC_EDMA3_QCHA_2 (SOC_EDMA3_QCHA_BASE + 2) /* QDMA Channel 2 */ -#define SOC_EDMA3_QCHA_3 (SOC_EDMA3_QCHA_BASE + 3) /* QDMA Channel 3 */ -#define SOC_EDMA3_QCHA_4 (SOC_EDMA3_QCHA_BASE + 4) /* QDMA Channel 4 */ -#define SOC_EDMA3_QCHA_5 (SOC_EDMA3_QCHA_BASE + 5) /* QDMA Channel 5 */ -#define SOC_EDMA3_QCHA_6 (SOC_EDMA3_QCHA_BASE + 6) /* QDMA Channel 6 */ -#define SOC_EDMA3_QCHA_7 (SOC_EDMA3_QCHA_BASE + 7) /* QDMA Channel 7 */ - - -/* Enumerations for EDMA Controlleres */ -#define SOC_EDMACC_ANY -1 /* Any instance of EDMACC module*/ -#define SOC_EDMACC_0 0 /* EDMACC Instance 0 */ - - -/* Enumerations for EDMA Event Queues */ -#define SOC_EDMA3_QUE_0 0 /* Queue 0 */ -#define SOC_EDMA3_QUE_1 1 /* Queue 1 */ - -/* Enumerations for EDMA Transfer Controllers - * - * There are 2 Transfer Controllers. Typically a one to one mapping exists - * between Event Queues and Transfer Controllers. */ -#define SOC_EDMATC_ANY -1 /* Any instance of EDMATC */ -#define SOC_EDMATC_0 0 /* EDMATC Instance 0 */ -#define SOC_EDMATC_1 1 /* EDMATC Instance 1 */ - - -#define SOC_EDMA3_REGION_GLOBAL (-1) -#define SOC_EDMA3_REGION_0 0 -#define SOC_EDMA3_REGION_1 1 -#define SOC_EDMA3_REGION_2 2 -#define SOC_EDMA3_REGION_3 3 - - -/****************************************************************************** -** DAT RELATED DEFINITIONS -******************************************************************************/ - -/* Parameterizable Configuration:- These are fed directly from the RTL - * parameters for the given SOC */ - - /****************************************************************************** -** CHANNEL INSTANCE COUNT -******************************************************************************/ -/** \brief Number of Generic Channel instances */ - - -/** \brief Enumerations for EDMA channels - * - * There are 8 QDMA channels - - */ - -#define SOC_DAT_QCHA_0 0 /**< QDMA Channel 0 */ -#define SOC_DAT_QCHA_1 1 /**< QDMA Channel 1 */ -#define SOC_DAT_QCHA_2 2 /**< QDMA Channel 2 */ -#define SOC_DAT_QCHA_3 3 /**< QDMA Channel 3 */ -#define SOC_DAT_QCHA_4 4 /**< QDMA Channel 4 */ -#define SOC_DAT_QCHA_5 5 /**< QDMA Channel 5 */ -#define SOC_DAT_QCHA_6 6 /**< QDMA Channel 6 */ -#define SOC_DAT_QCHA_7 7 /**< QDMA Channel 7 */ - -/** \brief Enumerations for EDMA Event Queues -* -* There are two Event Queues. Q0 is the highest priority and Q1 is the least -* priority -* -*/ -#define SOC_DAT_PRI_DEFAULT 0 /* Queue 0 is default */ -#define SOC_DAT_PRI_0 0 /* Queue 0 */ -#define SOC_DAT_PRI_1 1 /* Queue 1 */ - -/** \brief Enumeration for EDMA Regions -* -* -*/ - -#define SOC_DAT_REGION_GLOBAL (-1) /* Global Region */ -#define SOC_DAT_REGION_0 0 /* EDMA Region 0 */ -#define SOC_DAT_REGION_1 1 /* EDMA Region 1 */ -#define SOC_DAT_REGION_2 2 /* EDMA Region 2 */ -#define SOC_DAT_REGION_3 3 /* EDMA Region 3 */ - -/** \brief Enumeration for peripheral frequencies -* -* -*/ - -#define SOC_SYSCLK_1_FREQ (300000000) -#define SOC_SYSCLK_2_FREQ (SOC_SYSCLK_1_FREQ/2) -#define SOC_SYSCLK_3_FREQ (SOC_SYSCLK_1_FREQ/3) -#define SOC_SYSCLK_4_FREQ (SOC_SYSCLK_1_FREQ/4) - -#define SOC_ASYNC_2_FREQ (24000000) - -/** I2C */ -#define SOC_I2C_0_MODULE_FREQ (SOC_ASYNC_2_FREQ) -#define SOC_I2C_1_MODULE_FREQ (SOC_SYSCLK_4_FREQ) - -/** MCBSP */ -#define SOC_MCBSP_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ) -#define SOC_MCBSP_1_MODULE_FREQ (SOC_SYSCLK_2_FREQ) - -/** LCDC */ -#define SOC_LCDC_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ) - -/** SPI */ -#define SOC_SPI_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ) -#define SOC_SPI_1_MODULE_FREQ (SOC_SYSCLK_2_FREQ) - -/** UART */ -#define SOC_UART_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ) -#define SOC_UART_1_MODULE_FREQ (SOC_SYSCLK_2_FREQ) -#define SOC_UART_2_MODULE_FREQ (SOC_SYSCLK_2_FREQ) - -/** EHRPWM */ -#define SOC_EHRPWM_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ) -#define SOC_EHRPWM_1_MODULE_FREQ (SOC_SYSCLK_2_FREQ) - -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_OMAPL138_H_ */ diff --git a/lib/tiam1808/tiam1808/hw/soc_TI814x.h b/lib/tiam1808/tiam1808/hw/soc_TI814x.h deleted file mode 100644 index e84cea7a0..000000000 --- a/lib/tiam1808/tiam1808/hw/soc_TI814x.h +++ /dev/null @@ -1,84 +0,0 @@ -/** ============================================================================ - * \file soc_TI814x.h - * - * \brief This file contains the peripheral information for AM1808 SOC - * - * ============================================================================ - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _SOC_TI814x_H_ -#define _SOC_TI814x_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief Base address of AINTC memory mapped registers */ -#define SOC_AINTC_REGS (0x48200000) - -#define SOC_CONTROL_MODULE (0x48140000) - -/** @brief Base address of Channel controller memory mapped registers */ -#define SOC_EDMA30CC_0_REGS (0x49000000) -#define SOC_GPMC_REGS (0x50000000) -#define SOC_ELM_REGS (0x48080000) - -#define TPCC_MUX(n) 0xF90 + ((n) * 4) - - -#define SOC_I2C_0_REGS (0x48028000) -/******************************************************************************\ -* Parameterizable Configuration:- These are fed directly from the RTL -* parameters for the given SOC -\******************************************************************************/ - -#define SOC_EDMA3_NUM_DMACH 64 -#define SOC_EDMA3_NUM_QDMACH 8 -#define SOC_EDMA3_NUM_PARAMSETS 512 -#define SOC_EDMA3_NUM_EVQUE 4 -#define SOC_EDMA3_CHMAPEXIST 0 -#define SOC_EDMA3_NUM_REGIONS 8 -#define SOC_EDMA3_MEMPROTECT 0 - -#define SOC_HSMMCSD_1_REGS 0x481D8000 - -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_TI814x_H_ */ diff --git a/lib/tiam1808/tiam1808/lan8710a.h b/lib/tiam1808/tiam1808/lan8710a.h deleted file mode 100644 index 5b6d6b3f0..000000000 --- a/lib/tiam1808/tiam1808/lan8710a.h +++ /dev/null @@ -1,133 +0,0 @@ -/** - * \file lan8710a.h - * - * \brief Macros and function definitions for LAN8710A PHY - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#ifndef _LAN8710_H_ -#define _LAN8710_H_ - -#ifdef __cplusplus -extern "C" { -#endif -/* PHY register offset definitions */ -#define PHY_BCR (0u) -#define PHY_BSR (1u) -#define PHY_ID1 (2u) -#define PHY_ID2 (3u) -#define PHY_AUTONEG_ADV (4u) -#define PHY_LINK_PARTNER_ABLTY (5u) - -/* PHY status definitions */ -#define PHY_ID_SHIFT (16u) -#define PHY_SOFTRESET (0x8000) -#define PHY_AUTONEG_ENABLE (0x1000u) -#define PHY_AUTONEG_RESTART (0x0200u) -#define PHY_AUTONEG_COMPLETE (0x0020u) -#define PHY_AUTONEG_INCOMPLETE (0x0000u) -#define PHY_AUTONEG_STATUS (0x0020u) -#define PHY_AUTONEG_ABLE (0x0008u) -#define PHY_LPBK_ENABLE (0x4000u) -#define PHY_LINK_STATUS (0x0004u) - - - -/* PHY ID. The LSB nibble will vary between different phy revisions */ -#define LAN8710A_PHY_ID (0x0007C0F0u) -#define LAN8710A_PHY_ID_REV_MASK (0x0000000Fu) - -/* Pause operations */ -#define LAN8710A_PAUSE_NIL (0x0000u) -#define LAN8710A_PAUSE_SYM (0x0400u) -#define LAN8710A_PAUSE_ASYM (0x0800u) -#define LAN8710A_PAUSE_BOTH_SYM_ASYM (0x0C00u) - -/* 100 Base TX Full Duplex capablity */ -#define LAN8710A_100BTX_HD (0x0000u) -#define LAN8710A_100BTX_FD (0x0100u) - -/* 100 Base TX capability */ -#define LAN8710A_NO_100BTX (0x0000u) -#define LAN8710A_100BTX (0x0080u) - -/* 10 BaseT duplex capabilities */ -#define LAN8710A_10BT_HD (0x0000u) -#define LAN8710A_10BT_FD (0x0040u) - -/* 10 BaseT ability*/ -#define LAN8710A_NO_10BT (0x0000u) -#define LAN8710A_10BT (0x0020u) - -/************************************************************************** - API function Prototypes -**************************************************************************/ -extern unsigned int Lan8710aIDGet(unsigned int mdioBaseAddr, - unsigned int phyAddr); -extern void Lan8710aReset(unsigned int mdioBaseAddr, - unsigned int phyAddr); -extern unsigned int Lan8710aLoopBackEnable(unsigned int mdioBaseAddr, - unsigned int phyAddr); -extern unsigned int Lan8710aLoopBackDisable(unsigned int mdioBaseAddr, - unsigned int phyAddr); - -extern unsigned int Lan8710aConfigure(unsigned int mdioBaseAddr, - unsigned int phyAddr, - unsigned short speed, - unsigned short dulplexMode); -extern unsigned int Lan8710aAutoNegotiate(unsigned int mdioBaseAddr, - unsigned int phyAddr, - unsigned short advVal); -extern unsigned int Lan8710aRegRead(unsigned int mdioBaseAddr, - unsigned int phyAddr, - unsigned int regIdx, - unsigned short *regValAdr); -extern void Lan8710aRegWrite(unsigned int mdioBaseAddr, - unsigned int phyAddr, - unsigned int regIdx, - unsigned short regVal); - -extern unsigned int Lan8710aPartnerAbilityGet(unsigned int mdioBaseAddr, - unsigned int phyAddr, - unsigned short *ptnerAblty); - -unsigned int Lan8710aLinkStatusGet(unsigned int mdioBaseAddr, - unsigned int phyAddr, - volatile unsigned int retries); -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/tiam1808/tiam1808/lidd.h b/lib/tiam1808/tiam1808/lidd.h deleted file mode 100644 index e54d5b3e6..000000000 --- a/lib/tiam1808/tiam1808/lidd.h +++ /dev/null @@ -1,144 +0,0 @@ -/** - * \file lidd.h - * - * \brief Definitions used for LIDD driver - * - * This file contains the LIDD Device Abstraction Layer API prototypes - * and user interface macro definitions - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#ifndef _LIDD_H_ -#define _LIDD_H_ - -#include "hw_lcdc.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/******************************************************************************* - * MACRO DEFINTIONS - ******************************************************************************/ - -/* Disable/ enable LIDD Done interrupt */ -#define LIDD_DONE_INT_ENABLE (LCDC_LIDD_CTRL_DONE_INT_EN) -#define LIDD_DONE_INT_DISABLE (0) - -/* Interrupt status definitions */ -#define LIDD_FRAME_DONE_INT_STAT LCDC_LCD_STAT_DONE - -#define LIDD_SYNC_LOST_INT_STAT LCDC_LCD_STAT_SYNC - -#define LIDD_ACBIAS_COUNT_INT_STAT LCDC_LCD_STAT_ABC - -#define LIDD_FIFO_UNDERFLOW_INT_STAT LCDC_LCD_STAT_FUF - -#define LIDD_PALETTE_LOADED_INT_STAT LCDC_LCD_STAT_PL - -#define LIDD_END_OF_FRAME0_INT_STAT LCDC_LCD_STAT_EOF0 - -#define LIDD_END_OF_FRAME1_INT_STAT LCDC_LCD_STAT_EOF1 - -/* LIDD DMA control */ -#define LIDD_DMA_ENABLE (LCDC_LIDD_CTRL_LIDD_DMA_EN) -#define LIDD_DMA_DISABLE (0) - -/* LIDD CSn polarity control */ -#define LIDD_CS0_ACTIVE_LOW (0) -#define LIDD_CS0_ACTIVE_HIGH (1 << LCDC_LIDD_CTRL_CS0_E0_POL_SHIFT) -#define LIDD_CS1_ACTIVE_LOW (0) -#define LIDD_CS1_ACTIVE_HIGH (1 << LCDC_LIDD_CTRL_CS1_E1_POL_SHIFT) - -/* LIDD Strobe polarity control */ -#define LIDD_WSTROBE_ACTIVE_LOW (0) -#define LIDD_WSTROBE_ACTIVE_HIGH (1 << LCDC_LIDD_CTRL_WS_DIR_POL_SHIFT) -#define LIDD_RSTROBE_ACTIVE_LOW (0) -#define LIDD_RSTROBE_ACTIVE_HIGH (1 << LCDC_LIDD_CTRL_RS_EN_POL_SHIFT) - -/* LIDD ALE polarity control */ -#define LIDD_ALE_ACTIVE_LOW (0) -#define LIDD_ALE_ACTIVE_HIGH (1 << LCDC_LIDD_CTRL_ALEPOL_SHIFT) - -/* LIDD Mode Selection */ -#define LIDD_MODE_SYNC_MPU68 (LCDC_LIDD_CTRL_LIDD_MODE_SEL_SYNC_MPU68 \ - << LCDC_LIDD_CTRL_LIDD_MODE_SEL_SHIFT) -#define LIDD_MODE_ASYNC_MPU68 (LCDC_LIDD_CTRL_LIDD_MODE_SEL_ASYNC_MPU68 \ - << LCDC_LIDD_CTRL_LIDD_MODE_SEL_SHIFT) -#define LIDD_MODE_SYNC_MPU80 (LCDC_LIDD_CTRL_LIDD_MODE_SEL_SYNC_MPU80 \ - << LCDC_LIDD_CTRL_LIDD_MODE_SEL_SHIFT) -#define LIDD_MODE_ASYNC_MPU80 (LCDC_LIDD_CTRL_LIDD_MODE_SEL_ASYNC_MPU80 \ - << LCDC_LIDD_CTRL_LIDD_MODE_SEL_SHIFT) -#define LIDD_MODE_HITACHI (LCDC_LIDD_CTRL_LIDD_MODE_SEL_HITACHI \ - << LCDC_LIDD_CTRL_LIDD_MODE_SEL_SHIFT) - -/* LIDD CS/Strobe/Enable Polarity control */ -#define LIDD_CS_STROBE_POLARITY(cs1, cs0, ws, rs, ale) ((unsigned int) \ - (cs1 | cs0 | ws | rs | ale)) -/* LIDD CSn Timing configuration */ -#define LIDD_CS_CONF(wsu, ws, wh, rsu, rs, rh, ta) ((unsigned int) \ - (((wsu & 0x1F) << LCDC_LIDD_CS0_CONF_W_SU_SHIFT) | \ - ((ws & 0x3F) << LCDC_LIDD_CS0_CONF_W_STROBE_SHIFT) | \ - ((wh & 0xF) << LCDC_LIDD_CS0_CONF_W_HOLD_SHIFT) | \ - ((rsu & 0x1F) << LCDC_LIDD_CS0_CONF_R_SU_SHIFT) | \ - ((rs & 0x3F) << LCDC_LIDD_CS0_CONF_R_STROBE_SHIFT) | \ - ((rh & 0xF) << LCDC_LIDD_CS0_CONF_R_HOLD_SHIFT) | \ - ((ta & 0x3) << LCDC_LIDD_CS0_CONF_TA_SHIFT))) - - -/* LIDD DMA configuration */ -#define LIDD_DMA_CONFIG(thres, burst, endian) ((unsigned int) \ - (((thres & 0x7) << LCDC_LCDDMA_CTRL_TH_FIFO_READY_SHIFT) | \ - ((burst & 0x7) << LCDC_LCDDMA_CTRL_BURST_SIZE_SHIFT) | \ - ((endian & 0x1) << LCDC_LCDDMA_CTRL_BIGENDIAN_SHIFT))) - -/* Function prototypes */ -void LIDDStringWrite(unsigned int baseAddr, unsigned int cs, unsigned int start, char *data, unsigned int len); -void LIDDDMAConfigSet(unsigned int baseAddr, unsigned int dmaEnable, unsigned int doneEnable); -void LIDDClkConfig(unsigned int baseAddr, unsigned int freq, unsigned int moduleFreq); -void LIDDCSTimingConfig(unsigned int baseAddr, unsigned int cs, unsigned int conf); -void LIDDAddrIndexSet(unsigned int baseAddr, unsigned int cs, unsigned int index); -void LIDDDataWrite(unsigned int baseAddr, unsigned int cs, unsigned int data); -void LIDDPolaritySet(unsigned int baseAddr, unsigned int polarity); -void LIDDModeSet(unsigned int baseAddr, unsigned int mode); -void LIDDDMACSSet(unsigned int baseAddr, unsigned int cs); -unsigned int LIDDStatusGet(unsigned int baseAddr); -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/tiam1808/tiam1808/mailbox.h b/lib/tiam1808/tiam1808/mailbox.h deleted file mode 100644 index 18a4bd129..000000000 --- a/lib/tiam1808/tiam1808/mailbox.h +++ /dev/null @@ -1,111 +0,0 @@ - -/** - * \file mailbox.h - * - * \brief This file contains the function prototypes for Mail box access - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#ifndef __MAIL_BOX_H__ -#define __MAIL_BOX_H__ - -#include "hw_control_AM335x.h" -#include "hw_mailbox.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/********************** MACROS ***************************/ - -/* User Id's */ -#define MAILBOX_USER_A8 0 -#define MAILBOX_USER_PRU0 1 -#define MAILBOX_USER_PRU1 2 -#define MAILBOX_USER_CM3WKUP 3 - -/* Mailbox Queue's */ -#define MAILBOX_QUEUE_0 0 -#define MAILBOX_QUEUE_1 1 -#define MAILBOX_QUEUE_2 2 -#define MAILBOX_QUEUE_3 3 -#define MAILBOX_QUEUE_4 4 -#define MAILBOX_QUEUE_5 5 -#define MAILBOX_QUEUE_6 6 -#define MAILBOX_QUEUE_7 7 - -#define MESSAGE_VALID 0 -#define MESSAGE_INVALID 1 - - -/***************************************************************************** -** FUNCTION DECLARATIONS -*****************************************************************************/ - -/* Queue Access API's */ - -void MBresetMailbox(unsigned int baseAdd); - -void MBconfigIdleMode(unsigned int baseAdd, unsigned int idleMode); - -unsigned int MBgetMessage(unsigned int baseAdd, unsigned int queueId, unsigned int *msgPtr); - -unsigned int MBsendMessage(unsigned int baseAdd, unsigned int queueId, unsigned int msg); - - -/* Mailbox user(hw using mailbox) access API's */ -void MBenableNewMsgInt(unsigned int baseAdd, unsigned int userId, unsigned int queueId); -void MBenableQueueNotFullInt(unsigned int baseAdd, unsigned int userId, unsigned int queueId); - -void MBdisableNewMsgInt(unsigned int baseAdd, unsigned int userId, unsigned int queueId); -void MBdisableQueueNotFullInt(unsigned int baseAdd, unsigned int userId, unsigned int queueId); - -unsigned int MBgetNewMsgStatus(unsigned int baseAdd, unsigned int userId, unsigned int queueId); -unsigned int MBgetQueueNotFullStatus(unsigned int baseAdd, unsigned int userId, unsigned int queueId); - -void MBclrNewMsgStatus(unsigned int baseAdd, unsigned int userId, unsigned int queueId); -void MBclrQueueNotFullStatus(unsigned int baseAdd, unsigned int userId, unsigned int queueId); - -unsigned int MBgetRawNewMsgStatus(unsigned int baseAdd, unsigned int userId, unsigned int queueId); -unsigned int MBgetRawQueueNotFullStatus(unsigned int baseAdd, unsigned int userId, unsigned int queueId); - - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/lib/tiam1808/tiam1808/nand.h b/lib/tiam1808/tiam1808/nand.h deleted file mode 100644 index 5da5af864..000000000 --- a/lib/tiam1808/tiam1808/nand.h +++ /dev/null @@ -1,165 +0,0 @@ -/** - * \file nand.h - * - * \brief Definitions used for NAND - * - * This file contains the nand middle layer API prototypes and macro definitions. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _NAND_H_ -#define _NAND_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* -* MACRO DEFINITIONS -*******************************************************************************/ -/* Resister Location of NAND to communicate */ - -#define AM1808 -#ifdef AM1808 - #define CS3_NAND_DATA_REG (0x62000000u) - #define CS3_NAND_CMD_REG (0x62000010u) - #define CS3_NAND_ADDR_REG (0x62000008u) -#endif - -/* Macro to read the Data from Data Register */ -#define NANDDataRead (*(volatile unsigned char*)(CS3_NAND_DATA_REG)) - -/* Macro to write the Address To NAND address Register */ -#define NANDAddressWrite(address) \ - (*(volatile unsigned char*)(CS3_NAND_ADDR_REG) = (address)) - -/* Macro to write the Command To NAND Command Register */ -#define NANDCommandWrite(command) \ - (*(volatile unsigned char*)(CS3_NAND_CMD_REG) = (command)) - -/* Macro to write the Data to Data Register */ -#define NANDDataWrite(data) \ - (*(volatile unsigned char*)(CS3_NAND_DATA_REG) = (data)) -#define NANDDataWrite16(data) \ - (*(volatile unsigned short*)(CS3_NAND_DATA_REG) = (data)) - -/* Macro to read the Data from Data Register */ -#define NANDDataRead (*(volatile unsigned char*)(CS3_NAND_DATA_REG)) -#define NANDDataRead16 (*(volatile unsigned short*)(CS3_NAND_DATA_REG)) - -/* Number Of Pages Per Blk */ -#define NAND_PAGES_PER_BLK (64) -#define NAND_PAGE_SIZE (2048) -#define NAND_RD_WR_SIZE (NAND_PAGE_SIZE) -#define NAND_NUM_OF_TRNFS (4) -#define NAND_BYTES_PER_TRNFS (NAND_RD_WR_SIZE / \ - NAND_NUM_OF_TRNFS) -#define NAND_SPARE_AREA_BAD_BLOCK_MARK_OFFSET (2048) - - -/* NAND STATUS VALUES */ -#define NAND_STATUS_CMD_PASSED (0) -#define NAND_STATUS_CMD_FAILED (1) -#define NAND_STATUS_WAIT_TIMEOUT (2) -#define NAND_STATUS_WRITE_PROTECTED (3) - -#define NAND_1BIT_ECC (1) -#define NAND_4BIT_ECC (2) - -#define NAND_ECC_CHECK_PASSED (0u) -#define NAND_ECC_CHECK_FAILED (1u) -#define NAND_ECC_CORRECTION_ECCSTATE_0 (0u) -#define NAND_ECC_CORRECTION_ECCSTATE_2 (2u) -#define NAND_ECC_CORRECTION_ECCSTATE_3 (3u) -#define NAND_ECC_CORRECTION_NO_ERROR (0) -#define NAND_ECC_ERROR_CORRECTED (1) -#define NAND_ECC_CORRECTION_UNCORRECTABLE_ERROR (2) - -#define NAND_BLOCK_GOOD (0) -#define NAND_BLOCK_BAD (1) -#define NAND_BLOCK_SPARE_AREA_READ_FAILED (2) - - -#define NAND_BLK_GOOD_MARK (0xFF) -#define NAND_BLK_BAD_MARK (0) - -#ifdef NAND_ECC_TYPE_1BIT - #define NAND_ECC_DATA_SIZE (12u) -#else - #define NAND_ECC_DATA_SIZE (40u) -#endif - -#define NAND_ECC_BYTES_FOR_BYTES_PER_TRNFS (NAND_ECC_DATA_SIZE/ \ - NAND_NUM_OF_TRNFS) - -/***************************************************************************/ -/* -** Function Prototypes -*/ -extern unsigned int NANDIdRead(); -extern unsigned int NANDStatusGet(); -extern unsigned int NANDResetDevice(); -extern unsigned int NANDWaitUntilReady(); -extern unsigned int NANDPageWriteCmdEnd(); -extern void NANDDelay(volatile unsigned int delay); -extern void NANDECCRead(unsigned char *ptrEccData,unsigned int eccType, - unsigned int csNum); -extern unsigned int NANDECCCheck(unsigned char *ptrEccData, - unsigned int eccType, unsigned int csNum); -extern unsigned int NANDBlockErase (unsigned int blkNum); -extern void NANDECCSelectAndStart(unsigned int csNum,unsigned int eccType); -extern unsigned int NANDBadBlockCheck(unsigned int blkNum); -extern unsigned int NANDMarkBlockAsBad(unsigned int blkNum); -extern unsigned int NANDECCCorrect(unsigned char * ptrData,unsigned eccType, - unsigned int eccDiffVal); -extern void NANDPageWriteCmdStart(unsigned int blkNum, unsigned int pageNum, - unsigned int columnAddr); -extern unsigned int NANDPageReadCmdSend(unsigned int blkNum, - unsigned int pageNum, - unsigned int columnAddr); -extern unsigned int NANDSpareAreaWrite(unsigned int blkNum, - unsigned int pageNum, - unsigned int columnAddr, - unsigned int numOfBytes,unsigned char *data); -extern unsigned int NANDSpareAreaRead(unsigned int blkNum, unsigned int pageNum, - unsigned int columnAddr, - unsigned int numOfBytes,unsigned char *data); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/tiam1808/tiam1808/phy.h b/lib/tiam1808/tiam1808/phy.h deleted file mode 100644 index be4392cdf..000000000 --- a/lib/tiam1808/tiam1808/phy.h +++ /dev/null @@ -1,144 +0,0 @@ -/** - * \file phy.h - * - * \brief Macros and function definitions for EMAC PHY - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _PHY_H_ -#define _PHY_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* PHY register offset definitions */ -#define PHY_BCR (0u) -#define PHY_BSR (1u) -#define PHY_ID1 (2u) -#define PHY_ID2 (3u) -#define PHY_AUTONEG_ADV (4u) -#define PHY_LINK_PARTNER_ABLTY (5u) -#define PHY_1000BT_CONTROL (9u) -#define PHY_1000BT_STATUS (10u) - -/* PHY status definitions */ -#define PHY_ID_SHIFT (16u) -#define PHY_SOFTRESET (0x8000) -#define PHY_AUTONEG_ENABLE (0x1000u) -#define PHY_AUTONEG_RESTART (0x0200u) -#define PHY_AUTONEG_COMPLETE (0x0020u) -#define PHY_AUTONEG_INCOMPLETE (0x0000u) -#define PHY_AUTONEG_STATUS (0x0020u) -#define PHY_AUTONEG_ABLE (0x0008u) -#define PHY_LPBK_ENABLE (0x4000u) -#define PHY_LINK_STATUS (0x0004u) - -/* PHY ID. The LSB nibble will vary between different phy revisions */ -#define PHY_ID_REV_MASK (0x0000000Fu) - -/* Pause operations */ -#define PHY_PAUSE_NIL (0x0000u) -#define PHY_PAUSE_SYM (0x0400u) -#define PHY_PAUSE_ASYM (0x0800u) -#define PHY_PAUSE_BOTH_SYM_ASYM (0x0C00u) - -/* 1000 Base-T capabilities */ -#define PHY_NO_1000BT (0x0000u) -#define PHY_1000BT_HD (0x0100u) -#define PHY_1000BT_FD (0x0200u) - -/* 100 Base TX Full Duplex capablity */ -#define PHY_100BTX_HD (0x0000u) -#define PHY_100BTX_FD (0x0100u) - -/* 100 Base TX capability */ -#define PHY_NO_100BTX (0x0000u) -#define PHY_100BTX (0x0080u) - -/* 10 BaseT duplex capabilities */ -#define PHY_10BT_HD (0x0000u) -#define PHY_10BT_FD (0x0040u) - -/* 10 BaseT ability*/ -#define PHY_NO_10BT (0x0000u) -#define PHY_10BT (0x0020u) - -#define PHY_LINK_PARTNER_1000BT_FD (0x0800u) -#define PHY_LINK_PARTNER_1000BT_HD (0x0400u) - - -/************************************************************************** - API function Prototypes -**************************************************************************/ -extern unsigned int PhyIDGet(unsigned int mdioBaseAddr, - unsigned int phyAddr); -extern void PhyReset(unsigned int mdioBaseAddr, - unsigned int phyAddr); -extern unsigned int PhyLoopBackEnable(unsigned int mdioBaseAddr, - unsigned int phyAddr); -extern unsigned int PhyLoopBackDisable(unsigned int mdioBaseAddr, - unsigned int phyAddr); - -extern unsigned int PhyConfigure(unsigned int mdioBaseAddr, - unsigned int phyAddr, - unsigned short speed, - unsigned short dulplexMode); -extern unsigned int PhyAutoNegotiate(unsigned int mdioBaseAddr, - unsigned int phyAddr, - unsigned short *advPtr, - unsigned short *gigAdvPtr); -extern unsigned int PhyRegRead(unsigned int mdioBaseAddr, - unsigned int phyAddr, - unsigned int regIdx, - unsigned short *regValAdr); -extern void PhyRegWrite(unsigned int mdioBaseAddr, - unsigned int phyAddr, - unsigned int regIdx, - unsigned short regVal); -extern unsigned int PhyPartnerAbilityGet(unsigned int mdioBaseAddr, - unsigned int phyAddr, - unsigned short *ptnerAblty); -extern unsigned int PhyLinkStatusGet(unsigned int mdioBaseAddr, - unsigned int phyAddr, - volatile unsigned int retries); -extern unsigned int PhyAutoNegStatusGet(unsigned int mdioBaseAddr, - unsigned int phyAddr); -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/tiam1808/tiam1808/raster.h b/lib/tiam1808/tiam1808/raster.h deleted file mode 100644 index ab93b9bb6..000000000 --- a/lib/tiam1808/tiam1808/raster.h +++ /dev/null @@ -1,393 +0,0 @@ -/** - * \file raster.h - * - * \brief Definitions used for raster LCD - * - * This file contains the driver API prototypes and macro definitions. - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - - -#ifndef _RASTER_H_ -#define _RASTER_H_ - -#include "hw_lcdc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* -* MACRO DEFINITIONS -*******************************************************************************/ -/*****************************************************************************/ -/* -** Values that can be passed to RasterModeConfig API as displayType to select -** type of display -*/ - - /* Configure display type to TFT */ -#define RASTER_DISPLAY_MODE_TFT (1 << LCDC_RASTER_CTRL_TFT_STN_SHIFT) - - /* Configure display type to STN */ -#define RASTER_DISPLAY_MODE_STN 0 - -/* Configure display type to TFT with 24 bit data packed mode */ -#define RASTER_DISPLAY_MODE_TFT_PACKED (1 << LCDC_RASTER_CTRL_TFT_STN_SHIFT)|\ - (1 << LCDC_RASTER_CTRL_TFT24_SHIFT) - -/* Configure display type to TFT with 24 bit data packed mode */ -#define RASTER_DISPLAY_MODE_TFT_UNPACKED (1 << LCDC_RASTER_CTRL_TFT_STN_SHIFT)|\ - (1 << LCDC_RASTER_CTRL_TFT24_SHIFT) |\ - (1 << LCDC_RASTER_CTRL_TFT24UNPACKED_SHIFT) - -/******************************************************************************/ -/* -** Values that can be passed to RasterModeConfig API as paletteMode to select -** mode of palette loading. -*/ - /* Both palette and data will be loaded */ -#define RASTER_PALETTE_DATA 0 - - /* Only palette will be loaded */ -#define RASTER_PALETTE (1 << LCDC_RASTER_CTRL_PLM_SHIFT) - - /* Only data will be loaded */ -#define RASTER_DATA (2 << LCDC_RASTER_CTRL_PLM_SHIFT) - -/*********************************************************************************/ -/* -** Values that can be passed to RasterModeConfig API as displayMode to select -** mode of display as either color or monochrome. -*/ - - /* Select displayMode as COLOR */ -#define RASTER_COLOR 0 - - /* Select displayMode as monochrome */ -#define RASTER_MONOCHROME (1 << LCDC_RASTER_CTRL_MONO_COLOR_SHIFT) -/*********************************************************************************/ -/* -** Values that can be passed to RasterModeConfig API as flag for signal mappping -** if out pixel data is of 1,2,4 or 8 bits per pixel -*/ - /* Out put pixel data will be right aligned */ -#define RASTER_RIGHT_ALIGNED 0 - - /* Out put pixel data will be mapped to 565 format */ -#define RASTER_EXTRAPOLATE (1 << LCDC_RASTER_CTRL_TFT_ALT_MAP_SHIFT) - -/*******************************************************************************/ -/* -** Values that can be passed to RasterModeConfig API as flag to select how many -** bits to output each pixel clock when momochrome displayMode is used -*/ - - /* Eight bits are output each pClk */ -#define RASTER_MONO8B (1 << LCDC_RASTER_CTRL_MONO8B_SHIFT) - - /* Four bits are output each pClk */ -#define RASTER_MONO4B 0 -/******************************************************************************/ -/* -** Values that can be passed to RasterDMAConfig API as frmMode to select either -** to signle frame buffer or double frmae buffer(ping pong) -*/ - - /* Selects single frmae buffer */ -#define RASTER_SINGLE_FRAME_BUFFER 0 - - /* Selects double frmae buffer */ -#define RASTER_DOUBLE_FRAME_BUFFER LCDC_LCDDMA_CTRL_FRAME_MODE -/*****************************************************************************/ -/* -** Values that can be passed to RasterDMAConfig API as endian to enable or -** disable bigendian for data reordering -*/ - - /* Enable bigendian for data reordering */ -#define RASTER_BIG_ENDIAN_ENABLE (1 << LCDC_LCDDMA_CTRL_BIGENDIAN_SHIFT) - - /* Disable bigendian for data reordering */ -#define RASTER_BIG_ENDIAN_DISABLE 0 -/*****************************************************************************/ -/* -** Values that can be passed to RasterDMAConfig API as bustSz to select burst -** size for DMA transfer -*/ - - /* Select burst size as one */ -#define RASTER_BURST_SIZE_1 0 - - /* Select burst size as two */ -#define RASTER_BURST_SIZE_2 (1 << LCDC_LCDDMA_CTRL_BURST_SIZE_SHIFT) - - /* Select burst size as four */ -#define RASTER_BURST_SIZE_4 (2 << LCDC_LCDDMA_CTRL_BURST_SIZE_SHIFT) - - /* Select burst size as eight*/ -#define RASTER_BURST_SIZE_8 (3 << LCDC_LCDDMA_CTRL_BURST_SIZE_SHIFT) - - /* Select burst size as sixteen */ -#define RASTER_BURST_SIZE_16 (4 << LCDC_LCDDMA_CTRL_BURST_SIZE_SHIFT) -/*****************************************************************************/ -/* -** Values that can be passed to RasterDMAConfig API as fifoTh to select DMA -** fifo threshold -*/ - -#define RASTER_FIFO_THRESHOLD_8 (0 << LCDC_LCDDMA_CTRL_TH_FIFO_READY_SHIFT) -#define RASTER_FIFO_THRESHOLD_16 (1 << LCDC_LCDDMA_CTRL_TH_FIFO_READY_SHIFT) -#define RASTER_FIFO_THRESHOLD_32 (2 << LCDC_LCDDMA_CTRL_TH_FIFO_READY_SHIFT) -#define RASTER_FIFO_THRESHOLD_64 (3 << LCDC_LCDDMA_CTRL_TH_FIFO_READY_SHIFT) -#define RASTER_FIFO_THRESHOLD_128 (4 << LCDC_LCDDMA_CTRL_TH_FIFO_READY_SHIFT) -#define RASTER_FIFO_THRESHOLD_256 (5 << LCDC_LCDDMA_CTRL_TH_FIFO_READY_SHIFT) -#define RASTER_FIFO_THRESHOLD_512 (6 << LCDC_LCDDMA_CTRL_TH_FIFO_READY_SHIFT) - -/*********************************************************************************/ -/* -** Values that can be passed to RasterTiming2Configure API as flag to select the -** polarity of timing parameters of LCD controller. -*/ - - /* Selects active high frame clock */ -#define RASTER_FRAME_CLOCK_HIGH 0 - - /* Selects active low frame clock */ -#define RASTER_FRAME_CLOCK_LOW LCDC_RASTER_TIMING_2_IVS - - /* Selects active high line clock */ -#define RASTER_LINE_CLOCK_HIGH 0 - - /* Selects active low line clock */ -#define RASTER_LINE_CLOCK_LOW LCDC_RASTER_TIMING_2_IHS - - /* Selects active high pixel clock */ -#define RASTER_PIXEL_CLOCK_HIGH 0 - - /* Selects active low pixel clock */ -#define RASTER_PIXEL_CLOCK_LOW LCDC_RASTER_TIMING_2_IPC - - /* Selects acbias as active high*/ -#define RASTER_AC_BIAS_HIGH 0 - - /* Selects acbias as active low*/ -#define RASTER_AC_BIAS_LOW LCDC_RASTER_TIMING_2_BIAS - - /* Selects horizontal and vertical sync edge as rising edge*/ -#define RASTER_SYNC_EDGE_RISING 0 - - /* Selects horizontal and vertical sync edge as falling edge*/ -#define RASTER_SYNC_EDGE_FALLING LCDC_RASTER_TIMING_2_SYNC_EDGE - - /* Selects horizontal and vertical sync control as active */ -#define RASTER_SYNC_CTRL_ACTIVE LCDC_RASTER_TIMING_2_SYNC_CTRL - - /* Selects horizontal and vertical sync control as active */ -#define RASTER_SYNC_CTRL_INACTIVE 0 -/**************************************************************************/ -/* -** Values that can be passed to RasterIntEnable or RasterIntDisable API -** as flag to select the interrupt to be enabled or disabled -*/ - -#ifdef am1808 - -#define RASTER_ACBIAS_COUNT_INT LCDC_RASTER_CTRL_AC_EN - -#define RASTER_FRAME_DONE_INT LCDC_RASTER_CTRL_DONE_EN - -#define RASTER_PALETTE_LOADED_INT LCDC_RASTER_CTRL_PL_EN - -#define RASTER_SYNC_LOST_INT LCDC_RASTER_CTRL_SL_EN - -#define RASTER_FIFO_UNDRFLOW_INT LCDC_RASTER_CTRL_FUF_EN - -#endif - - -#if defined(am335x) || defined(am335x_13x13) || defined(am335x_15x15) - -#define RASTER_ACBIAS_COUNT_INT LCDC_IRQENABLE_SET_ACB - -#define RASTER_FRAME_DONE_INT LCDC_IRQENABLE_SET_DONE - -#define RASTER_PALETTE_LOADED_INT LCDC_IRQENABLE_SET_PL - -#define RASTER_SYNC_LOST_INT LCDC_IRQENABLE_SET_SYNC - -#define RASTER_FIFO_UNDRFLOW_INT LCDC_IRQENABLE_SET_FUF - -#endif - -#define RASTER_DONE_INT LCDC_IRQENABLE_SET_RECURRENT_RASTER - -#define RASTER_END_OF_FRAME0_INT LCDC_IRQENABLE_SET_EOF0 - -#define RASTER_END_OF_FRAME1_INT LCDC_IRQENABLE_SET_EOF1 - -/***************************************************************************/ -/* -** Values that can be passed to RasterIntSatus API as flag -** to get interrupt status of rquired interrupt. -*/ - -#if defined(am1808) || defined(omapl138) || defined(c6748) - -#define RASTER_FRAME_DONE_INT_STAT LCDC_LCD_STAT_DONE - -#define RASTER_SYNC_LOST_INT_STAT LCDC_LCD_STAT_SYNC - -#define RASTER_ACBIAS_COUNT_INT_STAT LCDC_LCD_STAT_ABC - -#define RASTER_FIFO_UNDERFLOW_INT_STAT LCDC_LCD_STAT_FUF - -#define RASTER_PALETTE_LOADED_INT_STAT LCDC_LCD_STAT_PL - -#define RASTER_END_OF_FRAME0_INT_STAT LCDC_LCD_STAT_EOF0 - -#define RASTER_END_OF_FRAME1_INT_STAT LCDC_LCD_STAT_EOF1 - -#endif - -#if defined(am335x) || defined(am335x_13x13) || defined(am335x_15x15) - -#define RASTER_FRAME_DONE_INT_STAT LCDC_IRQSTATUS_DONE - -#define RASTER_SYNC_LOST_INT_STAT LCDC_IRQSTATUS_SYNC - -#define RASTER_ACBIAS_COUNT_INT_STAT LCDC_IRQSTATUS_ACB - -#define RASTER_FIFO_UNDERFLOW_INT_STAT LCDC_IRQSTATUS_FUF - -#define RASTER_PALETTE_LOADED_INT_STAT LCDC_IRQSTATUS_PL - -#define RASTER_END_OF_FRAME0_INT_STAT LCDC_IRQSTATUS_EOF0 - -#define RASTER_END_OF_FRAME1_INT_STAT LCDC_IRQSTATUS_EOF1 - -#endif - - -/***************************************************************************/ -/* -** Values that can be passed to RasterSoftawreResetControl API as flag -** to Reset required module(i.e Raster or DMA or LCD). -*/ - -#define RASTER_CORE_RESET LCDC_CLKC_RESET_CORE -#define RASTER_DMA_RESET LCDC_CLKC_RESET_DMA -#define RASTER_LCD_MODULE_RESET LCDC_CLKC_RESET_MAIN - - -#define RASTER_REV_AM335X 2u -#define RASTER_REV_AM1808 1u -/***************************************************************************/ - -typedef struct rasterContext { - unsigned int clkcEnable; - unsigned int lcdCtrl; - unsigned int lcddmaCtrl; - unsigned int rasterTiming0; - unsigned int rasterTiming1; - unsigned int rasterTiming2; - unsigned int rasterCtrl; - unsigned int irqEnableSet; - unsigned int lcddmaFb0Base; - unsigned int lcddmaFb0Ceiling; - unsigned int lcddmaFb1Base; - unsigned int lcddmaFb1Ceiling; -}RASTERCONTEXT; - - -/* -** Function Prototypes -*/ -extern void RasterEnable(unsigned int baseAddr); -extern void RasterDisable(unsigned int baseAddr); -extern void RasterNibbleModeEnable(unsigned int baseAddr); -extern void RasterNibbleModeDisable(unsigned int baseAddr); -extern void RasterMSBDataOrderSelect(unsigned int baseAddr); -extern void RasterLSBDataOrderSelect(unsigned int baseAddr); -extern void RasterEndOfFrameIntEnable(unsigned int baseAddr); -extern void RasterEndOfFrameIntDisable(unsigned int baseAddr); -extern void RasterIntEnable(unsigned int baseAddr, unsigned int flag); -extern void RasterDMAFBConfig(unsigned int baseAddr, unsigned int base, - unsigned int ceiling, unsigned int flag); -extern void RasterDMAConfig(unsigned int baseAddr, unsigned int frmMode, - unsigned int bustSz, unsigned int fifoTh, - unsigned int endian); -extern void RasterIntDisable(unsigned int baseAddr, unsigned int flag); -extern void RasterClkConfig(unsigned int baseAddr, unsigned int pClk, - unsigned int moduleClk); -extern void RasterModeConfig(unsigned int baseAddr, unsigned int displayMode, - unsigned int paletteMode, unsigned int displayType, - unsigned int flag); - -extern unsigned int RasterIntStatus(unsigned int baseAddr, unsigned int flag); -extern void RasterVparamConfig(unsigned int baseAddr, unsigned int Lpp, - unsigned int vsw, unsigned int vfp, - unsigned vbp); - -extern void RasterHparamConfig(unsigned int baseAddr, unsigned int numOfppl, - unsigned int hsw, unsigned int hfp, - unsigned hbp); - -extern void RasterTiming2Configure(unsigned int baseAddr, unsigned int flag, - unsigned int acb_i, unsigned int acb); - -extern void RasterFIFODMADelayConfig(unsigned int baseAddr, unsigned int delay); - -extern void RasterSubPanelEnable(unsigned int baseAddr); - -extern void RasterSubPanelDisable(unsigned int baseAddr); - -extern void RasterSubPanelConfig(unsigned int baseAddr, unsigned int hols, - unsigned int lppt, unsigned int dpd); -extern unsigned int RasterClearGetIntStatus(unsigned int baseAddr, - unsigned int flag); - - -extern void RasterEndOfInterrupt(unsigned int baseAddr, unsigned int flag); - -extern void RasterClocksEnable(unsigned int baseAddr); -extern unsigned int LCDVersionGet(void); -extern void RasterContextSave(unsigned int baseAddr, RASTERCONTEXT *contextPtr); -extern void RasterContextRestore(unsigned int baseAddr, RASTERCONTEXT *contextPtr); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/tiam1808/tiam1808/tsc_adc.h b/lib/tiam1808/tiam1808/tsc_adc.h deleted file mode 100644 index f14d06eb1..000000000 --- a/lib/tiam1808/tiam1808/tsc_adc.h +++ /dev/null @@ -1,326 +0,0 @@ -/** - * \file tsc_adc.h - * - * \brief This file contains the function prototypes for the device - * abstraction layer for Touch Screen. It also contains some - * related macro definitions and some files to be included. - */ - - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#ifndef _TSCADC_H_ -#define _TSCADC_H_ - -#include "hw_tsc_adc_ss.h" - - -#define TSCADC_FORCE_IDLE (0) - -#define TSCADC_NO_IDLE (1) - -#define TSCADC_SMART_IDLE (2) - -#define TSCADC_SMART_IDLE_WAKEUP (3) - -#define TSCADC_ASYNC_HW_PEN_EVENT_INT TSC_ADC_SS_IRQSTATUS_RAW_HW_PEN_EVENT - -#define TSCADC_SYNC_PEN_EVENT_INT TSC_ADC_SS_IRQSTATUS_RAW_PEN_IRQ - -#define TSCADC_FIFO0_UNDER_FLOW_INT TSC_ADC_SS_IRQSTATUS_RAW_FIFO0_UNDERFLOW - -#define TSCADC_FIFO1_UNDER_FLOW_INT TSC_ADC_SS_IRQSTATUS_RAW_FIFO1_UNDERFLOW - -#define TSCADC_END_OF_SEQUENCE_INT TSC_ADC_SS_IRQSTATUS_RAW_END_OF_SEQUENCE - -#define TSCADC_FIFO0_THRESHOLD_INT TSC_ADC_SS_IRQSTATUS_RAW_FIFO0_THRESHOLD - -#define TSCADC_FIFO1_THRESHOLD_INT TSC_ADC_SS_IRQSTATUS_RAW_FIFO1_THRESHOLD - -#define TSCADC_FIFO0_OVER_RUN_INT TSC_ADC_SS_IRQSTATUS_RAW_FIFO0_OVERRUN - -#define TSCADC_FIFO1_OVER_RUN_INT TSC_ADC_SS_IRQSTATUS_RAW_FIFO1_OVERRUN - -#define TSCADC_OUT_OF_RANGE_INT TSC_ADC_SS_IRQSTATUS_RAW_OUT_OF_RANGE - -#define TSCADC_PEN_UP_EVENT_INT TSC_ADC_SS_IRQSTATUS_RAW_PEN_UP_EVENT - -#define TSCADC_FIFO_0 (0) - -#define TSCADC_FIFO_1 (1) - -#define TSCADC_FOUR_WIRE_MODE (1) - -#define TSCADC_FIVE_WIRE_MODE (2) - -#define TSCADC_GENERAL_PURPOSE_MODE (0) - -#define TSCADC_PEN_IRQ_0 (0) - -#define TSCADC_PEN_IRQ_1 (1) - -#define TSCADC_SINGLE_ENDED_OPER_MODE (0) - -#define TSCADC_DIFFERENTIAL_OPER_MODE (1) - -#define TSCADC_TWO_SAMPLES_AVG (1) - -#define TSCADC_FOUR_SAMPLES_AVG (2) - -#define TSCADC_EIGHT_SAMPLES_AVG (3) - -#define TSCADC_SIXTEEN_SAMPLES_AVG (4) - -#define TSCADC_ONE_SHOT_SOFTWARE_ENABLED (0) - -#define TSCADC_CONTINIOUS_SOFTWARE_ENABLED (1) - -#define TSCADC_ONE_SHOT_HARDWARE_SYNC (2) - -#define TSCADC_CONTINIOUS_HARDWARE_SYNC (3) - -#define TSCADC_WAKEUP_DISABLE (0) - -#define TSCADC_WAKEUO_ENABLE (1) - -#define TSCADC_HW_INPUT_EVENT (1) - -#define TSCADC_PEN_TOUCH (0) - -#define TSCADC_TRANSISTOR_DISABLE (0) - -#define TSCADC_TRANSISTOR_ENABLE (1) - -#define TSCADC_INTERNAL_AC_BIAS (0) - -#define TSCADC_EXTERNAL_AC_BIAS (1) - -#define TSCADC_MODULE_DISABLE (0) - -#define TSCADC_MODULE_ENABLE (1) - -#define TSCADC_NEGATIVE_REF_VSSA (0) - -#define TSCADC_NEGATIVE_REF_XNUR (1) - -#define TSCADC_NEGATIVE_REF_YNLR (2) - -#define TSCADC_NEGATIVE_REF_ADCREFM (3) - -#define TSCADC_POSITIVE_REF_VDDA (0) - -#define TSCADC_POSITIVE_REF_XPUL (1) - -#define TSCADC_POSITIVE_REF_YPLL (2) - -#define TSCADC_POSITIVE_REF_ADCREFP (3) - -#define TSCADC_POSITIVE_INP_CHANNEL1 (0) - -#define TSCADC_POSITIVE_INP_CHANNEL2 (1) - -#define TSCADC_POSITIVE_INP_CHANNEL3 (2) - -#define TSCADC_POSITIVE_INP_CHANNEL4 (3) - -#define TSCADC_POSITIVE_INP_CHANNEL5 (4) - -#define TSCADC_POSITIVE_INP_CHANNEL6 (5) - -#define TSCADC_POSITIVE_INP_CHANNEL7 (6) - -#define TSCADC_POSITIVE_INP_CHANNEL8 (7) - -#define TSCADC_POSITIVE_INP_ADCREFM (8) - -#define TSCADC_NEGATIVE_INP_CHANNEL1 (0) - -#define TSCADC_NEGATIVE_INP_CHANNEL2 (1) - -#define TSCADC_NEGATIVE_INP_CHANNEL3 (2) - -#define TSCADC_NEGATIVE_INP_CHANNEL4 (3) - -#define TSCADC_NEGATIVE_INP_CHANNEL5 (4) - -#define TSCADC_NEGATIVE_INP_CHANNEL6 (5) - -#define TSCADC_NEGATIVE_INP_CHANNEL7 (6) - -#define TSCADC_NEGATIVE_INP_CHANNEL8 (7) - -#define TSCADC_NEGATIVE_INP_ADCREFM (8) - -#define TSCADC_XPPSW_PIN_ON (1) - -#define TSCADC_XPPSW_PIN_OFF (0) - -#define TSCADC_XNNSW_PIN_ON (1) - -#define TSCADC_XNNSW_PIN_OFF (0) - -#define TSCADC_YPPSW_PIN_ON (1) - -#define TSCADC_YPPSW_PIN_OFF (0) - -#define TSCADC_YNNSW_PIN_ON (1) - -#define TSCADC_YNNSW_PIN_OFF (0) - -#define TSCADC_XNPSW_PIN_ON (1) - -#define TSCADC_XNPSW_PIN_OFF (0) - -#define TSCADC_YPNSW_PIN_ON (1) - -#define TSCADC_YPNSW_PIN_OFF (0) - -#define TSCADC_WPNSW_PIN_ON (1) - -#define TSCADC_WPNSW_PIN_OFF (0) - - -void TSCADCSetADCPowerDown(unsigned int baseAdd); -unsigned int TSCADCGetRevision(unsigned int baseAdd); -unsigned int TSCADCEventIrqStatus(unsigned int baseAdd); -void TSCADCStepConfigProtectionEnable(unsigned int baseAdd); -void TSCADCStepConfigProtectionDisable(unsigned int baseAdd); -void TSCADCTSChargeStepOpenDelayConfig(unsigned int baseAdd, - unsigned int openDelay); -unsigned int TSCADCSequencerFSMBusyStatus(unsigned int baseAdd); -unsigned int TSCADCSequencerCurrentStepID(unsigned int baseAdd); -void TSCADCEOIControl(unsigned int baseAdd, unsigned int irq_EOC); -void TSCADCTSModeConfig(unsigned int baseAdd, unsigned int tsMode); -void TSCADCIdleModeSet(unsigned int baseAdd, unsigned int idleMode); -void TSCADCHWEventMapSet(unsigned int baseAdd, unsigned int hwEvent); -unsigned int TSCADCSequencerPenIrqStatusRead(unsigned int baseAdd, - unsigned int penIRQSel); -void TSCADCTSStepModeConfig(unsigned int baseAdd, unsigned int stepSel, - unsigned int mode); -void TSCADCDMAFIFOEnable(unsigned int baseAdd, unsigned char fifoSel); -void TSCADCDMAFIFODisable(unsigned int baseAdd, unsigned char fifoSel); -void TSCADCADCBiasConfig(unsigned int baseAdd, unsigned int adcBiasSel); -void TSCADCIntStatusClear(unsigned int baseAdd, unsigned int intFlag); -void TSCADCEventInterruptEnable(unsigned int baseAdd, unsigned int event); -void TSCADCEventInterruptDisable(unsigned int baseAdd, unsigned int event); -void TSCADCTSStepFIFOSelConfig(unsigned int baseAdd, unsigned int stepSel, - unsigned int FIFOSel); -void TSCADCTSStepSampleDelayConfig(unsigned int baseAdd, unsigned int stepSel, - unsigned int delay); -void TSCADCTSStepOpenDelayConfig(unsigned int baseAdd, unsigned int stepSel, - unsigned int delay); - - -void TSCADCTSStepAverageConfig(unsigned int baseAdd, unsigned int stepSel, - unsigned int average); -void TSCADCTSStepConfig(unsigned int baseAdd, unsigned int stepSelect, - unsigned int adcNegativeRef, unsigned int adcPositiveInp, - unsigned int adcNegativeInp, unsigned int adcPositiveRef); - -void TSCADCConfigureAFEClock(unsigned int baseAdd, unsigned int moduleClk, - unsigned int inputClk); -void TSCADCADCOutputRangeConfig(unsigned int baseAdd, unsigned short lowVal, - unsigned short highVal); -void TSCADCTSStepOperationModeControl(unsigned int baseAdd, unsigned int mode, - unsigned int stepSelect); -void TSCADCTSStepAnalogSupplyConfig(unsigned int baseAdd, unsigned int xppsw, - unsigned int xnpsw, unsigned int yppsw, - unsigned int stepSelect); -void TSCADCTSStepAnalogGroundConfig(unsigned int baseAdd, unsigned int xnnsw, - unsigned int ypnsw, unsigned int ynnsw, - unsigned int wpnsw, unsigned int stepSelect); -void TSCADCChargeStepAnalogSupplyConfig(unsigned int baseAdd, unsigned int xppsw, - unsigned int xnpsw, unsigned int yppsw); -void TSCADCChargeStepAnalogSupplyConfig(unsigned int baseAdd, unsigned int xppsw, - unsigned int xnpsw, unsigned int yppsw); -void TSCADCIdleStepConfig(unsigned int baseAdd, unsigned int adcNegativeRef, - unsigned int adcPositiveInp, unsigned int adcNegativeInp, - unsigned int adcPositiveRef); -void TSCADCConfigureMisc(unsigned int baseAdd, unsigned char spareInputVal, - unsigned char spareOutputVal); -void TSCADCConfigureStepEnable(unsigned int baseAdd, unsigned int stepSel, - unsigned int stepEn_Dis); -void TSCADCIdleStepAnalogSupplyConfig(unsigned int baseAdd, unsigned int xppsw, - unsigned int xnpsw, unsigned int yppsw); -void TSCADCIdleStepAnalogGroundConfig(unsigned int baseAdd, unsigned int xnnsw, - unsigned int ypnsw, unsigned int ynnsw, - unsigned int wpnsw); -void TSCADCChargeStepConfig(unsigned int baseAdd, unsigned int adcNegativeRef, - unsigned int adcPositiveInp,unsigned int adcNegativeInp, - unsigned int adcPositiveRef); -void TSCADCChargeStepAnalogGroundConfig(unsigned int baseAdd, unsigned int xnnsw, - unsigned int ypnsw, unsigned int ynnsw, - unsigned int wpnsw); -void TSCADCModuleStateSet(unsigned int baseAdd, unsigned int enableModule); -void TSCADCRawIntStatusSet(unsigned int baseAdd, unsigned int intFlag); -void TSCADCStepIDTagConfig(unsigned int baseAdd, unsigned int enableStepIDTag); -unsigned int TSCADCFIFOADCDataRead(unsigned int baseAdd, unsigned int FIFOSel); -unsigned int TSCADCIsDMAFIFOEnabled(unsigned int baseAdd, unsigned int fifoSel); -unsigned int TSCADCIntStatusRead(unsigned int baseAdd, unsigned int intFlag); -void TSCADCWakeUpPenEventConfig(unsigned int baseAdd, unsigned int enableWakeUp); -unsigned int TSCADCFIFOWordCountRead(unsigned int baseAdd, unsigned int FIFOSel); -unsigned int TSCADCFIFOChannelIDRead(unsigned int baseAdd, unsigned int FIFOSel); -void TSCADCIdleStepOperationModeControl(unsigned int baseAdd, unsigned int mode); -void TSCADCTSStepOutOfRangeCheckEnable(unsigned int baseAdd, unsigned int stepSel); -void TSCADCTSStepOutOfRangeCheckDisable(unsigned int baseAdd, unsigned int stepSel); -unsigned int TSCADCRawIntStatusRead(unsigned int baseAdd, unsigned int intFlag); -void TSCADCChargeStepOperationModeControl(unsigned int baseAdd, unsigned int mode); -void TSCADCTSTransistorConfig(unsigned int baseAdd, unsigned int enableTSTransistor); -void TSCADCConfigHWEventPrempt(unsigned int baseAdd, unsigned int enableHWEventPreempt); -void TSCADCFIFOIRQThresholdLevelConfig(unsigned int baseAdd, unsigned char FIFOSel, - unsigned char numberOfSamples); -void TSCADCFIFODMAThresholdLevelConfig(unsigned int baseAdd, - unsigned int FIFOSel, - unsigned int numberOfSamples); - -unsigned int TSCADCIntStatus(unsigned int baseAdd); - -typedef struct { - signed int x; - signed int y; - }POINT; - - -typedef struct { - signed int Divider; - signed int An; - signed int Bn; - signed int Cn; - signed int Dn; - signed int En; - signed int Fn; - }MATRIX; - -#endif diff --git a/lib/tiam1808/tiam1808/uart_irda_cir.h b/lib/tiam1808/tiam1808/uart_irda_cir.h deleted file mode 100644 index 3adff0b2c..000000000 --- a/lib/tiam1808/tiam1808/uart_irda_cir.h +++ /dev/null @@ -1,639 +0,0 @@ -/** - * \file uart_irda_cir.h - * - * \brief This file contains the prototyes of the functions defined in - * . This also contains some related macro - * definitions and some files to be included. - * - */ - -/* -* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -*/ -/* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -#ifndef _UART_IRDA_CIR_H_ -#define _UART_IRDA_CIR_H_ - -#include "hw_uart_irda_cir.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/**************************************************************************** -** MACRO DEFINITIONS -****************************************************************************/ - -/* -** Values to configure the Operating modes of UART. -*/ -#define UART16x_OPER_MODE (UART_MDR1_MODE_SELECT_UART16X) -#define UART_SIR_OPER_MODE (UART_MDR1_MODE_SELECT_SIR) -#define UART16x_AUTO_BAUD_OPER_MODE (UART_MDR1_MODE_SELECT_UART16XAUTO) -#define UART13x_OPER_MODE (UART_MDR1_MODE_SELECT_UART13X) -#define UART_MIR_OPER_MODE (UART_MDR1_MODE_SELECT_MIR) -#define UART_FIR_OPER_MODE (UART_MDR1_MODE_SELECT_FIR) -#define UART_CIR_OPER_MODE (UART_MDR1_MODE_SELECT_CIR) -#define UART_DISABLED_MODE (UART_MDR1_MODE_SELECT_DISABLED) - -/****************************************************************************/ -/* -** Values to control the Line characteristics. -*/ - -/* Break condition generation controls. */ -#define UART_BREAK_COND_DISABLE (UART_LCR_BREAK_EN_NORMAL << \ - UART_LCR_BREAK_EN_SHIFT) -#define UART_BREAK_COND_ENABLE (UART_LCR_BREAK_EN_FORCE << \ - UART_LCR_BREAK_EN_SHIFT) - -/* Values to control parity feature. */ - -#define UART_ODD_PARITY_REPR_1 (UART_LCR_PARITY_TYPE2 | \ - (UART_LCR_PARITY_TYPE1_ODD << \ - UART_LCR_PARITY_TYPE1_SHIFT) | \ - UART_LCR_PARITY_EN) - -#define UART_EVEN_PARITY_REPR_0 (UART_LCR_PARITY_TYPE2 | \ - (UART_LCR_PARITY_TYPE1_EVEN << \ - UART_LCR_PARITY_TYPE1_SHIFT) | \ - UART_LCR_PARITY_EN) - -#define UART_ODD_PARITY ((UART_LCR_PARITY_TYPE1_ODD << \ - UART_LCR_PARITY_TYPE1_SHIFT) | \ - UART_LCR_PARITY_EN) - -#define UART_EVEN_PARITY ((UART_LCR_PARITY_TYPE1_EVEN << \ - UART_LCR_PARITY_TYPE1_SHIFT) | \ - UART_LCR_PARITY_EN) - -#define UART_PARITY_NONE (UART_LCR_PARITY_EN_DISABLE << \ - UART_LCR_PARITY_EN_SHIFT) - - -/* Number of Stop Bits per frame. */ - -#define UART_FRAME_NUM_STB_1 (UART_LCR_NB_STOP_1BIT << \ - UART_LCR_NB_STOP_SHIFT) -#define UART_FRAME_NUM_STB_1_5_2 (UART_LCR_NB_STOP_2BIT << \ - UART_LCR_NB_STOP_SHIFT) - -/* Word Length per frame. */ - -#define UART_FRAME_WORD_LENGTH_5 (UART_LCR_CHAR_LENGTH_5BIT) -#define UART_FRAME_WORD_LENGTH_6 (UART_LCR_CHAR_LENGTH_6BIT) -#define UART_FRAME_WORD_LENGTH_7 (UART_LCR_CHAR_LENGTH_7BIT) -#define UART_FRAME_WORD_LENGTH_8 (UART_LCR_CHAR_LENGTH_8BIT) - -/****************************************************************************/ -/* -** Values associated with setting the Trigger Levels and DMA mode selection. -*/ - -/* Values for trigger level for the Receiver FIFO. */ - -#define UART_FCR_RX_TRIG_LVL_8 (UART_FCR_RX_FIFO_TRIG_8CHAR << \ - UART_FCR_RX_FIFO_TRIG_SHIFT) -#define UART_FCR_RX_TRIG_LVL_16 (UART_FCR_RX_FIFO_TRIG_16CHAR << \ - UART_FCR_RX_FIFO_TRIG_SHIFT) -#define UART_FCR_RX_TRIG_LVL_56 (UART_FCR_RX_FIFO_TRIG_56CHAR << \ - UART_FCR_RX_FIFO_TRIG_SHIFT) -#define UART_FCR_RX_TRIG_LVL_60 (UART_FCR_RX_FIFO_TRIG_60CHAR << \ - UART_FCR_RX_FIFO_TRIG_SHIFT) - - -/* Values for the trigger level for the Transmitter FIFO. */ - -#define UART_FCR_TX_TRIG_LVL_8 (UART_FCR_TX_FIFO_TRIG_8SPACES << \ - UART_FCR_TX_FIFO_TRIG_SHIFT) -#define UART_FCR_TX_TRIG_LVL_16 (UART_FCR_TX_FIFO_TRIG_16SPACES << \ - UART_FCR_TX_FIFO_TRIG_SHIFT) -#define UART_FCR_TX_TRIG_LVL_32 (UART_FCR_TX_FIFO_TRIG_32SPACES << \ - UART_FCR_TX_FIFO_TRIG_SHIFT) -#define UART_FCR_TX_TRIG_LVL_56 (UART_FCR_TX_FIFO_TRIG_56SPACES << \ - UART_FCR_TX_FIFO_TRIG_SHIFT) - -/* Values corresponding to DMA mode selection. */ - -#define UART_DMA_MODE_0_ENABLE (UART_SCR_DMA_MODE_2_MODE0) -#define UART_DMA_MODE_1_ENABLE (UART_SCR_DMA_MODE_2_MODE1) -#define UART_DMA_MODE_2_ENABLE (UART_SCR_DMA_MODE_2_MODE2) -#define UART_DMA_MODE_3_ENABLE (UART_SCR_DMA_MODE_2_MODE3) - -/* -** Values used to choose the path for configuring the DMA Mode. -** DMA Mode could be configured either through FCR or SCR. -*/ -#define UART_DMA_EN_PATH_FCR (UART_SCR_DMA_MODE_CTL_FCR) -#define UART_DMA_EN_PATH_SCR (UART_SCR_DMA_MODE_CTL_SCR) - -/****************************************************************************/ -/* -** Values related to enabling/disabling of Interrupts. -*/ - -/* Values for enabling/disabling the interrupts of UART. */ - -#define UART_INT_CTS (UART_IER_CTS_IT) -#define UART_INT_RTS (UART_IER_RTS_IT) -#define UART_INT_XOFF (UART_IER_XOFF_IT) -#define UART_INT_SLEEPMODE (UART_IER_SLEEP_MODE_IT) -#define UART_INT_MODEM_STAT (UART_IER_MODEM_STS_IT) -#define UART_INT_LINE_STAT (UART_IER_LINE_STS_IT) -#define UART_INT_THR (UART_IER_THR_IT) -#define UART_INT_RHR_CTI (UART_IER_RHR_IT) - -/****************************************************************************/ -/* -** Values related to Line Status information. -*/ - -/* Values pertaining to UART Line Status information. */ - -#define UART_FIFO_PE_FE_BI_DETECTED (UART_LSR_RX_FIFO_STS) -#define UART_BREAK_DETECTED_ERROR (UART_LSR_RX_BI) -#define UART_FRAMING_ERROR (UART_LSR_RX_FE) -#define UART_PARITY_ERROR (UART_LSR_RX_PE) -#define UART_OVERRUN_ERROR (UART_LSR_RX_OE) - -/****************************************************************************/ -/* -** Values related to status of Interrupt souces. -*/ - -/* Values pertaining to status of UART Interrupt sources. */ - -#define UART_INTID_MODEM_STAT (UART_IIR_IT_TYPE_MODEMINT << \ - UART_IIR_IT_TYPE_SHIFT) -#define UART_INTID_TX_THRES_REACH (UART_IIR_IT_TYPE_THRINT << \ - UART_IIR_IT_TYPE_SHIFT) -#define UART_INTID_RX_THRES_REACH (UART_IIR_IT_TYPE_RHRINT << \ - UART_IIR_IT_TYPE_SHIFT) -#define UART_INTID_RX_LINE_STAT_ERROR (UART_IIR_IT_TYPE_RXSTATUSERROR << \ - UART_IIR_IT_TYPE_SHIFT) -#define UART_INTID_CHAR_TIMEOUT (UART_IIR_IT_TYPE_RXTIMEOUT << \ - UART_IIR_IT_TYPE_SHIFT) -#define UART_INTID_XOFF_SPEC_CHAR_DETECT (UART_IIR_IT_TYPE_XOFF << \ - UART_IIR_IT_TYPE_SHIFT) -#define UART_INTID_MODEM_SIG_STATE_CHANGE (UART_IIR_IT_TYPE_STATECHANGE << \ - UART_IIR_IT_TYPE_SHIFT) - -/* Values indicating the UART Interrupt pending status. */ -#define UART_INT_PENDING (0) -#define UART_N0_INT_PENDING (1) - - -/****************************************************************************/ -/* -** Values pertaining to control of Enhanced Features. -*/ - -/* Values for controlling Auto-CTS and Auto-RTS features. */ - -#define UART_AUTO_CTS_ENABLE (UART_EFR_AUTO_CTS_EN) -#define UART_AUTO_CTS_DISABLE (UART_EFR_AUTO_CTS_EN_NORMAL) - -#define UART_AUTO_RTS_ENABLE (UART_EFR_AUTO_RTS_EN) -#define UART_AUTO_RTS_DISABLE (UART_EFR_AUTO_RTS_EN_NORMAL) - -/* Values to enable/disable detection of Special Character. */ - -#define UART_SPECIAL_CHAR_DETECT_ENABLE (UART_EFR_SPECIAL_CHAR_DETECT) -#define UART_SPECIAL_CHAR_DETECT_DISABLE (UART_EFR_SPECIAL_CHAR_DETECT_NORMAL) - - -/* Values to configure the options for Software Flow Control. */ - -#define UART_NO_SOFTWARE_FLOW_CONTROL ((UART_EFR_SW_FLOW_CONTROL_TX_NONE << \ - UART_EFR_SW_FLOW_CONTROL_TX_SHIFT) | \ - (UART_EFR_SW_FLOW_CONTROL_RX_NONE << \ - UART_EFR_SW_FLOW_CONTROL_RX_SHIFT)) - -#define UART_TX_RX_XON1_XOFF1 ((UART_EFR_SW_FLOW_CONTROL_TX_XONOFF1 << \ - UART_EFR_SW_FLOW_CONTROL_TX_SHIFT) | \ - (UART_EFR_SW_FLOW_CONTROL_RX_XONOFF1 << \ - UART_EFR_SW_FLOW_CONTROL_RX_SHIFT)) - -#define UART_TX_RX_XON2_XOFF2 ((UART_EFR_SW_FLOW_CONTROL_TX_XONOFF2 << \ - UART_EFR_SW_FLOW_CONTROL_TX_SHIFT) | \ - (UART_EFR_SW_FLOW_CONTROL_RX_XONOFF2 << \ - UART_EFR_SW_FLOW_CONTROL_RX_SHIFT)) - -#define UART_TX_RX_XON1_XOFF1_XON2_XOFF2 ((UART_EFR_SW_FLOW_CONTROL_TX_XONOFF1AND2 << \ - UART_EFR_SW_FLOW_CONTROL_TX_SHIFT) | \ - (UART_EFR_SW_FLOW_CONTROL_RX_XONOFF1AND2 << \ - UART_EFR_SW_FLOW_CONTROL_RX_SHIFT)) - -/****************************************************************************/ -/* -** Values corresponding to Mode Definition Register 2. -*/ - -/* Values to enable/disable Pulse shaping for UART. */ -#define UART_PULSE_NORMAL (UART_MDR2_UART_PULSE_NORMAL << \ - UART_MDR2_UART_PULSE_SHIFT) -#define UART_PULSE_SHAPING (UART_MDR2_UART_PULSE_SHAPING << \ - UART_MDR2_UART_PULSE_SHIFT) - - -/****************************************************************************/ -/* -** Macros related to control and status of Modem Signals. -*/ - -/* Values to enable/disable XON any feature. */ - -#define UART_XON_ANY_ENABLE (UART_MCR_XON_EN_ENABLE << \ - UART_MCR_XON_EN_SHIFT) -#define UART_XON_ANY_DISABLE (UART_MCR_XON_EN_DISABLE << \ - UART_MCR_XON_EN_SHIFT) - -/* Values to enable/disable Loopback mode of operation. */ - -#define UART_LOOPBACK_MODE_ENABLE (UART_MCR_LOOPBACK_EN_LOOPBACK << \ - UART_MCR_LOOPBACK_EN_SHIFT) -#define UART_LOOPBACK_MODE_DISABLE (UART_MCR_LOOPBACK_EN_NORMAL << \ - UART_MCR_LOOPBACK_EN_SHIFT) - -/* Macros used to force the Modem Control lines to active/inactive states. */ - -#define UART_DCD_CONTROL (UART_MCR_CD_STS_CH) -#define UART_RI_CONTROL (UART_MCR_RI_STS_CH) -#define UART_RTS_CONTROL (UART_MCR_RTS) -#define UART_DTR_CONTROL (UART_MCR_DTR) - - -/* Values that indicate the values on Modem Control lines. */ - -#define UART_DCD_VALUE (UART_MSR_NCD_STS) -#define UART_RI_VALUE (UART_MSR_NRI_STS) -#define UART_DSR_VALUE (UART_MSR_NDSR_STS) -#define UART_CTS_VALUE (UART_MSR_NCTS_STS) - -/* Values used to detect the changes in Modem Control lines. */ - -#define UART_DCD_STS_CHANGED (UART_MSR_DCD_STS) -#define UART_RI_STS_CHANGED (UART_MSR_RI_STS) -#define UART_DSR_STS_CHANGED (UART_MSR_DSR_STS) -#define UART_CTS_STS_CHANGED (UART_MSR_CTS_STS) - - -/****************************************************************************/ -/* -** Values related to the control and status of Supplementary registers. -*/ - -/* -** Values used to enable/disable a granularity of 1 for TX and RX FIFO trigger -** levels. -*/ -#define UART_RX_TRIG_LVL_GRAN_1_DISABLE (UART_SCR_RX_TRIG_GRANU1_DISABLE << \ - UART_SCR_RX_TRIG_GRANU1_SHIFT) -#define UART_RX_TRIG_LVL_GRAN_1_ENABLE (UART_SCR_RX_TRIG_GRANU1_ENABLE << \ - UART_SCR_RX_TRIG_GRANU1_SHIFT) - -#define UART_TX_TRIG_LVL_GRAN_1_DISABLE (UART_SCR_TX_TRIG_GRANU1_DISABLE << \ - UART_SCR_TX_TRIG_GRANU1_SHIFT) -#define UART_TX_FIFO_LVL_GRAN_1_ENABLE (UART_SCR_TX_TRIG_GRANU1_ENABLE << \ - UART_SCR_TX_TRIG_GRANU1_SHIFT) - -/* Value used to enable/disable DSRn interrupt. */ - -#define UART_DSRn_INT_DISABLE (UART_SCR_DSR_IT_DISABLE << \ - UART_SCR_DSR_IT_SHIFT) -#define UART_DSRn_INT_ENABLE (UART_SCR_DSR_IT_ENABLE << \ - UART_SCR_DSR_IT_SHIFT) - -/* Values to control the module Wake-Up rights for RX, CTSn and DSRn pins. */ - -#define UART_RX_CTS_DSR_WAKEUP_DISABLE (UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_DISABLE << \ - UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_SHIFT) -#define UART_RX_CTS_DSR_WAKEUP_ENABLE (UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_ENABLE << \ - UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_SHIFT) - -/* Values to control the THR interrupt modes. */ - -#define UART_THR_INT_NORMAL (UART_SCR_TX_EMPTY_CTL_IT_NORMAL << \ - UART_SCR_TX_EMPTY_CTL_IT_SHIFT) -#define UART_THR_INT_FIFO_TSR_EMPTY (UART_SCR_TX_EMPTY_CTL_IT_EMPTY << \ - UART_SCR_TX_EMPTY_CTL_IT_SHIFT) - -/* Values to control the DMA counter reset features. */ - -#define UART_DMA_CNTR_NO_RESET_FIFO_RESET (UART_SSR_DMA_COUNTER_RST_MODE0 << \ - UART_SSR_DMA_COUNTER_RST_SHIFT) -#define UART_DMA_CNTR_RESET_FIFO_RESET (UART_SSR_DMA_COUNTER_RST_MODE1 << \ - UART_SSR_DMA_COUNTER_RST_SHIFT) - -/* Values indicating the Falling edge status on RX, CTSn and DSRn pins. */ - -#define UART_RX_CTS_DSR_NO_FALL_EDGE (UART_SSR_RX_CTS_DSR_WAKE_UP_STS_NONE << \ - UART_SSR_RX_CTS_DSR_WAKE_UP_STS_SHIFT) -#define UART_RX_CTS_DSR_FALL_EDGE (UART_SSR_RX_CTS_DSR_WAKE_UP_STS_DETECTED << \ - UART_SSR_RX_CTS_DSR_WAKE_UP_STS_SHIFT) - -/* Values indicating the filled status of TX FIFO. */ - -#define UART_TX_FIFO_NOT_FULL (UART_SSR_TX_FIFO_FULL_NOTFULL) -#define UART_TX_FIFO_FULL (UART_SSR_TX_FIFO_FULL_FULL) - -/****************************************************************************/ -/* -** Values related to Auxilliary Control Register(ACREG). -*/ - -/* Values to set/clear the SD pin. */ - -#define UART_SD_PIN_LOW (UART_ACREG_SD_MOD_LOW << \ - UART_ACREG_SD_MOD_SHIFT) -#define UART_SD_PIN_HIGH (UART_ACREG_SD_MOD_HIGH << \ - UART_ACREG_SD_MOD_SHIFT) - -/****************************************************************************/ -/* -** Values controlling System Configuration functions. -*/ - -/* Values controlling Power Management Request/Acknowledgement modes. */ - -#define UART_IDLEMODE_FORCE_IDLE (UART_SYSC_IDLEMODE_FORCE << \ - UART_SYSC_IDLEMODE_SHIFT) -#define UART_IDLEMODE_NO_IDLE (UART_SYSC_IDLEMODE_NOIDLE << \ - UART_SYSC_IDLEMODE_SHIFT) -#define UART_IDLEMODE_SMART_IDLE (UART_SYSC_IDLEMODE_SMART << \ - UART_SYSC_IDLEMODE_SHIFT) -#define UART_IDLEMODE_SMART_IDLE_WAKEUP (UART_SYSC_IDLEMODE_WAKEUP << \ - UART_SYSC_IDLEMODE_SHIFT) - -/* Values enabling/disabling WakeUp capability. */ - -#define UART_WAKEUP_ENABLE (UART_SYSC_ENAWAKEUP_ENABLE << \ - UART_SYSC_ENAWAKEUP_SHIFT) -#define UART_WAKEUP_DISABLE (UART_SYSC_ENAWAKEUP_DISABLE << \ - UART_SYSC_ENAWAKEUP_SHIFT) - -/* Values to enable /disable Autoidle mode. */ -#define UART_AUTO_IDLE_MODE_ENABLE (UART_SYSC_AUTOIDLE_ENABLE) -#define UART_AUTO_IDLE_MODE_DISABLE (UART_SYSC_AUTOIDLE_DISABLE) - -/****************************************************************************/ -/* -** Values configuring Wake-up modes for the UART in Wake-Up Enable Register. -*/ - -/* Values that enable/disable Wake-Up generation ability for various signals. */ -#define UART_WAKEUP_TX_INTERRUPT (UART_WER_EVENT_7_TX_WAKEUP_EN) -#define UART_WAKEUP_RLS_INTERRUPT (UART_WER_EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT) -#define UART_WAKEUP_RHR_INTERRUPT (UART_WER_EVENT_5_RHR_INTERRUPT) -#define UART_WAKEUP_RX_ACTIVITY (UART_WER_EVENT_4_RX_ACTIVITY) -#define UART_WAKEUP_DCD_ACTIVITY (UART_WER_EVENT_3_DCD_CD_ACTIVITY) -#define UART_WAKEUP_RI_ACTIVITY (UART_WER_EVENT_2_RI_ACTIVITY) -#define UART_WAKEUP_DSR_ACTIVITY (UART_WER_EVENT_1_DSR_ACTIVITY) -#define UART_WAKEUP_CTS_ACTIVITY (UART_WER_EVENT_0_CTS_ACTIVITY) - -/****************************************************************************/ -/* -** Values indicating the line characteristics of UART Autobauding mode -** communication. -*/ - -/* Values indicating the parity in UART Autobauding mode. */ - -#define UART_AUTOBAUD_NO_PARITY (UART_UASR_PARITY_TYPE_NONE << \ - UART_UASR_PARITY_TYPE_SHIFT) -#define UART_AUTOBAUD_PARITY_SPACE (UART_UASR_PARITY_TYPE_SPACE << \ - UART_UASR_PARITY_TYPE_SHIFT) -#define UART_AUTOBAUD_EVEN_PARITY (UART_UASR_PARITY_TYPE_EVEN << \ - UART_UASR_PARITY_TYPE_SHIFT) -#define UART_AUTOBAUD_ODD_PARITY (UART_UASR_PARITY_TYPE_ODD << \ - UART_UASR_PARITY_TYPE_SHIFT) - -/* Values indicating the word length in UART Autobaud mode. */ - -#define UART_AUTOBAUD_CHAR_LENGTH_7 (UART_UASR_BIT_BY_CHAR_7BITS << \ - UART_UASR_BIT_BY_CHAR_SHIFT) -#define UART_AUTOBAUD_CHAR_LENGTH_8 (UART_UASR_BIT_BY_CHAR_8BITS << \ - UART_UASR_BIT_BY_CHAR_SHIFT) - -/* Values indicating the baud rate in UART Autobaud mode. */ - -#define UART_AUTOBAUD_NO_SPEED_IDEN (UART_UASR_SPEED_NONE) -#define UART_AUTOBAUD_SPEED_115200 (UART_UASR_SPEED_115200) -#define UART_AUTOBAUD_SPEED_57600 (UART_UASR_SPEED_57600) -#define UART_AUTOBAUD_SPEED_38400 (UART_UASR_SPEED_38400) -#define UART_AUTOBAUD_SPEED_28800 (UART_UASR_SPEED_28800) -#define UART_AUTOBAUD_SPEED_19200 (UART_UASR_SPEED_19200) -#define UART_AUTOBAUD_SPEED_14400 (UART_UASR_SPEED_14400) -#define UART_AUTOBAUD_SPEED_9600 (UART_UASR_SPEED_9600) -#define UART_AUTOBAUD_SPEED_4800 (UART_UASR_SPEED_4800) -#define UART_AUTOBAUD_SPEED_2400 (UART_UASR_SPEED_2400) -#define UART_AUTOBAUD_SPEED_1200 (UART_UASR_SPEED_1200) - -/****************************************************************************/ -/* -** Miscellaneous macros. -*/ -/* -** Values used to choose the trigger level granularity. -*/ -#define UART_TRIG_LVL_GRANULARITY_4 (0x0000) -#define UART_TRIG_LVL_GRANULARITY_1 (0x0001) - -/* Values to be used while switching between register configuration modes. */ - -#define UART_REG_CONFIG_MODE_A (0x0080) -#define UART_REG_CONFIG_MODE_B (0x00BF) -#define UART_REG_OPERATIONAL_MODE (0x007F) - -/* Parameterized macro to configure the FIFO settings. */ -#define UART_FIFO_CONFIG(txGra, rxGra, txTrig, rxTrig, txClr, rxClr, dmaEnPath, dmaMode) \ - ((unsigned int) \ - (((txGra & 0xF) << 26) | \ - ((rxGra & 0xF) << 22) | \ - ((txTrig & 0xFF) << 14) | \ - ((rxTrig & 0xFF) << 6) | \ - ((txClr & 0x1) << 5) | \ - ((rxClr & 0x1) << 4) | \ - ((dmaEnPath & 0x1) << 3) | \ - (dmaMode & 0x7))) - -#define UART_FIFO_CONFIG_TXGRA (0xF << 26) -#define UART_FIFO_CONFIG_RXGRA (0xF << 22) -#define UART_FIFO_CONFIG_TXTRIG (0xFF << 14) -#define UART_FIFO_CONFIG_RXTRIG (0xFF << 6) -#define UART_FIFO_CONFIG_TXCLR (0x1 << 5) -#define UART_FIFO_CONFIG_RXCLR (0x1 << 4) -#define UART_FIFO_CONFIG_DMAENPATH (0x1 << 3) -#define UART_FIFO_CONFIG_DMAMODE (0x7 << 0) - -/* Parameterized macro used to determine a value to be written to FCR. */ -#define UART_FCR_PROGRAM(rxFIFOTrig, txFIFOTrig, dmaMode, txClr, rxClr, fifoEn) \ - ((unsigned int) \ - (((rxFIFOTrig & 0x3) << 6) | \ - ((txFIFOTrig & 0x3) << 4) | \ - ((dmaMode & 0x1) << 3) | \ - ((txClr & 0x1) << 2) | \ - ((rxClr & 0x1) << 1) | \ - (fifoEn & 0x1))) - -/* Over-sampling rate for MIR mode used to obtain the Divisor Values. */ -#define UART_MIR_OVERSAMPLING_RATE_41 (41) -#define UART_MIR_OVERSAMPLING_RATE_42 (42) - -/****************************************************************************** -** FUNCTION PROTOTYPES -******************************************************************************/ - -/* APIs pertaining to UART. */ - -extern unsigned int UARTOperatingModeSelect(unsigned int baseAdd, - unsigned int modeFlag); -extern unsigned int UARTDivisorValCompute(unsigned int moduleClk, - unsigned int baudRate, - unsigned int modeFlag, - unsigned int mirOverSampRate); -extern unsigned int UARTDivisorLatchWrite(unsigned int baseAdd, - unsigned int divisorValue); -extern void UARTDivisorLatchEnable(unsigned int baseAdd); -extern void UARTDivisorLatchDisable(unsigned int baseAdd); -extern unsigned int UARTRegConfigModeEnable(unsigned int baseAdd, - unsigned int modeFlag); -extern void UARTRegConfModeRestore(unsigned int baseAdd, - unsigned int lcrRegValue); -extern void UARTBreakCtl(unsigned int baseAdd, unsigned int breakState); -extern void UARTLineCharacConfig(unsigned int baseAdd, - unsigned int wLenStbFlag, - unsigned int parityFlag); -extern void UARTParityModeSet(unsigned int baseAdd, unsigned int parityFlag); - -extern unsigned int UARTParityModeGet(unsigned int baseAdd); -extern void UARTDMAEnable(unsigned int baseAdd, unsigned int dmaModeFlag); -extern void UARTDMADisable(unsigned int baseAdd); -extern void UARTFIFOEnable(unsigned int baseAdd); -extern void UARTFIFODisable(unsigned int baseAdd); -extern unsigned int UARTFIFOConfig(unsigned int baseAdd, - unsigned int fifoConfig); -extern unsigned int UARTEnhanFuncEnable(unsigned int baseAdd); -extern void UARTEnhanFuncBitValRestore(unsigned int baseAdd, - unsigned int enhanFnBitVal); -extern unsigned int UARTSubConfigMSRSPRModeEn(unsigned int baseAdd); - -extern unsigned int UARTSubConfigTCRTLRModeEn(unsigned int baseAdd); -extern unsigned int UARTSubConfigXOFFModeEn(unsigned int baseAdd); -extern void UARTTCRTLRBitValRestore(unsigned int baseAdd, - unsigned int tcrTlrBitVal); -extern void UARTIntEnable(unsigned int baseAdd, unsigned int intFlag); -extern void UARTIntDisable(unsigned int baseAdd, unsigned int intFlag); -extern unsigned int UARTSpaceAvail(unsigned int baseAdd); -extern unsigned int UARTCharsAvail(unsigned int baseAdd); -extern unsigned int UARTCharPutNonBlocking(unsigned int baseAdd, - unsigned char byteWrite); -extern signed char UARTCharGetNonBlocking(unsigned int baseAdd); -extern signed char UARTCharGet(unsigned int baseAdd); - -extern void UARTCharPut(unsigned int baseAdd, unsigned char byteTx); -extern unsigned int UARTRxErrorGet(unsigned int baseAdd); -extern unsigned int UARTIntIdentityGet(unsigned int baseAdd); -extern unsigned int UARTIntPendingStatusGet(unsigned int baseAdd); -extern unsigned int UARTFIFOEnableStatusGet(unsigned int baseAdd); -extern void UARTAutoRTSAutoCTSControl(unsigned int baseAdd, - unsigned int autoCtsControl, - unsigned int autoRtsControl); -extern void UARTSpecialCharDetectControl(unsigned int baseAdd, - unsigned int controlFlag); -extern void UARTSoftwareFlowCtrlOptSet(unsigned int baseAdd, - unsigned int swFlowCtrl); -extern void UARTPulseShapingControl(unsigned int baseAdd, - unsigned int shapeControl); - -extern void UARTModuleReset(unsigned int baseAdd); -extern void UARTIdleModeConfigure(unsigned int baseAdd, unsigned int modeFlag); -extern void UARTWakeUpControl(unsigned int baseAdd, unsigned int controlFlag); -extern void UARTAutoIdleModeControl(unsigned int baseAdd, - unsigned int modeFlag); -extern void UARTFlowCtrlTrigLvlConfig(unsigned int baseAdd, - unsigned int rtsHaltFlag, - unsigned int rtsStartFlag); -extern void UARTXON1XOFF1ValProgram(unsigned int baseAdd, - unsigned char xon1Value, - unsigned char xoff1Value); -extern void UARTXON2XOFF2ValProgram(unsigned int baseAdd, - unsigned char xon2Value, - unsigned char xoff2Value); -extern void UARTXONAnyFeatureControl(unsigned int baseAdd, - unsigned int controlFlag); -extern void UARTLoopbackModeControl(unsigned int baseAdd, - unsigned int controlFlag); -extern void UARTModemControlSet(unsigned int baseAdd, unsigned int modeFlag); - -extern void UARTModemControlClear(unsigned int baseAdd, unsigned int modeFlag); -extern unsigned int UARTModemStatusGet(unsigned int baseAdd); -extern unsigned int UARTModemStatusChangeCheck(unsigned int baseAdd); -extern void UARTResumeOperation(unsigned int baseAdd); - -extern void UARTWakeUpEventsEnable(unsigned int baseAdd, - unsigned int wakeUpFlag); -extern void UARTWakeUpEventsDisable(unsigned int baseAdd, - unsigned int wakeUpFlag); -extern void UARTFIFOTrigLvlGranControl(unsigned int baseAdd, - unsigned int rxFIFOGranCtrl, - unsigned int txFIFOGranCtrl); -extern void UARTDSRInterruptControl(unsigned int baseAdd, - unsigned int controlFlag); -extern void UARTTxEmptyIntControl(unsigned int baseAdd, - unsigned int controlFlag); -extern void UARTRXCTSDSRWakeUpConfigure(unsigned int baseAdd, - unsigned int wakeUpFlag); -extern unsigned int UARTRXCTSDSRTransitionStatusGet(unsigned int baseAdd); - -extern void UARTDMACounterResetControl(unsigned int baseAdd, - unsigned int controlFlag); -extern unsigned int UARTTxFIFOFullStatusGet(unsigned int baseAdd); -extern unsigned int UARTAutobaudParityGet(unsigned int baseAdd); -extern unsigned int UARTAutobaudWordLenGet(unsigned int baseAdd); -extern unsigned int UARTAutobaudSpeedGet(unsigned int baseAdd); -extern void UARTScratchPadRegWrite(unsigned int baseAdd, - unsigned int scratchValue); -extern unsigned int UARTScratchPadRegRead(unsigned int baseAdd); -extern unsigned int UARTModuleVersionNumberGet(unsigned int baseAdd); -extern void UARTFIFORegisterWrite(unsigned int baseAdd, unsigned int fcrValue); - - -#ifdef __cplusplus -} -#endif - -#endif - -/********************************* End of File********************************/ -