diff --git a/lib/pbio/drv/block_device/block_device_ev3.c b/lib/pbio/drv/block_device/block_device_ev3.c
index 028fd8af7..8e1f6a669 100644
--- a/lib/pbio/drv/block_device/block_device_ev3.c
+++ b/lib/pbio/drv/block_device/block_device_ev3.c
@@ -192,8 +192,7 @@ static void spi_bus_init(void) {
     SPIReset(SOC_SPI_0_REGS);
     SPIOutOfReset(SOC_SPI_0_REGS);
     SPIModeConfigure(SOC_SPI_0_REGS, SPI_MASTER_MODE);
-    unsigned int spipc0 = SPI_SPIPC0_SOMIFUN | SPI_SPIPC0_SIMOFUN | SPI_SPIPC0_CLKFUN | SPI_SPIPC0_SCS0FUN0 | SPI_SPIPC0_SCS0FUN3;
-    SPIPinControl(SOC_SPI_0_REGS, 0, 0, &spipc0);
+    SPIPinControlSet(SOC_SPI_0_REGS, 0, SPI_SPIPC0_SOMIFUN | SPI_SPIPC0_SIMOFUN | SPI_SPIPC0_CLKFUN | SPI_SPIPC0_SCS0FUN0 | SPI_SPIPC0_SCS0FUN3);
     SPIDefaultCSSet(SOC_SPI_0_REGS, (1 << PBDRV_EV3_SPI0_FLASH_CS) | (1 << PBDRV_EV3_SPI0_ADC_CS));
 
     // SPI module data formats
diff --git a/lib/pbio/drv/display/display_ev3.c b/lib/pbio/drv/display/display_ev3.c
index e2a8a446b..a836d9023 100644
--- a/lib/pbio/drv/display/display_ev3.c
+++ b/lib/pbio/drv/display/display_ev3.c
@@ -429,9 +429,8 @@ static void pbdrv_display_ev3_spi_init(void) {
     SPIOutOfReset(SOC_SPI_1_REGS);
 
     // Mode.
-    uint32_t spipc0 = SPI_SPIPC0_SOMIFUN | SPI_SPIPC0_SIMOFUN | SPI_SPIPC0_CLKFUN | SPI_SPIPC0_ENAFUN;
     SPIModeConfigure(SOC_SPI_1_REGS, SPI_MASTER_MODE);
-    SPIPinControl(SOC_SPI_1_REGS, 0, 0, (unsigned int *)&spipc0);
+    SPIPinControlSet(SOC_SPI_1_REGS, 0, SPI_SPIPC0_SOMIFUN | SPI_SPIPC0_SIMOFUN | SPI_SPIPC0_CLKFUN | SPI_SPIPC0_ENAFUN);
 
     // Config.
     SPIClkConfigure(SOC_SPI_1_REGS, SOC_SYSCLK_2_FREQ, 10000000, SPI_DATA_FORMAT0);
diff --git a/lib/tiam1808/drivers/cppi41dma.c b/lib/tiam1808/drivers/cppi41dma.c
index b2720ea7b..2dd3eff1f 100644
--- a/lib/tiam1808/drivers/cppi41dma.c
+++ b/lib/tiam1808/drivers/cppi41dma.c
@@ -59,25 +59,25 @@
 
 static void Cppi41DmaModeSet(unsigned short usbDevInst, endpointInfo *epInfo);
 static void Cppi41DmaInitBdPool();
-static unsigned int Cppi41DmaReadCompletionQueue(unsigned short usbDevInst, 
+static unsigned int Cppi41DmaReadCompletionQueue(unsigned short usbDevInst,
 													unsigned int queueNum);
 
 static void Cppi41DmaConfigRxhostPacket(unsigned short usbDevInst, unsigned short chan,
 										unsigned int rxSubmitqA, unsigned int rxSubmitqB);
 
-static void Cppi41DmaConfigRxCompletionQueue(unsigned short usbDevInst, 
+static void Cppi41DmaConfigRxCompletionQueue(unsigned short usbDevInst,
 												unsigned short rxChan,unsigned int rxCompq);
-static void Cppi41DmaConfigTxCompletionQueue(unsigned short usbDevInst, 
+static void Cppi41DmaConfigTxCompletionQueue(unsigned short usbDevInst,
 												unsigned short txChan,unsigned int txCompq);
 
 static void Cppi41DmaClearINTD0Status(unsigned short usbDevInst);
 
 static void Cppi41DmaControlScheduler(unsigned short usbDevInst,
-												unsigned short enableDisable, 
+												unsigned short enableDisable,
 													unsigned short numOfentries);
 
-static void Cppi41DmaProcessBD( unsigned short usbDevInst, hostPacketDesc *current_bd, 
-											unsigned short direction, unsigned char * buffadd, 
+static void Cppi41DmaProcessBD( unsigned short usbDevInst, hostPacketDesc *current_bd,
+											unsigned short direction, unsigned char * buffadd,
 												unsigned int length, unsigned int ulEndpoint);
 static void cppi41DmaInitBuffer();
 
@@ -135,9 +135,9 @@ dmaDataBuffer dmaBuffer[CPDMA_NUMOF_BUFFERS]__attribute__((aligned(32)));
 
 /**
 * \brief	  This API initializes the DMA. This API should be called by the application
-*		  API .  API populates cppi Info structure according to the information 
+*		  API .  API populates cppi Info structure according to the information
 *		  passed from the application. This information is used by this API and all other
-*		  APIs. This API configures Channels queues and schedulers as per the 
+*		  APIs. This API configures Channels queues and schedulers as per the
 *		  information passed from the application.
 *
 * \param	  usbDevIns :- This is the USB device instance
@@ -149,20 +149,20 @@ dmaDataBuffer dmaBuffer[CPDMA_NUMOF_BUFFERS]__attribute__((aligned(32)));
 * \return	  None.
 *
 **/
-void Cppi41DmaInit(unsigned short usbDevInst, endpointInfo *epInfo, 
+void Cppi41DmaInit(unsigned short usbDevInst, endpointInfo *epInfo,
 						unsigned short numOfEndPoimts)
 {
-	/* This function need to be changed for porting to different SoC , 
+	/* This function need to be changed for porting to different SoC ,
 	 * to initialise base addresses and other details. */
-	
+
 	unsigned int descAddress = 0;
-	unsigned short i= 0;	
+	unsigned short i= 0;
 	usbInstance *usbInstance;
 #if defined (am335x_15x15) || defined(am335x)
 	unsigned short j = 0;
 #endif
 
-	usbInstance = &(cppiInfo.usbInst[usbDevInst]);	
+	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
 
 	/*Populate the CPPI info structure */
 	cppiInfo.head_bd = NULL;
@@ -170,7 +170,7 @@ void Cppi41DmaInit(unsigned short usbDevInst, endpointInfo *epInfo,
 
 #if defined (am335x_15x15) || defined(am335x)
 	for(i =0; i < 15; i++)
-	{	
+	{
 		/*TX Completion queues */
 		cppiInfo.txCompletionq[i]= TX_COMPQ1 + i;
 		/*RX Completion queues */
@@ -205,55 +205,55 @@ void Cppi41DmaInit(unsigned short usbDevInst, endpointInfo *epInfo,
 	cppiInfo.txSubmitq[2][1]=TX_SUBMITQ6;
 	cppiInfo.txSubmitq[3][0]=TX_SUBMITQ7;
 	cppiInfo.txSubmitq[3][1]=TX_SUBMITQ8;
-#endif	
+#endif
 
 	/*USB base address and OTG basse adress  for USB instance 0 */
 	cppiInfo.usbInst[0].usbBaseAddress = USB0_BASE;
 	cppiInfo.usbInst[0].otgBaseAddress = USB_OTGBASE;
-	
+
 	/*This function initializes the buffer Management system */
 	cppi41DmaInitBuffer();
 
-	/* This loop populates the RX and TX queues(both submission and completion queues), 
+	/* This loop populates the RX and TX queues(both submission and completion queues),
 	 * channels and dma mode for each end point */
 	for(i= 0;i< numOfEndPoimts;i++)
 	{
 		if((epInfo + i)->direction == CPDMA_DIR_RX)
 		{
-			usbInstance->rxEndPoint[(epInfo + i)->endPoint].channel = 
+			usbInstance->rxEndPoint[(epInfo + i)->endPoint].channel =
 												   (epInfo + i)->endPoint - 1;
-			
-			usbInstance->rxEndPoint[(epInfo + i)->endPoint].complettionq = 
+
+			usbInstance->rxEndPoint[(epInfo + i)->endPoint].complettionq =
 									 cppiInfo.rxCompletionq[(epInfo + i)->endPoint - 1];
-			
-			usbInstance->rxEndPoint[(epInfo + i)->endPoint].submitq = 
+
+			usbInstance->rxEndPoint[(epInfo + i)->endPoint].submitq =
 													(epInfo + i)->endPoint - 1;
-			
-			usbInstance->rxEndPoint[(epInfo + i)->endPoint].mode = 
+
+			usbInstance->rxEndPoint[(epInfo + i)->endPoint].mode =
 														(epInfo + i)->dmaMode;
 		}
 		else
 		{
-			usbInstance->txEndPoint[(epInfo + i)->endPoint].channel = 
+			usbInstance->txEndPoint[(epInfo + i)->endPoint].channel =
 													(epInfo + i)->endPoint - 1;
-			usbInstance->txEndPoint[(epInfo + i)->endPoint].complettionq = 
+			usbInstance->txEndPoint[(epInfo + i)->endPoint].complettionq =
 									cppiInfo.txCompletionq[(epInfo + i)->endPoint - 1];
-			
-			usbInstance->txEndPoint[(epInfo + i)->endPoint].submitq = 
+
+			usbInstance->txEndPoint[(epInfo + i)->endPoint].submitq =
 									 cppiInfo.txSubmitq[(epInfo + i)->endPoint - 1][0];
-			
-			usbInstance->txEndPoint[(epInfo + i)->endPoint].mode = 
+
+			usbInstance->txEndPoint[(epInfo + i)->endPoint].mode =
 														(epInfo + i)->dmaMode;
 		}
 	}
-	
+
 	/* Set  mode for each end pont*/
 	for(i = 0;i < numOfEndPoimts; i++)
 		Cppi41DmaModeSet(usbDevInst, &epInfo[i]);
-	
+
 	/*Link Ram setup	 */
 	HWREG(usbInstance->otgBaseAddress + CPDMA_LRAM_0_BASE) = (unsigned int)&linking_ram0[0];
-	HWREG(usbInstance->otgBaseAddress + CPDMA_LRAM_0_SIZE) = sizeof(linking_ram0); 
+	HWREG(usbInstance->otgBaseAddress + CPDMA_LRAM_0_SIZE) = sizeof(linking_ram0);
 	HWREG(usbInstance->otgBaseAddress + CPDMA_LRAM_1_BASE) = 0x0;
 
 	/*Queue region setup */
@@ -264,11 +264,11 @@ void Cppi41DmaInit(unsigned short usbDevInst, endpointInfo *epInfo,
 	/*Align the strating adress */
 	descAddress &= ~0x3F;
 	cppiInfo.region0DescriptorAddress = (unsigned int *)descAddress;
-	
-	HWREG(usbInstance->otgBaseAddress + CPDMA_QUEUEMGR_REGION_0)= 
+
+	HWREG(usbInstance->otgBaseAddress + CPDMA_QUEUEMGR_REGION_0)=
 									(unsigned int)cppiInfo.region0DescriptorAddress;
 	/*queue manager cotrol setup */
-	HWREG(usbInstance->otgBaseAddress + CPDMA_QUEUEMGR_REGION_0_CONTROL) = 
+	HWREG(usbInstance->otgBaseAddress + CPDMA_QUEUEMGR_REGION_0_CONTROL) =
 										QUEUE_MGR_DESCSIZE | QUEUE_MGR_REGSIZE;
 
 	/*initialize the  BD pool */
@@ -279,10 +279,10 @@ void Cppi41DmaInit(unsigned short usbDevInst, endpointInfo *epInfo,
 	{
 		if((epInfo + i)->direction == CPDMA_DIR_RX)
 			Cppi41DmaConfigRxhostPacket(usbDevInst, usbInstance
-				->rxEndPoint[(epInfo + i)->endPoint].channel, 
-				usbInstance->rxEndPoint[(epInfo + i)->endPoint].submitq, 
+				->rxEndPoint[(epInfo + i)->endPoint].channel,
+				usbInstance->rxEndPoint[(epInfo + i)->endPoint].submitq,
 				usbInstance->rxEndPoint[(epInfo + i)->endPoint].submitq);
-		
+
 	}
 
 	/*configure the RX and TX completion queues for each end point */
@@ -293,7 +293,7 @@ void Cppi41DmaInit(unsigned short usbDevInst, endpointInfo *epInfo,
 		 	Cppi41DmaConfigRxCompletionQueue(usbDevInst, usbInstance
 		 	->rxEndPoint[(epInfo + i)->endPoint].channel, usbInstance
 		 					->rxEndPoint[(epInfo + i)->endPoint].complettionq);
-		}	
+		}
 		else
 		{
 		 	Cppi41DmaConfigTxCompletionQueue(usbDevInst, usbInstance
@@ -308,10 +308,10 @@ void Cppi41DmaInit(unsigned short usbDevInst, endpointInfo *epInfo,
 	HWREG(usbInstance->otgBaseAddress + CPDMA_SCHED_TABLE_1) = SCHEDULE_RX_CHANNEL;
 
 	/*Specify the number of entries in the scheduler table 0 */
-	HWREG(usbInstance->otgBaseAddress + CPDMA_SCHED_CONTROL_REG )= 
-								(ENABLE_CPPIDMA<< SCHEDULER_ENABLE_SHFT) | 
+	HWREG(usbInstance->otgBaseAddress + CPDMA_SCHED_CONTROL_REG )=
+								(ENABLE_CPPIDMA<< SCHEDULER_ENABLE_SHFT) |
 											(NUM_OF_SCHEDULER_ENTRIES - 1);
-	
+
 }
 
 /**
@@ -330,18 +330,18 @@ void Cppi41DmaModeSet(unsigned short usbDevInst, endpointInfo *epInfo)
 	usbInstance *usbInstance;
 
 	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
-	
+
 	/* Enable RNDIS from Global Level */
 	if (epInfo->dmaMode == CPDMA_MODE_SET_RNDIS)
 	{
 		HWREG(usbInstance->otgBaseAddress + USB_0_CTRL)|=
-												CPDMA_MODE_ENABLE_GLOBAL_RNDIS;	
+												CPDMA_MODE_ENABLE_GLOBAL_RNDIS;
 	}
-	
+
 	/* Disable RNDIS from Global Level	 */
 	else
 	{
-		HWREG(usbInstance->otgBaseAddress + USB_0_CTRL)&= 
+		HWREG(usbInstance->otgBaseAddress + USB_0_CTRL)&=
 												~CPDMA_MODE_ENABLE_GLOBAL_RNDIS;
 	}
 
@@ -351,7 +351,7 @@ void Cppi41DmaModeSet(unsigned short usbDevInst, endpointInfo *epInfo)
 		HWREG(usbInstance->otgBaseAddress + USB_0_MODE)|=
 					(epInfo->dmaMode << USB_TX_MODE_SHIFT(epInfo->endPoint));
 	}
-	
+
 	else
 	{
 		HWREG(usbInstance->otgBaseAddress + USB_0_MODE)|=
@@ -361,16 +361,16 @@ void Cppi41DmaModeSet(unsigned short usbDevInst, endpointInfo *epInfo)
 	/* For GRNDIS mode, set the maximum packet length */
 	if (epInfo->dmaMode == CPDMA_MODE_SET_GRNDIS)
 	{
-		HWREG(usbInstance->otgBaseAddress + USB_0_GEN_RNDIS_SIZE_EP1) = 
+		HWREG(usbInstance->otgBaseAddress + USB_0_GEN_RNDIS_SIZE_EP1) =
 			GRNDIS_MAX_PACKET_LENGTH;
 	}
 }
 
 
 /**
-* \brief	  This API enables the TX DMA for an endpoint. The API access the CSR 
-*		  register of  the particular endpoint to set appropriate bits. This API is 
-*		  called by the stack to enable DMA when it is requied. 
+* \brief	  This API enables the TX DMA for an endpoint. The API access the CSR
+*		  register of  the particular endpoint to set appropriate bits. This API is
+*		  called by the stack to enable DMA when it is requied.
 *
 * \param	  usbDevInst:- USB device instance
 *
@@ -379,7 +379,7 @@ void Cppi41DmaModeSet(unsigned short usbDevInst, endpointInfo *epInfo)
 * \return	  None.
 *
 **/
-void enableCoreTxDMA(unsigned short usbDevInst, unsigned int ulEndpoint) 
+void enableCoreTxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
 {
 	unsigned int ulRegister;
 	usbInstance *usbInstance;
@@ -393,18 +393,18 @@ void enableCoreTxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
 	while ((HWREGH(usbInstance->usbBaseAddress + ulRegister) & 0x2) == 0x02);
 
 	/* Clear Autoset */
-	HWREGH(usbInstance->usbBaseAddress + ulRegister)&= CPDMA_TX_CLR_AUTO_SET; 
+	HWREGH(usbInstance->usbBaseAddress + ulRegister)&= CPDMA_TX_CLR_AUTO_SET;
 
 	/* Set DMAReqEnab & DMAReqMode */
-	HWREGH(usbInstance->usbBaseAddress + ulRegister)|=CPDMA_TX_SET_REQ_ENABLE; 
+	HWREGH(usbInstance->usbBaseAddress + ulRegister)|=CPDMA_TX_SET_REQ_ENABLE;
 
 }
 
 
 /**
-* \brief	  This API enables the RX DMA for an endPoint.The API access the CSR 
-*		  register of  the particular endpoint to set appropriate bits. This API is 
-*		  called by the stack to enable DMA when it is requied. 
+* \brief	  This API enables the RX DMA for an endPoint.The API access the CSR
+*		  register of  the particular endpoint to set appropriate bits. This API is
+*		  called by the stack to enable DMA when it is requied.
 *
 * \param	  usbDevInst:- USB device instance
 *
@@ -419,7 +419,7 @@ void enableCoreRxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
 	usbInstance *usbInstance;
 
 	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
-	
+
 	/*Find out the RX CSR  address */
 	ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint);
 
@@ -430,20 +430,20 @@ void enableCoreRxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
 	Cppi41DmaControlScheduler(usbDevInst, ENABLE_CPPIDMA, NUM_OF_SCHEDULER_ENTRIES);
 
 	/*Configure the completion queue */
-	Cppi41DmaConfigRxCompletionQueue(usbDevInst, usbInstance->rxEndPoint[ulEndpoint].channel, 
-		 				 			usbInstance->rxEndPoint[ulEndpoint].complettionq);	
+	Cppi41DmaConfigRxCompletionQueue(usbDevInst, usbInstance->rxEndPoint[ulEndpoint].channel,
+		 				 			usbInstance->rxEndPoint[ulEndpoint].complettionq);
 
 	/* Clear AUTOCLEAR and DMAReqMode */
-	HWREGH(usbInstance->usbBaseAddress + ulRegister)&=CPDMA_RX_CLR_AUTO_CLEAR; 
-	
+	HWREGH(usbInstance->usbBaseAddress + ulRegister)&=CPDMA_RX_CLR_AUTO_CLEAR;
+
 	/* Set DMAReqEnab */
-	HWREGH(usbInstance->usbBaseAddress + ulRegister)|=CPDMA_RX_SET_REQ_ENABLE; 
+	HWREGH(usbInstance->usbBaseAddress + ulRegister)|=CPDMA_RX_SET_REQ_ENABLE;
 }
 
 /**
-* \brief	  This API disables the RX DMA for an endpoint. The API access the CSR 
-*		  register of  the particular endpoint to set appropriate bits. This API is 
-*		  Called by the stack to disable DMA when it is required 
+* \brief	  This API disables the RX DMA for an endpoint. The API access the CSR
+*		  register of  the particular endpoint to set appropriate bits. This API is
+*		  Called by the stack to disable DMA when it is required
 *
 * \param	  usbDevInst:- USB device instance
 *
@@ -452,7 +452,7 @@ void enableCoreRxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
 * \return	  None.
 *
 **/
-void disableCoreRxDMA(unsigned short usbDevInst, unsigned int ulEndpoint) 
+void disableCoreRxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
 {
 	unsigned int ulRegister;
 	usbInstance *usbInstance;
@@ -464,15 +464,15 @@ void disableCoreRxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
 
 	/*wait till completion of any previos transaction */
 	while ((HWREGH(usbInstance->usbBaseAddress + ulRegister) & 0x1) == 0x01);
-	
+
 	/* Clear DMAReqEnab */
-	HWREGH(usbInstance->usbBaseAddress + ulRegister)&= CPDMA_RX_CLR_REQ_ENABLE; 
+	HWREGH(usbInstance->usbBaseAddress + ulRegister)&= CPDMA_RX_CLR_REQ_ENABLE;
 }
 
 /**
-* \brief	  This API enables the TX DMA for an endpont. The API access the CSR 
-*		  register of  the particular endpoint to set appropriate bits. This API is 
-*		  Called by the stack to disable DMA when it is required 
+* \brief	  This API enables the TX DMA for an endpont. The API access the CSR
+*		  register of  the particular endpoint to set appropriate bits. This API is
+*		  Called by the stack to disable DMA when it is required
 *
 * \param	  usbDevInst:- USB device instance
 *
@@ -481,7 +481,7 @@ void disableCoreRxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
 * \return	  None.
 *
 **/
-void disableCoreTxDMA(unsigned short usbDevInst, unsigned int ulEndpoint) 
+void disableCoreTxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
 {
 	unsigned int ulRegister;
 	usbInstance *usbInstance;
@@ -490,16 +490,16 @@ void disableCoreTxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
 
 	ulRegister = USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint);
 	while ((HWREGH(usbInstance->usbBaseAddress + ulRegister) & 0x2) == 0x02);
-	
+
 	/* Clear AUTOSET */
 	HWREGH(usbInstance->usbBaseAddress + ulRegister)&=CPDMA_TX_CLR_AUTO_SET;
-	
+
 	/* Clear DMAReqEnab & DMAReqMode */
-	HWREGH(usbInstance->usbBaseAddress + ulRegister)&=CPDMA_TX_CLR_REQ_ENABLE; 
+	HWREGH(usbInstance->usbBaseAddress + ulRegister)&=CPDMA_TX_CLR_REQ_ENABLE;
 }
 
 /**
-* \brief	  This API reads the complettion queue. This is called from the stack when a completion 
+* \brief	  This API reads the complettion queue. This is called from the stack when a completion
 * 		   interrupt comes. RX/TX completion queue number can be passed as an argument to
 *		   this function. The function returns completed BD address.
 *
@@ -510,17 +510,17 @@ void disableCoreTxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
 * \return	  None.
 *
 **/
-unsigned int Cppi41DmaReadCompletionQueue(unsigned short usbDevInst, 
-														unsigned int queueNum) 
+unsigned int Cppi41DmaReadCompletionQueue(unsigned short usbDevInst,
+														unsigned int queueNum)
 {
 	unsigned int  descAddress;
 	usbInstance *usbInstance;
 
 	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
-	
+
 	/*Read the completetion queue register */
-	descAddress=(unsigned int)HWREG(usbInstance->otgBaseAddress + 
-							(CPDMA_QUEUE_REGISTER_D + QUEUE_OFFSET(queueNum)));	
+	descAddress=(unsigned int)HWREG(usbInstance->otgBaseAddress +
+							(CPDMA_QUEUE_REGISTER_D + QUEUE_OFFSET(queueNum)));
 	/*Extract the BD address  */
 	descAddress&=0xFFFFFFE0;
 	return(descAddress);
@@ -540,16 +540,16 @@ unsigned int Cppi41DmaReadCompletionQueue(unsigned short usbDevInst,
 * \return	  None.
 *
 **/
-void Cppi41DmaConfigRxhostPacket(unsigned short usbDevInst, unsigned short chan, 
+void Cppi41DmaConfigRxhostPacket(unsigned short usbDevInst, unsigned short chan,
 							unsigned int rxSubmitqA, unsigned int rxSubmitqB)
 {
 	usbInstance *usbInstance;
 
 	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
-	
-	HWREG(usbInstance->otgBaseAddress + (CPDMA_RX_CHANNEL_REG_A + 
+
+	HWREG(usbInstance->otgBaseAddress + (CPDMA_RX_CHANNEL_REG_A +
 											CHANNEL_OFFSET(chan))) = (rxSubmitqA | rxSubmitqA << 16);
-	HWREG(usbInstance->otgBaseAddress + (CPDMA_RX_CHANNEL_REG_B + 
+	HWREG(usbInstance->otgBaseAddress + (CPDMA_RX_CHANNEL_REG_B +
 											CHANNEL_OFFSET(chan))) = (rxSubmitqB | rxSubmitqB << 16) ;
 }
 
@@ -565,16 +565,16 @@ void Cppi41DmaConfigRxhostPacket(unsigned short usbDevInst, unsigned short chan,
 * \return	  None.
 *
 **/
-void Cppi41DmaConfigRxCompletionQueue(unsigned short usbDevInst, 
+void Cppi41DmaConfigRxCompletionQueue(unsigned short usbDevInst,
 								unsigned short rxChan,unsigned int rxCompq)
 {
 	usbInstance *usbInstance;
 
 	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
-	
-	HWREG(usbInstance->otgBaseAddress + (CPDMA_RX_CHANNEL_CONFIG_REG + 
+
+	HWREG(usbInstance->otgBaseAddress + (CPDMA_RX_CHANNEL_CONFIG_REG +
 				CHANNEL_OFFSET(rxChan))) = CPDMA_RX_CHANNEL_ENABLE	 | rxCompq;
-	
+
 }
 
 
@@ -590,13 +590,13 @@ void Cppi41DmaConfigRxCompletionQueue(unsigned short usbDevInst,
 * \return	  None.
 *
 **/
-void Cppi41DmaConfigTxCompletionQueue(unsigned short usbDevInst, 
-									unsigned short txChan, unsigned int txCompq)	
+void Cppi41DmaConfigTxCompletionQueue(unsigned short usbDevInst,
+									unsigned short txChan, unsigned int txCompq)
 {
 	usbInstance *usbInstance;
 
 	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
-	
+
 	HWREG(usbInstance->otgBaseAddress + (CPDMA_TX_CHANNEL_CONFIG_REG +
 				CHANNEL_OFFSET(txChan))) = 	CPDMA_TX_CHANNEL_ENABLE	 | txCompq;
 }
@@ -606,7 +606,7 @@ void Cppi41DmaConfigTxCompletionQueue(unsigned short usbDevInst,
 /**
 * \brief	 Initializes the BD pool
 *
-* \param	  
+* \param
 *
 * \return	  None.
 *
@@ -618,7 +618,7 @@ void Cppi41DmaInitBdPool()
 
 	temp_bd = (hostPacketDesc *)cppiInfo.region0DescriptorAddress;
 	for(i=0;i<MAX_BD_NUM; i++, temp_bd++)
-	{		
+	{
 		if(!cppiInfo.head_bd)
 		{
 			cppiInfo.head_bd = temp_bd;
@@ -639,7 +639,7 @@ void Cppi41DmaInitBdPool()
 /**
 * \brief	This API will get a free BD from the BD pool
 *
-* \param	  
+* \param
 *
 * \return	  None.
 *
@@ -649,13 +649,13 @@ hostPacketDesc * getFreeBd()
 	hostPacketDesc *free_bd;
 
 	free_bd = NULL;
-	
+
 	if(cppiInfo.head_bd)
 	{
 		free_bd = cppiInfo.head_bd;
 		cppiInfo.head_bd = cppiInfo.head_bd->nextHBDptr;
 		free_bd->nextHBDptr = NULL;
-	}	
+	}
 
 	return free_bd;
 }
@@ -663,7 +663,7 @@ hostPacketDesc * getFreeBd()
 /**
 * \brief	 This API puts the free BD back to the BD pool
 *
-* \param	  
+* \param
 *
 * \return	  None.
 *
@@ -678,8 +678,8 @@ void putFreeBd(hostPacketDesc *free_bd)
 	else
 	{
 		cppiInfo.head_bd = free_bd;
-		cppiInfo.head_bd->nextHBDptr = NULL;		
-	}	
+		cppiInfo.head_bd->nextHBDptr = NULL;
+	}
 }
 
 /**
@@ -694,8 +694,8 @@ void putFreeBd(hostPacketDesc *free_bd)
 * \return	  None.
 *
 **/
-void pushToSubmitQ(unsigned short usbDevInst, 
-							unsigned int  queueNum, hostPacketDesc *curr_bd) 
+void pushToSubmitQ(unsigned short usbDevInst,
+							unsigned int  queueNum, hostPacketDesc *curr_bd)
 {
 
 	unsigned int submitqAdd;
@@ -711,16 +711,16 @@ void pushToSubmitQ(unsigned short usbDevInst,
 	curr_bdAdd |= SIZE_OF_SINGLE_BD;
 	bdAddr = (hostPacketDesc *)curr_bdAdd;
 	/*Get the submit queue address */
-	submitqAdd = usbInstance->otgBaseAddress + (CPDMA_QUEUE_REGISTER_D + 
+	submitqAdd = usbInstance->otgBaseAddress + (CPDMA_QUEUE_REGISTER_D +
 														QUEUE_OFFSET(queueNum));
 	/*submit the queue */
 	HWREG(submitqAdd) = (unsigned int) bdAddr;
-	
-}	
+
+}
 
 /**
-* \brief	 This API gets a free BD , process it for TX transfer and submit it to the TX queue. 
-*		 The API can take care of packetizing the data according to USB transfer size and 
+* \brief	 This API gets a free BD , process it for TX transfer and submit it to the TX queue.
+*		 The API can take care of packetizing the data according to USB transfer size and
 *		 attach to the BDs. This API will work in both transparent mode and GRNDIS mode .
 *
 * \param	  lenght:- length of the data buffer
@@ -856,7 +856,7 @@ void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff,
 
 }
 #else
-void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff, 
+void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff,
 								unsigned int length, unsigned int endPoint)
 {
 	hostPacketDesc *current_bd = NULL;
@@ -869,7 +869,7 @@ void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff,
 	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
 
 	endPoint = USB_EP_TO_INDEX(endPoint);
-	
+
 	/*This code segment will take care of the transparent mode transaction */
 	if(CPDMA_MODE_SET_TRANSPARENT == usbInstance->txEndPoint[endPoint].mode)
 	{
@@ -889,7 +889,7 @@ void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff,
 			current_bd->packetId = EOP;
 
 			/*Clean the cache so that bd  will have proper data */
-			CP15DCacheCleanBuff((unsigned int)current_bd,sizeof(hostPacketDesc));	
+			CP15DCacheCleanBuff((unsigned int)current_bd,sizeof(hostPacketDesc));
 
 			/*Submit the BD to the queue for transaction	 */
 			pushToSubmitQ(usbDevInst, usbInstance->txEndPoint[endPoint]
@@ -897,7 +897,7 @@ void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff,
 		}
 
 		/*If the length is more than packet size, then packetize it  */
-		else 
+		else
 		{
 			numOfBlocks = length / USB_PACKET_LENGTH;
 			residue = length -  (numOfBlocks * USB_PACKET_LENGTH);
@@ -912,7 +912,7 @@ void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff,
 					USB_PACKET_LENGTH);
 
 				/*This API will initialize the BD fields */
-				Cppi41DmaProcessBD(usbDevInst, current_bd, CPDMA_DIR_TX, 
+				Cppi41DmaProcessBD(usbDevInst, current_bd, CPDMA_DIR_TX,
 									&buff[i*USB_PACKET_LENGTH], USB_PACKET_LENGTH, endPoint);
 
 				/*Set the packet id to identify the packet position */
@@ -921,19 +921,19 @@ void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff,
 				else if(i==0)
 					current_bd->packetId = SOP;
 				else if((numOfBlocks != 1) && (i < (numOfBlocks -1)))
-					current_bd->packetId = MOP;	
+					current_bd->packetId = MOP;
 				else if(i == (numOfBlocks -1) && residue == 0)
 					current_bd->packetId = EOP;
 				else
 					current_bd->packetId = MOP;
-				
-				CP15DCacheCleanBuff((unsigned int)current_bd,sizeof(hostPacketDesc));	
-				
+
+				CP15DCacheCleanBuff((unsigned int)current_bd,sizeof(hostPacketDesc));
+
 				/*Submit the BD to the queue for transaction	 */
 				pushToSubmitQ(usbDevInst, usbInstance->txEndPoint[endPoint]
 					.submitq, current_bd);
 			}
-			
+
 			/*If there are some remaining data then send it also */
 			if(residue)
 			{
@@ -942,21 +942,21 @@ void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff,
 				ASSERT(current_bd != NULL);
 
 				CP15DCacheCleanBuff((unsigned int)&buff[i*USB_PACKET_LENGTH], residue);
-				
+
 				/*This API will initialize the BD fields */
-				Cppi41DmaProcessBD(usbDevInst, current_bd, CPDMA_DIR_TX, 
+				Cppi41DmaProcessBD(usbDevInst, current_bd, CPDMA_DIR_TX,
 									&buff[i*USB_PACKET_LENGTH], residue, endPoint);
-				
+
 				current_bd->packetId = EOP;
 
 				/*This API will initialize the BD fields */
 				CP15DCacheCleanBuff((unsigned int)current_bd,sizeof(hostPacketDesc));
-				
+
 				/*Submit the BD to the queue for transaction	 */
 				pushToSubmitQ(usbDevInst, usbInstance->txEndPoint[endPoint]
 					.submitq, current_bd);
 			}
-		
+
 		}
 	}
 
@@ -966,16 +966,16 @@ void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff,
 		/*get a free db from the BD pool	 */
 		current_bd = getFreeBd();
 		ASSERT(current_bd != NULL);
-		
+
 		CP15DCacheCleanBuff((unsigned int)buff, length);
 
 		/*This API will initialize the BD fields */
 		Cppi41DmaProcessBD(usbDevInst, current_bd, CPDMA_DIR_TX, buff, length, endPoint);
 
 		current_bd->packetId = EOP;
-		
+
 		CP15DCacheCleanBuff((unsigned int)current_bd,sizeof(hostPacketDesc));
-		
+
 		/*Submit the BD to the queue for transaction	 */
 		pushToSubmitQ(usbDevInst, usbInstance->txEndPoint[endPoint]
 			.submitq, current_bd);
@@ -986,7 +986,7 @@ void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff,
 
 /**
 * \brief	 This API gets a free BD , process it for RX transfer and submit it to the RX queue.
-*		 This API will work in both transparent mode and GRNDIS mode. . Max transfer size 
+*		 This API will work in both transparent mode and GRNDIS mode. . Max transfer size
 *		 of this rx transfer is max USB packet size
 *
 * \param	  lenght:- length of the data buffer
@@ -999,7 +999,7 @@ void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff,
 *
 **/
 #ifdef _TMS320C6X
-void doDmaRxTransfer(unsigned short usbDevInst, unsigned int length, 
+void doDmaRxTransfer(unsigned short usbDevInst, unsigned int length,
 								unsigned char *buff, unsigned int endPoint)
 {
 	hostPacketDesc *current_bd = NULL;
@@ -1046,9 +1046,9 @@ void doDmaRxTransfer(unsigned short usbDevInst, unsigned int length,
 }
 #endif
 /**
-* \brief	 This API reads the TX completion queue and puts the free bd to the BD pool. 
-*		 Extracts the buffer address from the BD and frees it. This will return the 
-*		 current DMA status on TX operation to the caller. his API will be called on 
+* \brief	 This API reads the TX completion queue and puts the free bd to the BD pool.
+*		 Extracts the buffer address from the BD and frees it. This will return the
+*		 current DMA status on TX operation to the caller. his API will be called on
 *		reception of a completion interrupt
 *
 * \param	 usbDevIns:- The USB device instacnce
@@ -1112,12 +1112,12 @@ unsigned int dmaTxCompletion(unsigned short usbDevInst, unsigned int ulEndpoint
 	usbInstance *usbInstance;
 
 	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
-	
+
 	ulRegister = USB_O_TXCSRL1 + EP_OFFSET( ulEndpoint);
 
 	ulEndpoint = USB_EP_TO_INDEX(ulEndpoint);
 
-	
+
 	/*read the compltetion queue */
 	completed_bd = (hostPacketDesc *)Cppi41DmaReadCompletionQueue(usbDevInst, usbInstance
 											->txEndPoint[ulEndpoint].complettionq);
@@ -1127,10 +1127,10 @@ unsigned int dmaTxCompletion(unsigned short usbDevInst, unsigned int ulEndpoint
 		state = DMA_TX_COMPLETED;
 	else
 		state = DMA_TX_IN_PROGRESS;
-	
+
 	/*wait till Tx completion */
 	if(state == DMA_TX_COMPLETED)
-		while ((HWREGH(usbInstance->usbBaseAddress + ulRegister) & 0x2) == 0x02);	
+		while ((HWREGH(usbInstance->usbBaseAddress + ulRegister) & 0x2) == 0x02);
 
 	CP15ICacheFlushBuff((unsigned int)completed_bd->buffAdd, sizeof(completed_bd->buffAdd));
 
@@ -1147,8 +1147,8 @@ unsigned int dmaTxCompletion(unsigned short usbDevInst, unsigned int ulEndpoint
 #endif
 /**
 * \brief	 This API reads the RX completion queue and puts the free bd to the BD pool
-*		Extracts the data buffer from the DB and pass it to the caller . Extracts the 
-*		data buffer from the DB and pass it to the caller . This API will be called on 
+*		Extracts the data buffer from the DB and pass it to the caller . Extracts the
+*		data buffer from the DB and pass it to the caller . This API will be called on
 *		reception of a completion interrupt
 *
 * \param	  usbDevInst:- The USB Intance  Number
@@ -1195,34 +1195,34 @@ unsigned int dmaRxCompletion(unsigned short usbDevInst, unsigned int ulEndpoint
 	unsigned int bufferAdd;
 	unsigned int length;
 	usbInstance *usbInstance;
-    
+
     hostPacketDesc *rx_bd =NULL;;
 
 	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
 
-	ulEndpoint = USB_EP_TO_INDEX(ulEndpoint);	
-	
-	/*read the compltetion queue */	
+	ulEndpoint = USB_EP_TO_INDEX(ulEndpoint);
+
+	/*read the compltetion queue */
 	rx_bd = (hostPacketDesc *)Cppi41DmaReadCompletionQueue(usbDevInst, usbInstance
 												->rxEndPoint[ulEndpoint].complettionq);
 
 	/*Fush the cache to update the BD */
-	CP15ICacheFlushBuff((unsigned int)rx_bd, sizeof(hostPacketDesc));	
+	CP15ICacheFlushBuff((unsigned int)rx_bd, sizeof(hostPacketDesc));
 
-	bufferAdd = rx_bd->buffAdd;	
+	bufferAdd = rx_bd->buffAdd;
 	length = rx_bd->buffLength;
 
 	/*Flush the cache to update the buffer */
 	CP15ICacheFlushBuff(bufferAdd, length);
 
 	putFreeBd(rx_bd);
-	
+
 	return bufferAdd;
 }
 #endif
 
 /**
-* \brief	 This API gets the transfer completion interupt status. This API will be on 
+* \brief	 This API gets the transfer completion interupt status. This API will be on
 *		 reception of a USB interrupt to check the cause of interrupt.
 *
 * \param	 usbDevInst:- The USB Intance  Number
@@ -1231,15 +1231,15 @@ unsigned int dmaRxCompletion(unsigned short usbDevInst, unsigned int ulEndpoint
 *
 **/
 unsigned int CppiDmaGetPendStatus(unsigned short usbDevInst)
-{	
+{
 
 #if defined (am335x_15x15) || defined(am335x)
 	unsigned int pendReg2 = 0;
-	unsigned int pendReg3 = 0;	
+	unsigned int pendReg3 = 0;
 #endif
 
 	unsigned int pendReg0 = 0;
-	
+
 #if defined (am335x_15x15) || defined(am335x)
 	pendReg2 = HWREG(USB_OTGBASE + CPDMA_PEND_2_REGISTER);
 	pendReg3 = HWREG(USB_OTGBASE + CPDMA_PEND_3_REGISTER);
@@ -1257,9 +1257,9 @@ unsigned int CppiDmaGetPendStatus(unsigned short usbDevInst)
 }
 
 /**
-* \brief	 This API gets the starvation interupt status. This API will be on 
+* \brief	 This API gets the starvation interupt status. This API will be on
 *		 reception of a USB interrupt to check the cause of interrupt.
-*		 This API will also disable the scheduler and clear the starvation 
+*		 This API will also disable the scheduler and clear the starvation
 *		 interrupt status in order to avoid over flooding of interrupt
 *
 * \param	 usbDevInst:- The USB Intance  Number
@@ -1279,11 +1279,11 @@ unsigned int CppiDmaGetINTD0Status(unsigned short usbDevInst)
 
 	if(intdReg0 == CPDMA_STAR_0_PEND ||intdReg0 == CPDMA_STAR_1_PEND)
 	{
-		Cppi41DmaControlScheduler(usbDevInst, ENABLE_CPPIDMA, 
+		Cppi41DmaControlScheduler(usbDevInst, ENABLE_CPPIDMA,
 										(NUM_OF_SCHEDULER_ENTRIES / 2));
 		Cppi41DmaClearINTD0Status(usbDevInst);
 	}
-	
+
 	return intdReg0;
 }
 
@@ -1300,9 +1300,9 @@ void Cppi41DmaClearINTD0Status(unsigned short usbDevInst)
 	usbInstance *usbInstance;
 
 	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
-	
+
 	HWREG(usbInstance->otgBaseAddress + CPDMA_CLEAR_INTD_0_STATUS) = CLAER_INTDO_STATUS;
-	
+
 }
 
 /**
@@ -1313,14 +1313,14 @@ void Cppi41DmaClearINTD0Status(unsigned short usbDevInst)
 * \return	  None.
 *
 **/
-void Cppi41DmaControlScheduler(unsigned short usbDevInst, unsigned short enableDisable, 
+void Cppi41DmaControlScheduler(unsigned short usbDevInst, unsigned short enableDisable,
 												unsigned short numOfentries)
 {
 	usbInstance *usbInstance;
 
 	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
-	
-	HWREG(usbInstance->otgBaseAddress + CPDMA_SCHED_CONTROL_REG ) =(enableDisable 
+
+	HWREG(usbInstance->otgBaseAddress + CPDMA_SCHED_CONTROL_REG ) =(enableDisable
 								<< SCHEDULER_ENABLE_SHFT) | (numOfentries - 1);
 
 }
@@ -1334,20 +1334,20 @@ void Cppi41DmaControlScheduler(unsigned short usbDevInst, unsigned short enableD
 *
 * \param	 buffadd:- The buffer address
 *
-* \param	 length:- Length of the buffer	
+* \param	 length:- Length of the buffer
 *
 * \return	  None.
 *
 **/
-void Cppi41DmaProcessBD(unsigned short usbDevInst, hostPacketDesc *current_bd, 
-								 unsigned short direction, unsigned char * buffadd, 
+void Cppi41DmaProcessBD(unsigned short usbDevInst, hostPacketDesc *current_bd,
+								 unsigned short direction, unsigned char * buffadd,
 									   unsigned int length, unsigned int ulEndpoint)
 {
 
 	usbInstance *usbInstance;
 
 	usbInstance = &(cppiInfo.usbInst[usbDevInst]);
-	
+
 	/*These values are fixed for a PD */
 	current_bd->hPDword0.hostPktType = CPDMA_BD_PACKET_TYPE;
 	current_bd->hPDword0.protSize=0;
@@ -1357,7 +1357,7 @@ void Cppi41DmaProcessBD(unsigned short usbDevInst, hostPacketDesc *current_bd,
 		current_bd->hPDword0.pktLength= length;
 	else
 		current_bd->hPDword0.pktLength= 0;
-	
+
 	/* These vlaues are always initialized to zero */
 	current_bd->hPDword1.dstTag=0;
 	current_bd->hPDword1.srcSubChNum=0;
@@ -1370,7 +1370,7 @@ void Cppi41DmaProcessBD(unsigned short usbDevInst, hostPacketDesc *current_bd,
 	else
 		current_bd->hPDword1.srcPrtNum = usbInstance->rxEndPoint[ulEndpoint]
 																		.channel + 1; /*chan_num+1; */
-		
+
 	/*Completion Queues */
 	if(direction == CPDMA_DIR_TX)
 		current_bd->hPDword2.pktRetQueue=usbInstance->txEndPoint[ulEndpoint]
@@ -1393,7 +1393,7 @@ void Cppi41DmaProcessBD(unsigned short usbDevInst, hostPacketDesc *current_bd,
 	current_bd->nextHBDptr=0;
 	current_bd->gBuffLength=current_bd->buffLength;
 	current_bd->gBuffLength |= (unsigned int)(1<<31);
-	current_bd->gBuffAdd=current_bd->buffAdd;	
+	current_bd->gBuffAdd=current_bd->buffAdd;
 	current_bd->endPoint = (unsigned short)ulEndpoint;
 	if(direction == CPDMA_DIR_TX)
 		current_bd->channel = usbInstance->txEndPoint[ulEndpoint].channel;
@@ -1415,20 +1415,20 @@ void Cppi41DmaProcessBD(unsigned short usbDevInst, hostPacketDesc *current_bd,
 void cppi41DmaInitBuffer()
 {
 	int i;
-	
+
 	for(i =0;i<CPDMA_NUMOF_BUFFERS;i++)
 		{
 			 dmaBuffer[i].dataBuffer =(unsigned int *)&dBuffer[i][0];
 			 dmaBuffer[i].usedFlag = CPDMA_BUFFER_NOT_USED;
-			 dmaBuffer[i].nBlocks = 0;		 
+			 dmaBuffer[i].nBlocks = 0;
 		}
 
 }
 
 
 /**
-* \brief	 This API will allocate 1unit(512 bytes) of  buffer. This API is called 
-*		just before the RX and TX transfer. The API returns a pointer to the 
+* \brief	 This API will allocate 1unit(512 bytes) of  buffer. This API is called
+*		just before the RX and TX transfer. The API returns a pointer to the
 *		buffer allocated , which can used by the caller for data transfer.
 *
 * \param	 none
@@ -1449,14 +1449,14 @@ unsigned int * cppiDmaAllocBuffer()
 			return dmaBuffer[i].dataBuffer;
 		}
 	}
-	
-	return NULL;	
+
+	return NULL;
 }
 
 
 /**
-* \brief	 This API will free 1 unit of buffer. Caller needs to pass the buffer 
-*		address to be freed. Once buffer is freed, the usage flag will set 
+* \brief	 This API will free 1 unit of buffer. Caller needs to pass the buffer
+*		address to be freed. Once buffer is freed, the usage flag will set
 *		as BUFFER _NOT_USED
 *
 * \param	 dataBuffer:- Buffer address
@@ -1467,7 +1467,7 @@ unsigned int * cppiDmaAllocBuffer()
 void cppiDmaFreeBuffer(unsigned int *dataBuffer)
 {
 	int i;
-	
+
 	for(i=0;i<CPDMA_NUMOF_BUFFERS;i++)
 	{
 		if(dmaBuffer[i].dataBuffer == dataBuffer)
@@ -1481,8 +1481,8 @@ void cppiDmaFreeBuffer(unsigned int *dataBuffer)
 }
 
 /**
-* \brief	 This API will allocate N (N*512 bytes) number of buffers. This API is called 
-*		just before the RX and TX transfer. The API returns a pointer to the 
+* \brief	 This API will allocate N (N*512 bytes) number of buffers. This API is called
+*		just before the RX and TX transfer. The API returns a pointer to the
 *		buffer allocated , which can used by the caller for data transfer.
 *
 * \param	 numOfBlocks:- Number of buffers
@@ -1495,7 +1495,7 @@ unsigned int * cppiDmaAllocnBuffer(unsigned int numOfBlocks)
 	unsigned int nBlocks = numOfBlocks;
 	unsigned int i,j;
 
-	
+
 
 	for(i =0;i<CPDMA_NUMOF_BUFFERS;i++)
 	{
@@ -1506,29 +1506,29 @@ unsigned int * cppiDmaAllocnBuffer(unsigned int numOfBlocks)
 
 		if(nBlocks == 0)
 			break;
-	
+
 	}
 
-	
+
 	if(nBlocks == 0)
 	{
 		for(j = i; j>(i-numOfBlocks); j--)
 		{
 			dmaBuffer[j].usedFlag =  CPDMA_BUFFER_USED;
 		}
-		dmaBuffer[j+1].nBlocks = numOfBlocks;	
+		dmaBuffer[j+1].nBlocks = numOfBlocks;
 		return dmaBuffer[j+1].dataBuffer;
 	}
 	else
-		return NULL;	
-	
+		return NULL;
+
 }
 
 
 /**
-* \brief	 This API will free N(N *512 Bytes) buffers. Caller needs to pass the buffer 
-*		address to be freed. Once buffer is freed, the usage flag will set 
-*		as BUFFER _NOT_USED. 
+* \brief	 This API will free N(N *512 Bytes) buffers. Caller needs to pass the buffer
+*		address to be freed. Once buffer is freed, the usage flag will set
+*		as BUFFER _NOT_USED.
 *
 * \param	 dataBuffer:- Buffer address
 *
@@ -1540,11 +1540,11 @@ void cppiDmaFreenBuffer(unsigned int *dataBuffer)
 {
 	unsigned int i,j;
 	unsigned int nBlocks = 0;
-	
+
 	for(i=0;i<CPDMA_NUMOF_BUFFERS;i++)
 	{
 		if(dmaBuffer[i].dataBuffer == dataBuffer)
-		{	
+		{
 			nBlocks= dmaBuffer[i].nBlocks;
 			break;
 		}
@@ -1559,12 +1559,12 @@ void cppiDmaFreenBuffer(unsigned int *dataBuffer)
 		}
 
 	}
-		
+
 }
 
 /**
-* \brief	 This API will Handle the starvation Error.  The API will enable the 
-*		 scheduler which is disabled due to the starvation interrupt. 
+* \brief	 This API will Handle the starvation Error.  The API will enable the
+*		 scheduler which is disabled due to the starvation interrupt.
 *		 This will help the DMA to resume the operation after clearing the starvation
 *		 interrupt.
 *
diff --git a/lib/tiam1808/drivers/cpsw.c b/lib/tiam1808/drivers/cpsw.c
index 4548aa724..c459b393e 100644
--- a/lib/tiam1808/drivers/cpsw.c
+++ b/lib/tiam1808/drivers/cpsw.c
@@ -71,7 +71,7 @@ void CPSWSSReset(unsigned int baseAddr)
     /* Reset the CPSW */
     HWREG(baseAddr + CPSW_SS_SOFT_RESET) = CPSW_SS_SOFT_RESET_SOFT_RESET;
 
-    while(HWREG(baseAddr + CPSW_SS_SOFT_RESET) 
+    while(HWREG(baseAddr + CPSW_SS_SOFT_RESET)
           & CPSW_SS_SOFT_RESET_SOFT_RESET);
 }
 
@@ -106,10 +106,10 @@ void CPSWSlRxShortFramesCopyDisable(unsigned int baseAddr)
 /**
  * \brief   Enables limiting the number of short gap packets transmitted to
  *          100ppm. Each time a short gap packet is sent, a counter is loaded
- *          with 10,000 and decremented on each wireside clock. Another short 
- *          gap packet will not be sent out until the counter decrements to 
- *          zero. This mode is included to preclude the host from filling up 
- *          the FIFO and sending every packet out with short gap which would 
+ *          with 10,000 and decremented on each wireside clock. Another short
+ *          gap packet will not be sent out until the counter decrements to
+ *          zero. This mode is included to preclude the host from filling up
+ *          the FIFO and sending every packet out with short gap which would
  *          violate the maximum number of packets per second allowed.
  *
  * \param   baseAddr    Base address of the CPSW Sliver Module registers.
@@ -180,11 +180,11 @@ void CPSWSlControlExtEnable(unsigned int baseAddr)
 void CPSWSlGigModeForceDisable(unsigned int baseAddr)
 {
     HWREG(baseAddr + CPSW_SL_MACCONTROL) &= ~CPSW_SL_MACCONTROL_GIG_FORCE;
-} 
+}
 
 /**
  * \brief   Sets the Transfer mode, 10/100 or gigabit mode  and the duplex
- *          mode  for the sliver.  
+ *          mode  for the sliver.
  *
  * \param   baseAddr    Base address of the CPSW Sliver Module registers.
  * \param   mode        The transfer mode
@@ -200,7 +200,7 @@ void CPSWSlTransferModeSet(unsigned int baseAddr, unsigned int mode)
 {
     HWREG(baseAddr + CPSW_SL_MACCONTROL) &= ~(CPSW_SL_MACCONTROL_GIG
                                               | CPSW_SL_MACCONTROL_FULLDUPLEX);
-      
+
     HWREG(baseAddr + CPSW_SL_MACCONTROL) |= mode;
 }
 
@@ -223,15 +223,15 @@ void CPSWSlTransferModeSet(unsigned int baseAddr, unsigned int mode)
  *            The MAC status register value returned can be compared against
  *            the below tokens. \n
  *              CPSW_SLIVER_STATE_IDLE - The Sliver is in idle state. \n
- *              CPSW_SLIVER_EXT_GIG_INPUT_HIGH - The EXT_GIG input 
+ *              CPSW_SLIVER_EXT_GIG_INPUT_HIGH - The EXT_GIG input
  *                                                 bit is in HIGH state.\n
- *              CPSW_SLIVER_EXT_FULL_DUPLEX_HIGH - The EXT_FULLDUPLEX input 
+ *              CPSW_SLIVER_EXT_FULL_DUPLEX_HIGH - The EXT_FULLDUPLEX input
  *                                                   bit is in HIGH state. \n
  *              CPSW_SLIVER_RX_FLOWCTRL_ACTIVE - The receive flow control is
  *                                                 active. \n
- *              CPSW_SLIVER_TX_FLOWCTRL_ACTIVE - The pause time period is 
- *                                                 observed for a received 
- *                                                 pause frame 
+ *              CPSW_SLIVER_TX_FLOWCTRL_ACTIVE - The pause time period is
+ *                                                 observed for a received
+ *                                                 pause frame
  *
  **/
 unsigned int CPSWSlMACStatusGet(unsigned int baseAddr, unsigned int statFlag)
@@ -252,20 +252,20 @@ void CPSWSlReset(unsigned int baseAddr)
 {
     /* Reset the sliver logic */
     HWREG(baseAddr + CPSW_SL_SOFT_RESET) = CPSW_SL_SOFT_RESET_SOFT_RESET;
-    
+
     /* Wait till the reset completes */
-    while(CPSW_SL_SOFT_RESET_SOFT_RESET == 
-          ((HWREG(baseAddr + CPSW_SL_SOFT_RESET)) 
+    while(CPSW_SL_SOFT_RESET_SOFT_RESET ==
+          ((HWREG(baseAddr + CPSW_SL_SOFT_RESET))
            & CPSW_SL_SOFT_RESET_SOFT_RESET));
 }
 
 
 /**
- * \brief   Sets the maximum length for received frame. 
+ * \brief   Sets the maximum length for received frame.
  *
  * \param   baseAddr    Base address of the CPSW Sliver Module registers.
  * \param   rxMaxLen    Maximum length for a received frame
- *     The default value for 'rxMaxLen' is 1518. The maximum value 
+ *     The default value for 'rxMaxLen' is 1518. The maximum value
  *     which can be set is 16383.
  *
  * \return  None
@@ -334,7 +334,7 @@ unsigned int CPSWSlTxPauseTmrGet(unsigned int baseAddr)
 }
 
 /**
- * \brief   Sets the transmitter inter-packet gap value. 
+ * \brief   Sets the transmitter inter-packet gap value.
  *
  * \param   baseAddr    Base address of the CPSW Sliver Module registers.
  * \param   intrPktGap  The transmit inter-packet gap value.
@@ -374,8 +374,8 @@ void CPSWSlGMIIEnable(unsigned int baseAddr)
  **/
 void CPSWSlRGMIIEnable(unsigned int baseAddr)
 {
-   HWREG(baseAddr + CPSW_SL_MACCONTROL) |= (CPSW_SL_MACCONTROL_GMII_EN 
-                                            | CPSW_SL_MACCONTROL_IFCTL_A 
+   HWREG(baseAddr + CPSW_SL_MACCONTROL) |= (CPSW_SL_MACCONTROL_GMII_EN
+                                            | CPSW_SL_MACCONTROL_IFCTL_A
                                             | CPSW_SL_MACCONTROL_IFCTL_B);
 }
 
@@ -391,7 +391,7 @@ void CPSWWrReset(unsigned int baseAddr)
     /* Reset the CPSW Wrapper */
     HWREG(baseAddr + CPSW_WR_SOFT_RESET) = CPSW_WR_SOFT_RESET_SOFT_RESET;
 
-    while(HWREG(baseAddr + CPSW_WR_SOFT_RESET) 
+    while(HWREG(baseAddr + CPSW_WR_SOFT_RESET)
           & CPSW_WR_SOFT_RESET_SOFT_RESET);
 }
 
@@ -426,7 +426,7 @@ void CPSWWrControlRegReset(unsigned int baseAddr)
 void CPSWWrCoreIntEnable(unsigned int baseAddr, unsigned int core,
                          unsigned int channel, unsigned int intFlag)
 {
-    HWREG(baseAddr + CPSW_WR_C_RX_THRESH_EN(core) + intFlag) |= (1 << channel); 
+    HWREG(baseAddr + CPSW_WR_C_RX_THRESH_EN(core) + intFlag) |= (1 << channel);
 }
 
 /**
@@ -444,11 +444,11 @@ void CPSWWrCoreIntEnable(unsigned int baseAddr, unsigned int core,
  *
  * \return  None
  **/
-void CPSWWrCoreIntDisable(unsigned int baseAddr, unsigned int core, 
+void CPSWWrCoreIntDisable(unsigned int baseAddr, unsigned int core,
                           unsigned int channel, unsigned int intFlag)
 {
-    HWREG(baseAddr + CPSW_WR_C_RX_THRESH_EN(core) + intFlag) &= 
-                                                            ~(1 << channel); 
+    HWREG(baseAddr + CPSW_WR_C_RX_THRESH_EN(core) + intFlag) &=
+                                                            ~(1 << channel);
 }
 
 /**
@@ -487,7 +487,7 @@ unsigned int CPSWWrCoreIntStatusGet(unsigned int baseAddr, unsigned int core,
  *        CPSW_RGMII1_DUPLEX - Duplex of RGMII1 \n
  *        CPSW_RGMII1_SPEED - Speed of RGMII1 \n
  *        CPSW_RGMII1_LINK_STAT - Link Status of RGMII1 \n
- *  
+ *
  *    The returned value can be compared agains the below values \n
  *        CPSW_RGMII2_DUPLEX_FULL - RGMII2 full duplex \n
  *        CPSW_RGMII2_DUPLEX_HALF - RGMII2 half duplex \n
@@ -505,7 +505,7 @@ unsigned int CPSWWrCoreIntStatusGet(unsigned int baseAddr, unsigned int core,
  *        CPSW_RGMII1_LINK_DOWN - RGMII1 link is down \n
  *
  * \return  Status of RGMII. Return value can be compared agains the same
- *          statFlag passed. 
+ *          statFlag passed.
  **/
 unsigned int CPSWWrRGMIIStatusGet(unsigned int baseAddr, unsigned int statFlag)
 {
@@ -518,12 +518,12 @@ unsigned int CPSWWrRGMIIStatusGet(unsigned int baseAddr, unsigned int statFlag)
  * \param   baseAddr    Base address of the CPSW Wrapper Module
  * \param   pacFlag     The interrpupts for which pacing to be enabled
  *    'pacFlag' can take any combination of the below values. \n
- *         CPSW_INT_PACING_C0_RX_PULSE  - Core 0 RX pulse interrupt pacing \n 
- *         CPSW_INT_PACING_C0_TX_PULSE  - Core 0 TX pulse interrupt pacing \n 
- *         CPSW_INT_PACING_C1_RX_PULSE  - Core 1 RX pulse interrupt pacing \n 
- *         CPSW_INT_PACING_C1_TX_PULSE  - Core 1 TX pulse interrupt pacing \n 
- *         CPSW_INT_PACING_C2_RX_PULSE  - Core 2 RX pulse interrupt pacing \n 
- *         CPSW_INT_PACING_C2_TX_PULSE  - Core 2 TX pulse interrupt pacing \n 
+ *         CPSW_INT_PACING_C0_RX_PULSE  - Core 0 RX pulse interrupt pacing \n
+ *         CPSW_INT_PACING_C0_TX_PULSE  - Core 0 TX pulse interrupt pacing \n
+ *         CPSW_INT_PACING_C1_RX_PULSE  - Core 1 RX pulse interrupt pacing \n
+ *         CPSW_INT_PACING_C1_TX_PULSE  - Core 1 TX pulse interrupt pacing \n
+ *         CPSW_INT_PACING_C2_RX_PULSE  - Core 2 RX pulse interrupt pacing \n
+ *         CPSW_INT_PACING_C2_TX_PULSE  - Core 2 TX pulse interrupt pacing \n
  *
  * \return  None
  **/
@@ -566,7 +566,7 @@ void CPSWWrIntRxPerMsSet(unsigned int baseAddr, unsigned int core,
 }
 
 /**
- * \brief   Disables pacing of interrupts                           
+ * \brief   Disables pacing of interrupts
  *
  * \param   baseAddr    Base address of the CPSW Wrapper Module
  * \param   pacFlag     The interrpupts for which pacing to be disabled
@@ -595,7 +595,7 @@ void CPSWWrIntPacingDisable(unsigned int baseAddr, unsigned int pacFlag)
  **/
 void CPSWALEInit(unsigned int baseAddr)
 {
-    HWREG(baseAddr + CPSW_ALE_CONTROL) = (CPSW_ALE_CONTROL_CLEAR_TABLE 
+    HWREG(baseAddr + CPSW_ALE_CONTROL) = (CPSW_ALE_CONTROL_CLEAR_TABLE
                                           | CPSW_ALE_CONTROL_ENABLE_ALE);
 }
 
@@ -626,12 +626,12 @@ void CPSWALEPortStateSet(unsigned int baseAddr, unsigned int portNum,
  * \brief   Sets an ALE table entry
  *
  * \param   baseAddr    Base address of the ALE Module
- * \param   aleTblIdx   The Index of the table entry 
+ * \param   aleTblIdx   The Index of the table entry
  * \param   aleEntryPtr The address of the entry to be set
  *
  * \return  None
  **/
-void CPSWALETableEntrySet(unsigned int baseAddr, unsigned int aleTblIdx, 
+void CPSWALETableEntrySet(unsigned int baseAddr, unsigned int aleTblIdx,
                           unsigned int *aleEntryPtr)
 {
     unsigned int cnt;
@@ -639,8 +639,8 @@ void CPSWALETableEntrySet(unsigned int baseAddr, unsigned int aleTblIdx,
     for (cnt = 0; cnt < ALE_ENTRY_WORDS; cnt++)
     {
         HWREG(baseAddr +  CPSW_ALE_TBLW(cnt)) =  *(aleEntryPtr + cnt);
-    }     
-    
+    }
+
     HWREG(baseAddr +  CPSW_ALE_TBLCTL) =
                                 aleTblIdx | CPSW_ALE_TBLCTL_WRITE_RDZ;
 }
@@ -649,7 +649,7 @@ void CPSWALETableEntrySet(unsigned int baseAddr, unsigned int aleTblIdx,
  * \brief   Returns an ALE table entry
  *
  * \param   baseAddr    Base address of the ALE Module
- * \param   aleTblIdx   The Index of the table entry 
+ * \param   aleTblIdx   The Index of the table entry
  * \param   aleEntryPtr The address where the ALE entry to be written
  *
  * \return  None
@@ -671,14 +671,14 @@ void CPSWALETableEntryGet(unsigned int baseAddr, unsigned int aleTblIdx,
  * \brief   Enables the ALE port to leaning an address
  *
  * \param   baseAddr      Base Address of the ALE module
- * \param   portNum       The port number 
+ * \param   portNum       The port number
  *
  * \return  None
  *
  **/
 void CPSWALELearnModeEnable(unsigned int baseAddr, unsigned int  portNum)
 {
-    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) &= 
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) &=
                                          ~CPSW_ALE_PORTCTL0_NO_LEARN;
 }
 
@@ -686,23 +686,23 @@ void CPSWALELearnModeEnable(unsigned int baseAddr, unsigned int  portNum)
  * \brief   Disables the ALE port from leaning an address
  *
  * \param   baseAddr      Base Address of the ALE module
- * \param   portNum       The port number 
+ * \param   portNum       The port number
  *
  * \return  None
  *
  **/
 void CPSWALELearnModeDisable(unsigned int baseAddr, unsigned int  portNum)
 {
-    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) |= 
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) |=
                                          CPSW_ALE_PORTCTL0_NO_LEARN;
 }
 
 /**
- * \brief   Sets the rate limit for broadcast packets. Each prescale pulse 
+ * \brief   Sets the rate limit for broadcast packets. Each prescale pulse
  *          loads the rate limit into the port counter, which gets decremented
  *          with each packet received or transmitted. If the counters
  *          decrement to zero, then further packets are rate limited until the
- *          next prescale pulse. 
+ *          next prescale pulse.
  *
  * \param   baseAddr      Base Address of the ALE module
  * \param   portNum       The port number
@@ -715,16 +715,16 @@ void CPSWALEBCastPktRateLimitSet(unsigned int baseAddr, unsigned int  portNum,
                                  unsigned int rateLtVal)
 {
     HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) &= ~CPSW_ALE_PORTCTL0_BCAST_LIMIT;
-    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) |= 
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) |=
                                (rateLtVal << CPSW_ALE_PORTCTL0_BCAST_LIMIT_SHIFT);
 }
 
 /**
- * \brief   Sets the rate limit for multicast packets. Each prescale pulse 
+ * \brief   Sets the rate limit for multicast packets. Each prescale pulse
  *          loads the rate limit into the port counter, which gets decremented
  *          with each packet received or transmitted. If the counters
  *          decrement to zero, then further packets are rate limited until the
- *          next prescale pulse. 
+ *          next prescale pulse.
  *
  * \param   baseAddr      Base Address of the ALE module
  * \param   portNum       The port number
@@ -737,40 +737,40 @@ void CPSWALEMCastPktRateLimitSet(unsigned int baseAddr, unsigned int  portNum,
                                  unsigned int rateLtVal)
 {
     HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) &= ~CPSW_ALE_PORTCTL0_MCAST_LIMIT;
-    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) |= 
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) |=
                                (rateLtVal << CPSW_ALE_PORTCTL0_MCAST_LIMIT_SHIFT);
 
 }
 
 /**
- * \brief   Enables the port for updating the source port number in the ALE 
+ * \brief   Enables the port for updating the source port number in the ALE
  *          table entry.
  *
  * \param   baseAddr      Base Address of the ALE module
- * \param   portNum       The port number 
+ * \param   portNum       The port number
  *
  * \return  None
  *
  **/
 void CPSWALESrcPortNumUpdateEnable(unsigned int baseAddr, unsigned int portNum)
 {
-    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) &= 
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) &=
                                            ~CPSW_ALE_PORTCTL0_NO_SA_UPDATE;
 }
 
 /**
- * \brief   Disables the port from updating the source port number in the ALE 
+ * \brief   Disables the port from updating the source port number in the ALE
  *          table entry.
  *
  * \param   baseAddr      Base Address of the ALE module
- * \param   portNum       The port number 
+ * \param   portNum       The port number
  *
  * \return  None
  *
  **/
 void CPSWALESrcPortNumUpdateDisable(unsigned int baseAddr, unsigned int portNum)
 {
-    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) |= 
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) |=
                                            CPSW_ALE_PORTCTL0_NO_SA_UPDATE;
 }
 
@@ -785,8 +785,8 @@ void CPSWALESrcPortNumUpdateDisable(unsigned int baseAddr, unsigned int portNum)
  **/
 unsigned int CPSWALEPrescaleGet(unsigned int baseAddr)
 {
-    return (HWREG(baseAddr + CPSW_ALE_PRESCALE) 
-            & CPSW_ALE_PRESCALE_ALE_PRESCALE);   
+    return (HWREG(baseAddr + CPSW_ALE_PRESCALE)
+            & CPSW_ALE_PRESCALE_ALE_PRESCALE);
 }
 
 /**
@@ -801,13 +801,13 @@ unsigned int CPSWALEPrescaleGet(unsigned int baseAddr)
  **/
 void CPSWALEPrescaleSet(unsigned int baseAddr, unsigned int psVal)
 {
-    HWREG(baseAddr + CPSW_ALE_PRESCALE) |= psVal 
+    HWREG(baseAddr + CPSW_ALE_PRESCALE) |= psVal
                                    & CPSW_ALE_PRESCALE_ALE_PRESCALE ;
 }
 
 /**
  * \brief   By calling this APIs, The ALE hardware removes (free up) any
- *          ageable table entry that does not have a set touch bit 
+ *          ageable table entry that does not have a set touch bit
  *
  * \param   baseAddr      Base Address of the ALE module
  *
@@ -817,7 +817,7 @@ void CPSWALEPrescaleSet(unsigned int baseAddr, unsigned int psVal)
 void CPSWALEAddrTblAgeOut(unsigned int baseAddr)
 {
     HWREG(baseAddr + CPSW_ALE_CONTROL) |= CPSW_ALE_CONTROL_AGE_OUT_NOW ;
-   
+
     /* Wait till ageout completes */
     while(HWREG(baseAddr +  CPSW_ALE_CONTROL) & CPSW_ALE_CONTROL_AGE_OUT_NOW);
 }
@@ -913,11 +913,11 @@ void CPSWRxFlowControlDisable(unsigned int baseAddr, unsigned int portNum)
  **/
 void CPSWSoftwareIdleEnable(unsigned int baseAddr)
 {
-    HWREG(baseAddr + CPSW_SS_SOFT_IDLE) |= CPSW_SS_SOFT_IDLE_SOFT_IDLE; 
+    HWREG(baseAddr + CPSW_SS_SOFT_IDLE) |= CPSW_SS_SOFT_IDLE_SOFT_IDLE;
 }
 
 /**
- * \brief   Disables the software idle mode, causing the switch fabric to 
+ * \brief   Disables the software idle mode, causing the switch fabric to
  *          forward packets at the next start of packet.
  *
  * \param   baseAddr      Base Address of the CPSW subsystem
@@ -970,19 +970,19 @@ void CPSWVLANAwareDisable(unsigned int baseAddr)
  **/
 void CPSWPortSrcAddrSet(unsigned int baseAddr, unsigned char *ethAddr)
 {
- 
-    HWREG(baseAddr + CPSW_PORT_SA_HI) = 
-                   ethAddr[0] 
+
+    HWREG(baseAddr + CPSW_PORT_SA_HI) =
+                   ethAddr[0]
                    | (ethAddr[1] << CPSW_PORT_P1_SA_HI_MACSRCADDR_39_32_SHIFT)
-                   | (ethAddr[2] << CPSW_PORT_P1_SA_HI_MACSRCADDR_31_24_SHIFT) 
+                   | (ethAddr[2] << CPSW_PORT_P1_SA_HI_MACSRCADDR_31_24_SHIFT)
                    | (ethAddr[3] << CPSW_PORT_P1_SA_HI_MACSRCADDR_23_16_SHIFT);
-    HWREG(baseAddr + CPSW_PORT_SA_LO) = 
-                   ethAddr[4]  
+    HWREG(baseAddr + CPSW_PORT_SA_LO) =
+                   ethAddr[4]
                    | (ethAddr[5] << CPSW_PORT_P1_SA_LO_MACSRCADDR_7_0_SHIFT);
 }
 
 /**
- * \brief   Sets the Tx Header Priority to Switch Pri Mapping 
+ * \brief   Sets the Tx Header Priority to Switch Pri Mapping
  *
  * \param   baseAddr      Base address of the CPSW Port Module registers.
  * \param   txPriMap      TX header priority map
@@ -996,31 +996,31 @@ void CPSWPortTxHdrPriMapSet(unsigned int baseAddr, unsigned int txPriMap)
 }
 
 /**
- * \brief   Sets the maximum number of 1k memory blocks that may be allocated 
+ * \brief   Sets the maximum number of 1k memory blocks that may be allocated
  *          to the FIFOs logical transmit priority queues. Port 0 should
  *          remain in flow control mode. 0x10 is the recommended value.
  *
  * \param   baseAddr      Base address of the CPSW Port Module registers.
- * \param   maxBlks       Number of blocks 
+ * \param   maxBlks       Number of blocks
  *
  * \return  None
  *
  **/
 void CPSWPortTxMaxBlksSet(unsigned int baseAddr, unsigned int maxBlks)
 {
-    HWREG(baseAddr + CPSW_PORT_MAX_BLKS) &= 
+    HWREG(baseAddr + CPSW_PORT_MAX_BLKS) &=
                        ~(CPSW_PORT_P0_MAX_BLKS_P0_TX_MAX_BLKS);
- 
-    HWREG(baseAddr + CPSW_PORT_MAX_BLKS) |= 
+
+    HWREG(baseAddr + CPSW_PORT_MAX_BLKS) |=
                        (maxBlks << CPSW_PORT_P0_MAX_BLKS_P0_TX_MAX_BLKS_SHIFT);
 }
 
 /**
  * \brief   Sets the maximum number of 1k memory blocks that may be allocated
- *          to the FIFOs logical receive queues. 0x4 is the recommended value. 
+ *          to the FIFOs logical receive queues. 0x4 is the recommended value.
  *
  * \param   baseAddr      Base address of the CPSW Port Module registers.
- * \param   maxBlks       Number of blocks 
+ * \param   maxBlks       Number of blocks
  *           0x3 <= 'maxBlks' <= 0x6
  *
  * \return  None
@@ -1028,10 +1028,10 @@ void CPSWPortTxMaxBlksSet(unsigned int baseAddr, unsigned int maxBlks)
  **/
 void CPSWPortRxMaxBlksSet(unsigned int baseAddr, unsigned int maxBlks)
 {
-    HWREG(baseAddr + CPSW_PORT_MAX_BLKS) &= 
+    HWREG(baseAddr + CPSW_PORT_MAX_BLKS) &=
                        ~(CPSW_PORT_P0_MAX_BLKS_P0_RX_MAX_BLKS);
- 
-    HWREG(baseAddr + CPSW_PORT_MAX_BLKS) |= 
+
+    HWREG(baseAddr + CPSW_PORT_MAX_BLKS) |=
                        (maxBlks << CPSW_PORT_P0_MAX_BLKS_P0_RX_MAX_BLKS_SHIFT);
 }
 
@@ -1087,7 +1087,7 @@ void CPSWPortTxFIFODualMACModeSet(unsigned int baseAddr, unsigned int blksRem)
 {
     HWREG(baseAddr + CPSW_PORT_TX_IN_CTL) &= ~(CPSW_PORT_P0_TX_IN_CTL_TX_IN_SEL
                                          | CPSW_PORT_P0_TX_IN_CTL_TX_BLKS_REM);
-    HWREG(baseAddr + CPSW_PORT_TX_IN_CTL) |= 
+    HWREG(baseAddr + CPSW_PORT_TX_IN_CTL) |=
                      (CPSW_PORT_DUAL_MAC_MODE
                       | (blksRem << CPSW_PORT_P0_TX_IN_CTL_TX_BLKS_REM_SHIFT));
 }
@@ -1122,7 +1122,7 @@ void CPSWPortTxFIFOWordsSet(unsigned int baseAddr, unsigned int txPriWds)
 }
 
 /**
- * \brief   Sets the RX DSCP priority map. 
+ * \brief   Sets the RX DSCP priority map.
  *
  * \param   baseAddr      Base address of the CPSW Port Module registers.
  * \param   priReg        The priority Register to be set
@@ -1152,17 +1152,17 @@ unsigned int CPSWStatisticsGet(unsigned int baseAddr, unsigned int statReg)
 }
 
 /**
- * \brief   Sets the the threshold value for issuing receive threshold 
+ * \brief   Sets the the threshold value for issuing receive threshold
  *          pending interrupts
  *
  * \param   baseAddr      Base address of the CPDMA Module registers.
- * \param   channel       Channel number 
+ * \param   channel       Channel number
  * \param   threshVal     Threshold value to be set
  *
  * \return  None
  *
  **/
-void CPSWCPDMARxFlowThreshSet(unsigned int baseAddr, unsigned int channel, 
+void CPSWCPDMARxFlowThreshSet(unsigned int baseAddr, unsigned int channel,
                               unsigned int threshVal)
 {
     HWREG(baseAddr + CPSW_CPDMA_RX_PENDTHRESH(channel)) = threshVal;
@@ -1209,13 +1209,13 @@ void CPSWCPDMAReset(unsigned int baseAddr)
     unsigned int cnt;
 
     /* Reset the CPDMA */
-    HWREG(baseAddr + CPSW_CPDMA_CPDMA_SOFT_RESET) =  
+    HWREG(baseAddr + CPSW_CPDMA_CPDMA_SOFT_RESET) =
                      CPSW_CPDMA_CPDMA_SOFT_RESET_SOFT_RESET;
 
     /* Wait till the reset completes */
     while(HWREG(baseAddr + CPSW_CPDMA_CPDMA_SOFT_RESET)
           & CPSW_CPDMA_CPDMA_SOFT_RESET_SOFT_RESET);
- 
+
     /* Initialize all the header descriptor pointer registers */
     for(cnt =  0; cnt< CPSW_MAX_HEADER_DESC; cnt++)
     {
@@ -1357,14 +1357,14 @@ void CPSWCPDMARxHdrDescPtrWrite(unsigned int baseAddr, unsigned int descHdr,
  *
  * \param   baseAddr      Base Address of the CPDMA module registers.
  * \param   eoiFlag       Type of interrupt to acknowledge to the CPDMA
- *            'eoiFlag' can take the following values \n                            
- *                CPSW_EOI_TX_PULSE - TX Pulse Interrupt \n                                    
- *                CPSW_EOI_RX_PULSE - RX Pulse Interrupt \n                                    
- *                CPSW_EOI_RX_THRESH_PULSE - RX Pulse Threshold Interrupt \n                   
- *                CPSW_EOI_MISC_PULSE - Misc Interrupt \n                                      
+ *            'eoiFlag' can take the following values \n
+ *                CPSW_EOI_TX_PULSE - TX Pulse Interrupt \n
+ *                CPSW_EOI_RX_PULSE - RX Pulse Interrupt \n
+ *                CPSW_EOI_RX_THRESH_PULSE - RX Pulse Threshold Interrupt \n
+ *                CPSW_EOI_MISC_PULSE - Misc Interrupt \n
  *
  * \return  None
- * 
+ *
  **/
 void CPSWCPDMAEndOfIntVectorWrite(unsigned int baseAddr, unsigned int eoiFlag)
 {
@@ -1382,7 +1382,7 @@ void CPSWCPDMAEndOfIntVectorWrite(unsigned int baseAddr, unsigned int eoiFlag)
  * \return  None
  *
  **/
-void CPSWCPDMATxCPWrite(unsigned int baseAddr, unsigned int channel, 
+void CPSWCPDMATxCPWrite(unsigned int baseAddr, unsigned int channel,
                         unsigned int comPtr)
 {
     HWREG(baseAddr + CPSW_CPDMA_TX_CP(channel)) = comPtr;
@@ -1398,7 +1398,7 @@ void CPSWCPDMATxCPWrite(unsigned int baseAddr, unsigned int channel,
  * \return  None
  *
  **/
-void CPSWCPDMARxCPWrite(unsigned int baseAddr, unsigned int channel, 
+void CPSWCPDMARxCPWrite(unsigned int baseAddr, unsigned int channel,
                         unsigned int comPtr)
 {
     HWREG(baseAddr + CPSW_CPDMA_RX_CP(channel)) = comPtr;
@@ -1431,47 +1431,47 @@ void CPSWCPDMANumFreeBufSet(unsigned int baseAddr, unsigned int channel,
  *            CPDMA_STAT_TX_HOST_ERR_CHAN - TX host error channel. \n
  *            CPDMA_STAT_RX_HOST_ERR_CODE - RX host error code. \n
  *            CPDMA_STAT_RX_HOST_ERR_CHAN - RX host error channel. \n
- * 
+ *
  * \return  the DMA status for the status flag passed.
  *          The return values for CPDMA_STAT_IDLE are, \n
  *            CPDMA_STAT_IDLE - CPDMA is in idle state \n
  *            CPDMA_STAT_NOT_IDLE - CPDMA is not in idle state \n
  *
  *          The return values for CPDMA_STAT_TX_HOST_ERR_CODE are, \n
- *            CPDMA_STAT_TX_NO_ERR - No error \n 
- *            CPDMA_STAT_TX_SOP_ERR - SOP error \n 
+ *            CPDMA_STAT_TX_NO_ERR - No error \n
+ *            CPDMA_STAT_TX_SOP_ERR - SOP error \n
  *            CPDMA_STAT_TX_OWN_ERR - Ownership bit not
- *                                                  set in SOP buffer \n 
- *            CPDMA_STAT_TX_ZERO_DESC - Zero Next Buffer 
- *                                       Descriptor Pointer Without EOP \n 
- *            CPDMA_STAT_TX_ZERO_BUF_PTR - Zero Buffer Pointer \n 
- *            CPDMA_STAT_TX_ZERO_BUF_LEN - Zero Buffer Length \n 
- *            CPDMA_STAT_TX_PKT_LEN_ERR - Packet Length Error \n 
+ *                                                  set in SOP buffer \n
+ *            CPDMA_STAT_TX_ZERO_DESC - Zero Next Buffer
+ *                                       Descriptor Pointer Without EOP \n
+ *            CPDMA_STAT_TX_ZERO_BUF_PTR - Zero Buffer Pointer \n
+ *            CPDMA_STAT_TX_ZERO_BUF_LEN - Zero Buffer Length \n
+ *            CPDMA_STAT_TX_PKT_LEN_ERR - Packet Length Error \n
  *
  *          The return values for CPDMA_STAT_RX_HOST_ERR_CODE are, \n
- *            CPDMA_STAT_RXi_NO_ERR - No error \n 
- *            CPDMA_STAT_RX_OWN_NOT_SET - Ownership bit not set in 
+ *            CPDMA_STAT_RXi_NO_ERR - No error \n
+ *            CPDMA_STAT_RX_OWN_NOT_SET - Ownership bit not set in
                                           input buffer \n
- *            CPDMA_STAT_RX_ZERO_BUF_PTR - Zero Buffer Pointer\n 
- *            CPDMA_STAT_RX_ZERO_BUF_LEN - Zero Buffer Length on 
- *                                       non-SOP descriptor \n 
+ *            CPDMA_STAT_RX_ZERO_BUF_PTR - Zero Buffer Pointer\n
+ *            CPDMA_STAT_RX_ZERO_BUF_LEN - Zero Buffer Length on
+ *                                       non-SOP descriptor \n
  *            CPDMA_STAT_RX_SOP_BUF_LEN_ERR - SOP buffer length not
- *                                       greater than offset\n 
+ *                                       greater than offset\n
  *
  **/
 unsigned int CPSWCPDMAStatusGet(unsigned int baseAddr, unsigned int statFlag)
 {
-    return (((HWREG(baseAddr + CPSW_CPDMA_DMASTATUS)) & statFlag) 
-            >> (statFlag & CPDMA_ERR_CHANNEL_POS));   
+    return (((HWREG(baseAddr + CPSW_CPDMA_DMASTATUS)) & statFlag)
+            >> (statFlag & CPDMA_ERR_CHANNEL_POS));
 }
 
 /**
  * \brief   Configures the CPDMA module by writing the configuration value
- *          to the DMA control register. 
+ *          to the DMA control register.
  *
  * \param   baseAddr      Base Address of the CPDMA module registers
  * \param   cfg           CPDMA configuration written to control register
- *     'cfg' shall be CPDMA_CFG(tx_rlim, rx_cef, cmd_idle, 
+ *     'cfg' shall be CPDMA_CFG(tx_rlim, rx_cef, cmd_idle,
  *                              rx_offlen_blk, rx_own, tx_ptype). \n
  *        The parameter 'tx_rlim' to CPDMA_CFG can take one of the below
  *        values, showing which all channels are rate-limited. \n
@@ -1483,7 +1483,7 @@ unsigned int CPSWCPDMAStatusGet(unsigned int baseAddr, unsigned int statFlag)
  *            CPDMA_CFG_TX_RATE_LIM_CH_7_TO_2 \n
  *            CPDMA_CFG_TX_RATE_LIM_CH_7_TO_1 \n
  *            CPDMA_CFG_TX_RATE_LIM_CH_7_TO_0 \n
- *        The parameter 'rx_cef' to CPDMA_CFG can take one of the below 
+ *        The parameter 'rx_cef' to CPDMA_CFG can take one of the below
  *        values \n
  *            CPDMA_CFG_COPY_ERR_FRAMES - To copy error frames to memory \n
  *            CPDMA_CFG_NO_COPY_ERR_FRAMES - Not to copy error frames \n
@@ -1491,27 +1491,27 @@ unsigned int CPSWCPDMAStatusGet(unsigned int baseAddr, unsigned int statFlag)
  *        values \n
  *            CPDMA_CFG_IDLE_COMMAND - Idle commanded \n
  *            CPDMA_CFG_IDLE_COMMAND_NONE - Idle not commanded \n
- *        The parameter 'rx_offlen_blk' to CPDMA_CFG can take one of the below 
+ *        The parameter 'rx_offlen_blk' to CPDMA_CFG can take one of the below
  *        values \n
  *            CPDMA_CFG_BLOCK_RX_OFF_LEN_WRITE - Block the DMA writes to the
- *                                               offset/length field during 
+ *                                               offset/length field during
  *                                               packet processing. \n
  *            CPDMA_CFG_NOT_BLOCK_RX_OFF_LEN_WRITE - Do not Block the DMA writes
- *                                              to the offset/length field during 
+ *                                              to the offset/length field during
  *                                              packet processing. \n
- *        The parameter 'rx_own' to CPDMA_CFG can take one of the below 
+ *        The parameter 'rx_own' to CPDMA_CFG can take one of the below
  *        values \n
- *            CPDMA_CFG_RX_OWN_1 - The CPDMA writes 1 to the ownership bit at 
+ *            CPDMA_CFG_RX_OWN_1 - The CPDMA writes 1 to the ownership bit at
  *                                 the end of packet processing. \n
- *            CPDMA_CFG_RX_OWN_0 - The CPDMA writes 0 to the ownership bit at 
+ *            CPDMA_CFG_RX_OWN_0 - The CPDMA writes 0 to the ownership bit at
  *                                 the end of packet processing. \n
- *        The parameter 'tx_ptype' to CPDMA_CFG can take one of the below 
+ *        The parameter 'tx_ptype' to CPDMA_CFG can take one of the below
  *        values \n
  *            CPDMA_CFG_TX_PRI_ROUND_ROBIN - The next channel for transmit is
- *                                           chosen round-robin. \n 
+ *                                           chosen round-robin. \n
  *            CPDMA_CFG_TX_PRI_FIXED - The next channel for transmit is
  *                                     chosen priority based, channel 7 with the
- *                                     highest priority \n 
+ *                                     highest priority \n
  *
  * \return  None
  *
@@ -1536,14 +1536,14 @@ void CPSWCPDMAConfig(unsigned int baseAddr, unsigned int cfg)
 void CPSWCPDMACmdIdleEnable(unsigned int baseAddr)
 {
     HWREG(baseAddr + CPSW_CPDMA_DMACONTROL) |= CPSW_CPDMA_DMACONTROL_CMD_IDLE;
-    
+
     /* Wait till the state changes to idle */
     while((HWREG(baseAddr + CPSW_CPDMA_DMASTATUS) & CPSW_CPDMA_DMASTATUS_IDLE)
-          != CPSW_CPDMA_DMASTATUS_IDLE); 
+          != CPSW_CPDMA_DMASTATUS_IDLE);
 }
 
 /**
- * \brief   Disable the command idle mode for CPDMA. 
+ * \brief   Disable the command idle mode for CPDMA.
  *
  * \param   baseAddr      Base Address of the CPDMA module registers
  *
@@ -1557,9 +1557,9 @@ void CPSWCPDMACmdIdleDisable(unsigned int baseAddr)
 
 /**
  * \brief   Sets the RX buffer offset value. The RX buffer offset will be
- *          written by the port into each frame SOP buffer descriptor 
- *          buffer_offset field. The frame data will begin after the 
- *          rx_buffer_offset value of bytes. This value will be used for  
+ *          written by the port into each frame SOP buffer descriptor
+ *          buffer_offset field. The frame data will begin after the
+ *          rx_buffer_offset value of bytes. This value will be used for
  *          all the channels .
  *
  * \param   baseAddr      Base Address of the CPDMA module registers
@@ -1588,7 +1588,7 @@ void CPSWCPDMARxBufOffsetSet(unsigned int baseAddr, unsigned int bufOff)
  *                                                              pending \n
  *
  **/
-unsigned int CPSWCPDMATxIntStatRawGet(unsigned int baseAddr, 
+unsigned int CPSWCPDMATxIntStatRawGet(unsigned int baseAddr,
                                       unsigned int chanMask)
 {
     return (HWREG(baseAddr + CPSW_CPDMA_TX_INTSTAT_RAW) & chanMask);
@@ -1609,7 +1609,7 @@ unsigned int CPSWCPDMATxIntStatRawGet(unsigned int baseAddr,
  *                                                              pending \n
  *
  **/
-unsigned int CPSWCPDMATxIntStatMaskedGet(unsigned int baseAddr, 
+unsigned int CPSWCPDMATxIntStatMaskedGet(unsigned int baseAddr,
                                          unsigned int chanMask)
 {
     return (HWREG(baseAddr + CPSW_CPDMA_TX_INTSTAT_MASKED) & chanMask);
@@ -1625,8 +1625,8 @@ unsigned int CPSWCPDMATxIntStatMaskedGet(unsigned int baseAddr,
  *         0x01- for 0th channel, 0x80 for 7th channel, 0x81 for both 0th
  *         and 7th channel etc. \n
  *    'intType' can take one of the following values. \n
- *         CPDMA_RX_INT_THRESH_PEND - RX threshold interrupt pending \n               
- *         CPDMA_RX_INT_PULSE_PEND - RX pulse interrupt pending \n                    
+ *         CPDMA_RX_INT_THRESH_PEND - RX threshold interrupt pending \n
+ *         CPDMA_RX_INT_PULSE_PEND - RX pulse interrupt pending \n
  *
  * \return  Raw receive interrupt status \n
  *          bits for the 'chanMask' will be set if interrupt is pending \n
@@ -1634,12 +1634,12 @@ unsigned int CPSWCPDMATxIntStatMaskedGet(unsigned int baseAddr,
  *                                                              pending \n
  *
  **/
-unsigned int CPSWCPDMARxIntStatRawGet(unsigned int baseAddr, 
-                                      unsigned int chanMask, 
+unsigned int CPSWCPDMARxIntStatRawGet(unsigned int baseAddr,
+                                      unsigned int chanMask,
                                       unsigned int intType)
 {
     return ((HWREG(baseAddr + CPSW_CPDMA_RX_INTSTAT_RAW) >> intType)
-             & chanMask);    
+             & chanMask);
 }
 
 /**
@@ -1652,21 +1652,21 @@ unsigned int CPSWCPDMARxIntStatRawGet(unsigned int baseAddr,
  *         0x01- for 0th channel, 0x80 for 7th channel, 0x81 for both 0th
  *         and 7th channel etc. \n
  *    'intType' can take one of the following values. \n
- *         CPDMA_RX_INT_THRESH_PEND - RX threshold interrupt pending \n               
- *         CPDMA_RX_INT_PULSE_PEND - RX pulse interrupt pending \n                    
+ *         CPDMA_RX_INT_THRESH_PEND - RX threshold interrupt pending \n
+ *         CPDMA_RX_INT_PULSE_PEND - RX pulse interrupt pending \n
  *
  * \return  Masked receive interrupt status \n
  *          bits for the 'chanMask' will be set if interrupt is pending \n
- *          bits for the 'chanMask' will be cleared if interrupt is not 
+ *          bits for the 'chanMask' will be cleared if interrupt is not
  *                                                              pending \n
  *
  **/
-unsigned int CPSWCPDMARxIntStatMaskedGet(unsigned int baseAddr, 
+unsigned int CPSWCPDMARxIntStatMaskedGet(unsigned int baseAddr,
                                          unsigned int chanMask,
                                          unsigned int intType)
 {
-    return ((HWREG(baseAddr + CPSW_CPDMA_RX_INTMASK_SET) >> intType) 
-             & chanMask);    
+    return ((HWREG(baseAddr + CPSW_CPDMA_RX_INTMASK_SET) >> intType)
+             & chanMask);
 }
 
 /**
@@ -1699,22 +1699,22 @@ void CPSWContextSave(CPSWCONTEXT *contextPtr)
 
     for(idx = 0; idx < CPSW_MAX_NUM_ALE_ENTRY; idx++)
     {
-        CPSWALETableEntryGet(contextPtr->aleBase, idx, 
+        CPSWALETableEntryGet(contextPtr->aleBase, idx,
                              &(contextPtr->aleEntry[idx * 3]));
-    } 
+    }
 
     contextPtr->ssStatPortEn = HWREG(contextPtr->ssBase + CPSW_SS_STAT_PORT_EN);
     contextPtr->port1SaHi = HWREG(contextPtr->port1Base + CPSW_PORT_SA_HI);
     contextPtr->port1SaLo = HWREG(contextPtr->port1Base + CPSW_PORT_SA_LO);
     contextPtr->port2SaHi = HWREG(contextPtr->port2Base + CPSW_PORT_SA_HI);
     contextPtr->port2SaLo = HWREG(contextPtr->port2Base + CPSW_PORT_SA_LO);
-    contextPtr->cpdmaRxFB = HWREG(contextPtr->cpdmaBase 
+    contextPtr->cpdmaRxFB = HWREG(contextPtr->cpdmaBase
                                   + CPSW_CPDMA_RX_FREEBUFFER(0));
-    contextPtr->cpdmaTxCtl = HWREG(contextPtr->cpdmaBase 
+    contextPtr->cpdmaTxCtl = HWREG(contextPtr->cpdmaBase
                                    + CPSW_CPDMA_TX_CONTROL);
     contextPtr->cpdmaRxCtl = HWREG(contextPtr->cpdmaBase
                                    + CPSW_CPDMA_RX_CONTROL);
-    contextPtr->cpdmaRxHdp = HWREG(contextPtr->cpdmaBase 
+    contextPtr->cpdmaRxHdp = HWREG(contextPtr->cpdmaBase
                                    + CPSW_CPDMA_RX_HDP(0));
     contextPtr->txIntMaskSet = HWREG(contextPtr->cpdmaBase
                                      + CPSW_CPDMA_TX_INTMASK_SET);
@@ -1741,7 +1741,7 @@ void CPSWContextSave(CPSWCONTEXT *contextPtr)
 void CPSWContextRestore(CPSWCONTEXT *contextPtr)
 {
     unsigned int idx;
-    unsigned int *cppiDest = (unsigned int*)contextPtr->cppiRamBase; 
+    unsigned int *cppiDest = (unsigned int*)contextPtr->cppiRamBase;
 
     /* Restore the CPPI RAM contents */
     for(idx = 0; idx < (CPSW_SIZE_CPPI_RAM / 4); idx++, cppiDest++)
@@ -1767,15 +1767,15 @@ void CPSWContextRestore(CPSWCONTEXT *contextPtr)
     HWREG(contextPtr->port2Base + CPSW_PORT_SA_LO) = contextPtr->port2SaLo;
     HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_RX_FREEBUFFER(0)) =
                                 contextPtr->cpdmaRxFB;
-    HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_TX_CONTROL) 
+    HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_TX_CONTROL)
                                  = contextPtr->cpdmaTxCtl;
     HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_RX_CONTROL)
                                  = contextPtr->cpdmaRxCtl;
     HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_RX_HDP(0))
                                  = contextPtr->cpdmaRxHdp;
-    HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_TX_INTMASK_SET) 
+    HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_TX_INTMASK_SET)
                                  = contextPtr->txIntMaskSet;
-    HWREG(contextPtr->wrBase + CPSW_WR_C_RX_THRESH_EN(0) + 0x04) 
+    HWREG(contextPtr->wrBase + CPSW_WR_C_RX_THRESH_EN(0) + 0x04)
                                  = contextPtr->wrCoreIntTxPulse;
     HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_RX_INTMASK_SET)
                                  = contextPtr->rxIntMaskSet;
diff --git a/lib/tiam1808/drivers/cpu.c b/lib/tiam1808/drivers/cpu.c
index 259b9687c..595c5d109 100644
--- a/lib/tiam1808/drivers/cpu.c
+++ b/lib/tiam1808/drivers/cpu.c
@@ -43,7 +43,7 @@
 ******************************************************************************/
 /**
  * \brief     This API can be used to switch from user mode to privileged mode
- *            The priviledge mode will be system mode. System mode will share 
+ *            The priviledge mode will be system mode. System mode will share
  *            the same resources as user mode, but with privileges.
  *
  * \param     None.
@@ -59,7 +59,7 @@ void CPUSwitchToPrivilegedMode(void)
 }
 
 /**
- * \brief     This API can be used to switch from any previleged mode of ARM to 
+ * \brief     This API can be used to switch from any previleged mode of ARM to
  *            user mode. After this API is called, the program will continue
  *            to operate in non-privileged mode, until any exception occurs.
  *            After the exception is serviced, execution will continue in user
@@ -83,13 +83,13 @@ void CPUSwitchToUserMode(void)
 /**
  * \brief     This API is called when the CPU is aborted or during execution
  *            of any undefined instruction. Both IRQ and FIQ will be disabled
- *            when the CPU gets an abort and calls this API. 
+ *            when the CPU gets an abort and calls this API.
  *
  * \param     None.
  *
  * \return    None.
  *
- * Note : The user can perform error handling such as an immediate reset 
+ * Note : The user can perform error handling such as an immediate reset
  *        inside this API if required.
  **/
 void CPUAbortHandler(void)
@@ -109,7 +109,7 @@ unsigned int CPUIntStatus(void)
     /* IRQ and FIQ in CPSR */
     __asm("    mrs     r0, CPSR\n\t"
           "    and     %[result], r0, #0xC0" : [result] "=r" (stat));
-    
+
     return stat;
 }
 
diff --git a/lib/tiam1808/drivers/dmtimer.c b/lib/tiam1808/drivers/dmtimer.c
index 04071ba55..9c90b8e59 100644
--- a/lib/tiam1808/drivers/dmtimer.c
+++ b/lib/tiam1808/drivers/dmtimer.c
@@ -55,7 +55,7 @@
 *******************************************************************************/
 
 /**
- * \brief   This API will start the timer. 
+ * \brief   This API will start the timer.
  *
  * \param   baseAdd       Base Address of the DMTimer Module Register.
  *
@@ -71,7 +71,7 @@ void DMTimerEnable(unsigned int baseAdd)
 }
 
 /**
- * \brief   This API will stop the timer. 
+ * \brief   This API will stop the timer.
  *
  * \param   baseAdd      Base Address of the DMTimer Module Register.
  *
@@ -85,9 +85,9 @@ void DMTimerDisable(unsigned int baseAdd)
 }
 
 /**
- * \brief   This API will configure the timer in combinations of 
- *          'One Shot timer' and 'Compare' Mode or 'Auto-reload timer' 
- *          and 'Compare' Mode.  
+ * \brief   This API will configure the timer in combinations of
+ *          'One Shot timer' and 'Compare' Mode or 'Auto-reload timer'
+ *          and 'Compare' Mode.
  *
  * \param   baseAdd      Base Address of the DMTimer Module Register.
  * \param   timerMode    Mode for enabling the timer.
@@ -96,7 +96,7 @@ void DMTimerDisable(unsigned int baseAdd)
  *    DMTIMER_ONESHOT_CMP_ENABLE - One shot and compare mode enabled \n
  *    DMTIMER_ONESHOT_NOCMP_ENABLE - One shot enabled, compare mode disabled \n
  *    DMTIMER_AUTORLD_CMP_ENABLE - Auto-reload and compare mode enabled \n
- *    DMTIMER_AUTORLD_NOCMP_ENABLE - Auto-reload enabled, compare mode 
+ *    DMTIMER_AUTORLD_NOCMP_ENABLE - Auto-reload enabled, compare mode
  *                                   disabled \n
  *
  * \return  None.
@@ -108,7 +108,7 @@ void DMTimerModeConfigure(unsigned int baseAdd, unsigned int timerMode)
     HWREG(baseAdd + DMTIMER_TCLR) &= ~(DMTIMER_TCLR_AR | DMTIMER_TCLR_CE);
 
     /* Set the timer mode in TCLR register */
-    HWREG(baseAdd + DMTIMER_TCLR) |= (timerMode & (DMTIMER_TCLR_AR | 
+    HWREG(baseAdd + DMTIMER_TCLR) |= (timerMode & (DMTIMER_TCLR_AR |
                                                    DMTIMER_TCLR_CE));
 }
 
@@ -162,7 +162,7 @@ void DMTimerPreScalerClkDisable(unsigned int baseAdd)
  *
  * \return  None.
  *
- * \note    Value can be loaded into the counter register when the counter is 
+ * \note    Value can be loaded into the counter register when the counter is
  *          stopped or when it is running.
  **/
 void DMTimerCounterSet(unsigned int baseAdd, unsigned int counter)
@@ -196,7 +196,7 @@ unsigned int DMTimerCounterGet(unsigned int baseAdd)
  *
  * \return  None.
  *
- * \note:   It is recommended to not use reload value as 0xFFFFFFFF as it can 
+ * \note:   It is recommended to not use reload value as 0xFFFFFFFF as it can
  *          lead to undesired results.
  **/
 void DMTimerReloadSet(unsigned int baseAdd, unsigned int reload)
@@ -223,7 +223,7 @@ unsigned int DMTimerReloadGet(unsigned int baseAdd)
  * \brief   Configure and enable PWM feature of DMTimer.
  *
  * \param   baseAdd       Base Address of the DMTimer Module Register.
- * \param   ptMode        Pulse or toggle mode also positive or negative pulse 
+ * \param   ptMode        Pulse or toggle mode also positive or negative pulse
  *                        for PWM pin.
  * \param   trgOpMode     Trigger output mode on PWM pin.
  *
@@ -244,11 +244,11 @@ void DMTimerPWMEnable(unsigned int baseAdd, unsigned int ptMode,
                       unsigned int trgOpMode)
 {
     /* Clear the PT, and TRG field of TCLR */
-    HWREG(baseAdd + DMTIMER_TCLR) &= ~(DMTIMER_TCLR_PT | DMTIMER_TCLR_TRG | 
-                                       DMTIMER_TCLR_SCPWM);  
+    HWREG(baseAdd + DMTIMER_TCLR) &= ~(DMTIMER_TCLR_PT | DMTIMER_TCLR_TRG |
+                                       DMTIMER_TCLR_SCPWM);
 
     /* Write to TCLR */
-    HWREG(baseAdd + DMTIMER_TCLR) |= ((ptMode | trgOpMode) & (DMTIMER_TCLR_PT | 
+    HWREG(baseAdd + DMTIMER_TCLR) |= ((ptMode | trgOpMode) & (DMTIMER_TCLR_PT |
                                        DMTIMER_TCLR_TRG | DMTIMER_TCLR_SCPWM));
 }
 
@@ -257,9 +257,9 @@ void DMTimerPWMEnable(unsigned int baseAdd, unsigned int ptMode,
  *
  * \param   baseAdd       Base Address of the DMTimer Module Register.
  *
- * \return  None. 
+ * \return  None.
  *
- * \note:   Modulation on PWM pin is stopped only after this API is called 
+ * \note:   Modulation on PWM pin is stopped only after this API is called
  *          and overflow occurs.
  **/
 void DMTimerPWMDisable(unsigned int baseAdd)
@@ -288,15 +288,15 @@ void DMTimerPWMDisable(unsigned int baseAdd)
  * \return  None.
  *
  **/
-void DMTimerCaptureConfigure(unsigned int baseAdd, unsigned int tcm, 
+void DMTimerCaptureConfigure(unsigned int baseAdd, unsigned int tcm,
                              unsigned int captMode)
 {
     /* Clear the TCM and CAPT_MODE fields of TCLR */
-    HWREG(baseAdd + DMTIMER_TCLR) &= ~(DMTIMER_TCLR_TCM | 
+    HWREG(baseAdd + DMTIMER_TCLR) &= ~(DMTIMER_TCLR_TCM |
                                        DMTIMER_TCLR_CAPT_MODE);
 
     /* Write tcm and captMode fields to TCLR */
-    HWREG(baseAdd + DMTIMER_TCLR) |= ((tcm | captMode) & (DMTIMER_TCLR_TCM | 
+    HWREG(baseAdd + DMTIMER_TCLR) |= ((tcm | captMode) & (DMTIMER_TCLR_TCM |
                                        DMTIMER_TCLR_CAPT_MODE));
 }
 
@@ -305,10 +305,10 @@ void DMTimerCaptureConfigure(unsigned int baseAdd, unsigned int tcm,
  *
  * \param   baseAdd       Base Address of the DMTimer Module Register.
  * \param   gpoCfg        General purpose output.
- * 
+ *
  * 'gpoCfg' can take the following values \n
  *    DMTIMER_GPO_CFG_0 - PORGPOCFG drives 0 \n
- *    DMTIMER_GPO_CFG_1 - PORGPOCFG drives 1 \n  
+ *    DMTIMER_GPO_CFG_1 - PORGPOCFG drives 1 \n
  *
  * \return  None.
  *
@@ -389,7 +389,7 @@ unsigned int DMTimerCapture2Get(unsigned int baseAdd)
  *    DMTIMER_EMUFREE_FREE - Emulation mode free \n
  *    DMTIMER_EMUFREE_FROZEN - Emulation mode is frozen \n
  *
- * \return  None. 
+ * \return  None.
  *
  **/
 void DMTimerEmulationModeConfigure(unsigned int baseAdd, unsigned int emuMode)
@@ -422,7 +422,7 @@ void DMTimerPwrMngmntConfigure(unsigned int baseAdd, unsigned int pwrMngMode)
     HWREG(baseAdd + DMTIMER_TIOCP_CFG) &= ~DMTIMER_TIOCP_CFG_IDLEMODE;
 
     /* Configure power mangagement mode */
-    HWREG(baseAdd + DMTIMER_TIOCP_CFG) |= (pwrMngMode & 
+    HWREG(baseAdd + DMTIMER_TIOCP_CFG) |= (pwrMngMode &
                                            DMTIMER_TIOCP_CFG_IDLEMODE);
 }
 
@@ -433,7 +433,7 @@ void DMTimerPwrMngmntConfigure(unsigned int baseAdd, unsigned int pwrMngMode)
  *
  * \return  None.
  *
- * \note    This API has to be called in the Interrupt service routine after 
+ * \note    This API has to be called in the Interrupt service routine after
  *          servicing the interrupts.
  *
  **/
@@ -460,7 +460,7 @@ void DMTimerEndOfInterrupt(unsigned int baseAdd)
 void DMTimerIntRawStatusSet(unsigned int baseAdd, unsigned int intFlags)
 {
     /* Trigger the events in IRQSTATUS_RAW register */
-    HWREG(baseAdd + DMTIMER_IRQSTATUS_RAW) = (intFlags & 
+    HWREG(baseAdd + DMTIMER_IRQSTATUS_RAW) = (intFlags &
                                            (DMTIMER_IRQSTATUS_RAW_MAT_IT_FLAG |
                                             DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG |
                                             DMTIMER_IRQSTATUS_RAW_TCAR_IT_FLAG));
@@ -511,9 +511,9 @@ unsigned int DMTimerIntStatusGet(unsigned int baseAdd)
 void DMTimerIntStatusClear(unsigned int baseAdd, unsigned int intFlags)
 {
     /* Clear the interrupt status from IRQSTATUS register */
-    HWREG(baseAdd + DMTIMER_IRQSTATUS) = (intFlags & 
-                                         (DMTIMER_IRQSTATUS_TCAR_IT_FLAG | 
-                                          DMTIMER_IRQSTATUS_OVF_IT_FLAG | 
+    HWREG(baseAdd + DMTIMER_IRQSTATUS) = (intFlags &
+                                         (DMTIMER_IRQSTATUS_TCAR_IT_FLAG |
+                                          DMTIMER_IRQSTATUS_OVF_IT_FLAG |
                                           DMTIMER_IRQSTATUS_MAT_IT_FLAG));
 }
 
@@ -534,9 +534,9 @@ void DMTimerIntStatusClear(unsigned int baseAdd, unsigned int intFlags)
 void DMTimerIntEnable(unsigned int baseAdd, unsigned int intFlags)
 {
     /* Enable the DMTimer interrupts represented by intFlags */
-    HWREG(baseAdd + DMTIMER_IRQENABLE_SET) = (intFlags & 
+    HWREG(baseAdd + DMTIMER_IRQENABLE_SET) = (intFlags &
                                            (DMTIMER_IRQENABLE_SET_TCAR_EN_FLAG |
-                                            DMTIMER_IRQENABLE_SET_OVF_EN_FLAG | 
+                                            DMTIMER_IRQENABLE_SET_OVF_EN_FLAG |
                                             DMTIMER_IRQENABLE_SET_MAT_EN_FLAG));
 }
 
@@ -570,9 +570,9 @@ void DMTimerIntDisable(unsigned int baseAdd, unsigned int intFlags)
  *
  * \return  None.
  *
- * \note    When we have enabled the timer in Auto-reload mode, the value from 
- *          TLDR is reloaded into TCRR when a overflow condition occurs. But if 
- *           we want to load the contents from TLDR to TCRR before overflow 
+ * \note    When we have enabled the timer in Auto-reload mode, the value from
+ *          TLDR is reloaded into TCRR when a overflow condition occurs. But if
+ *           we want to load the contents from TLDR to TCRR before overflow
  *          occurs then call this API.
  **/
 void DMTimerTriggerSet(unsigned int baseAdd)
@@ -633,10 +633,10 @@ unsigned int DMTimerIntEnableGet(unsigned int baseAdd)
  **/
 void DMTimerWakeUpEnable(unsigned int baseAdd, unsigned int wakeUpFlags)
 {
-    /* Write to the fields of IRQWAKEEN register */    
-    HWREG(baseAdd + DMTIMER_IRQWAKEEN) |= (wakeUpFlags & 
-                                          (DMTIMER_IRQWAKEEN_TCAR_WUP_ENA | 
-                                           DMTIMER_IRQWAKEEN_OVF_WUP_ENA | 
+    /* Write to the fields of IRQWAKEEN register */
+    HWREG(baseAdd + DMTIMER_IRQWAKEEN) |= (wakeUpFlags &
+                                          (DMTIMER_IRQWAKEEN_TCAR_WUP_ENA |
+                                           DMTIMER_IRQWAKEEN_OVF_WUP_ENA |
                                            DMTIMER_IRQWAKEEN_MAT_WUP_ENA));
 }
 
@@ -674,7 +674,7 @@ void DMTimerWakeUpDisable(unsigned int baseAdd, unsigned int wakeUpFlags)
 unsigned int DMTimerWritePostedStatusGet(unsigned int baseAdd)
 {
     /* Return the status of TWPS register */
-    return (HWREG(baseAdd + DMTIMER_TWPS)); 
+    return (HWREG(baseAdd + DMTIMER_TWPS));
 }
 
 /**
@@ -682,10 +682,10 @@ unsigned int DMTimerWritePostedStatusGet(unsigned int baseAdd)
  *
  * \param   baseAdd       Base Address of the DMTimer Module Register.
  * \param   rstOption     Enable/Disable reset option for DMTimer.
- *          
+ *
  * 'rstOption' can take the following values \n
  *    DMTIMER_SFT_RESET_ENABLE - Software reset is enabled \n
- *    DMTIMER_SFT_RESET_DISABLE - Software reset is disabled \n   
+ *    DMTIMER_SFT_RESET_DISABLE - Software reset is disabled \n
  *
  * \return  None.
  *
diff --git a/lib/tiam1808/drivers/ecap.c b/lib/tiam1808/drivers/ecap.c
index 9d7c32041..9904cb95f 100644
--- a/lib/tiam1808/drivers/ecap.c
+++ b/lib/tiam1808/drivers/ecap.c
@@ -126,7 +126,7 @@ unsigned int ECAPClockDisableStatusGet(unsigned int baseAdd)
  **/
 void ECAPCaptureLoadingEnable(unsigned int baseAdd)
 {
-    HWREGH(baseAdd + ECAP_ECCTL1) |= ECAP_ECCTL1_CAPLDEN; 
+    HWREGH(baseAdd + ECAP_ECCTL1) |= ECAP_ECCTL1_CAPLDEN;
 }
 
 /**
@@ -139,7 +139,7 @@ void ECAPCaptureLoadingEnable(unsigned int baseAdd)
  **/
 void ECAPCaptureLoadingDisable(unsigned int baseAdd)
 {
-    HWREGH(baseAdd + ECAP_ECCTL1) &= ~ECAP_ECCTL1_CAPLDEN; 
+    HWREGH(baseAdd + ECAP_ECCTL1) &= ~ECAP_ECCTL1_CAPLDEN;
 }
 
 /**
@@ -167,7 +167,7 @@ void ECAPPrescaleConfig(unsigned int baseAdd, unsigned int prescale)
  * \param   baseAdd     It is the Memory address of the ECAP instance used.
  * \param   modeSelect  It is the value which determines whether ecapture
  *                      module to operate in capture mode or in APWM mode.\n
- * 
+ *
  *         modeSelect can take following macros.
  *
  *         ECAP_CAPTURE_MODE - Capture Mode.\n
@@ -187,14 +187,14 @@ void ECAPOperatingModeSelect(unsigned int baseAdd, unsigned int modeSelect)
          HWREGH(baseAdd + ECAP_ECCTL2) |=  ECAP_ECCTL2_CAP_APWM;
     }
 }
-    
+
 /**
  * \brief   This function returns time-stamp for a given capture event.
  *
  * \param   baseAdd     It is the Memory address of the ECAP instance used.
  * \param   capEvtFlag  It is the value which determines for which capture event
  *                      time-stam has to returned.
- * 
+ *
  *         capEvtFlag can take following macros.
  *
  *         ECAP_CAPTURE_EVENT_1 - Capture Event 1.\n
@@ -211,7 +211,7 @@ unsigned int ECAPTimeStampRead(unsigned int baseAdd, unsigned int capEvtFlag)
 }
 
 /**
- * \brief   This function configures the counter register which is used as 
+ * \brief   This function configures the counter register which is used as
  *          Capture Time base.
  *
  * \param   baseAdd     It is the Memory address of the ECAP instance used.
@@ -227,7 +227,7 @@ void ECAPCounterConfig(unsigned int baseAdd, unsigned int countVal)
 
 /**
  * \brief   This function configures Capture Event polarity.
- *          
+ *
  * \param   baseAdd     It is the Memory address of the ECAP instance used.
  * \param   capEvt1pol  It determines whether Capture Event1 has to be generated
  *                      on rising edge or falling edge of pulse.
@@ -240,7 +240,7 @@ void ECAPCounterConfig(unsigned int baseAdd, unsigned int countVal)
  *
  * \param   capEvt4pol  It determines whether Capture Event4 has to be generated
  *                      on rising edge or falling edge of pulse.
- * 
+ *
  *                      0 - falling edge
  *                      1 - rising  edge
  * \return  None.
@@ -258,18 +258,18 @@ void ECAPCapeEvtPolarityConfig(unsigned int baseAdd, unsigned int capEvt1pol,
 
 /**
  * \brief   This function enables reset of the counters upon Capture Events.
- *          
+ *
  * \param   baseAdd      It is the Memory address of the ECAP instance used.
- * \param   CounterRst1  It determines whether counter has to be reset upon 
+ * \param   CounterRst1  It determines whether counter has to be reset upon
  *                       Capture Event1.
  *
- * \param   CounterRst2  It determines whether counter has to be reset upon 
+ * \param   CounterRst2  It determines whether counter has to be reset upon
  *                       Capture Event2.
  *
- * \param   CounterRst3  It determines whether counter has to be reset upon 
+ * \param   CounterRst3  It determines whether counter has to be reset upon
  *                       Capture Event3.
  *
- * \param   CounterRst4  It determines whether counter has to be reset upon 
+ * \param   CounterRst4  It determines whether counter has to be reset upon
  *                       Capture Event4.
  *
  *                       0 - Don't reset counter upon capture event.\n
@@ -300,7 +300,7 @@ void ECAPCaptureEvtCntrRstConfig(unsigned int baseAdd, unsigned int CounterRst1,
  **/
 void ECAPContinousModeConfig(unsigned int baseAdd)
 {
-    HWREGH(baseAdd + ECAP_ECCTL2) &= ~ECAP_ECCTL2_CONT_ONESHT;  
+    HWREGH(baseAdd + ECAP_ECCTL2) &= ~ECAP_ECCTL2_CONT_ONESHT;
 }
 
 /**
@@ -327,11 +327,11 @@ void ECAPContinousModeConfig(unsigned int baseAdd)
 void ECAPOneShotModeConfig(unsigned int baseAdd, unsigned int stopVal)
 {
     HWREGH(baseAdd + ECAP_ECCTL2) |= ECAP_ECCTL2_CONT_ONESHT;
-   
+
     HWREGH(baseAdd + ECAP_ECCTL2) &= 0xfffffff9;
 
     HWREGH(baseAdd + ECAP_ECCTL2) |= stopVal;
-}  
+}
 
 /**
  * \brief   This function configures ECAP to One-Short Re-arming.
@@ -339,7 +339,7 @@ void ECAPOneShotModeConfig(unsigned int baseAdd, unsigned int stopVal)
  * \param   baseAdd   It is the Memory address of the ECAP instance used.
  *
  * \return  None.\n
- * 
+ *
  * When this API is invoked following things happen.\n
  *
  * 1. Resets Mod4 counter to zero.\n
@@ -365,7 +365,7 @@ void ECAPOneShotREARM(unsigned int baseAdd)
  *         ECAP_APWM_ACTIVE_LOW.\n
  *
  * \return  None.
- * 
+ *
  **/
 void ECAPAPWMPolarityConfig(unsigned int baseAdd, unsigned int flag)
 {
@@ -393,7 +393,7 @@ void ECAPAPWMPolarityConfig(unsigned int baseAdd, unsigned int flag)
  *         ECAP_COUNTER_FREE_RUNNING.\n
  *
  * \return  None.
- * 
+ *
  **/
 void ECAPCounterControl(unsigned int baseAdd, unsigned int flag)
 {
@@ -424,7 +424,7 @@ void ECAPCounterControl(unsigned int baseAdd, unsigned int flag)
  * \param   syncOut   It is the value which select type of syncOut signal
  *                    (i.e select syncIn event to be the Sync-Out signal,
  *                         select PRD_eq event to be Sync-Out signal).\n
- *                    
+ *
  *
  *         syncOut can take following macros.\n
  *
@@ -433,7 +433,7 @@ void ECAPCounterControl(unsigned int baseAdd, unsigned int flag)
  *         ECAP_SYNC_OUT_DISABLE - Disable syncOut signal.\n
  *
  * \return  None.
- * 
+ *
  **/
 void ECAPSyncInOutSelect(unsigned int baseAdd, unsigned int syncIn,
                          unsigned int syncOut)
@@ -452,15 +452,15 @@ void ECAPSyncInOutSelect(unsigned int baseAdd, unsigned int syncIn,
  * \param   baseAdd    It is the Memory address of the ECAP instance used.
  * \param   compareVal It is the Compare value to be configured.
  * \param   periodVal  It is the Period value to be configured.
- * 
+ *
  * \return  None.
  *
  **/
 void ECAPAPWMCaptureConfig(unsigned int baseAdd, unsigned int compareVal,
                            unsigned int periodVal)
 {
-    HWREG(baseAdd + ECAP_CAP1) = periodVal; 
-    HWREG(baseAdd + ECAP_CAP2) = compareVal; 
+    HWREG(baseAdd + ECAP_CAP1) = periodVal;
+    HWREG(baseAdd + ECAP_CAP2) = compareVal;
 }
 
 /**
@@ -469,15 +469,15 @@ void ECAPAPWMCaptureConfig(unsigned int baseAdd, unsigned int compareVal,
  * \param   baseAdd    It is the Memory address of the ECAP instance used.
  * \param   compareVal It is the Compare value to be configured.
  * \param   periodVal  It is the Period value to be configured.
- * 
+ *
  * \return  None.
  *
  **/
 void ECAPAPWMShadowCaptureConfig(unsigned int baseAdd, unsigned int compareVal,
                                  unsigned int periodVal)
 {
-    HWREG(baseAdd + ECAP_CAP1) = periodVal; 
-    HWREG(baseAdd + ECAP_CAP2) = compareVal; 
+    HWREG(baseAdd + ECAP_CAP1) = periodVal;
+    HWREG(baseAdd + ECAP_CAP2) = compareVal;
 }
 
 /**
@@ -497,7 +497,7 @@ void ECAPCounterPhaseValConfig(unsigned int baseAdd, unsigned int cntPhaseVal)
 
 /**
  * \brief   This function enables the generation of interrupts if any of
- *          event interrupt are enable and corresponding event interrupt 
+ *          event interrupt are enable and corresponding event interrupt
  *          flag is set.
  *
  * \param   baseAdd   It is the Memory address of the ECAP instance used.
@@ -525,7 +525,7 @@ void ECAPGlobalIntEnable(unsigned int baseAdd)
  *          ECAP_CEVT4_INT   - Enable Capture Event 4 interrupt.\n
  *          ECAP_CNTOVF_INT  - Enable Counter Overflow interrupt.\n
  *          ECAP_PRDEQ_INT   - Enable Period equal interrupt.\n
- *          ECAP_CMPEQ_INT   - Enable Compare equal interrupt.\n  
+ *          ECAP_CMPEQ_INT   - Enable Compare equal interrupt.\n
  *
  * \return  None.
  *
@@ -550,7 +550,7 @@ void ECAPIntEnable(unsigned int baseAdd, unsigned int flag)
  *          ECAP_CEVT4_INT   - Enable Capture Event 4 interrupt.\n
  *          ECAP_CNTOVF_INT  - Enable Counter Overflow interrupt.\n
  *          ECAP_PRDEQ_INT   - Enable Period equal interrupt.\n
- *          ECAP_CMPEQ_INT   - Enable Compare equal interrupt.\n  
+ *          ECAP_CMPEQ_INT   - Enable Compare equal interrupt.\n
  *
  * \return  None.
  *
@@ -575,8 +575,8 @@ void ECAPIntDisable(unsigned int baseAdd, unsigned int flag)
  *          ECAP_CEVT4_INT   - Status of Capture Event 4 interrupt.\n
  *          ECAP_CNTOVF_INT  - Status of Counter Overflow interrupt.\n
  *          ECAP_PRDEQ_INT   - Status of Period equal interrupt.\n
- *          ECAP_CMPEQ_INT   - Status of Compare equal interrupt.\n  
- *          ECAP_GLOBAL_INT  - Global interrupt status.\n 
+ *          ECAP_CMPEQ_INT   - Status of Compare equal interrupt.\n
+ *          ECAP_GLOBAL_INT  - Global interrupt status.\n
  *
  * \returns Status of the specified interrupts.
  *
@@ -601,7 +601,7 @@ unsigned int ECAPIntStatus(unsigned int baseAdd, unsigned int flag)
  *          ECAP_CEVT4_INT   - Status of Capture Event 4 interrupt.\n
  *          ECAP_CNTOVF_INT  - Status of Counter Overflow interrupt.\n
  *          ECAP_PRDEQ_INT   - Status of Period equal interrupt.\n
- *          ECAP_CMPEQ_INT   - Status of Compare equal interrupt.\n  
+ *          ECAP_CMPEQ_INT   - Status of Compare equal interrupt.\n
  *
  * \return  None.
  *
diff --git a/lib/tiam1808/drivers/edma.c b/lib/tiam1808/drivers/edma.c
index cd1b0aafe..1b75dd7c9 100644
--- a/lib/tiam1808/drivers/edma.c
+++ b/lib/tiam1808/drivers/edma.c
@@ -57,7 +57,7 @@ unsigned int regionId;
 
 /**
  *  \brief   EDMA3 Initialization
- *  
+ *
  *  This function initializes the EDMA3 Driver
  *  Clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) &
  *  initialize the Queue Number Registers
@@ -71,7 +71,7 @@ unsigned int regionId;
  *  \return None
  *
  *  \note   The regionId is the shadow region(0 or 1) used and the,
- *          Event Queue used is either (0 or 1). There are only four shadow 
+ *          Event Queue used is either (0 or 1). There are only four shadow
  *          regions and only two event Queues
  */
 void EDMA3Init(unsigned int baseAdd,
@@ -79,7 +79,7 @@ void EDMA3Init(unsigned int baseAdd,
 {
     unsigned int count = 0;
     unsigned int i = 0;
-    
+
 #ifdef _TMS320C6X
     /* For DSP, regionId is assigned here and used globally in the driver */
     regionId = (unsigned int)1u;
@@ -97,15 +97,15 @@ void EDMA3Init(unsigned int baseAdd,
     /* Clear CCERR register                                                 */
     HWREG(baseAdd + EDMA3CC_CCERRCLR) = EDMA3_SET_ALL_BITS;
 
-    /* FOR TYPE EDMA*/ 
+    /* FOR TYPE EDMA*/
     /* Enable the DMA (0 - 64) channels in the DRAE and DRAEH register */
-       
+
     HWREG(baseAdd + EDMA3CC_DRAE(regionId)) = EDMA3_SET_ALL_BITS;
     HWREG(baseAdd + EDMA3CC_DRAEH(regionId)) = EDMA3_SET_ALL_BITS;
 
 
     if((EDMA_REVID_AM335X == EDMAVersionGet()))
-    {           
+    {
          for(i = 0; i < 64; i++)
          {
               /* All events are one to one mapped with the channels */
@@ -116,9 +116,9 @@ void EDMA3Init(unsigned int baseAdd,
     /* Initialize the DMA Queue Number Registers                            */
     for (count = 0;count < SOC_EDMA3_NUM_DMACH; count++)
     {
-         HWREG(baseAdd + EDMA3CC_DMAQNUM(count >> 3u)) &= 
+         HWREG(baseAdd + EDMA3CC_DMAQNUM(count >> 3u)) &=
                                                     EDMA3CC_DMAQNUM_CLR(count);
-         HWREG(baseAdd + EDMA3CC_DMAQNUM(count >> 3u)) |= 
+         HWREG(baseAdd + EDMA3CC_DMAQNUM(count >> 3u)) |=
                                                     EDMA3CC_DMAQNUM_SET(count,queNum);
     }
 
@@ -130,7 +130,7 @@ void EDMA3Init(unsigned int baseAdd,
     for (count = 0;count < SOC_EDMA3_NUM_QDMACH; count++)
     {
         HWREG(baseAdd + EDMA3CC_QDMAQNUM) &= EDMA3CC_QDMAQNUM_CLR(count);
-        HWREG(baseAdd + EDMA3CC_QDMAQNUM) |= 
+        HWREG(baseAdd + EDMA3CC_QDMAQNUM) |=
                        EDMA3CC_QDMAQNUM_SET(count,queNum);
     }
 }
@@ -150,7 +150,7 @@ unsigned int EDMA3PeripheralIdGet(unsigned int baseAdd)
 /**
  * \brief  Enable channel to Shadow region mapping
  *
- * This API allocates DMA/QDMA channels or TCCs, and the same resources are 
+ * This API allocates DMA/QDMA channels or TCCs, and the same resources are
  * enabled in the shadow region specific register (DRAE/DRAEH/QRAE).
  * Here only one shadow region is used since, there is only one Master.
  *
@@ -168,14 +168,14 @@ unsigned int EDMA3PeripheralIdGet(unsigned int baseAdd)
  *
  *  \return  None
  */
-void EDMA3EnableChInShadowReg(unsigned int baseAdd, 
-                              unsigned int chType, 
+void EDMA3EnableChInShadowReg(unsigned int baseAdd,
+                              unsigned int chType,
                               unsigned int chNum)
 {
     /* Allocate the DMA/QDMA channel */
     if (EDMA3_CHANNEL_TYPE_DMA == chType)
     {
-         /* FOR TYPE EDMA*/ 
+         /* FOR TYPE EDMA*/
          if(chNum < 32)
          {
               /* Enable the DMA channel in the DRAE registers */
@@ -186,7 +186,7 @@ void EDMA3EnableChInShadowReg(unsigned int baseAdd,
               /* Enable the DMA channel in the DRAEH registers */
               HWREG(baseAdd + EDMA3CC_DRAEH(regionId)) |= (0x01u << (chNum - 32));
          }
-        
+
     }
     else if (EDMA3_CHANNEL_TYPE_QDMA== chType)
     {
@@ -199,7 +199,7 @@ void EDMA3EnableChInShadowReg(unsigned int baseAdd,
 /**
  * \brief  Disable channel to Shadow region mapping
  *
- * This API allocates DMA/QDMA channels or TCCs, and the same resources are 
+ * This API allocates DMA/QDMA channels or TCCs, and the same resources are
  * enabled in the shadow region specific register (DRAE/DRAEH/QRAE).
  * Here only one shadow region is used since, there is only one Master.
  *
@@ -217,8 +217,8 @@ void EDMA3EnableChInShadowReg(unsigned int baseAdd,
  *
  *  \return  None
  */
-void EDMA3DisableChInShadowReg(unsigned int baseAdd, 
-                               unsigned int chType, 
+void EDMA3DisableChInShadowReg(unsigned int baseAdd,
+                               unsigned int chType,
                                unsigned int chNum)
 {
     /* Allocate the DMA/QDMA channel */
@@ -226,7 +226,7 @@ void EDMA3DisableChInShadowReg(unsigned int baseAdd,
     {
         /* FOR TYPE EDMA*/
          if(chNum < 32)
-         { 
+         {
               /* Enable the DMA channel in the DRAE registers */
               HWREG(baseAdd + EDMA3CC_DRAE(regionId)) &= ~(0x01u << chNum);
          }
@@ -262,7 +262,7 @@ void EDMA3ChannelToParamMap(unsigned int baseAdd,
                             unsigned int paramSet)
 {
     HWREG(baseAdd + EDMA3CC_DCHMAP(channel)) = paramSet << 5;
-} 
+}
 
 /**
  *  \brief  Map channel to Event Queue
@@ -287,24 +287,24 @@ void EDMA3ChannelToParamMap(unsigned int baseAdd,
  *
  *  \return  None
  */
-void EDMA3MapChToEvtQ(unsigned int baseAdd, 
-                      unsigned int chType, 
-                      unsigned int chNum, 
+void EDMA3MapChToEvtQ(unsigned int baseAdd,
+                      unsigned int chType,
+                      unsigned int chNum,
                       unsigned int evtQNum)
 {
     if (EDMA3_CHANNEL_TYPE_DMA == chType)
     {
         /* Associate DMA Channel to Event Queue                             */
-        HWREG(baseAdd + EDMA3CC_DMAQNUM((chNum) >> 3u)) &= 
+        HWREG(baseAdd + EDMA3CC_DMAQNUM((chNum) >> 3u)) &=
                              EDMA3CC_DMAQNUM_CLR(chNum);
 
-        HWREG(baseAdd + EDMA3CC_DMAQNUM((chNum) >> 3u)) |= 
+        HWREG(baseAdd + EDMA3CC_DMAQNUM((chNum) >> 3u)) |=
                       EDMA3CC_DMAQNUM_SET((chNum), evtQNum);
     }
     else if (EDMA3_CHANNEL_TYPE_QDMA == chType)
     {
         /* Associate QDMA Channel to Event Queue                            */
-        HWREG(baseAdd + EDMA3CC_QDMAQNUM) |= 
+        HWREG(baseAdd + EDMA3CC_QDMAQNUM) |=
                        EDMA3CC_QDMAQNUM_SET(chNum, evtQNum);
     }
 }
@@ -328,20 +328,20 @@ void EDMA3MapChToEvtQ(unsigned int baseAdd,
  *
  *  \return  None
  */
-void EDMA3UnmapChToEvtQ(unsigned int baseAdd, 
-                        unsigned int chType, 
+void EDMA3UnmapChToEvtQ(unsigned int baseAdd,
+                        unsigned int chType,
                         unsigned int chNum)
 {
     if (EDMA3_CHANNEL_TYPE_DMA == chType)
     {
         /* Unmap DMA Channel to Event Queue                                */
-        HWREG(baseAdd + EDMA3CC_DMAQNUM((chNum) >> 3u)) |= 
+        HWREG(baseAdd + EDMA3CC_DMAQNUM((chNum) >> 3u)) |=
                           EDMA3CC_DMAQNUM_CLR(chNum);
     }
     else if (EDMA3_CHANNEL_TYPE_QDMA == chType)
     {
         /* Unmap QDMA Channel to Event Queue                               */
-        HWREG(baseAdd + EDMA3CC_QDMAQNUM) |= 
+        HWREG(baseAdd + EDMA3CC_QDMAQNUM) |=
                              EDMA3CC_QDMAQNUM_CLR(chNum);
     }
 }
@@ -349,7 +349,7 @@ void EDMA3UnmapChToEvtQ(unsigned int baseAdd,
 /**
  *  \brief  Enables the user to map a QDMA channel to PaRAM set
  *          This API Needs to be called before programming the paRAM sets for
- *          the QDMA Channels.Application needs to maitain the paRAMId 
+ *          the QDMA Channels.Application needs to maitain the paRAMId
  *          provided by this API.This paRAMId is used to set paRAM and get
  *          paRAM. Refer corresponding API's for more details.
  *
@@ -362,10 +362,10 @@ void EDMA3UnmapChToEvtQ(unsigned int baseAdd,
  *
  *  \return None
  *
- *  Note : The PaRAMId requested must be greater than 32(SOC_EDMA3_NUM_DMACH). 
- *         and lesser than SOC_EDMA3_NUM_DMACH + chNum  Because, the first 
+ *  Note : The PaRAMId requested must be greater than 32(SOC_EDMA3_NUM_DMACH).
+ *         and lesser than SOC_EDMA3_NUM_DMACH + chNum  Because, the first
  *         32 PaRAM's are directly mapped to first 32 DMA channels and (32 - 38)
- *         for QDMA Channels. (32 - 38) is assigned by driver in this API. 
+ *         for QDMA Channels. (32 - 38) is assigned by driver in this API.
  *
  */
 void EDMA3MapQdmaChToPaRAM(unsigned int baseAdd,
@@ -374,7 +374,7 @@ void EDMA3MapQdmaChToPaRAM(unsigned int baseAdd,
 {
     /* First 32 channels are for DMA only                                   */
     /* if (((*paRAMId) > SOC_EDMA3_NUM_DMACH) &&
-            ((*paRAMId) < SOC_EDMA3_NUM_DMACH+SOC_EDMA3_NUM_QDMACH))  */ 
+            ((*paRAMId) < SOC_EDMA3_NUM_DMACH+SOC_EDMA3_NUM_QDMACH))  */
     if ((SOC_EDMA3_NUM_DMACH + chNum) == (*paRAMId))
     {
         /* Map Parameter RAM Set Number for specified channelId             */
@@ -422,10 +422,10 @@ void EDMA3SetQdmaTrigWord(unsigned int baseAdd,
  *  \param   baseAdd                Memory address of the EDMA instance used.\n
  *
  *  \param   chNum                  Allocated channel number.\n
- * 
+ *
  *  \return  None
  */
-void EDMA3ClrMissEvt(unsigned int baseAdd, 
+void EDMA3ClrMissEvt(unsigned int baseAdd,
                      unsigned int chNum)
 {
     if(chNum < 32)
@@ -436,7 +436,7 @@ void EDMA3ClrMissEvt(unsigned int baseAdd,
          HWREG(baseAdd + EDMA3CC_EMCR) |= (0x01u <<  chNum);
     }
     else
-    { 
+    {
          HWREG(baseAdd + EDMA3CC_S_SECRH(regionId)) = (0x01u << (chNum - 32));
          /*clear EMCRH to clean any previous NULL request                         */
          HWREG(baseAdd + EDMA3CC_EMCRH) |= (0x01u <<  (chNum - 32));
@@ -450,15 +450,15 @@ void EDMA3ClrMissEvt(unsigned int baseAdd,
  *  \param   baseAdd                Memory address of the EDMA instance used.\n
  *
  *  \param   chNum                  Allocated channel number.\n
- * 
+ *
  *  \return  None
  */
-void EDMA3QdmaClrMissEvt(unsigned int baseAdd, 
+void EDMA3QdmaClrMissEvt(unsigned int baseAdd,
                          unsigned int chNum)
 {
     /*clear SECR to clean any previous NULL request                         */
     HWREG(baseAdd + EDMA3CC_S_QSECR(regionId)) = (0x01u << chNum);
-    
+
     /*clear EMCR to clean any previous NULL request                         */
     HWREG(baseAdd + EDMA3CC_QEMCR) |= (0x01u <<  chNum);
 }
@@ -472,14 +472,14 @@ void EDMA3QdmaClrMissEvt(unsigned int baseAdd,
  *
  *  Flags can have values:
  *
- *  EDMA3CC_CLR_TCCERR            Clears the TCCERR bit in the EDMA3CC 
+ *  EDMA3CC_CLR_TCCERR            Clears the TCCERR bit in the EDMA3CC
  *                                ERR Reg\n
  *  EDMA3CC_CLR_QTHRQ0            Queue threshold error clear for queue 0.\n
  *  EDMA3CC_CLR_QTHRQ1            Queue threshold error clear for queue 1.
  *
  *  \return  None
  */
-void EDMA3ClrCCErr(unsigned int baseAdd, 
+void EDMA3ClrCCErr(unsigned int baseAdd,
                    unsigned int Flags)
 {
     /* (CCERRCLR) - clear channel controller error register                 */
@@ -487,7 +487,7 @@ void EDMA3ClrCCErr(unsigned int baseAdd,
 }
 
 /**
- *  \brief   Enables the user to Set an event. This API helps user to manually 
+ *  \brief   Enables the user to Set an event. This API helps user to manually
  *           set events to initiate DMA transfer requests.
  *
  *  \param   baseAdd                Memory address of the EDMA instance used.\n
@@ -498,11 +498,11 @@ void EDMA3ClrCCErr(unsigned int baseAdd,
  *
  *  Note :   This API is generally used during Manual transfers.\n
  */
-void EDMA3SetEvt(unsigned int baseAdd, 
+void EDMA3SetEvt(unsigned int baseAdd,
                  unsigned int chNum)
 {
     if(chNum < 32)
-    { 
+    {
          /* (ESR) - set corresponding bit to set a event                         */
          HWREG(baseAdd + EDMA3CC_S_ESR(regionId)) |= (0x01u <<  chNum);
     }
@@ -524,8 +524,8 @@ void EDMA3SetEvt(unsigned int baseAdd,
  *
  *  Note :   This API is generally used during Manual transfers.\n
  */
-void EDMA3ClrEvt(unsigned int baseAdd, 
-                 unsigned int chNum) 
+void EDMA3ClrEvt(unsigned int baseAdd,
+                 unsigned int chNum)
 {
     if(chNum < 32)
     {
@@ -548,19 +548,19 @@ void EDMA3ClrEvt(unsigned int baseAdd,
  *
  *  \return  None
  *
- *  Note :   Writes of 1 to the bits in EESR sets the corresponding event 
+ *  Note :   Writes of 1 to the bits in EESR sets the corresponding event
  *           bits in EER. This is generally used for Event Based transfers.\n
  */
-void EDMA3EnableDmaEvt(unsigned int baseAdd, 
+void EDMA3EnableDmaEvt(unsigned int baseAdd,
                        unsigned int chNum)
 {
     if(chNum < 32)
-    { 
+    {
          /* (EESR) - set corresponding bit to enable DMA event                   */
          HWREG(baseAdd + EDMA3CC_S_EESR(regionId)) |= (0x01u <<  chNum);
     }
     else
-    { 
+    {
          /* (EESRH) - set corresponding bit to enable DMA event                   */
          HWREG(baseAdd + EDMA3CC_S_EESRH(regionId)) |= (0x01u << (chNum - 32));
     }
@@ -575,11 +575,11 @@ void EDMA3EnableDmaEvt(unsigned int baseAdd,
  *
  *  \return  None
  *
- *  Note :   Writes of 1 to the bits in EECR clear the corresponding event bits 
- *           in EER; writes of 0 have no effect.. This is generally used for 
+ *  Note :   Writes of 1 to the bits in EECR clear the corresponding event bits
+ *           in EER; writes of 0 have no effect.. This is generally used for
  *           Event Based transfers.\n
  */
-void EDMA3DisableDmaEvt(unsigned int baseAdd, 
+void EDMA3DisableDmaEvt(unsigned int baseAdd,
                         unsigned int chNum)
 {
     if(chNum < 32)
@@ -603,10 +603,10 @@ void EDMA3DisableDmaEvt(unsigned int baseAdd,
  *
  *  \return  None
  *
- *  Note :   Writes of 1 to the bits in QEESR sets the corresponding event 
+ *  Note :   Writes of 1 to the bits in QEESR sets the corresponding event
               bits in QEER.\n
  */
-void EDMA3EnableQdmaEvt(unsigned int baseAdd, 
+void EDMA3EnableQdmaEvt(unsigned int baseAdd,
                         unsigned int chNum)
 {
     /* (QEESR) - set corresponding bit to enable QDMA event                 */
@@ -622,10 +622,10 @@ void EDMA3EnableQdmaEvt(unsigned int baseAdd,
  *
  *  \return  None
  *
- *  Note :   Writes of 1 to the bits in QEECR clears the corresponding event 
+ *  Note :   Writes of 1 to the bits in QEECR clears the corresponding event
               bits in QEER.\n
  */
-void EDMA3DisableQdmaEvt(unsigned int baseAdd, 
+void EDMA3DisableQdmaEvt(unsigned int baseAdd,
                          unsigned int chNum)
 {
     /* (QEESR) - set corresponding bit to enable QDMA event                 */
@@ -737,7 +737,7 @@ unsigned int EDMA3QdmaGetErrIntrStatus(unsigned int baseAdd)
 }
 
 /**
- *  \brief   Enables the user to enable the transfer completion interrupt 
+ *  \brief   Enables the user to enable the transfer completion interrupt
  *           generation by the EDMA3CC for all DMA/QDMA channels.
  *
  *  \param   baseAdd                Memory address of the EDMA instance used.\n
@@ -746,11 +746,11 @@ unsigned int EDMA3QdmaGetErrIntrStatus(unsigned int baseAdd)
  *
  *  \return  None
  *
- *  Note :   To set any interrupt bit in IER, a 1 must be written to the 
+ *  Note :   To set any interrupt bit in IER, a 1 must be written to the
  *           corresponding interrupt bit in the interrupt enable set register.
  */
-void EDMA3EnableEvtIntr(unsigned int baseAdd, 
-                        unsigned int chNum) 
+void EDMA3EnableEvtIntr(unsigned int baseAdd,
+                        unsigned int chNum)
 {
     if(chNum < 32)
     {
@@ -773,11 +773,11 @@ void EDMA3EnableEvtIntr(unsigned int baseAdd,
  *
  *  \return  None
  *
- *  Note :   Writes of 1 to the bits in IECR clear the corresponding interrupt 
- *           bits in the interrupt enable registers (IER); writes of 0 have 
+ *  Note :   Writes of 1 to the bits in IECR clear the corresponding interrupt
+ *           bits in the interrupt enable registers (IER); writes of 0 have
  *           no effect.\n
  */
-void EDMA3DisableEvtIntr(unsigned int baseAdd, 
+void EDMA3DisableEvtIntr(unsigned int baseAdd,
                          unsigned int chNum)
 {
     if(chNum < 32)
@@ -818,18 +818,18 @@ void EDMA3ClrIntr(unsigned int baseAdd, unsigned int value)
 /**
  *  \brief   Retrieve existing PaRAM set associated with specified logical
  *           channel (DMA/Link).
- *  
+ *
  *  \param   baseAdd                Memory address of the EDMA instance used.\n
- *  
+ *
  *  \param   chNum                  Logical Channel whose PaRAM set is
  *                                  requested.\n
- *  
+ *
  *  \param   currPaRAM              User gets the existing PaRAM here.\n
- *  
+ *
  *  \return  None
  */
-void EDMA3GetPaRAM(unsigned int baseAdd, 
-                   unsigned int PaRAMId, 
+void EDMA3GetPaRAM(unsigned int baseAdd,
+                   unsigned int PaRAMId,
                    EDMA3CCPaRAMEntry* currPaRAM)
 {
     unsigned int i = 0;
@@ -847,19 +847,19 @@ void EDMA3GetPaRAM(unsigned int baseAdd,
 /**
  * \brief   Retrieve existing PaRAM set associated with specified logical
  *          channel (QDMA).
- * 
+ *
  * \param   baseAdd                Memory address of the EDMA instance used.\n
- * 
+ *
  * \param   chNum                  Logical Channel whose PaRAM set is
  *                                 requested.\n
- * 
+ *
  * \param   currPaRAM              User gets the existing PaRAM here.\n
- * 
+ *
  * \return  None
  */
-void EDMA3QdmaGetPaRAM(unsigned int baseAdd, 
+void EDMA3QdmaGetPaRAM(unsigned int baseAdd,
                        unsigned int chNum,
-                       unsigned int paRAMId, 
+                       unsigned int paRAMId,
                        EDMA3CCPaRAMEntry* currPaRAM)
 {
     unsigned int i = 0;
@@ -877,7 +877,7 @@ void EDMA3QdmaGetPaRAM(unsigned int baseAdd,
 }
 
 /**
- * \brief   Copy the user specified PaRAM Set onto the PaRAM Set associated 
+ * \brief   Copy the user specified PaRAM Set onto the PaRAM Set associated
  *          with the logical channel (DMA/Link).
  *
  * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set
@@ -895,7 +895,7 @@ void EDMA3QdmaGetPaRAM(unsigned int baseAdd,
  *
  * \return  None
  */
-void EDMA3SetPaRAM(unsigned int baseAdd, 
+void EDMA3SetPaRAM(unsigned int baseAdd,
                    unsigned int chNum,
                    EDMA3CCPaRAMEntry* newPaRAM)
 {
@@ -903,7 +903,7 @@ void EDMA3SetPaRAM(unsigned int baseAdd,
     unsigned int i = 0;
     unsigned int *sr = (unsigned int *)newPaRAM;
     volatile unsigned int *ds;
- 
+
     ds = (unsigned int *)(baseAdd + EDMA3CC_OPT(PaRAMId));
 
     for(i=0; i < EDMA3CC_PARAM_ENTRY_FIELDS; i++)
@@ -915,7 +915,7 @@ void EDMA3SetPaRAM(unsigned int baseAdd,
 }
 
 /**
- * \brief   Copy the user specified PaRAM Set onto the PaRAM Set associated 
+ * \brief   Copy the user specified PaRAM Set onto the PaRAM Set associated
  *          with the logical channel (QDMA only).
  *
  * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set
@@ -929,14 +929,14 @@ void EDMA3SetPaRAM(unsigned int baseAdd,
  *                                 requested.\n
  *
  * \param  paRaMID                 PaRAM Id to which the QDMA channel is
- *                        mapped to. 
+ *                        mapped to.
  *
  * \param   newPaRAM               Parameter RAM set to be copied onto existing
  *                                 PaRAM.\n
  *
  * \return  None
  */
-void EDMA3QdmaSetPaRAM(unsigned int baseAdd, 
+void EDMA3QdmaSetPaRAM(unsigned int baseAdd,
                        unsigned int chNum,
                        unsigned int paRAMId,
                        EDMA3CCPaRAMEntry* newPaRAM)
@@ -944,7 +944,7 @@ void EDMA3QdmaSetPaRAM(unsigned int baseAdd,
     unsigned int i = 0;
     unsigned int *sr = (unsigned int *)newPaRAM;
     unsigned int *ds;
- 
+
     ds = (unsigned int *)(baseAdd + EDMA3CC_OPT(paRAMId));
 
     for(i=0;i<EDMA3CC_PARAM_ENTRY_FIELDS;i++)
@@ -966,7 +966,7 @@ void EDMA3QdmaSetPaRAM(unsigned int baseAdd,
  * \param   paRAMEntry        Specify the PaRAM set entry which needs
  *                            to be set.
  *
- * \param   newPaRAMEntryVal  The new field setting. Make sure this field is 
+ * \param   newPaRAMEntryVal  The new field setting. Make sure this field is
  *                            packed for setting certain fields in paRAM.
  *
  *  paRAMEntry can have values:
@@ -979,7 +979,7 @@ void EDMA3QdmaSetPaRAM(unsigned int baseAdd,
  *  EDMA3CC_PARAM_ENTRY_LINK_BCNTRLD
  *  EDMA3CC_PARAM_ENTRY_SRC_DST_CIDX
  *  EDMA3CC_PARAM_ENTRY_CCNT
- * 
+ *
  * \return  None
  *
  * \note    This API should be used while setting the PaRAM set entry
@@ -992,10 +992,10 @@ void EDMA3QdmaSetPaRAMEntry(unsigned int baseAdd,
                             unsigned int paRAMEntry,
                             unsigned int newPaRAMEntryVal)
 {
-    if((paRAMEntry > EDMA3CC_PARAM_ENTRY_OPT) || 
+    if((paRAMEntry > EDMA3CC_PARAM_ENTRY_OPT) ||
             (paRAMEntry < EDMA3CC_PARAM_ENTRY_CCNT))
     {
-        HWREG(baseAdd + EDMA3CC_OPT(paRAMId) + 
+        HWREG(baseAdd + EDMA3CC_OPT(paRAMId) +
                     (unsigned int)(paRAMEntry * 0x04)) = newPaRAMEntryVal;
     }
 }
@@ -1022,12 +1022,12 @@ void EDMA3QdmaSetPaRAMEntry(unsigned int baseAdd,
  *  EDMA3CC_PARAM_ENTRY_SRC_DST_CIDX
  *  EDMA3CC_PARAM_ENTRY_CCNT
  *
- * \return  paRAMEntryVal     The value of the paRAM field pointed by the  
+ * \return  paRAMEntryVal     The value of the paRAM field pointed by the
  *                            paRAMEntry.
  *
  * \note    This API should be used while reading the PaRAM set entry
  *          for QDMA channels. And the paRAMEntryVal is a packed value for
- *          certain fields of paRAMEntry.The user has to make sure the value 
+ *          certain fields of paRAMEntry.The user has to make sure the value
  *          is unpacked appropriately.
  *          For example, the third field is A_B_CNT. Hence he will have to
  *          unpack it to two 16 bit fields to get ACNT and BCNT.
@@ -1055,17 +1055,17 @@ unsigned int EDMA3QdmaGetPaRAMEntry(unsigned int baseAdd,
  *  This API is used to allocate a logical channel (DMA/QDMA/Link) along with
  *  the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are
  *  also allocated along with the requested channel.
- *  
+ *
  *  User can request a specific logical channel by passing the channel number
  *  in 'chNum'.
- *  
+ *
  *  For DMA/QDMA channels, after allocating all the EDMA3 resources, this API
  *  sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets
  *  the event queue for the channel allocated. The event queue needs to be
  *  specified by the user.
- *  
+ *
  *  For DMA channel, it also sets the DCHMAP register.
- *  
+ *
  *  For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and
  *  enables the QDMA channel by writing to the QEESR register.
  *
@@ -1089,10 +1089,10 @@ unsigned int EDMA3QdmaGetPaRAMEntry(unsigned int baseAdd,
  *
  *  \return  TRUE if parameters are valid, else FALSE
  */
-unsigned int EDMA3RequestChannel(unsigned int baseAdd, 
-                                 unsigned int chType, 
-                                 unsigned int chNum, 
-                                 unsigned int tccNum, 
+unsigned int EDMA3RequestChannel(unsigned int baseAdd,
+                                 unsigned int chType,
+                                 unsigned int chNum,
+                                 unsigned int tccNum,
                                  unsigned int evtQNum)
 {
     unsigned int retVal = FALSE;
@@ -1124,7 +1124,7 @@ unsigned int EDMA3RequestChannel(unsigned int baseAdd,
                 /* Enable the Event Interrupt                             */
                 EDMA3EnableEvtIntr(baseAdd, chNum);
                 retVal = TRUE;
-            } 
+            }
             HWREG(baseAdd + EDMA3CC_OPT(chNum)) &= EDMA3CC_OPT_TCC_CLR;
             HWREG(baseAdd + EDMA3CC_OPT(chNum)) |= EDMA3CC_OPT_TCC_SET(chNum);
         }
@@ -1135,9 +1135,9 @@ unsigned int EDMA3RequestChannel(unsigned int baseAdd,
 /**
  *  \brief    Free the specified channel (DMA/QDMA/Link) and its associated
  *            resources (PaRAM Set, TCC etc) and removes various mappings.
- *  
+ *
  *  For Link channels, this API only frees the associated PaRAM Set.
- *  
+ *
  *  For DMA/QDMA channels, it does the following operations:
  *  1) Disable any ongoing transfer on the channel,\n
  *  2) Remove the channel to Event Queue mapping,\n
@@ -1172,7 +1172,7 @@ unsigned int EDMA3RequestChannel(unsigned int baseAdd,
  *
  *  \return  TRUE if parameters are valid else return FALSE
  */
-unsigned int EDMA3FreeChannel(unsigned int baseAdd, unsigned int chType, 
+unsigned int EDMA3FreeChannel(unsigned int baseAdd, unsigned int chType,
                               unsigned int chNum, unsigned int trigMode,
                               unsigned int tccNum, unsigned int evtQNum)
 {
@@ -1180,7 +1180,7 @@ unsigned int EDMA3FreeChannel(unsigned int baseAdd, unsigned int chType,
     if (chNum < SOC_EDMA3_NUM_DMACH)
     {
         EDMA3DisableTransfer(baseAdd, chNum, trigMode);
-        /* Disable the DMA channel in the shadow region specific register 
+        /* Disable the DMA channel in the shadow region specific register
          */
         EDMA3DisableChInShadowReg(baseAdd, chType, chNum);
 
@@ -1215,15 +1215,15 @@ unsigned int EDMA3FreeChannel(unsigned int baseAdd, unsigned int chType,
  *  There are multiple ways to trigger an EDMA3 transfer. The triggering mode
  *  option allows choosing from the available triggering modes: Event,
  *  Manual or QDMA.
- *  
+ *
  *  In event triggered, a peripheral or an externally generated event triggers
  *  the transfer. This API clears the Event and Event Miss Register and then
  *  enables the DMA channel by writing to the EESR.
- *  
+ *
  *  In manual triggered mode, CPU manually triggers a transfer by writing a 1
- *  in the Event Set Register ESR. This API writes to the ESR to start the 
+ *  in the Event Set Register ESR. This API writes to the ESR to start the
  *  transfer.
- *  
+ *
  *  In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other
  *  EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set
  *  (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set
@@ -1245,8 +1245,8 @@ unsigned int EDMA3FreeChannel(unsigned int baseAdd, unsigned int chType,
  *  \return  retVal         TRUE or FALSE depending on the param passed.\n
  *
  */
-unsigned int EDMA3EnableTransfer(unsigned int baseAdd, 
-                                 unsigned int chNum, 
+unsigned int EDMA3EnableTransfer(unsigned int baseAdd,
+                                 unsigned int chNum,
                                  unsigned int trigMode)
 {
     unsigned int retVal = FALSE;
@@ -1259,7 +1259,7 @@ unsigned int EDMA3EnableTransfer(unsigned int baseAdd,
                 retVal = TRUE;
             }
            break;
-    
+
         case EDMA3_TRIG_MODE_QDMA :
             if (chNum < SOC_EDMA3_NUM_QDMACH)
             {
@@ -1267,7 +1267,7 @@ unsigned int EDMA3EnableTransfer(unsigned int baseAdd,
                 retVal = TRUE;
             }
         break;
-    
+
         case EDMA3_TRIG_MODE_EVENT :
             if (chNum < SOC_EDMA3_NUM_DMACH)
             {
@@ -1279,7 +1279,7 @@ unsigned int EDMA3EnableTransfer(unsigned int baseAdd,
                 retVal = TRUE;
             }
         break;
-    
+
         default :
             retVal = FALSE;
         break;
@@ -1289,18 +1289,18 @@ unsigned int EDMA3EnableTransfer(unsigned int baseAdd,
 
 /**
  *  \brief   Disable DMA transfer on the specified channel
- *  
+ *
  *  There are multiple ways by which an EDMA3 transfer could be triggered.
  *  The triggering mode option allows choosing from the available triggering
  *  modes.
- *  
+ *
  *  To disable a channel which was previously triggered in manual mode,
  *  this API clears the Secondary Event Register and Event Miss Register,
  *  if set, for the specific DMA channel.
- *  
+ *
  *  To disable a channel which was previously triggered in QDMA mode, this
  *  API clears the QDMA Event Enable Register, for the specific QDMA channel.
- *  
+ *
  *  To disable a channel which was previously triggered in event mode, this API
  *  clears the Event Enable Register, Event Register, Secondary Event Register
  *  and Event Miss Register, if set, for the specific DMA channel.
@@ -1321,8 +1321,8 @@ unsigned int EDMA3EnableTransfer(unsigned int baseAdd,
  *  \return  retVal         TRUE or FALSE depending on the param passed.\n
  *
  */
-unsigned int EDMA3DisableTransfer(unsigned int baseAdd, 
-                                  unsigned int chNum, 
+unsigned int EDMA3DisableTransfer(unsigned int baseAdd,
+                                  unsigned int chNum,
                                   unsigned int trigMode)
 {
     unsigned int retVal = FALSE;
@@ -1335,7 +1335,7 @@ unsigned int EDMA3DisableTransfer(unsigned int baseAdd,
                 retVal = TRUE;
             }
         break;
-    
+
         case EDMA3_TRIG_MODE_QDMA :
             if (chNum < SOC_EDMA3_NUM_QDMACH)
             {
@@ -1343,7 +1343,7 @@ unsigned int EDMA3DisableTransfer(unsigned int baseAdd,
                 retVal = TRUE;
             }
         break;
-    
+
         case EDMA3_TRIG_MODE_EVENT :
             if (chNum < SOC_EDMA3_NUM_DMACH)
             {
@@ -1355,7 +1355,7 @@ unsigned int EDMA3DisableTransfer(unsigned int baseAdd,
                 retVal = TRUE;
             }
         break;
-    
+
         default :
             retVal = FALSE;
         break;
@@ -1382,8 +1382,8 @@ unsigned int EDMA3DisableTransfer(unsigned int baseAdd,
  *
  *  \return none.\n
  */
-void EDMA3ClearErrorBits(unsigned int baseAdd, 
-             unsigned int chNum, 
+void EDMA3ClearErrorBits(unsigned int baseAdd,
+             unsigned int chNum,
              unsigned int evtQNum)
 {
     if(chNum < SOC_EDMA3_NUM_DMACH)
@@ -1410,39 +1410,39 @@ void EDMA3ClearErrorBits(unsigned int baseAdd,
     /* Clear the global CC Error Register */
     if (0 == evtQNum)
     {
-         HWREG(baseAdd + EDMA3CC_CCERRCLR) &= (EDMA3CC_CCERRCLR_QTHRXCD0 | 
+         HWREG(baseAdd + EDMA3CC_CCERRCLR) &= (EDMA3CC_CCERRCLR_QTHRXCD0 |
                                 EDMA3CC_CCERRCLR_TCCERR);
     }
     else if(1 == evtQNum)
     {
-         HWREG(baseAdd + EDMA3CC_CCERRCLR) &= (EDMA3CC_CCERRCLR_QTHRXCD1 | 
+         HWREG(baseAdd + EDMA3CC_CCERRCLR) &= (EDMA3CC_CCERRCLR_QTHRXCD1 |
                                 EDMA3CC_CCERRCLR_TCCERR);
     }
     else if(2 == evtQNum)
     {
-         HWREG(baseAdd + EDMA3CC_CCERRCLR) &= (EDMA3CC_CCERRCLR_QTHRXCD2 | 
+         HWREG(baseAdd + EDMA3CC_CCERRCLR) &= (EDMA3CC_CCERRCLR_QTHRXCD2 |
                                 EDMA3CC_CCERRCLR_TCCERR);
     }
     else if(3 == evtQNum)
     {
-         HWREG(baseAdd + EDMA3CC_CCERRCLR) &= (EDMA3CC_CCERRCLR_QTHRXCD2 | 
+         HWREG(baseAdd + EDMA3CC_CCERRCLR) &= (EDMA3CC_CCERRCLR_QTHRXCD2 |
                                 EDMA3CC_CCERRCLR_TCCERR);
     }
 }
 
 /**
  *  \brief   EDMA3 Deinitialization
- *  
+ *
  *  This function deinitializes the EDMA3 Driver
  *  Clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) &
  *  deinitialize the Queue Number Registers
- *  
+ *
  *  \param  baseAdd         Memory address of the EDMA instance used.\n
- *  
- *  \param  queNum          Event Queue used 
- *  
+ *
+ *  \param  queNum          Event Queue used
+ *
  *  \return  None
- *  
+ *
  *  \note     The regionId is the shadow region(0 or 1) used and the,
  *            Event Queue used is either (0 or 1). There are only two shadow regions
  *            and only two event Queues
@@ -1455,9 +1455,9 @@ void EDMA3Deinit(unsigned int baseAdd,
     /* Disable the DMA (0 - 62) channels in the DRAE register */
     HWREG(baseAdd + EDMA3CC_DRAE(regionId)) = EDMA3_CLR_ALL_BITS;
     HWREG(baseAdd + EDMA3CC_DRAEH(regionId)) = EDMA3_CLR_ALL_BITS;
-    
+
     EDMA3ClrCCErr(baseAdd, EDMA3CC_CLR_TCCERR);
-    
+
     /* Clear the Event miss Registers                      */
     HWREG(baseAdd + EDMA3CC_EMCR)  = EDMA3_SET_ALL_BITS;
     HWREG(baseAdd + EDMA3CC_EMCRH) = EDMA3_SET_ALL_BITS;
@@ -1493,38 +1493,38 @@ void EDMA3ContextSave(unsigned int baseAddr, EDMACONTEXT *edmaCntxPtr)
     unsigned int maxPar;
 
     /* Get the Channel mapping reg Val */
-    
+
     for(i = 0; i < 64; i++)
     {
-         /* All events are one to one mapped with the channels */        
+         /* All events are one to one mapped with the channels */
          edmaCntxPtr->dchMap[i] = HWREG(baseAddr + EDMA3CC_DCHMAP(i));
     }
-      
+
     /* Get DMA Queue Number Register Val */
     for(i=0; i < 8; i++)
-    {    
-        edmaCntxPtr->dmaQNum[i] = HWREG(baseAddr + EDMA3CC_DMAQNUM((i)));    
-    }         
+    {
+        edmaCntxPtr->dmaQNum[i] = HWREG(baseAddr + EDMA3CC_DMAQNUM((i)));
+    }
 
     /* Get the DMA Region Access Enable Register val */
-               
-    edmaCntxPtr->regAccEnableLow = HWREG(baseAddr + EDMA3CC_DRAE(0));            
-    edmaCntxPtr->regAccEnableHigh = HWREG(baseAddr + EDMA3CC_DRAEH(0));            
-    
+
+    edmaCntxPtr->regAccEnableLow = HWREG(baseAddr + EDMA3CC_DRAE(0));
+    edmaCntxPtr->regAccEnableHigh = HWREG(baseAddr + EDMA3CC_DRAEH(0));
+
     /* Get Event Set Register value */
-        
-    edmaCntxPtr->eventSetRegLow  = HWREG(baseAddr + EDMA3CC_S_ESR(0));                
-    edmaCntxPtr->eventSetRegHigh = HWREG(baseAddr + EDMA3CC_S_ESRH(0));                    
-                  
+
+    edmaCntxPtr->eventSetRegLow  = HWREG(baseAddr + EDMA3CC_S_ESR(0));
+    edmaCntxPtr->eventSetRegHigh = HWREG(baseAddr + EDMA3CC_S_ESRH(0));
+
     /* Get Event Enable Set Register value */
-      
-    edmaCntxPtr->enableEvtSetRegLow = HWREG(baseAddr + EDMA3CC_S_EER(0));                   
-    edmaCntxPtr->enableEvtSetRegHigh = HWREG(baseAddr + EDMA3CC_S_EERH(0));                       
-          
+
+    edmaCntxPtr->enableEvtSetRegLow = HWREG(baseAddr + EDMA3CC_S_EER(0));
+    edmaCntxPtr->enableEvtSetRegHigh = HWREG(baseAddr + EDMA3CC_S_EERH(0));
+
     /* Get Interrupt Enable Set Register value */
-           
-    edmaCntxPtr->intEnableSetRegLow =  HWREG(baseAddr + EDMA3CC_S_IER(0));                    
-    edmaCntxPtr->intEnableSetRegHigh =  HWREG(baseAddr + EDMA3CC_S_IERH(0));                        
+
+    edmaCntxPtr->intEnableSetRegLow =  HWREG(baseAddr + EDMA3CC_S_IER(0));
+    edmaCntxPtr->intEnableSetRegHigh =  HWREG(baseAddr + EDMA3CC_S_IERH(0));
 
     maxPar = 128;
 
@@ -1535,10 +1535,10 @@ void EDMA3ContextSave(unsigned int baseAddr, EDMACONTEXT *edmaCntxPtr)
 
     for(i = 0; i < maxPar; i++)
     {
-        /* Get the  PaRAM  values */            
-        EDMA3GetPaRAM(baseAddr, i, 
+        /* Get the  PaRAM  values */
+        EDMA3GetPaRAM(baseAddr, i,
                       (struct EDMA3CCPaRAMEntry *)(&(edmaCntxPtr->dmaParEntry[i])));
-    }	                      
+    }
 }
 
 /**
@@ -1555,36 +1555,36 @@ void EDMA3ContextRestore(unsigned int baseAddr, EDMACONTEXT *edmaCntxPtr)
 {
     unsigned int i;
     unsigned int maxPar;
-    
+
     /* set the Channel mapping reg Val */
     for(i = 0; i < 64; i++)
     {
-         /* All events are one to one mapped with the channels */        
+         /* All events are one to one mapped with the channels */
          HWREG(baseAddr + EDMA3CC_DCHMAP(i)) = edmaCntxPtr->dchMap[i] ;
     }
-      
+
     /* set DMA Queue Number Register Val */
     for(i=0; i < 8; i++)
-    {    
-	HWREG(baseAddr + EDMA3CC_DMAQNUM((i))) = edmaCntxPtr->dmaQNum[i];    
-    }         
+    {
+	HWREG(baseAddr + EDMA3CC_DMAQNUM((i))) = edmaCntxPtr->dmaQNum[i];
+    }
 
     /* set the DMA Region Access Enable Register val */
-               
+
     HWREG(baseAddr + EDMA3CC_DRAE(0)) = edmaCntxPtr->regAccEnableLow;
-    HWREG(baseAddr + EDMA3CC_DRAEH(0)) = edmaCntxPtr->regAccEnableHigh;            
-    
+    HWREG(baseAddr + EDMA3CC_DRAEH(0)) = edmaCntxPtr->regAccEnableHigh;
+
     /* set Event Set Register value */
-    HWREG(baseAddr + EDMA3CC_S_ESR(0)) = edmaCntxPtr->eventSetRegLow;                
-    HWREG(baseAddr + EDMA3CC_S_ESRH(0)) = edmaCntxPtr->eventSetRegHigh;                    
-                  
+    HWREG(baseAddr + EDMA3CC_S_ESR(0)) = edmaCntxPtr->eventSetRegLow;
+    HWREG(baseAddr + EDMA3CC_S_ESRH(0)) = edmaCntxPtr->eventSetRegHigh;
+
     /* set Event Enable Set Register value */
-    HWREG(baseAddr + EDMA3CC_S_EESR(0)) = edmaCntxPtr->enableEvtSetRegLow;                   
-    HWREG(baseAddr + EDMA3CC_S_EESRH(0)) = edmaCntxPtr->enableEvtSetRegHigh;                       
-          
+    HWREG(baseAddr + EDMA3CC_S_EESR(0)) = edmaCntxPtr->enableEvtSetRegLow;
+    HWREG(baseAddr + EDMA3CC_S_EESRH(0)) = edmaCntxPtr->enableEvtSetRegHigh;
+
     /* set Interrupt Enable Set Register value */
-    HWREG(baseAddr + EDMA3CC_S_IESR(0)) = edmaCntxPtr->intEnableSetRegLow;                    
-    HWREG(baseAddr + EDMA3CC_S_IESRH(0)) = edmaCntxPtr->intEnableSetRegHigh;                        
+    HWREG(baseAddr + EDMA3CC_S_IESR(0)) = edmaCntxPtr->intEnableSetRegLow;
+    HWREG(baseAddr + EDMA3CC_S_IESRH(0)) = edmaCntxPtr->intEnableSetRegHigh;
 
     maxPar = 128;
 
@@ -1595,10 +1595,10 @@ void EDMA3ContextRestore(unsigned int baseAddr, EDMACONTEXT *edmaCntxPtr)
 
     for(i = 0; i < maxPar; i++)
     {
-        /* Get the  PaRAM  values */            
-        EDMA3SetPaRAM(baseAddr, i, 
+        /* Get the  PaRAM  values */
+        EDMA3SetPaRAM(baseAddr, i,
              (struct EDMA3CCPaRAMEntry *)(&(edmaCntxPtr->dmaParEntry[i])));
-    }	                   
+    }
 }
 
 /********************************* End of file ******************************/
diff --git a/lib/tiam1808/drivers/ehrpwm.c b/lib/tiam1808/drivers/ehrpwm.c
index dcc7b5585..59646b963 100644
--- a/lib/tiam1808/drivers/ehrpwm.c
+++ b/lib/tiam1808/drivers/ehrpwm.c
@@ -53,7 +53,7 @@
 /**
  * \brief  This API configures the clock divider of the Time base module.
  *         The clock divider can be calculated using the equation
- *         TBCLK = SYSCLKOUT/(HSPCLKDIV × CLKDIV)
+ *         TBCLK = SYSCLKOUT/(HSPCLKDIV � CLKDIV)
  *
  * \param   baseAddr      Base Address of the PWM Module Registers.
  * \param   tbClk         Timebase clock to be generated.
diff --git a/lib/tiam1808/drivers/emifa.c b/lib/tiam1808/drivers/emifa.c
index 9a1877fa1..732c082da 100644
--- a/lib/tiam1808/drivers/emifa.c
+++ b/lib/tiam1808/drivers/emifa.c
@@ -51,16 +51,16 @@
 * \brief   This function reads the module ID of EMIFA.\n
 *
 * \param   baseAddr  Memory address of EMIFA.\n
-* 
+*
 * \return  Module Id of EMIFA.\n
 */
 
 unsigned int  EMIFAModuleIdRead(unsigned int baseAddr)
 {
     unsigned int modId;
-    
+
     modId = HWREG(baseAddr + EMIFA_MIDR);
-    
+
     return (modId);
 }
 
@@ -101,7 +101,7 @@ void EMIFANANDCSSet(unsigned int baseAddr, unsigned int CSNum)
 }
 
 /**
-* \brief  This function start the NAND 4-bit ECC address 
+* \brief  This function start the NAND 4-bit ECC address
 *         and error value calculation.\n
 *
 * \param  baseAddr   Memory address of EMIFA.\n
@@ -124,8 +124,8 @@ void EMIFANAND4BitECCAddrCalcStart(unsigned int baseAddr)
 *                    EMIFA_NAND_1BIT_ECC - To start 1 bit ECC.
 *                    EMIFA_NAND_4BIT_ECC - To start 4 bit ecc
 *
-* \param  csNum      This parameter is only valid when ecc value is 
-*                    EMIFA_NAND_1BIT_ECC. This specifies the chip 
+* \param  csNum      This parameter is only valid when ecc value is
+*                    EMIFA_NAND_1BIT_ECC. This specifies the chip
 *                    select for which nand is interfaced.
 *                    This can take one of the following values :
 *                    EMIFA_CHIP_SELECT_2  -  Using nand on CS2.
@@ -163,7 +163,7 @@ void EMIFANANDECCStart(unsigned int baseAddr, unsigned int eccType,
     {
         HWREG(baseAddr + EMIFA_NANDFCR) |= EMIFA_NANDFCR_4BITECC_START;
     }
-} 
+}
 
 /**
 * \brief  This function selects the NAND for 4-bit ECC.\n
@@ -182,7 +182,7 @@ void EMIFANANDECCStart(unsigned int baseAddr, unsigned int eccType,
 
 void EMIFANAND4BitECCSelect(unsigned int baseAddr, unsigned int CSNum)
 {
-    HWREG(baseAddr + EMIFA_NANDFCR) &= ~EMIFA_NANDFCR_4BITECCSEL;   
+    HWREG(baseAddr + EMIFA_NANDFCR) &= ~EMIFA_NANDFCR_4BITECCSEL;
     switch(CSNum)
     {
         case EMIFA_CHIP_SELECT_2:
@@ -211,9 +211,9 @@ void EMIFANAND4BitECCSelect(unsigned int baseAddr, unsigned int CSNum)
 *
 * \param  baseAddr   Memory address of EMIFA.\n
 *
-* \param  waitVal    Maximum extended wait cycles.The EMIFA will wait for 
-*                    a maximum of (waitVal + 1)*16  clock cycles before it 
-*                    stops inserting asynchronous wait cycles and proceeds 
+* \param  waitVal    Maximum extended wait cycles.The EMIFA will wait for
+*                    a maximum of (waitVal + 1)*16  clock cycles before it
+*                    stops inserting asynchronous wait cycles and proceeds
 *                    to the hold period of the access.\n
 *
 * \return none.
@@ -221,8 +221,8 @@ void EMIFANAND4BitECCSelect(unsigned int baseAddr, unsigned int CSNum)
 
 void EMIFAMaxExtWaitCycleSet(unsigned int baseAddr, unsigned int waitVal)
 {
-    HWREG(baseAddr + EMIFA_AWCC) &= ~EMIFA_AWCC_MAX_EXT_WAIT;   
-    HWREG(baseAddr + EMIFA_AWCC) |=(waitVal & EMIFA_AWCC_MAX_EXT_WAIT); 
+    HWREG(baseAddr + EMIFA_AWCC) &= ~EMIFA_AWCC_MAX_EXT_WAIT;
+    HWREG(baseAddr + EMIFA_AWCC) |=(waitVal & EMIFA_AWCC_MAX_EXT_WAIT);
 }
 
 /**
@@ -243,7 +243,7 @@ void EMIFAMaxExtWaitCycleSet(unsigned int baseAddr, unsigned int waitVal)
 *                    EMIFA_EMA_WAIT_PIN1  -  To select EMA_WAIT[1] pin.\n
 * \return none.
 */
-void EMIFACSWaitPinSelect(unsigned int baseAddr, unsigned int CSNum, 
+void EMIFACSWaitPinSelect(unsigned int baseAddr, unsigned int CSNum,
                           unsigned int pin)
 {
     switch(CSNum)
@@ -256,17 +256,17 @@ void EMIFACSWaitPinSelect(unsigned int baseAddr, unsigned int CSNum,
         case EMIFA_CHIP_SELECT_3:
 	         HWREG(baseAddr + EMIFA_AWCC) &= ~EMIFA_AWCC_CS3_WAIT;
 	         HWREG(baseAddr + EMIFA_AWCC) |= ((pin << EMIFA_AWCC_CS3_WAIT_SHIFT)
-     		                                   &EMIFA_AWCC_CS3_WAIT);      
+     		                                   &EMIFA_AWCC_CS3_WAIT);
         break;
         case EMIFA_CHIP_SELECT_4:
 	         HWREG(baseAddr + EMIFA_AWCC) &= ~EMIFA_AWCC_CS4_WAIT;
 	         HWREG(baseAddr + EMIFA_AWCC) |= ((pin << EMIFA_AWCC_CS4_WAIT_SHIFT)
-	                                           &EMIFA_AWCC_CS4_WAIT);      
+	                                           &EMIFA_AWCC_CS4_WAIT);
         break;
         case EMIFA_CHIP_SELECT_5:
       	     HWREG(baseAddr + EMIFA_AWCC) &= ~EMIFA_AWCC_CS5_WAIT;
 	         HWREG(baseAddr + EMIFA_AWCC) |= ((pin << EMIFA_AWCC_CS5_WAIT_SHIFT)
-	                                           &EMIFA_AWCC_CS5_WAIT);      
+	                                           &EMIFA_AWCC_CS5_WAIT);
         break;
         default:
         break;
@@ -290,18 +290,18 @@ void EMIFACSWaitPinSelect(unsigned int baseAddr, unsigned int CSNum,
 *
 * \return none.
 */
-void EMIFAWaitPinPolaritySet(unsigned int baseAddr, unsigned int pin, 
+void EMIFAWaitPinPolaritySet(unsigned int baseAddr, unsigned int pin,
                              unsigned int pinPolarity)
 {
     if(pin == EMIFA_EMA_WAIT_PIN0)
-    {   
-        HWREG(baseAddr + EMIFA_AWCC) |= (pinPolarity << EMIFA_AWCC_WP0_SHIFT);      
-        
+    {
+        HWREG(baseAddr + EMIFA_AWCC) |= (pinPolarity << EMIFA_AWCC_WP0_SHIFT);
+
     }
     else if(pin == EMIFA_EMA_WAIT_PIN1)
     {
-        HWREG(baseAddr + EMIFA_AWCC) |= (pinPolarity << EMIFA_AWCC_WP1_SHIFT);              
-    }       
+        HWREG(baseAddr + EMIFA_AWCC) |= (pinPolarity << EMIFA_AWCC_WP1_SHIFT);
+    }
 }
 
 /**
@@ -374,15 +374,15 @@ void EMIFAAsyncDevOpModeSelect(unsigned int baseAddr,unsigned int CSNum,
         break;
         case EMIFA_CHIP_SELECT_3:
 	         HWREG(baseAddr + EMIFA_CE3CFG) |= ((mode << EMIFA_CE3CFG_SS_SHIFT)
-     		                                     &EMIFA_CE3CFG_SS);     
+     		                                     &EMIFA_CE3CFG_SS);
         break;
         case EMIFA_CHIP_SELECT_4:
 	         HWREG(baseAddr + EMIFA_CE4CFG) |= ((mode << EMIFA_CE4CFG_SS_SHIFT)
-     	                                        &EMIFA_CE4CFG_SS);     
+     	                                        &EMIFA_CE4CFG_SS);
         break;
         case EMIFA_CHIP_SELECT_5:
 	         HWREG(baseAddr + EMIFA_CE5CFG) |= ((mode << EMIFA_CE5CFG_SS_SHIFT)
-     	                                        &EMIFA_CE5CFG_SS);     
+     	                                        &EMIFA_CE5CFG_SS);
         break;
         default:
         break;
@@ -420,15 +420,15 @@ void EMIFAExtendedWaitConfig(unsigned int baseAddr,unsigned int CSNum,
         break;
         case EMIFA_CHIP_SELECT_3:
 	         HWREG(baseAddr + EMIFA_CE3CFG) |= ((flag << EMIFA_CE3CFG_EW_SHIFT)
-     		                                    &EMIFA_CE3CFG_EW);      
+     		                                    &EMIFA_CE3CFG_EW);
         break;
         case EMIFA_CHIP_SELECT_4:
 	         HWREG(baseAddr + EMIFA_CE4CFG) |= ((flag << EMIFA_CE4CFG_EW_SHIFT)
-     		                                    &EMIFA_CE4CFG_EW);      
+     		                                    &EMIFA_CE4CFG_EW);
         break;
         case EMIFA_CHIP_SELECT_5:
 	         HWREG(baseAddr + EMIFA_CE5CFG) |= ((flag << EMIFA_CE5CFG_EW_SHIFT)
-     	 	                                    &EMIFA_CE5CFG_EW);      
+     	 	                                    &EMIFA_CE5CFG_EW);
         break;
         default:
         break;
@@ -436,7 +436,7 @@ void EMIFAExtendedWaitConfig(unsigned int baseAddr,unsigned int CSNum,
 }
 
 /**
-* \brief  This function Configures the SDRAM.\n 
+* \brief  This function Configures the SDRAM.\n
 *
 * \param  baseAddr   Memory address of EMIFA.\n
 *
@@ -444,11 +444,11 @@ void EMIFAExtendedWaitConfig(unsigned int baseAddr,unsigned int CSNum,
 *                    macro to get the value of conf. \n
 *
 *  NOTE : Calling this funcion triggers the SDRAM initialization sequence.
-*         Hence first update the Self-Refresh mode,Power Down mode,refreshes 
+*         Hence first update the Self-Refresh mode,Power Down mode,refreshes
 *         during power down,refresh rate,sdram timing,self ref exit timing
 *         using EMIFASDRAMSelfRefModeConfig,EMIFASDRAMPowDownModeConfig
 *         EMIFASDRAMRefDurPowDownModeEnable,EMIFASDRAMRefRateSet,
-*         EMIFASDRAMTimingConfig,EMIFASDRAMSelfRefExitTimeConfig functions 
+*         EMIFASDRAMTimingConfig,EMIFASDRAMSelfRefExitTimeConfig functions
 *         respectively.\n
 *
 * \return none.
@@ -459,16 +459,16 @@ void EMIFASDRAMConfig(unsigned int baseAddr,unsigned int conf)
 }
 
 /**
-* \brief  This function configure the Self refresh mode of SDRAM.\n 
+* \brief  This function configure the Self refresh mode of SDRAM.\n
 *
 * \param  baseAddr   Memory address of EMIFA.\n
 *
-* \param  flag       Flag indicates whether to enter or exit the self refresh    
+* \param  flag       Flag indicates whether to enter or exit the self refresh
 *                    mode.
 *                    This can take one of the following values :
-*                    EMIFA_SDRAM_SELFREF_MODE_ENTER  -  To enter to self 
+*                    EMIFA_SDRAM_SELFREF_MODE_ENTER  -  To enter to self
 *                                                       refresh mode.
-*                    EMIFA_SDRAM_SELFREF_MODE_EXIT   -  To exit from self 
+*                    EMIFA_SDRAM_SELFREF_MODE_EXIT   -  To exit from self
 *                                                       refresh mode.\n
 *
 * \return none.
@@ -476,32 +476,32 @@ void EMIFASDRAMConfig(unsigned int baseAddr,unsigned int conf)
 void EMIFASDRAMSelfRefModeConfig(unsigned int baseAddr,unsigned int flag)
 {
     HWREG(baseAddr + EMIFA_SDCR) |= ((flag << EMIFA_SDCR_SR_SHIFT)
-                                    & EMIFA_SDCR_SR);       
+                                    & EMIFA_SDCR_SR);
 }
 
 /**
-* \brief  This function configure the Self refresh mode of SDRAM.\n 
+* \brief  This function configure the Self refresh mode of SDRAM.\n
 *
 * \param  baseAddr   Memory address of EMIFA.\n
 *
 * \param  flag       Flag indicate whether to enter or exit the power down
-*                    mode. 
+*                    mode.
 *                    This can take one of the following values :
-*                    EMIFA_SDRAM_POWDOWN_MODE_ENTER  -  To enter to power 
+*                    EMIFA_SDRAM_POWDOWN_MODE_ENTER  -  To enter to power
 *                                                       down mode.
-*                    EMIFA_SDRAM_POWDOEN_MODE_EXIT   -  To exit from power 
+*                    EMIFA_SDRAM_POWDOEN_MODE_EXIT   -  To exit from power
 *                                                       down mode.\n
 *
 * \return none.
 */
 void EMIFASDRAMPowDownModeConfig(unsigned int baseAddr,unsigned int flag)
 {
-    HWREG(baseAddr + EMIFA_SDCR) |= ((flag << EMIFA_SDCR_PD_SHIFT) 
-                                    & EMIFA_SDCR_PD);       
+    HWREG(baseAddr + EMIFA_SDCR) |= ((flag << EMIFA_SDCR_PD_SHIFT)
+                                    & EMIFA_SDCR_PD);
 }
 
 /**
-* \brief  This function enables the refresh during power down mode.\n 
+* \brief  This function enables the refresh during power down mode.\n
 *
 * \param  baseAddr   Memory address of EMIFA.\n
 *
@@ -509,25 +509,25 @@ void EMIFASDRAMPowDownModeConfig(unsigned int baseAddr,unsigned int flag)
 */
 void EMIFASDRAMRefDurPowDownModeEnable(unsigned int baseAddr)
 {
-    HWREG(baseAddr + EMIFA_SDCR) |= EMIFA_SDCR_PDWR;            
+    HWREG(baseAddr + EMIFA_SDCR) |= EMIFA_SDCR_PDWR;
 }
 
 /**
-* \brief  This function configure the Self refresh rate of SDRAM.\n 
+* \brief  This function configure the Self refresh rate of SDRAM.\n
 *
 * \param  baseAddr    Memory address of EMIFA.\n
-*   
+*
 *         refRate     SDRAM refresh rate interms of EMA_CLK cycles.\n
 *
 * \return none.
 */
 void EMIFASDRAMRefRateSet(unsigned int baseAddr,unsigned int refRate)
 {
-    HWREG(baseAddr + EMIFA_SDRCR) = (refRate & EMIFA_SDRCR_RR);                  
+    HWREG(baseAddr + EMIFA_SDRCR) = (refRate & EMIFA_SDRCR_RR);
 }
 
 /**
-* \brief  This function does the Timing Configurations of SDRAM.\n 
+* \brief  This function does the Timing Configurations of SDRAM.\n
 *
 * \param  baseAddr   Memory address of EMIFA.\n
 *
@@ -542,7 +542,7 @@ void EMIFASDRAMTimingConfig(unsigned int baseAddr,unsigned int conf)
 }
 
 /**
-* \brief  This function congigures the self refresh exit timing .\n 
+* \brief  This function congigures the self refresh exit timing .\n
 *
 * \param  baseAddr   Memory address of EMIFA.\n
 *
@@ -556,7 +556,7 @@ void EMIFASDRAMSelfRefExitTimeConfig(unsigned int baseAddr,unsigned int exitTime
 }
 
 /**
-* \brief  This function returns the status of EMA_WAIT[n] pins.\n 
+* \brief  This function returns the status of EMA_WAIT[n] pins.\n
 *
 * \param  baseAddr   Memory address of EMIFA.\n
 *
@@ -573,20 +573,20 @@ unsigned int EMIFAWaitPinStatusGet(unsigned int baseAddr,unsigned int pinNum)
     unsigned int status = 0;
 
     if( pinNum  == EMIFA_EMA_WAIT_PIN0)
-    {   
+    {
         status = (HWREG(baseAddr + EMIFA_NANDFSR) & 0x1);
-        
+
     }
     else if(pinNum == EMIFA_EMA_WAIT_PIN1)
     {
         status = ((HWREG(baseAddr + EMIFA_NANDFSR) >> 1) & 0x1);
-    }       
-    return status;   
+    }
+    return status;
 }
 
 /**
 * \brief  This function returns ECC correction state while performing 4-bit ECC
-*         Address and Error Value Calculation.\n 
+*         Address and Error Value Calculation.\n
 *
 * \param  baseAddr   Memory address of EMIFA.\n
 *
@@ -595,31 +595,31 @@ unsigned int EMIFAWaitPinStatusGet(unsigned int baseAddr,unsigned int pinNum)
 unsigned int EMIFANAND4BitECCStateGet(unsigned int baseAddr)
 {
     unsigned int eccState;
-    
-    eccState = ((HWREG(baseAddr + EMIFA_NANDFSR) & EMIFA_NANDFSR_ECC_STATE) >> 
-                EMIFA_NANDFSR_ECC_STATE_SHIFT); 
-                
-    return eccState;                
+
+    eccState = ((HWREG(baseAddr + EMIFA_NANDFSR) & EMIFA_NANDFSR_ECC_STATE) >>
+                EMIFA_NANDFSR_ECC_STATE_SHIFT);
+
+    return eccState;
 }
 
 /**
-* \brief  This function returns the Number of Errors found after the 4-Bit ECC 
+* \brief  This function returns the Number of Errors found after the 4-Bit ECC
 *         Error Address and Error Value Calculation.
 *
 * \param  baseAddr   Memory address of EMIFA.\n
 *
-* \return eccErrNum  Num of erros during 4-bit ECC add and err val 
+* \return eccErrNum  Num of erros during 4-bit ECC add and err val
 *                    calculation(ECC_ERRNUM).
 */
 unsigned int EMIFANAND4BitECCNumOfErrsGet(unsigned int baseAddr)
 {
     unsigned int eccErrNum;
-    
-    eccErrNum = ((HWREG(baseAddr + EMIFA_NANDFSR) & EMIFA_NANDFSR_ECC_ERRNUM) >> 
-                EMIFA_NANDFSR_ECC_ERRNUM_SHIFT);    
-                
-    return eccErrNum;   
-    
+
+    eccErrNum = ((HWREG(baseAddr + EMIFA_NANDFSR) & EMIFA_NANDFSR_ECC_ERRNUM) >>
+                EMIFA_NANDFSR_ECC_ERRNUM_SHIFT);
+
+    return eccErrNum;
+
 }
 
 /**
@@ -635,13 +635,13 @@ unsigned int EMIFANAND4BitECCNumOfErrsGet(unsigned int baseAddr)
 *                    EMIFA_CHIP_SELECT_5  -  NOR interfaced on CS5.\n
 *
 *         flag       Page mode to enable or disable.
-*                    This can take one of the following values :        
+*                    This can take one of the following values :
 *                    EMIFA_NOR_PAGEMODE_ENABLE  - Nor page mode enable
 *                    EMIFA_NOR_PAGEMODE_DISABLE - Nor page mode disable.\n
-* 
+*
 * \return none.
 */
-void EMIFANORPageModeConfig(unsigned int baseAddr, unsigned int CSNum, 
+void EMIFANORPageModeConfig(unsigned int baseAddr, unsigned int CSNum,
                                    unsigned int flag)
 {
     switch(CSNum)
@@ -683,7 +683,7 @@ void EMIFANORPageModeConfig(unsigned int baseAddr, unsigned int CSNum,
 *                    This can take one of the following values :
 *                    EMIFA_NOR_PAGE_SIZE_4WORDS  - Nor page size is 4 words
 *                    EMIFA_NOR_PAGE_SIZE_8WORDS  - Nor page size is 8 words
-* 
+*
 * \return none.
 */
 void EMIFANORPageSizeSet(unsigned int baseAddr,unsigned int CSNum,
@@ -692,22 +692,22 @@ void EMIFANORPageSizeSet(unsigned int baseAddr,unsigned int CSNum,
     switch(CSNum)
     {
         case EMIFA_CHIP_SELECT_2:
-        	 HWREG(baseAddr + EMIFA_PMCR) |= ((pageSize << 
+        	 HWREG(baseAddr + EMIFA_PMCR) |= ((pageSize <<
 											  EMIFA_PMCR_CS2_PG_SIZE_SHIFT)
                                               & EMIFA_PMCR_CS2_PG_SIZE);
         break;
         case EMIFA_CHIP_SELECT_3:
-	         HWREG(baseAddr + EMIFA_PMCR) |= ((pageSize << 
+	         HWREG(baseAddr + EMIFA_PMCR) |= ((pageSize <<
 							  	     		  EMIFA_PMCR_CS3_PG_SIZE_SHIFT)
                                               & EMIFA_PMCR_CS3_PG_SIZE);
         break;
         case EMIFA_CHIP_SELECT_4:
-	         HWREG(baseAddr + EMIFA_PMCR) |= ((pageSize << 
+	         HWREG(baseAddr + EMIFA_PMCR) |= ((pageSize <<
 											  EMIFA_PMCR_CS4_PG_SIZE_SHIFT)
 		                                      & EMIFA_PMCR_CS4_PG_SIZE);
         break;
         case EMIFA_CHIP_SELECT_5:
-		     HWREG(baseAddr + EMIFA_PMCR) |= ((pageSize << 
+		     HWREG(baseAddr + EMIFA_PMCR) |= ((pageSize <<
 								  			  EMIFA_PMCR_CS5_PG_SIZE_SHIFT)
 	                                          & EMIFA_PMCR_CS5_PG_SIZE);
         break;
@@ -729,8 +729,8 @@ void EMIFANORPageSizeSet(unsigned int baseAddr,unsigned int CSNum,
 *                    EMIFA_CHIP_SELECT_5  -  NOR interfaced on CS5.\n
 *
 *        delay      Page access delay for NOR Flash in EMA_CLK cycles.\n
-*        
-* 
+*
+*
 * \return none.\n
 */
 void EMIFANORPageAccessDelaySet(unsigned int baseAddr, unsigned int CSNum,
@@ -739,23 +739,23 @@ void EMIFANORPageAccessDelaySet(unsigned int baseAddr, unsigned int CSNum,
     switch(CSNum)
     {
         case EMIFA_CHIP_SELECT_2:
-        	 HWREG(baseAddr + EMIFA_PMCR) |= ((delay << 
-                                              EMIFA_PMCR_CS2_PG_DEL_SHIFT) 
+        	 HWREG(baseAddr + EMIFA_PMCR) |= ((delay <<
+                                              EMIFA_PMCR_CS2_PG_DEL_SHIFT)
              			                      & EMIFA_PMCR_CS2_PG_DEL);
         break;
         case EMIFA_CHIP_SELECT_3:
-	         HWREG(baseAddr + EMIFA_PMCR) |= ((delay << 
-											  EMIFA_PMCR_CS3_PG_DEL_SHIFT) 
+	         HWREG(baseAddr + EMIFA_PMCR) |= ((delay <<
+											  EMIFA_PMCR_CS3_PG_DEL_SHIFT)
 		                                      & EMIFA_PMCR_CS3_PG_DEL);
         break;
         case EMIFA_CHIP_SELECT_4:
 	         HWREG(baseAddr + EMIFA_PMCR) |= ((delay <<
-											   EMIFA_PMCR_CS4_PG_DEL_SHIFT) 
+											   EMIFA_PMCR_CS4_PG_DEL_SHIFT)
 			                                   & EMIFA_PMCR_CS4_PG_DEL);
         break;
         case EMIFA_CHIP_SELECT_5:
-	         HWREG(baseAddr + EMIFA_PMCR) |= ((delay << 
-					  						  EMIFA_PMCR_CS5_PG_DEL_SHIFT) 
+	         HWREG(baseAddr + EMIFA_PMCR) |= ((delay <<
+					  						  EMIFA_PMCR_CS5_PG_DEL_SHIFT)
 			                                  & EMIFA_PMCR_CS5_PG_DEL);
         break;
         default:
@@ -768,14 +768,14 @@ void EMIFANORPageAccessDelaySet(unsigned int baseAddr, unsigned int CSNum,
 *
 * \param  baseAddr   Memory address of EMIFA.\n
 *
-*         eccLdVal   ECC load value .\n  
-* 
+*         eccLdVal   ECC load value .\n
+*
 * \return none.\n
 */
 void EMIFANAND4BitECCLoad(unsigned int baseAddr,unsigned int eccLdVal)
 {
 
-    HWREG(baseAddr + EMIFA_NAND4BITECCLOAD) =( eccLdVal & 
+    HWREG(baseAddr + EMIFA_NAND4BITECCLOAD) =( eccLdVal &
                                              EMIFA_NAND4BITECCLOAD_4BITECCLOAD);
 }
 
@@ -789,16 +789,16 @@ void EMIFANAND4BitECCLoad(unsigned int baseAddr,unsigned int eccLdVal)
 *                          EMIFA_NAND_1BIT_ECC - To start 1 bit ECC.
 *                          EMIFA_NAND_4BIT_ECC - To start 4 bit ecc
 *
-*         eccValIndexOrCS  When ecc is EMIFA_NAND_1BIT_ECC, this argument 
-*                          acts as CS(chip select), where it can take one of 
-*                          the following values : 
+*         eccValIndexOrCS  When ecc is EMIFA_NAND_1BIT_ECC, this argument
+*                          acts as CS(chip select), where it can take one of
+*                          the following values :
 *                          EMIFA_CHIP_SELECT_2  -  Using nand on CS2.
 *                          EMIFA_CHIP_SELECT_3  -  Using nand on CS3.
 *                          EMIFA_CHIP_SELECT_4  -  Using nand on CS4.
 *                          EMIFA_CHIP_SELECT_5  -  Using nand on CS5.\n
 *
-*                          When ecc is EMIFA_NAND_4BIT_ECC, this argument 
-*                          acts asa ECC value index, where it can take one of     
+*                          When ecc is EMIFA_NAND_4BIT_ECC, this argument
+*                          acts asa ECC value index, where it can take one of
 *                          following values :
 *                          EMIFA_NAND_4BITECCVAL1 -- To retrive 4BITECCVAL1
 *                          EMIFA_NAND_4BITECCVAL2 -- To retrive 4BITECCVAL2
@@ -808,7 +808,7 @@ void EMIFANAND4BitECCLoad(unsigned int baseAddr,unsigned int eccLdVal)
 *                          EMIFA_NAND_4BITECCVAL6 -- To retrive 4BITECCVAL6
 *                          EMIFA_NAND_4BITECCVAL7 -- To retrive 4BITECCVAL7
 *                          EMIFA_NAND_4BITECCVAL8 -- To retrive 4BITECCVAL8
-*   
+*
 * \return eccVal           ECC value.
 */
 unsigned int EMIFANANDEccValGet(unsigned int baseAddr,unsigned int eccType,
@@ -842,42 +842,42 @@ unsigned int EMIFANANDEccValGet(unsigned int baseAddr,unsigned int eccType,
         {
             case EMIFA_NAND_4BITECCVAL1:
                  eccVal = ((HWREG(baseAddr + EMIFA_NAND4BITECC1) &
-                            EMIFA_NAND4BITECC1_4BITECCVAL1) >> 
+                            EMIFA_NAND4BITECC1_4BITECCVAL1) >>
                             EMIFA_NAND4BITECC1_4BITECCVAL1_SHIFT);
             break;
             case EMIFA_NAND_4BITECCVAL2:
                  eccVal = ((HWREG(baseAddr + EMIFA_NAND4BITECC1) &
-                            EMIFA_NAND4BITECC1_4BITECCVAL2) >> 
-                            EMIFA_NAND4BITECC1_4BITECCVAL2_SHIFT);                
+                            EMIFA_NAND4BITECC1_4BITECCVAL2) >>
+                            EMIFA_NAND4BITECC1_4BITECCVAL2_SHIFT);
             break;
             case EMIFA_NAND_4BITECCVAL3:
                  eccVal = ((HWREG(baseAddr + EMIFA_NAND4BITECC2) &
-                            EMIFA_NAND4BITECC2_4BITECCVAL3) >> 
+                            EMIFA_NAND4BITECC2_4BITECCVAL3) >>
                             EMIFA_NAND4BITECC2_4BITECCVAL3_SHIFT);
             break;
             case EMIFA_NAND_4BITECCVAL4:
                  eccVal = ((HWREG(baseAddr + EMIFA_NAND4BITECC2) &
-                            EMIFA_NAND4BITECC2_4BITECCVAL4) >> 
-                            EMIFA_NAND4BITECC2_4BITECCVAL4_SHIFT);        
+                            EMIFA_NAND4BITECC2_4BITECCVAL4) >>
+                            EMIFA_NAND4BITECC2_4BITECCVAL4_SHIFT);
             break;
             case EMIFA_NAND_4BITECCVAL5:
                  eccVal = ((HWREG(baseAddr + EMIFA_NAND4BITECC3) &
-                            EMIFA_NAND4BITECC3_4BITECCVAL5) >> 
-                            EMIFA_NAND4BITECC3_4BITECCVAL5_SHIFT);        
+                            EMIFA_NAND4BITECC3_4BITECCVAL5) >>
+                            EMIFA_NAND4BITECC3_4BITECCVAL5_SHIFT);
             break;
             case EMIFA_NAND_4BITECCVAL6:
                  eccVal = ((HWREG(baseAddr + EMIFA_NAND4BITECC3) &
-                            EMIFA_NAND4BITECC3_4BITECCVAL6) >> 
-                            EMIFA_NAND4BITECC3_4BITECCVAL6_SHIFT);        
+                            EMIFA_NAND4BITECC3_4BITECCVAL6) >>
+                            EMIFA_NAND4BITECC3_4BITECCVAL6_SHIFT);
             break;
             case EMIFA_NAND_4BITECCVAL7:
                  eccVal = ((HWREG(baseAddr + EMIFA_NAND4BITECC4) &
-                            EMIFA_NAND4BITECC4_4BITECCVAL7) >> 
-                            EMIFA_NAND4BITECC4_4BITECCVAL7_SHIFT);        
+                            EMIFA_NAND4BITECC4_4BITECCVAL7) >>
+                            EMIFA_NAND4BITECC4_4BITECCVAL7_SHIFT);
             break;
             case EMIFA_NAND_4BITECCVAL8:
                  eccVal = ((HWREG(baseAddr + EMIFA_NAND4BITECC4) &
-                            EMIFA_NAND4BITECC4_4BITECCVAL8) >> 
+                            EMIFA_NAND4BITECC4_4BITECCVAL8) >>
                             EMIFA_NAND4BITECC4_4BITECCVAL8_SHIFT);
             break;
             default:
@@ -885,30 +885,30 @@ unsigned int EMIFANANDEccValGet(unsigned int baseAddr,unsigned int eccType,
         }
     }
     return eccVal;
-}               
+}
 
 /**
 * \brief  This function retrives the Address of 4-bit ECC error.
 *
 * \param  baseAddr         Memory address of EMIFA.\n
 *
-*         eccErrAddrIndex  ECC address error index.\n    
-*                          This can take one of the following values : 
-*                          EMIFA_4BITECC_ERRADDR_INDEX_1 -- To retrice 
+*         eccErrAddrIndex  ECC address error index.\n
+*                          This can take one of the following values :
+*                          EMIFA_4BITECC_ERRADDR_INDEX_1 -- To retrice
 *                                                           4BITECCERRADD1
-*                          EMIFA_4BITECC_ERRADDR_INDEX_2 -- To retrice 
+*                          EMIFA_4BITECC_ERRADDR_INDEX_2 -- To retrice
 *                                                           4BITECCERRADD2
-*                          EMIFA_4BITECC_ERRADDR_INDEX_3 -- To retrice 
+*                          EMIFA_4BITECC_ERRADDR_INDEX_3 -- To retrice
 *                                                           4BITECCERRADD3
-*                          EMIFA_4BITECC_ERRADDR_INDEX_4 -- To retrice 
+*                          EMIFA_4BITECC_ERRADDR_INDEX_4 -- To retrice
 *                                                           4BITECCERRADD4
-*   
+*
 * \return eccAddrVal   Address of 4-bit ECC error.
 **/
 unsigned int EMIFANAND4BitEccErrAddrGet(unsigned int baseAddr,
                                         unsigned int eccErrAddrIndex)
 {
-    unsigned int eccAddrVal = 0;   
+    unsigned int eccAddrVal = 0;
 
     switch(eccErrAddrIndex)
     {
@@ -920,17 +920,17 @@ unsigned int EMIFANAND4BitEccErrAddrGet(unsigned int baseAddr,
         case EMIFA_4BITECC_ERRADDR_INDEX_2:
              eccAddrVal = ((HWREG(baseAddr + EMIFA_NANDERRADD1) &
                            EMIFA_NANDERRADD1_4BITECCERRADD2) >>
-                           EMIFA_NANDERRADD1_4BITECCERRADD2_SHIFT);  
+                           EMIFA_NANDERRADD1_4BITECCERRADD2_SHIFT);
         break;
         case EMIFA_4BITECC_ERRADDR_INDEX_3:
              eccAddrVal = ((HWREG(baseAddr + EMIFA_NANDERRADD2) &
                           EMIFA_NANDERRADD2_4BITECCERRADD3) >>
-                          EMIFA_NANDERRADD2_4BITECCERRADD3_SHIFT);  
+                          EMIFA_NANDERRADD2_4BITECCERRADD3_SHIFT);
         break;
         case EMIFA_4BITECC_ERRADDR_INDEX_4:
              eccAddrVal = ((HWREG(baseAddr + EMIFA_NANDERRADD2) &
                           EMIFA_NANDERRADD2_4BITECCERRADD4) >>
-                          EMIFA_NANDERRADD2_4BITECCERRADD4_SHIFT);  
+                          EMIFA_NANDERRADD2_4BITECCERRADD4_SHIFT);
         break;
         default:
         break;
@@ -949,13 +949,13 @@ unsigned int EMIFANAND4BitEccErrAddrGet(unsigned int baseAddr,
 *                    EMIFA_4BITECC_ERRVAL_INDEX_2 -- To retrice 4BITECCERRVAL2
 *                    EMIFA_4BITECC_ERRVAL_INDEX_3 -- To retrice 4BITECCERRVAL3
 *                    EMIFA_4BITECC_ERRVAL_INDEX_4 -- To retrice 4BITECCERRVAL4
-*   
+*
 * \return eccErrVal  Value of 4-bit ECC error.
 */
 unsigned int EMIFANAND4BitEccErrValGet(unsigned int baseAddr,
                                         unsigned int eccErrValIndex)
 {
-    unsigned int eccErrVal = 0;    
+    unsigned int eccErrVal = 0;
 
     switch(eccErrValIndex)
     {
@@ -967,27 +967,27 @@ unsigned int EMIFANAND4BitEccErrValGet(unsigned int baseAddr,
         case EMIFA_4BITECC_ERRVAL_INDEX_2:
 	         eccErrVal = ((HWREG(baseAddr + EMIFA_NANDERRVAL1) &
      	                   EMIFA_NANDERRVAL1_4BITECCERRVAL2) >>
-          		           EMIFA_NANDERRVAL1_4BITECCERRVAL2_SHIFT);  
+          		           EMIFA_NANDERRVAL1_4BITECCERRVAL2_SHIFT);
         break;
         case EMIFA_4BITECC_ERRVAL_INDEX_3:
 	         eccErrVal = ((HWREG(baseAddr + EMIFA_NANDERRVAL2) &
      	                   EMIFA_NANDERRVAL2_4BITECCERRVAL3) >>
-	                       EMIFA_NANDERRVAL2_4BITECCERRVAL3_SHIFT);  
+	                       EMIFA_NANDERRVAL2_4BITECCERRVAL3_SHIFT);
         break;
         case EMIFA_4BITECC_ERRVAL_INDEX_4:
 	         eccErrVal = ((HWREG(baseAddr + EMIFA_NANDERRVAL2) &
      	                   EMIFA_NANDERRVAL2_4BITECCERRVAL4) >>
-	                       EMIFA_NANDERRVAL2_4BITECCERRVAL4_SHIFT);  
+	                       EMIFA_NANDERRVAL2_4BITECCERRVAL4_SHIFT);
         break;
         default:
         break;
-    }    
- 
+    }
+
     return (eccErrVal);
 }
 
 /**
-* \brief  This function configures the wait timing for the device interfaced on 
+* \brief  This function configures the wait timing for the device interfaced on
 *         csNum.
 *
 * \param  baseAddr   Memory address of EMIFA.\n
@@ -1000,11 +1000,11 @@ unsigned int EMIFANAND4BitEccErrValGet(unsigned int baseAddr,
 *                    EMIFA_CHIP_SELECT_5  -  For CS5.\n
 *
 * \param  conf       Configuration value for the device connected to csNum.
-*                    Use the EMIFA_ASYNC_WAITTIME_CONFIG macro to get the value 
+*                    Use the EMIFA_ASYNC_WAITTIME_CONFIG macro to get the value
 *                    of conf. \n
 *
 * \return none.
-**/                    
+**/
 void EMIFAWaitTimingConfig(unsigned int baseAddr,unsigned int CSNum,
                            unsigned int conf)
 {
@@ -1012,30 +1012,30 @@ void EMIFAWaitTimingConfig(unsigned int baseAddr,unsigned int CSNum,
     switch(CSNum)
     {
         case EMIFA_CHIP_SELECT_2:
-     	     HWREG(baseAddr + EMIFA_CE2CFG) |= conf;     
+     	     HWREG(baseAddr + EMIFA_CE2CFG) |= conf;
         break;
         case EMIFA_CHIP_SELECT_3:
-	         HWREG(baseAddr + EMIFA_CE3CFG) |= conf;     
+	         HWREG(baseAddr + EMIFA_CE3CFG) |= conf;
         break;
         case EMIFA_CHIP_SELECT_4:
-	         HWREG(baseAddr + EMIFA_CE4CFG) |= conf;     
+	         HWREG(baseAddr + EMIFA_CE4CFG) |= conf;
         break;
         case EMIFA_CHIP_SELECT_5:
-	         HWREG(baseAddr + EMIFA_CE5CFG) |= conf;     
+	         HWREG(baseAddr + EMIFA_CE5CFG) |= conf;
         break;
         default:
         break;
     }
-}                          
+}
 
 /**
 * \brief  This function monitors/reads the EMIFA's hardware-generated interrupts
-*           
+*
 * \param  baseAddr   Memory address of EMIFA.\n
 *
 * \param  intFlag    Interrupt Flag for which interrupt status has to read.\n
 *                    This can take one of the following values :
-*                    EMIFA_ASYNC_TIMOUT_INT  -  For Asynchronous Timeout 
+*                    EMIFA_ASYNC_TIMOUT_INT  -  For Asynchronous Timeout
 *                                               interrupt.
 *                    EMIFA_LINE_TRAP_INT     -  For Line Trap interrupt.
 *                    EMIFA_WAIT_RISE_INT     -  For Wait Rise interrupt.
@@ -1053,19 +1053,19 @@ unsigned int EMIFARawIntStatusRead(unsigned int baseAddr,unsigned int intFlag)
     else if (intFlag == EMIFA_LINE_TRAP_INT)
     {
         intStatus = ((HWREG(baseAddr + EMIFA_INTRAW) & EMIFA_INTRAW_LT) >>
-                    EMIFA_INTRAW_LT_SHIFT);     
+                    EMIFA_INTRAW_LT_SHIFT);
     }
     else if (intFlag == EMIFA_WAIT_RISE_INT)
     {
         intStatus = ((HWREG(baseAddr + EMIFA_INTRAW) & EMIFA_INTRAW_WR) >>
-                    EMIFA_INTRAW_WR_SHIFT);             
-    }       
+                    EMIFA_INTRAW_WR_SHIFT);
+    }
     return intStatus;
 }
 
 /**
 * \brief  This function Clears the EMIFA hardware-generated interrupts
-*           
+*
 * \param  baseAddr   Memory address of EMIFA.\n
 *
 * \param  intFlag    Interrupt Flag for which interrupt has to clear.\n
@@ -1085,17 +1085,17 @@ void EMIFARawIntClear(unsigned int baseAddr,unsigned int intFlag)
     }
     else if (intFlag == EMIFA_LINE_TRAP_INT)
     {
-        HWREG(baseAddr + EMIFA_INTRAW) |= EMIFA_INTRAW_LT;       
+        HWREG(baseAddr + EMIFA_INTRAW) |= EMIFA_INTRAW_LT;
     }
     else if (intFlag == EMIFA_WAIT_RISE_INT)
     {
-        HWREG(baseAddr + EMIFA_INTRAW) |= EMIFA_INTRAW_WR;               
-    }       
+        HWREG(baseAddr + EMIFA_INTRAW) |= EMIFA_INTRAW_WR;
+    }
 }
 
 /**
 * \brief  This function monitors/reads the EMIFA's hardware-generated interrupts
-*           
+*
 * \param  baseAddr   Memory address of EMIFA.\n
 *
 * \param  intFlag    Interrupt Flag for which interrupt status has to read.\n
@@ -1107,9 +1107,9 @@ void EMIFARawIntClear(unsigned int baseAddr,unsigned int intFlag)
 *
 * \return Interrupt status.
 *
-*  NOTE : Main diffrence between EMIFAMskedIntStatusRead and 
-*         EMIFARawIntStatusRead is that when any int flag in 
-*         EMIFAMskedIntStatusRead is set an active-high pulse will be sent 
+*  NOTE : Main diffrence between EMIFAMskedIntStatusRead and
+*         EMIFARawIntStatusRead is that when any int flag in
+*         EMIFAMskedIntStatusRead is set an active-high pulse will be sent
 *         to the CPU interrupt controller.
 *
 */
@@ -1131,13 +1131,13 @@ unsigned int EMIFAMskedIntStatusRead(unsigned int baseAddr,unsigned int intFlag)
     {
        intStatus = ((HWREG(baseAddr + EMIFA_INTMSK) & EMIFA_INTMSK_WRED_MASK) >>
                      EMIFA_INTMSK_WRED_SHIFT);
-    }       
-    return intStatus;   
+    }
+    return intStatus;
 }
 
 /**
-* \brief  This function Clears the EMIFA’s hardware-generated interrupts
-*           
+* \brief  This function Clears the EMIFA�s hardware-generated interrupts
+*
 * \param  baseAddr   Memory address of EMIFA.\n
 *
 * \param  intFlag    Interrupt Flag for which interrupt has to clear.\n
@@ -1147,9 +1147,9 @@ unsigned int EMIFAMskedIntStatusRead(unsigned int baseAddr,unsigned int intFlag)
 *                    EMIFA_LINE_TRAP_INT     -  For Line Trap interrupt.\n
 *                    EMIFA_WAIT_RISE_INT     -  For Wait Rise interrupt.\n
 *
-*  NOTE : Main diffrence between EMIFAMskedIntStatusRead and 
-*         EMIFARawIntStatusRead is that when any int flag in 
-*         EMIFAMskedIntStatusRead is set an active-high pulse will be sent 
+*  NOTE : Main diffrence between EMIFAMskedIntStatusRead and
+*         EMIFARawIntStatusRead is that when any int flag in
+*         EMIFAMskedIntStatusRead is set an active-high pulse will be sent
 *         to the CPU interrupt controller.
 *
 * \return none.
@@ -1162,17 +1162,17 @@ void EMIFAMskedIntClear(unsigned int baseAddr,unsigned int intFlag)
     }
     else if (intFlag == EMIFA_LINE_TRAP_INT)
     {
-        HWREG(baseAddr + EMIFA_INTMSK) &= (~EMIFA_INTMSK_LTED_MASK);        
+        HWREG(baseAddr + EMIFA_INTMSK) &= (~EMIFA_INTMSK_LTED_MASK);
     }
     else if (intFlag == EMIFA_WAIT_RISE_INT)
     {
-        HWREG(baseAddr + EMIFA_INTMSK) &= (~EMIFA_INTMSK_WRED_MASK);                
-    }       
+        HWREG(baseAddr + EMIFA_INTMSK) &= (~EMIFA_INTMSK_WRED_MASK);
+    }
 }
 
 /**
 * \brief  This function Enables the interrupts.
-*           
+*
 * \param  baseAddr   Memory address of EMIFA.\n
 *
 * \param  intFlag    Interrupt Flag for which interrupt has to enable.\n
@@ -1183,7 +1183,7 @@ void EMIFAMskedIntClear(unsigned int baseAddr,unsigned int intFlag)
 *                    EMIFA_WAIT_RISE_INT     -  For Wait Rise interrupt.\n
 *
 * \return none.
-*/                 
+*/
 void EMIFAMskedIntEnable(unsigned int baseAddr,unsigned int intFlag)
 {
     if(intFlag == EMIFA_ASYNC_TIMOUT_INT)
@@ -1192,28 +1192,28 @@ void EMIFAMskedIntEnable(unsigned int baseAddr,unsigned int intFlag)
     }
     else if (intFlag == EMIFA_LINE_TRAP_INT)
     {
-        HWREG(baseAddr + EMIFA_INTMSKSET) |= EMIFA_INTMSKSET_LT_SET_MASK;       
+        HWREG(baseAddr + EMIFA_INTMSKSET) |= EMIFA_INTMSKSET_LT_SET_MASK;
     }
     else if (intFlag == EMIFA_WAIT_RISE_INT)
     {
-        HWREG(baseAddr + EMIFA_INTMSKSET) |= EMIFA_INTMSKSET_WR_SET_MASK;       
-    }           
+        HWREG(baseAddr + EMIFA_INTMSKSET) |= EMIFA_INTMSKSET_WR_SET_MASK;
+    }
 }
 
 /**
 * \brief  This function Disables the interrupts.
-*           
+*
 * \param  baseAddr   Memory address of EMIFA.\n
 *
 * \param  intFlag    Interrupt Flag for which interrupt has to disable.\n
 *                    This can take one of the following values :
-*                    EMIFA_ASYNC_TIMOUT_INT  -  For Asynchronous Timeout 
+*                    EMIFA_ASYNC_TIMOUT_INT  -  For Asynchronous Timeout
 *                                               interrupt.\n
 *                    EMIFA_LINE_TRAP_INT     -  For Line Trap interrupt.\n
 *                    EMIFA_WAIT_RISE_INT     -  For Wait Rise interrupt.\n
 *
 * \return none.
-*/                 
+*/
 void EMIFAMskedIntDisable(unsigned int baseAddr,unsigned int intFlag)
 {
     if(intFlag == EMIFA_ASYNC_TIMOUT_INT)
@@ -1222,11 +1222,11 @@ void EMIFAMskedIntDisable(unsigned int baseAddr,unsigned int intFlag)
     }
     else if (intFlag == EMIFA_LINE_TRAP_INT)
     {
-        HWREG(baseAddr + EMIFA_INTMSKCLR) |= EMIFA_INTMSKCLR_LT_CLR_MASK;       
+        HWREG(baseAddr + EMIFA_INTMSKCLR) |= EMIFA_INTMSKCLR_LT_CLR_MASK;
     }
     else if (intFlag == EMIFA_WAIT_RISE_INT)
     {
-        HWREG(baseAddr + EMIFA_INTMSKCLR) |= EMIFA_INTMSKCLR_WR_CLR_MASK;       
-    }           
+        HWREG(baseAddr + EMIFA_INTMSKCLR) |= EMIFA_INTMSKCLR_WR_CLR_MASK;
+    }
 }
 /***************************** End Of File ***********************************/
diff --git a/lib/tiam1808/drivers/gpio.c b/lib/tiam1808/drivers/gpio.c
index 68919ab6a..949069c13 100644
--- a/lib/tiam1808/drivers/gpio.c
+++ b/lib/tiam1808/drivers/gpio.c
@@ -1,6 +1,6 @@
 /**
  *  \file     gpio.c
- * 
+ *
  *  \brief    This file contains the device abstraction layer APIs for GPIO
  */
 
@@ -45,29 +45,29 @@
 
 
 /***********************************************************************/
-/*              API FUNCTION DEFINITIONS.                              */ 
+/*              API FUNCTION DEFINITIONS.                              */
 /***********************************************************************/
 
 /**
- * \brief    This function configures the direction of a pin as input or 
+ * \brief    This function configures the direction of a pin as input or
  *           output.
  *
  * \param    baseAdd     The memory address of the GPIO instance being used.
  * \param    pinNumber   The serial number of the GPIO pin.
  *                       The 144 GPIO pins have serial numbers from 1 to 144.
- *                       
+ *
  * \param    pinDir      The direction to be set for the pin.
  *                       This can take the values:
  *                       1> GPIO_DIR_INPUT, for configuring the pin as input.
  *                       2> GPIO_DIR_OUTPUT, for configuring the pin as output.
- * 
+ *
  * \return   None.
  *
- * \note     Here we write to the DIRn register. Writing a logic 1 configures 
+ * \note     Here we write to the DIRn register. Writing a logic 1 configures
  *           the pin as input and writing logic 0 as output. By default, all
  *           the pins are set as input pins.
  */
-void GPIODirModeSet(unsigned int baseAdd, unsigned int pinNumber, 
+void GPIODirModeSet(unsigned int baseAdd, unsigned int pinNumber,
                     unsigned int pinDir)
 
 {
@@ -80,11 +80,11 @@ void GPIODirModeSet(unsigned int baseAdd, unsigned int pinNumber,
     ** calculated based on 32 pins boundary.
     */
     regNumber = (pinNumber - 1)/32;
- 
+
     /*
     ** In every register the least significant bits starts with a GPIO number on
     ** a boundary of 32. Thus the pin offset must be calculated based on 32
-    ** pins boundary. Ex: 'pinNumber' of 1 corresponds to bit 0 in 
+    ** pins boundary. Ex: 'pinNumber' of 1 corresponds to bit 0 in
     ** 'register_name01'.
     */
     pinOffset = (pinNumber - 1) % 32;
@@ -102,10 +102,10 @@ void GPIODirModeSet(unsigned int baseAdd, unsigned int pinNumber,
 /**
  * \brief  This function gets the direction of a pin which has been configured
  *         as an input or an output pin.
- * 
+ *
  * \param   baseAdd    The memory address of the GPIO instance being used.
  * \param   pinNumber  The serial number of the GPIO pin.
- *                     The 144 GPIO pins have serial numbers from 1 to 144.                      
+ *                     The 144 GPIO pins have serial numbers from 1 to 144.
  *
  * \return  This returns one of the following two values:
  *          1> GPIO_DIR_INPUT, if the pin is configured as an input pin.
@@ -117,22 +117,22 @@ unsigned int GPIODirModeGet(unsigned int baseAdd, unsigned int pinNumber)
     unsigned int dir = GPIO_DIR_INPUT;
     unsigned int regNumber = 0;
     unsigned int pinOffset = 0;
-    
+
     /*
     ** Each register contains settings for each pin of two banks. The 32 bits
     ** represent 16 pins each from the banks. Thus the register number must be
     ** calculated based on 32 pins boundary.
     */
- 
+
     regNumber = (pinNumber - 1)/32;
-    
+
     /*
     ** In every register the least significant bits starts with a GPIO number on
     ** a boundary of 32. Thus the pin offset must be calculated based on 32
-    ** pins boundary. Ex: 'pinNumber' of 1 corresponds to bit 0 in 
+    ** pins boundary. Ex: 'pinNumber' of 1 corresponds to bit 0 in
     ** 'register_name01'.
     */
- 
+
     pinOffset = (pinNumber - 1) % 32;
 
     dir = (HWREG(baseAdd + GPIO_DIR(regNumber)) & (1 << pinOffset));
@@ -146,10 +146,10 @@ unsigned int GPIODirModeGet(unsigned int baseAdd, unsigned int pinNumber)
  *
  * \param   baseAdd    The memory address of the GPIO instance being used.
  * \param   pinNumber  The serial number of the GPIO pin.
- *                     The 144 GPIO pins have serial numbers from 1 to 144. 
+ *                     The 144 GPIO pins have serial numbers from 1 to 144.
  *
- * \param   bitValue   This signifies whether to write a logic 0 or logic 1 
- *                     to the specified pin.This variable can take any of the 
+ * \param   bitValue   This signifies whether to write a logic 0 or logic 1
+ *                     to the specified pin.This variable can take any of the
  *                     following two values:
  *                     1> GPIO_PIN_LOW, which indicates to clear(logic 0) the bit.
  *                     2> GPIO_PIN_HIGH, which indicates to set(logic 1) the bit.
@@ -159,27 +159,27 @@ unsigned int GPIODirModeGet(unsigned int baseAdd, unsigned int pinNumber)
  * \note    The pre-requisite to write to any pin is that the pin has to
  *          be configured as an output pin.
  */
-void GPIOPinWrite(unsigned int baseAdd, unsigned int pinNumber, 
+void GPIOPinWrite(unsigned int baseAdd, unsigned int pinNumber,
                   unsigned int bitValue)
 {
     unsigned int regNumber = 0;
     unsigned int pinOffset = 0;
-    
+
     /*
     ** Each register contains settings for each pin of two banks. The 32 bits
     ** represent 16 pins each from the banks. Thus the register number must be
     ** calculated based on 32 pins boundary.
     */
- 
+
     regNumber = (pinNumber - 1)/32;
 
     /*
     ** In every register the least significant bits starts with a GPIO number on
     ** a boundary of 32. Thus the pin offset must be calculated based on 32
-    ** pins boundary. Ex: 'pinNumber' of 1 corresponds to bit 0 in 
+    ** pins boundary. Ex: 'pinNumber' of 1 corresponds to bit 0 in
     ** 'register_name01'.
     */
-   
+
     pinOffset = (pinNumber - 1) % 32;
 
     if(GPIO_PIN_LOW == bitValue)
@@ -195,17 +195,17 @@ void GPIOPinWrite(unsigned int baseAdd, unsigned int pinNumber,
 /**
  * \brief    This function reads the value(logic level) of an input or an
  *           output pin.
- * 
+ *
  * \param    baseAdd     The memory address of the GPIO instance being used.
  * \param    pinNumber   The serial number of the GPIO pin.
- *                       The 144 GPIO pins have serial numbers from 1 to 144. 
+ *                       The 144 GPIO pins have serial numbers from 1 to 144.
  *
  * \return   This returns the value present on the specified pin. This returns
  *           one of the following values:
  *           1> GPIO_PIN_LOW, if the value on the pin is logic 0.
  *           2> GPIO_PIN_HIGH, if the value on the pin is logic 1.
  *
- * \note     Using this function, we can read the values of both input and 
+ * \note     Using this function, we can read the values of both input and
  *           output pins.
  */
 int GPIOPinRead(unsigned int baseAdd, unsigned int pinNumber)
@@ -221,14 +221,14 @@ int GPIOPinRead(unsigned int baseAdd, unsigned int pinNumber)
     */
 
     regNumber = (pinNumber - 1)/32;
-   
+
     /*
     ** In every register the least significant bits starts with a GPIO number on
     ** a boundary of 32. Thus the pin offset must be calculated based on 32
-    ** pins boundary. Ex: 'pinNumber' of 1 corresponds to bit 0 in 
+    ** pins boundary. Ex: 'pinNumber' of 1 corresponds to bit 0 in
     ** 'register_name01'.
     */
-    
+
     pinOffset = (pinNumber - 1) % 32;
 
     val = HWREG(baseAdd + GPIO_IN_DATA(regNumber)) & (1 << pinOffset);
@@ -237,34 +237,34 @@ int GPIOPinRead(unsigned int baseAdd, unsigned int pinNumber)
 }
 
 /**
- * \brief   This function configures the trigger level type for which an 
+ * \brief   This function configures the trigger level type for which an
  *          interrupt is required to occur.
- * 
+ *
  * \param   baseAdd    The memory address of the GPIO instance being used.
  *
  * \param   pinNumber  The serial number of the GPIO pin.
- *                     The 144 GPIO pins have serial numbers from 1 to 144. 
+ *                     The 144 GPIO pins have serial numbers from 1 to 144.
  *
- * \param   intType    This specifies the trigger level type. This can take 
+ * \param   intType    This specifies the trigger level type. This can take
  *                     one of the following four values:
  *                     1> GPIO_INT_TYPE_NOEDGE, to not generate any interrupts.
- *                     2> GPIO_INT_TYPE_FALLEDGE, to generate an interrupt on 
- *                        the falling edge of a signal on that pin. 
- *                     3> GPIO_INT_TYPE_RISEDGE, to generate an interrupt on the 
+ *                     2> GPIO_INT_TYPE_FALLEDGE, to generate an interrupt on
+ *                        the falling edge of a signal on that pin.
+ *                     3> GPIO_INT_TYPE_RISEDGE, to generate an interrupt on the
  *                        rising edge of a signal on that pin.
  *                     4> GPIO_INT_TYPE_BOTHEDGE, to generate interrupts on both
  *                        rising and falling edges of a signal on that pin.
  *
  * \return   None.
  *
- * \note     Configuring the trigger level type for generating interrupts is not 
- *           enough for the GPIO module to generate interrupts. The user should 
+ * \note     Configuring the trigger level type for generating interrupts is not
+ *           enough for the GPIO module to generate interrupts. The user should
  *           also enable the interrupt generation capability for the bank to which
- *           the pin belongs to. Use the function GPIOBankIntEnable() to do the same.             
+ *           the pin belongs to. Use the function GPIOBankIntEnable() to do the same.
  */
- 
 
-void GPIOIntTypeSet(unsigned int baseAdd, unsigned int pinNumber, 
+
+void GPIOIntTypeSet(unsigned int baseAdd, unsigned int pinNumber,
                     unsigned int intType)
 {
     unsigned int regNumber = 0;
@@ -277,14 +277,14 @@ void GPIOIntTypeSet(unsigned int baseAdd, unsigned int pinNumber,
     */
 
     regNumber = (pinNumber - 1)/32;
-    
+
     /*
     ** In every register the least significant bits starts with a GPIO number on
     ** a boundary of 32. Thus the pin offset must be calculated based on 32
     ** pins boundary. Ex: 'pinNumber' of 1 corresponds to bit 0 in
     ** 'register_name01'.
     */
-    
+
     pinOffset = (pinNumber - 1) % 32;
 
     switch (intType)
@@ -296,7 +296,7 @@ void GPIOIntTypeSet(unsigned int baseAdd, unsigned int pinNumber,
             break;
 
         case GPIO_INT_TYPE_FALLEDGE:
-            /* Setting Falling edge and clearing Rising edge trigger levels.*/ 
+            /* Setting Falling edge and clearing Rising edge trigger levels.*/
             HWREG(baseAdd + GPIO_SET_FAL_TRIG(regNumber)) = (1 << pinOffset);
             HWREG(baseAdd + GPIO_CLR_RIS_TRIG(regNumber)) = (1 << pinOffset);
             break;
@@ -321,19 +321,19 @@ void GPIOIntTypeSet(unsigned int baseAdd, unsigned int pinNumber,
 /**
  * \brief   This function reads the trigger level type being set for interrupts
  *          to be generated.
- * 
+ *
  * \param   baseAdd    The memory address of the GPIO instance being used.
  *
  * \param   pinNumber  The serial number of the GPIO pin to be accessed.
- *                     The 144 GPIO pins have serial numbers from 1 to 144. 
+ *                     The 144 GPIO pins have serial numbers from 1 to 144.
  *
- * \return  This returns a value which indicates the type of trigger level 
+ * \return  This returns a value which indicates the type of trigger level
  *          type being set. One of the following values is returned.
- *          1> GPIO_INT_TYPE_NOEDGE, indicating no interrupts will be 
+ *          1> GPIO_INT_TYPE_NOEDGE, indicating no interrupts will be
  *             generated over the corresponding pin.
- *          2> GPIO_INT_TYPE_FALLEDGE, indicating a falling edge on the 
+ *          2> GPIO_INT_TYPE_FALLEDGE, indicating a falling edge on the
  *             corresponding pin signifies an interrupt generation.
- *          3> GPIO_INT_TYPE_RISEDGE, indicating a rising edge on the 
+ *          3> GPIO_INT_TYPE_RISEDGE, indicating a rising edge on the
  *             corresponding pin signifies an interrupt generation.
  *          4> GPIO_INT_TYPE_BOTHEDGE, indicating both edges on the
  *             corresponding pin signifies an interrupt each being generated.
@@ -351,7 +351,7 @@ unsigned int GPIOIntTypeGet(unsigned int baseAdd, unsigned int pinNumber)
     ** calculated based on 32 pins boundary.
     */
     regNumber = (pinNumber - 1)/32;
-   
+
     /*
     ** In every register the least significant bits starts with a GPIO number on
     ** a boundary of 32. Thus the pin offset must be calculated based on 32
@@ -370,29 +370,29 @@ unsigned int GPIOIntTypeGet(unsigned int baseAdd, unsigned int pinNumber)
     {
         intType |= GPIO_INT_TYPE_RISEDGE;
     }
-  
-    return intType;    
+
+    return intType;
 }
 
 /**
  * \brief    This function determines the status of interrupt on a specified
- *           pin.  
- * 
+ *           pin.
+ *
  * \param    baseAdd    The memory address of the GPIO instance being used.
 
  * \param    pinNumber  The serial number of the GPIO pin to be accessed.
- *                      The 144 GPIO pins have serial numbers from 1 to 144. 
+ *                      The 144 GPIO pins have serial numbers from 1 to 144.
 
  * \return   This returns a value which expresses the status of an interrupt
  *           raised over the specified pin.
  *           1> GPIO_INT_NOPEND, if no interrupts are left to be serviced.
  *           2> GPIO_INT_PEND, if the interrupt raised over that pin is yet
  *              to be cleared and serviced.
- *              
- * \note     If an interrupt over a pin is found to be pending, then the 
+ *
+ * \note     If an interrupt over a pin is found to be pending, then the
  *           application can call GPIOPinIntClear() to clear the interrupt
- *           status.  
- *           
+ *           status.
+ *
  *
  */
 unsigned int GPIOPinIntStatus(unsigned int baseAdd, unsigned int pinNumber)
@@ -407,7 +407,7 @@ unsigned int GPIOPinIntStatus(unsigned int baseAdd, unsigned int pinNumber)
     ** calculated based on 32 pins boundary.
     */
     regNumber = (pinNumber - 1)/32;
-    
+
     /*
     ** In every register the least significant bits starts with a GPIO number on
     ** a boundary of 32. Thus the pin offset must be calculated based on 32
@@ -421,17 +421,17 @@ unsigned int GPIOPinIntStatus(unsigned int baseAdd, unsigned int pinNumber)
     {
         intStatus = GPIO_INT_PEND;
     }
-        
+
     return intStatus;
 }
 
 /**
- * \brief     This function clears the interrupt status of the pin being 
+ * \brief     This function clears the interrupt status of the pin being
  *            accessed.
  *
  * \param     baseAdd    The memory address of the GPIO instance being used.
  * \param     pinNumber  The serial number of the GPIO pin to be accessed.
- *                       The 144 GPIO pins have serial numbers from 1 to 144. 
+ *                       The 144 GPIO pins have serial numbers from 1 to 144.
  * \return    None.
  *
  */
@@ -447,7 +447,7 @@ void GPIOPinIntClear(unsigned int baseAdd, unsigned int pinNumber)
     ** calculated based on 32 pins boundary.
     */
     regNumber = (pinNumber - 1)/32;
-    
+
     /*
     ** In every register the least significant bits starts with a GPIO number on
     ** a boundary of 32. Thus the pin offset must be calculated based on 32
@@ -465,10 +465,10 @@ void GPIOPinIntClear(unsigned int baseAdd, unsigned int pinNumber)
  *          bank of GPIO pins specified.
  *
  * \param   baseAdd     The memory address of the GPIO instance being used.
- * \param   bankNumber  This is the bank for whose pins interrupt generation 
+ * \param   bankNumber  This is the bank for whose pins interrupt generation
  *                      capabiility needs to be enabled.
  *                      bankNumber is 0 for bank 0, 1 for bank 1 and so on.
- * \return  None. 
+ * \return  None.
  *
  */
 
@@ -476,7 +476,7 @@ void GPIOPinIntClear(unsigned int baseAdd, unsigned int pinNumber)
 void GPIOBankIntEnable(unsigned int baseAdd, unsigned int bankNumber)
 {
     HWREG(baseAdd + GPIO_BINTEN) |= (1 << bankNumber);
-} 
+}
 
 /**
  * \brief   This function disables the interrupt generation capability for the
@@ -503,21 +503,21 @@ void GPIOBankIntDisable(unsigned int baseAdd, unsigned int bankNumber)
  *          the specified bits.
  *
  * \param   baseAdd     The memory address of the GPIO instance being used.
- * \param   bankNumber  Numerical value of the bank whose pins are to be 
+ * \param   bankNumber  Numerical value of the bank whose pins are to be
  *                      modified.
  *
  * \param   setPins     The bit-mask of the pins whose values have to be set.
  *                      This could be the bitwise OR of the following macros:
  *                      -> GPIO_BANK_PIN_n where n >= 0 and n <= 15.
  *
- * \param   clrPins     The bit-mask of the pins whose values have to be 
+ * \param   clrPins     The bit-mask of the pins whose values have to be
  *                      cleared. This could be the bitwise OR of the following
  *                      macros:
  *                      -> GPIO_BANK_PIN_n where n >= 0 and n <= 15.
  *
  * \return  None.
  *
- * \note   The pre-requisite to write to any pins is that the pins have to be 
+ * \note   The pre-requisite to write to any pins is that the pins have to be
  *         configured as output pins.
  */
 
@@ -541,4 +541,4 @@ void GPIOBankPinsWrite(unsigned int baseAdd, unsigned int bankNumber,
 
 }
 
-/*****************************END OF FILE*************************************/ 
+/*****************************END OF FILE*************************************/
diff --git a/lib/tiam1808/drivers/gpio_v2.c b/lib/tiam1808/drivers/gpio_v2.c
index 5c57691ec..508a79b5c 100644
--- a/lib/tiam1808/drivers/gpio_v2.c
+++ b/lib/tiam1808/drivers/gpio_v2.c
@@ -44,7 +44,7 @@
 #include "hw_types.h"
 
 /*****************************************************************************
-**                       FUNCTION DEFINITIONS                                
+**                       FUNCTION DEFINITIONS
 *****************************************************************************/
 
 /**
@@ -63,7 +63,7 @@ void GPIOModuleReset(unsigned int baseAdd)
     ** Doing so would reset the GPIO module.
     */
     HWREG(baseAdd + GPIO_SYSCONFIG) |= (GPIO_SYSCONFIG_SOFTRESET);
-    
+
     /* Waiting until the GPIO Module is reset.*/
     while(!(HWREG(baseAdd + GPIO_SYSSTATUS) & GPIO_SYSSTATUS_RESETDONE));
 }
@@ -136,13 +136,13 @@ void GPIODirModeSet(unsigned int baseAdd,
 
 /**
  * \brief   This API determines the direction of a specified GPIO pin.
- * 
+ *
  * \param   baseAdd      The memory address of the GPIO instance being used
  * \param   pinNumber    The number of the pin in the GPIO instance
  *
  * 'pinNumber' can take one of the following values:
  * (0 <= pinNumber <= 31)\n
- * 
+ *
  * \return  The direction of the specified pin. This returns one of the
  *          following two values:
  *          - GPIO_DIR_INPUT - signifying that the pin is an input pin\n
@@ -270,7 +270,7 @@ unsigned int GPIOMultiplePinsRead(unsigned int baseAdd,
  * 'intLine' can take one of the following two values:
  * - GPIO_INT_LINE_1 - interrupt request be propagated over interrupt line 1\n
  * - GPIO_INT_LINE_2 - interrupt request be propagated over interrupt line 2\n
- * 
+ *
  * 'pinNumber' can take one of the following values:
  * (0 <= pinNumber <= 31)\n
  *
@@ -285,7 +285,7 @@ void GPIOPinIntEnable(unsigned int baseAdd,
     {
         HWREG(baseAdd + GPIO_IRQSTATUS_SET(0)) = (1 << pinNumber);
     }
-    else     
+    else
     {
         HWREG(baseAdd + GPIO_IRQSTATUS_SET(1)) = (1 << pinNumber);
     }
@@ -321,7 +321,7 @@ void GPIOPinIntDisable(unsigned int baseAdd,
     {
         HWREG(baseAdd + GPIO_IRQSTATUS_CLR(0)) = (1 << pinNumber);
     }
-    else 
+    else
     {
         HWREG(baseAdd + GPIO_IRQSTATUS_CLR(1)) = (1 << pinNumber);
     }
@@ -362,7 +362,7 @@ void GPIOPinIntDisable(unsigned int baseAdd,
  * \return  None
  *
  * \note  A typical use case of this API is explained below:
- * 
+ *
  *        If it is initially required that interrupt should be generated on
  *        LOW level only, then this API can be called with 'GPIO_INT_TYPE_LEVEL_0'
  *        as the parameter. At a later point of time, if logic HIGH level only
@@ -402,21 +402,21 @@ void GPIOIntTypeSet(unsigned int baseAdd,
 
             /* Enabling logic HIGH level detect interrupt generation. */
             HWREG(baseAdd + GPIO_LEVELDETECT(1)) |= (1 << pinNumber);
-        
+
         break;
 
         case GPIO_INT_TYPE_BOTH_LEVEL:
-            
+
             /* Enabling logic LOW level detect interrupt geenration. */
             HWREG(baseAdd + GPIO_LEVELDETECT(0)) |= (1 << pinNumber);
 
             /* Enabling logic HIGH level detect interrupt generation. */
             HWREG(baseAdd + GPIO_LEVELDETECT(1)) |= (1 << pinNumber);
-            
+
         break;
 
         case GPIO_INT_TYPE_NO_EDGE:
-            
+
             /* Disabling rising edge detect interrupt generation. */
             HWREG(baseAdd + GPIO_RISINGDETECT) &= ~(1 << pinNumber);
 
@@ -485,14 +485,14 @@ unsigned int GPIOIntTypeGet(unsigned int baseAdd,
 {
     unsigned int intEvent = (GPIO_INT_TYPE_NO_LEVEL | GPIO_INT_TYPE_NO_EDGE);
 
-    /* Checking if logic LOW level trigger interrupt is enabled. */ 
+    /* Checking if logic LOW level trigger interrupt is enabled. */
     if(HWREG(baseAdd + GPIO_LEVELDETECT(0)) & (1 << pinNumber))
     {
         intEvent &= ~(GPIO_INT_TYPE_NO_LEVEL);
         intEvent |= GPIO_INT_TYPE_LEVEL_0;
     }
 
-    /* Checking if logic HIGH level trigger interrupt is enabled. */ 
+    /* Checking if logic HIGH level trigger interrupt is enabled. */
     if(HWREG(baseAdd + GPIO_LEVELDETECT(1)) & (1 << pinNumber))
     {
         intEvent &= ~(GPIO_INT_TYPE_NO_LEVEL);
@@ -524,7 +524,7 @@ unsigned int GPIOIntTypeGet(unsigned int baseAdd,
  *                    enabled interrupt status register has to be accessed.
  *                    The status of the specified pin is returned in this API.
  * \param  pinNumber  The number of the pin in the GPIO instance
- * 
+ *
  * 'intLine' can take one of the following two values:
  * - GPIO_INT_LINE_1 - to read the enabled interrupt status register
  *   corresponding to interrupt line 1\n
@@ -549,7 +549,7 @@ unsigned int GPIOPinIntStatus(unsigned int baseAdd,
     {
         intStatus = (HWREG(baseAdd + GPIO_IRQSTATUS(0)) & (1 << pinNumber));
     }
-    else 
+    else
     {
         intStatus = (HWREG(baseAdd + GPIO_IRQSTATUS(1)) & (1 << pinNumber));
     }
@@ -573,7 +573,7 @@ unsigned int GPIOPinIntStatus(unsigned int baseAdd,
  *   corresponding to interrupt line 1\n
  * - GPIO_INT_LINE_2 - to access the enabled interrupt status register
  *   corresponding to interrupt line 2\n
- * 
+ *
  * 'pinNumber' can take one of the following values:
  * (0 <= pinNumber <= 31)\n
  *
@@ -625,7 +625,7 @@ unsigned int GPIORawIntStatus(unsigned int baseAdd,
     {
         intStatus = HWREG(baseAdd + GPIO_IRQSTATUS_RAW(0)) & readMask;
     }
-    else  
+    else
     {
         intStatus = HWREG(baseAdd + GPIO_IRQSTATUS_RAW(1)) & readMask;
     }
@@ -634,8 +634,8 @@ unsigned int GPIORawIntStatus(unsigned int baseAdd,
 }
 
 /**
- * \brief  This API manually triggers an interrupt request due to a specified 
- *         GPIO pin. 
+ * \brief  This API manually triggers an interrupt request due to a specified
+ *         GPIO pin.
  *
  * \param  baseAdd    The memory address of the GPIO instance being used
  * \param  intLine    This specifies the interrupt line over which the
@@ -754,18 +754,18 @@ void GPIOGatingRatioConfigure(unsigned int baseAdd, unsigned int configFlag)
     HWREG(baseAdd + GPIO_CTRL) &= ~(GPIO_CTRL_GATINGRATIO);
 
     /* Programming the GATINGRATIO field in GPIO_CTRL register. */
-    HWREG(baseAdd + GPIO_CTRL) |= (configFlag & GPIO_CTRL_GATINGRATIO);    
+    HWREG(baseAdd + GPIO_CTRL) |= (configFlag & GPIO_CTRL_GATINGRATIO);
 }
 
 /**
  * \brief  This API enables/disables debouncing feature for a specified input
  *         GPIO pin.
- * 
+ *
  * \param  baseAdd      The memory address of the GPIO instance being used
  * \param  pinNumber    The number of the pin in the GPIO instance
  * \param  controlFlag  This specifies whether to enable/disable Debouncing
  *                      feature for the specified input pin
- * 
+ *
  * 'pinNumber' can take one of the following values:
  * (0 <= pinNumber <= 31)\n
  *
@@ -782,7 +782,7 @@ void GPIODebounceFuncControl(unsigned int baseAdd,
                              unsigned int pinNumber,
                              unsigned int controlFlag)
 {
-    
+
     /* Clearing the DEBOUNCEENABLE[n] bit in GPIO_DEBOUNCEENABLE register. */
     HWREG(baseAdd + GPIO_DEBOUNCENABLE) &= ~(1 << pinNumber);
 
@@ -810,7 +810,7 @@ void GPIODebounceTimeConfig(unsigned int baseAdd,
                             unsigned int debounceTime)
 {
     /* Programming the DEBOUNCETIME field in GPIO_DEBOUNCINGTIME register. */
-    HWREG(baseAdd + GPIO_DEBOUNCINGTIME) = (debounceTime & 
+    HWREG(baseAdd + GPIO_DEBOUNCINGTIME) = (debounceTime &
                                             GPIO_DEBOUNCINGTIME_DEBOUNCETIME);
 }
 
@@ -820,7 +820,7 @@ void GPIODebounceTimeConfig(unsigned int baseAdd,
  *
  * \param  baseAdd    The memory address of the GPIO instance being used
  * \param  intLine    This specifies the interrupt line for which the EOI
- *                    signal has to be generated 
+ *                    signal has to be generated
  *
  * 'intLine' can take one of the following values:
  * - GPIO_INT_LINE_1 - for EOI generation for interrupt line 1\n
diff --git a/lib/tiam1808/drivers/gpmc.c b/lib/tiam1808/drivers/gpmc.c
index c6c093c66..cd4f29aa7 100644
--- a/lib/tiam1808/drivers/gpmc.c
+++ b/lib/tiam1808/drivers/gpmc.c
@@ -51,7 +51,7 @@
 * \brief   This function reads the IP revision code of GPMC.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
+*
 * \return  ipRev          IP revision code of GPMC.\n
 */
 unsigned int  GPMCRevisionGet(unsigned int baseAddr)
@@ -67,12 +67,12 @@ unsigned int  GPMCRevisionGet(unsigned int baseAddr)
 * \brief   This function sets the idle mode for gpmc.\n
 *
 * \param   baseaddr       Memory address of gpmc.\n
-* 
+*
 * \param   mode           Idle mode.\n
 *                         This can take one of the following values :\n
 *                         GPMC_IDLEMODE_FORCEIDLE -- for force-idle. \n
 *                         GPMC_IDLEMODE_NOIDLE    -- for no-idle. \n
-*                         GPMC_IDLEMODE_SMARTIDLE -- for smart-idle.\n 
+*                         GPMC_IDLEMODE_SMARTIDLE -- for smart-idle.\n
 *
 * \return  none.\n
 */
@@ -88,12 +88,12 @@ void  GPMCIdleModeSelect(unsigned int baseAddr, unsigned int mode)
 * \brief   This function configs the internal OCP clock gating strategy.\n
 *
 * \param   baseaddr       Memory address of gpmc.\n
-* 
+*
 * \param   configVal      Config value.\n
 *                         This can take one of the following values :\n
-*                         GPMC_AUTOIDLE_FREERUN -- When Interface clock is 
+*                         GPMC_AUTOIDLE_FREERUN -- When Interface clock is
 *                                                  free-running. \n
-*                         GPMC_AUTOIDLE_AUTORUN -- When Automatic Interface clk 
+*                         GPMC_AUTOIDLE_AUTORUN -- When Automatic Interface clk
 *                                                  gating strategy is applied.\n
 *
 * \return  none.\n
@@ -110,7 +110,7 @@ void  GPMCAutoIdleConfig(unsigned int baseAddr, unsigned int configVal)
 * \brief   This function resets the GPMC.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
+*
 * \return  None.\n
 */
 
@@ -125,7 +125,7 @@ void  GPMCModuleSoftReset(unsigned int baseAddr)
 * \brief   This function gets the software resets status of GPMC.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
+*
 * \return  status         Reset status : \n
 *                            0 : Module reset is on-going.\n
 *                            1 : Module reset is completed.\n
@@ -144,10 +144,10 @@ unsigned int  GPMCModuleResetStatusGet(unsigned int baseAddr)
 * \brief   This function gets Interrupt status of interrupt passed.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
+*
 * \param   flag           Flag for which interrupt status has to get.\n
 *                         This can take one of the following values :\n
-*                         GPMC_FIFOEVENT_STATUS         : For FIFOEvent 
+*                         GPMC_FIFOEVENT_STATUS         : For FIFOEvent
 *                                                         interrupt status.\n
 *                         GPMC_TERMINALCOUNT_STATUS     : For TerminalCountEvent
 *                                                         interrupt status.\n
@@ -155,18 +155,18 @@ unsigned int  GPMCModuleResetStatusGet(unsigned int baseAddr)
 *                                                         Detection interrupt
 *                                                         status.\n
 *                         GPMC_WAIT1EDGEDETECTION_STATUS: For Wait1 Edge
-*                                                         Detection interrupt 
+*                                                         Detection interrupt
 *                                                         status.\n
 *
-* 
+*
 * \return  intSts         Interrupt Status. Return value meaning depends on the
 *                         interrupt flag passed. \n
 *                         if flag is GPMC_FIFOEVENT_STATUS, then \n
-*                            0 : Less than FIFOTHRESHOLD bytes are available in 
+*                            0 : Less than FIFOTHRESHOLD bytes are available in
 *                                prefetch/read mode.\n
 *                                Less than FIFOTHRESHOLD byte free spaces are
 *                                available in write-posting/write mode. \n
-*                            1 : Atleast FIFOTHRESHOLD bytes are available in 
+*                            1 : Atleast FIFOTHRESHOLD bytes are available in
 *                                prefetch/read mode.\n
 *                                Atlease FIFOTHRESHOLD byte free places are
 *                                available in write-posting/write mode.\n
@@ -174,16 +174,16 @@ unsigned int  GPMCModuleResetStatusGet(unsigned int baseAddr)
 *                            0 : CountValue is greater than 0.\n
 *                            1 : CountValue is equal to 0.\n
 *                         if flag is GPMC_WAIT0EDGEDETECTION_STATUS, then \n
-*                            0 : A transition on WAIT0 input pin has not been 
+*                            0 : A transition on WAIT0 input pin has not been
 *                                detected.\n
-*                            1 : A transition on WAIT0 input pin has been 
+*                            1 : A transition on WAIT0 input pin has been
 *                                detected.\n
 *                         if flag is GPMC_WAIT1EDGEDETECTION_STATUS, then \n
-*                            0 : A transition on WAIT1 input pin has not been 
+*                            0 : A transition on WAIT1 input pin has not been
 *                                detected.\n
-*                            1 : A transition on WAIT1 input pin has been 
+*                            1 : A transition on WAIT1 input pin has been
 *                                detected.\n
-*                
+*
 */
 unsigned int  GPMCIntStatusGet(unsigned int baseAddr, unsigned int flag)
 {
@@ -223,10 +223,10 @@ unsigned int  GPMCIntStatusGet(unsigned int baseAddr, unsigned int flag)
 * \brief   This function clears/resets the interrupt status.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
+*
 * \param   flag           Flag for which interrupt status has to reset.\n
 *                         This can take one of the following values :\n
-*                         GPMC_FIFOEVENT_STATUS         : For FIFOEvent 
+*                         GPMC_FIFOEVENT_STATUS         : For FIFOEvent
 *                                                         interrupt status.\n
 *                         GPMC_TERMINALCOUNT_STATUS     : For TerminalCountEvent
 *                                                         interrupt status.\n
@@ -234,10 +234,10 @@ unsigned int  GPMCIntStatusGet(unsigned int baseAddr, unsigned int flag)
 *                                                         Detection interrupt
 *                                                         status.\n
 *                         GPMC_WAIT1EDGEDETECTION_STATUS: For Wait1 Edge
-*                                                         Detection interrupt 
+*                                                         Detection interrupt
 *                                                         status.\n
 *
-* \return  None. 
+* \return  None.
 *
 */
 void  GPMCIntStatusClear(unsigned int baseAddr, unsigned int flag)
@@ -272,7 +272,7 @@ void  GPMCIntStatusClear(unsigned int baseAddr, unsigned int flag)
 * \brief   This function enables the interrupts.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
+*
 * \param   flag           Flag for which interrupt has to enable.
 *                         This can take one of the following values :\n
 *                         GPMC_FIFOEVENT_INT          : For FIFOEvent interrupt.\n
@@ -313,7 +313,7 @@ void  GPMCIntEnable(unsigned int baseAddr, unsigned int flag)
 * \brief   This function disable/masks the interrupts.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
+*
 * \param   flag           Flag for which interrupt has to mask.\n
 *                         This can take one of the following values :\n
 *                         GPMC_FIFOEVENT_INT          : For FIFOEvent interrupt.\n
@@ -324,7 +324,7 @@ void  GPMCIntEnable(unsigned int baseAddr, unsigned int flag)
 *                         GPMC_WAIT1EDGEDETECTION_INT : For Wait1 Edge
 *                                                       Detection interrupt. \n
 *
-* \return  None.\n 
+* \return  None.\n
 *
 */
 void  GPMCIntDisable(unsigned int baseAddr, unsigned int flag)
@@ -351,11 +351,11 @@ void  GPMCIntDisable(unsigned int baseAddr, unsigned int flag)
 }
 
 /**
-* \brief   This function sets the start timeout value(TIMEOUTSTARTVALUE) 
+* \brief   This function sets the start timeout value(TIMEOUTSTARTVALUE)
 *          of the timeout counter.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
+*
 * \param   timoutVal      Timeout start Value in GPMC_FCLK cycles.\n
 *
 * \return  None. \n
@@ -374,13 +374,13 @@ void  GPMCTimeOutStartValSet(unsigned int baseAddr, unsigned int timeoutVal)
 * \brief   This function configures the timeout feature.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
-* \param   flag           Flag to indicate whether to enable or disable the 
+*
+* \param   flag           Flag to indicate whether to enable or disable the
 *                         feature.\n
 *                         This can take one of the following values :\n
 *                         GPMC_TIMEOUTFEATURE_ENABLE  - To enable the timout
 *                                                       feature.\n
-*                         GPMC_TIMEOUTFEATURE_DISABLE - To disable the timout 
+*                         GPMC_TIMEOUTFEATURE_DISABLE - To disable the timout
 *                                                       feature.\n
 * \return  None. \n
 *
@@ -400,11 +400,11 @@ void  GPMCTimeOutFeatureConfig(unsigned int baseAddr, unsigned int flag)
 }
 
 /**
-* \brief   This function returns the address of illegal access when an error 
+* \brief   This function returns the address of illegal access when an error
 *          occures.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
+*
 * \return  illegalAddrVal Address of illegal access. \n
 *
 */
@@ -421,10 +421,10 @@ unsigned int  GPMCErrAddrGet(unsigned int baseAddr)
 * \brief   This function returns the status of error validity.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
+*
 * \return  ErrValstatus   Error validity status. \n
 *                         0 : Error fields are no longer valid.\n
-*                         1 : Error detected and logged in the 
+*                         1 : Error detected and logged in the
 *                             other error fields.\n
 *
 */
@@ -438,11 +438,11 @@ unsigned int  GPMCErrValStatusGet(unsigned int baseAddr)
 }
 
 /**
-* \brief   This function returns the System Command of the transaction 
+* \brief   This function returns the System Command of the transaction
 *          that caused the error.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
+*
 * \return  errCmd         System Command that caused the error. \n
 *
 */
@@ -457,7 +457,7 @@ unsigned int  GPMCErrSysCmdGet(unsigned int baseAddr)
 }
 
 /**
-* \brief   This function returns whether passed error is occured or not.\n 
+* \brief   This function returns whether passed error is occured or not.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -466,7 +466,7 @@ unsigned int  GPMCErrSysCmdGet(unsigned int baseAddr)
 *                         GPMC_TIMEOUT_ERROR     -- For timeout error.\n
 *                         GPMC_NOTSUPPMCMD_ERROR -- For non-supported cmd error.\n
 *                         GPMC_NOTSUPPADD_ERROR  -- For non-supported add error.\n
-* 
+*
 * \return  ErrStatus \n
 *
 *                         1 : If passed argument type of error occured.\n
@@ -501,7 +501,7 @@ unsigned int  GPMCErrStatusGet(unsigned int baseAddr, unsigned int err)
 }
 
 /**
-* \brief   This function sets/selects the waitpin polarity.\n 
+* \brief   This function sets/selects the waitpin polarity.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -509,7 +509,7 @@ unsigned int  GPMCErrStatusGet(unsigned int baseAddr, unsigned int err)
 *                         This can take one of the following values :\n
 *                         GPMC_WAIT_PIN0   -- For WAITPIN0.\n
 *                         GPMC_WAIT_PIN1   -- For WAITPIN1.\n
-* 
+*
 * \param  polarity        Wait pin polarity.\n
 *                         This can take one of the following values :\n
 *                         GPMC_WAIT_PIN_POLARITY_LOW  -- for active low.\n
@@ -546,10 +546,10 @@ void  GPMCWaitPinPolaritySelect(unsigned int baseAddr, unsigned int pin,
 }
 
 /**
-* \brief   This function controls the write protect output pin level.\n 
+* \brief   This function controls the write protect output pin level.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
+*
 * \param   pinLevel       Write Protect pin level.\n
 *                         This can take one of the following values :\n
 *                         GPMC_WP_PIN_LEVEL_LOW  -- for level low.\n
@@ -571,16 +571,16 @@ void  GPMCWriteProtectPinLevelCtrl(unsigned int baseAddr, unsigned int pinLevel)
 }
 
 /**
-* \brief   This function configs the limited address device support.\n 
+* \brief   This function configs the limited address device support.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
-* \param   flag           Flag to indicate whether to enable/disable the 
+*
+* \param   flag           Flag to indicate whether to enable/disable the
 *                         Limited Address device support.\n
 *                         This can take one of the following values :\n
-*                         GPMC_LIMITEDADDRESS_SUPPORT_ENABLE  -- To enable 
+*                         GPMC_LIMITEDADDRESS_SUPPORT_ENABLE  -- To enable
 *                                                                the support.\n
-*                         GPMC_LIMITEDADDRESS_SUPPORT_DISABLE -- To disable 
+*                         GPMC_LIMITEDADDRESS_SUPPORT_DISABLE -- To disable
 *                                                                the support.\n
 *
 * \return  None.\n
@@ -599,17 +599,17 @@ void  GPMCLimitedAddrDevSupportConfig(unsigned int baseAddr, unsigned int flag)
 }
 
 /**
-* \brief   This function configs the Force Posted Write feature to NAND 
-*          Cmd/Add/Data location.\n 
+* \brief   This function configs the Force Posted Write feature to NAND
+*          Cmd/Add/Data location.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
-* 
-* \param   flag           Flag to indicate whether to enable/disable the 
+*
+* \param   flag           Flag to indicate whether to enable/disable the
 *                         Force Posted Write feature.\n
 *                         This can take one of the following values :\n
-*                         GPMC_FORCEPOSTEDWRITE_ENABLE  -- To enable the 
+*                         GPMC_FORCEPOSTEDWRITE_ENABLE  -- To enable the
 *                                                          feature.\n
-*                         GPMC_FORCEPOSTEDWRITE_DISABLE -- To disable 
+*                         GPMC_FORCEPOSTEDWRITE_DISABLE -- To disable
 *                                                          the feature.\n
 *
 * \return  None.\n
@@ -629,7 +629,7 @@ void  GPMCNANDForcePostedWriteFeatureConfig(unsigned int baseAddr,
 }
 
 /**
-* \brief   This function gets the waitpin status.\n 
+* \brief   This function gets the waitpin status.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -664,7 +664,7 @@ unsigned int  GPMCWaitPinStatusGet(unsigned int baseAddr, unsigned int pin)
 }
 
 /**
-* \brief   This function gets the empty write buffer status.\n 
+* \brief   This function gets the empty write buffer status.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -684,7 +684,7 @@ unsigned int  GPMCEmptyWriteBuffStatusGet(unsigned int baseAddr)
 }
 
 /**
-* \brief   This function selects the FCLK DIVIDER for the chip select passed.\n 
+* \brief   This function selects the FCLK DIVIDER for the chip select passed.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -718,8 +718,8 @@ void  GPMCFclkDividerSelect(unsigned int baseAddr, unsigned int csNum,
 }
 
 /**
-* \brief   This function selects the signals timing latencies scalar factor 
-*          for the chip select.\n 
+* \brief   This function selects the signals timing latencies scalar factor
+*          for the chip select.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -752,7 +752,7 @@ void  GPMCTimeParaGranularitySelect(unsigned int baseAddr, unsigned int csNum,
 
 /**
 * \brief   This function selects the Address and data multiplexed protocol
-*          for the device connected to csNum.\n 
+*          for the device connected to csNum.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -787,8 +787,8 @@ void  GPMCAddrDataMuxProtocolSelect(unsigned int baseAddr, unsigned int csNum,
 }
 
 /**
-* \brief   This function selects the device type for the device connected to 
-*          csNum.\n 
+* \brief   This function selects the device type for the device connected to
+*          csNum.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -822,8 +822,8 @@ void  GPMCDevTypeSelect(unsigned int baseAddr, unsigned int csNum,
 }
 
 /**
-* \brief   This function selects the device size for the device connected to 
-*          csNum.\n 
+* \brief   This function selects the device size for the device connected to
+*          csNum.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -855,8 +855,8 @@ void  GPMCDevSizeSelect(unsigned int baseAddr, unsigned int csNum,
 }
 
 /**
-* \brief   This function selects the WAIT PIN for the device connected to 
-*          csNum.\n 
+* \brief   This function selects the WAIT PIN for the device connected to
+*          csNum.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -889,7 +889,7 @@ void  GPMCWaitPinSelect(unsigned int baseAddr, unsigned int csNum,
 
 /**
 * \brief   This function configs/selects the wait monitoring time for the device
-*          connected to csNum.\n 
+*          connected to csNum.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -908,10 +908,10 @@ void  GPMCWaitPinSelect(unsigned int baseAddr, unsigned int csNum,
 *                         This can take one of the following values :\n
 *                         GPMC_WAITMONITORINGTIME_WITH_VALIDDATA  -- For wait
 *                                               pin monitoring with valid data.\n
-*                         GPMC_WAITMONITORINGTIME_ONECLKB4_VALIDDATA  -- For 
+*                         GPMC_WAITMONITORINGTIME_ONECLKB4_VALIDDATA  -- For
 *                                               wait pin monitoring one GPMC_CLK
 *                                               before valid data. \n
-*                         GPMC_WAITMONITORINGTIME_TWOCLKB4_VALIDDATA  -- For 
+*                         GPMC_WAITMONITORINGTIME_TWOCLKB4_VALIDDATA  -- For
 *                                               wait pin monitoring two GPMC_CLK
 *                                               before valid data. \n
 * \return  None.\n
@@ -982,7 +982,7 @@ void  GPMCWaitPinMonitoringConfig(unsigned int baseAddr, unsigned int csNum,
 }
 
 /**
-* \brief   This function configs the output GPMC_CLK activation time.\n 
+* \brief   This function configs the output GPMC_CLK activation time.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -1023,7 +1023,7 @@ void  GPMCClkActivationTimeConfig(unsigned int baseAddr, unsigned int csNum,
 }
 
 /**
-* \brief   This function sets the device page length.\n 
+* \brief   This function sets the device page length.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -1040,9 +1040,9 @@ void  GPMCClkActivationTimeConfig(unsigned int baseAddr, unsigned int csNum,
 *
 * \param   pageLen        Device Page Length.\n
 *                         This can take one of the following values :\n
-*                         GPMC_DEV_PAGELENGTH_FOUR    -- For 4 words page 
+*                         GPMC_DEV_PAGELENGTH_FOUR    -- For 4 words page
 *                                                        length.\n
-*                         GPMC_DEV_PAGELENGTH_EIGHT   -- For 8 words page 
+*                         GPMC_DEV_PAGELENGTH_EIGHT   -- For 8 words page
 *                                                        length.\n
 *                         GPMC_DEV_PAGELENGTH_SIXTEEN -- For 16 words page
 *                                                        length. \n
@@ -1060,7 +1060,7 @@ void  GPMCDevPageLenSet(unsigned int baseAddr, unsigned int csNum,
 }
 
 /**
-* \brief   This function selects the write type.\n 
+* \brief   This function selects the write type.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -1093,7 +1093,7 @@ void  GPMCWriteTypeSelect(unsigned int baseAddr, unsigned int csNum,
 }
 
 /**
-* \brief   This function selects the read type.\n 
+* \brief   This function selects the read type.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -1126,7 +1126,7 @@ void  GPMCReadTypeSelect(unsigned int baseAddr, unsigned int csNum,
 }
 
 /**
-* \brief   This function configs the access type for read and write.\n 
+* \brief   This function configs the access type for read and write.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -1176,7 +1176,7 @@ void  GPMCAccessTypeSelect(unsigned int baseAddr, unsigned int csNum,
 }
 
 /**
-* \brief   This function configs the wrapping burst capability.\n 
+* \brief   This function configs the wrapping burst capability.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -1191,7 +1191,7 @@ void  GPMCAccessTypeSelect(unsigned int baseAddr, unsigned int csNum,
 *                         GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
 *                         GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
 *
-* \param   flag           Flag to indicate whether to enable/disable 
+* \param   flag           Flag to indicate whether to enable/disable
 *                         Synchronous wrapping burst capability.\n
 *                         This can take one of the following values :\n
 *                         GPMC_WRAPBURST_ENABLE   -- To enable the wrap burst
@@ -1228,7 +1228,7 @@ void  GPMCSyncWrapBurstConfig(unsigned int baseAddr, unsigned int csNum,
 *                         GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
 *
 * \param   conf           Configuration value for chip select timing parameters
-*                         Use the GPMC_CS_TIMING_CONFIG macro to get the value 
+*                         Use the GPMC_CS_TIMING_CONFIG macro to get the value
 *                         of conf. \n
 *
 * \return  None.\n
@@ -1241,7 +1241,7 @@ void  GPMCCSTimingConfig(unsigned int baseAddr, unsigned int csNum,
 }
 
 /**
-* \brief   This function configs the timing parameters for ADV# signal.\n 
+* \brief   This function configs the timing parameters for ADV# signal.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -1256,8 +1256,8 @@ void  GPMCCSTimingConfig(unsigned int baseAddr, unsigned int csNum,
 *                         GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
 *                         GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
 *
-* \param   conf           Configuration value for ADV# signal timing parameters 
-*                         Use the GPMC_ADV_TIMING_CONFIG macro to get the value 
+* \param   conf           Configuration value for ADV# signal timing parameters
+*                         Use the GPMC_ADV_TIMING_CONFIG macro to get the value
 *                         of conf. \n
 *
 * \return  None.\n
@@ -1299,8 +1299,8 @@ void  GPMCWEAndOETimingConfig(unsigned int baseAddr, unsigned int csNum,
 }
 
 /**
-* \brief   This function configs the RdAccessTime and CycleTime timing 
-*          parameters.\n 
+* \brief   This function configs the RdAccessTime and CycleTime timing
+*          parameters.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -1316,7 +1316,7 @@ void  GPMCWEAndOETimingConfig(unsigned int baseAddr, unsigned int csNum,
 *                         GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
 *
 * \param   conf           Configuration value for RdAccessTime and CycleTime
-*                         timing parameters. Use the 
+*                         timing parameters. Use the
 *                         GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG macro to
 *                         get the value of conf. \n
 *
@@ -1332,7 +1332,7 @@ void  GPMCRdAccessAndCycleTimeTimingConfig(unsigned int baseAddr,
 
 /**
 * \brief   This function configs the WrAccessTime, Cycle2Cycle and BusTurnAround
-*          timing parameters.\n 
+*          timing parameters.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -1347,13 +1347,13 @@ void  GPMCRdAccessAndCycleTimeTimingConfig(unsigned int baseAddr,
 *                         GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
 *                         GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
 *
-* \param   wrAccessTime   Write Access Time(Delay from StartAccessTime to the 
-*                         GPMC_FCLK rising edge corresponding the GPMC_CLK 
-*                         rising edge used by the attached memory for the 
+* \param   wrAccessTime   Write Access Time(Delay from StartAccessTime to the
+*                         GPMC_FCLK rising edge corresponding the GPMC_CLK
+*                         rising edge used by the attached memory for the
 *                         first data capture) in GPMC_FCLK cycles.\n
 *
-*        wrDataOnADmuxBus Specifies on which GPMC_FCLK rising edge the first 
-*                         data of the synchronous burst write is driven in the 
+*        wrDataOnADmuxBus Specifies on which GPMC_FCLK rising edge the first
+*                         data of the synchronous burst write is driven in the
 *                         add/data multiplexed bus.\n
 *
 * \return  None.\n
@@ -1376,7 +1376,7 @@ void  GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(unsigned int baseAddr,
 
 /**
 * \brief   This function configs the Cycle2Cycle and BusTurnAround  timing
-*          parameters.\n 
+*          parameters.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -1392,7 +1392,7 @@ void  GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(unsigned int baseAddr,
 *                         GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
 *
 * \param   conf           Configuration value for Cycle2Cycle and BusTurnAround
-*                         timing parameters. Use the 
+*                         timing parameters. Use the
 *                         GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG macro to
 *                         get the value of conf. \n
 *
@@ -1408,7 +1408,7 @@ void  GPMCycle2CycleAndTurnArndTimeTimingConfig(unsigned int baseAddr,
 
 /**
 * \brief   This function enables/disables the chip select. This function
-*          is called during the chip select configuration.\n 
+*          is called during the chip select configuration.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
@@ -1423,7 +1423,7 @@ void  GPMCycle2CycleAndTurnArndTimeTimingConfig(unsigned int baseAddr,
 *                         GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
 *                         GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
 *
-* \param   conf           Flag to indicate whether to enable or disable 
+* \param   conf           Flag to indicate whether to enable or disable
 *                         the Chip select.\n
 *                         This can take one of the following values :\n
 *                         GPMC_CS_ENABLE  -- To enable the chip select.\n
@@ -1457,7 +1457,7 @@ void  GPMCCSConfig(unsigned int baseAddr, unsigned int csNum,
 *                         GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
 *                         GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
 *
-* \param   addr           Chip Select Base address.Value can range from 
+* \param   addr           Chip Select Base address.Value can range from
 *                         0 to 0x3F\n
 *
 * \return  None.\n
@@ -1524,7 +1524,7 @@ void  GPMCMaskAddrSet(unsigned int baseAddr, unsigned int csNum,
 *                         GPMC_CHIP_SELECT_6 -- For Chip Select 6.
 *                         GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
 *
-* \param  cmd             COMMAND to write. 
+* \param  cmd             COMMAND to write.
 *
 * \return  None.\n
 *
@@ -1624,7 +1624,7 @@ unsigned int  GPMCNANDDataRead(unsigned int baseAddr, unsigned int csNum)
 *
 * \param   accessMode     Access mode of prefetch engine.\n
 *                         This can take one of the following values :\n
-*                         GPMC_PREFETCH_ACCESSMODE_READ  -- For READ Access 
+*                         GPMC_PREFETCH_ACCESSMODE_READ  -- For READ Access
 *                                                           mode.\n
 *                         GPMC_PREFETCH_ACCESSMODE_WRITE -- For WRITE Access
 *                                                            mode.\n
@@ -1643,7 +1643,7 @@ void GPMCPrefetchAccessModeSelect(unsigned int baseAddr,
 }
 
 /**
-* \brief   This function select the synchronization type to use on FIFO 
+* \brief   This function select the synchronization type to use on FIFO
 *          threshold crossing.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
@@ -1672,24 +1672,24 @@ void GPMCPrefetchSyncTypeSelect(unsigned int baseAddr, unsigned int syncType)
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
-* \param   flag           Flag to specify when PREFETCH engine has to start 
+* \param   flag           Flag to specify when PREFETCH engine has to start
 *                         the access to CS.\n
 *                         This can take one of the following values :\n
 *                         GPMC_PREFETCH_ACCESSCS_AT_START       --  To start the
-*                                                                   access as 
-*                                                                   soon as 
-*                                                                   STARTENGINE 
+*                                                                   access as
+*                                                                   soon as
+*                                                                   STARTENGINE
 *                                                                   is set.\n
 *                         GPMC_PREFETCH_ACCESSCS_AT_STARTANDWAIT -- To start the
-*                                                                   access as 
-*                                                                   soon as 
+*                                                                   access as
+*                                                                   soon as
 *                                                                   STARTENGINE
-*                                                                   is set and 
-*                                                                   non wait 
-*                                                                   edge  
-*                                                                   detection 
-*                                                                   on the  
-*                                                                   selected 
+*                                                                   is set and
+*                                                                   non wait
+*                                                                   edge
+*                                                                   detection
+*                                                                   on the
+*                                                                   selected
 *                                                                   wait pin.\n
 *
 * \return  None.\n
@@ -1705,16 +1705,16 @@ void GPMCPrefetchSyncModeConfig(unsigned int baseAddr,unsigned int flag)
 }
 
 /**
-* \brief   This function selects the wait pin edge detector to start the 
+* \brief   This function selects the wait pin edge detector to start the
 *          PREFETCH engine in synchronized mode.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
 * \param   waitPin        Wait pin to use for edge detector. \n
 *                         This can take one of the following values :\n
-*                         GPMC_PREFETCH_WAITPINSELECTOR_W0 -- To Selects 
+*                         GPMC_PREFETCH_WAITPINSELECTOR_W0 -- To Selects
 *                                                             Wait0EdgeDetection\n
-*                         GPMC_PREFETCH_WAITPINSELECTOR_W1 -- To Selects 
+*                         GPMC_PREFETCH_WAITPINSELECTOR_W1 -- To Selects
 *                                                             Wait1EdgeDetection\n
 *
 * \return  None.\n
@@ -1759,8 +1759,8 @@ void GPMCPrefetchEngineDisable(unsigned int baseAddr)
 }
 
 /**
-* \brief   This function sets the FIFOTHRESHOLD (maximum number of bytes read 
-*          from the FIFO or written to the FIFO by the host on a DMA or 
+* \brief   This function sets the FIFOTHRESHOLD (maximum number of bytes read
+*          from the FIFO or written to the FIFO by the host on a DMA or
 *          interrupt request) value for the PREFETCH and POSTWRITE engine.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
@@ -1780,7 +1780,7 @@ void GPMCPrefetchFifoThrldValSet(unsigned int baseAddr, unsigned int fifoThrsld)
 }
 
 /**
-* \brief   This function selects the chip select(CS) where Prefetch Postwrite 
+* \brief   This function selects the chip select(CS) where Prefetch Postwrite
 *          engine is active.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
@@ -1809,7 +1809,7 @@ void GPMCPrefetchCSSelect(unsigned int baseAddr, unsigned int csNum)
 }
 
 /**
-* \brief   This function configs the access cycle optimization for PREFETCH 
+* \brief   This function configs the access cycle optimization for PREFETCH
 *          engine. \n
 *
 * \param   baseAddr       Memory address of GPMC.\n
@@ -1817,12 +1817,12 @@ void GPMCPrefetchCSSelect(unsigned int baseAddr, unsigned int csNum)
 * \param   configVal      access cycle optimization config value.\n
 *                         This can take one of the following values :\n
 *                         GPMC_PREFETCH_OPTIMIZED_ACCESS_ENABLE  -- To enable
-*                                                                   the access 
+*                                                                   the access
 *                                                                   optimization\n
 *                         GPMC_PREFETCH_OPTIMIZED_ACCESS_DISABLE -- To disable
-*                                                                   the access 
+*                                                                   the access
 *                                                                   optimization\n
-*                                                                    
+*
 * \return  None.\n
 *
 */
@@ -1837,16 +1837,16 @@ void GPMCPrefetchAccessCycleOptConfig(unsigned int baseAddr,
 }
 
 /**
-* \brief   This function sets the number of GPMC_FCLK cycles to be substracted 
-*          from RdCycleTime,WrCycleTime, AccessTime, CSRdOffTime, CSWrOffTime, 
-*          ADVRdOffTime,ADVWrOffTime, OEOffTime, WEOffTime for PREFETCH 
+* \brief   This function sets the number of GPMC_FCLK cycles to be substracted
+*          from RdCycleTime,WrCycleTime, AccessTime, CSRdOffTime, CSWrOffTime,
+*          ADVRdOffTime,ADVWrOffTime, OEOffTime, WEOffTime for PREFETCH
 *          engine cycle optimization. \n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
 * \param   cleOptVal      Cycle optimization value. This can take value from
 *                         0 to 7.\n
-*                                                                    
+*
 * \return  None.\n
 *
 */
@@ -1869,11 +1869,11 @@ void GPMCPrefetchCycleOptValSet(unsigned int baseAddr, unsigned int cleOptVal)
 *                         This can take one of the following values :\n
 *                         GPMC_PREFETCH_RR_ARBITRATION_ENABLE   -- To enable
 *                                                                  the Round
-*                                                                  robin 
+*                                                                  robin
 *                                                                  arbitration\n
 *                         GPMC_PREFETCH_RR_ARBITRATION_DISABLE  -- To disable
 *                                                                  the Round
-*                                                                  robin 
+*                                                                  robin
 *                                                                  arbitration\n
 *
 * \return  None.\n
@@ -1890,11 +1890,11 @@ void GPMCPrefetchRRArbitrationConfig(unsigned int baseAddr,
 }
 
 /**
-* \brief   This function sets the number of access to be granted to PREFETCH 
+* \brief   This function sets the number of access to be granted to PREFETCH
 *          engine when ROUND ROBIN arbitration. i.e When an arbitration occurs
 *          between a direct memory access and a PFPW engine access, the direct
 *          memory access is always serviced. If the PFPWEnRoundRobin is enabled
-*          value set by this function plus one number of access is granted to  
+*          value set by this function plus one number of access is granted to
 *          the PREFETCH and WRITE POST engine.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
@@ -1935,7 +1935,7 @@ void GPMCPrefetchTrnsCntValSet(unsigned int baseAddr, unsigned int trnsCntVal)
 }
 
 /**
-* \brief   This function resets the FIFO pointer to 0 in prefetch mode 
+* \brief   This function resets the FIFO pointer to 0 in prefetch mode
 *           and 40h in postwrite mode starts the PREFETCH and POST WRITE engine.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
@@ -2009,7 +2009,7 @@ unsigned int  GPMCPrefetchCountValGet(unsigned int baseAddr)
 *
 * \return  stauts         Threshold status.\n
 *                            1 : FIFO Pointer is greater than FIFO Threshold.\n
-*                            0 : FIFO Pointer is smaller or equal to FIFO 
+*                            0 : FIFO Pointer is smaller or equal to FIFO
 *                                Threshold.\n
 *
 */
@@ -2027,7 +2027,7 @@ unsigned int  GPMCPrefetchFifoThrldStatusGet(unsigned int baseAddr)
 
 /**
 * \brief   This function gets the FIFO pointer value of PREFETCH engine.
-*          FIFO pointer value indicates number of bytes available to be read 
+*          FIFO pointer value indicates number of bytes available to be read
 *          or number of free empty place to write.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
@@ -2068,21 +2068,21 @@ void GPMCECCAlgoSelect(unsigned int baseAddr, unsigned int algo)
 }
 
 /**
-* \brief   This function selects the Error correction capability used for BCH 
+* \brief   This function selects the Error correction capability used for BCH
 *          ECC algorithm.\n
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
 * \param   errCorrCapVal  Error correction capability value.\n
 *                         This can take one of the following values :\n
-*                         GPMC_ECC_BCH_ERRCORRCAP_UPTO_4BITS  -- For Up to 4 
-*                                                                bits error 
+*                         GPMC_ECC_BCH_ERRCORRCAP_UPTO_4BITS  -- For Up to 4
+*                                                                bits error
 *                                                                 correction.\n
 *                         GPMC_ECC_BCH_ERRCORRCAP_UPTO_8BITS  -- For Up to 8
 *                                                                 bits error
 *                                                                 correction.\n
 *                         GPMC_ECC_BCH_ERRCORRCAP_UPTO_16BITS -- For Up to 16
-*                                                                 bits error 
+*                                                                 bits error
 *                                                                 correction.\n
 *
 * \return  None.\n
@@ -2146,7 +2146,7 @@ void GPMCECCColumnSelect(unsigned int baseAddr, unsigned int eccColVal)
 * \param   numOfSects     Number of sectors.\n
 *                         This can take one of the following values :\n
 *                         GPMC_ECC_BCH_NUMOFSECTS_1  -- For 1 sector (512 bytes
-*                                                       page).\n 
+*                                                       page).\n
 *                         GPMC_ECC_BCH_NUMOFSECTS_2  -- For 2 sectors. \n
 *                         GPMC_ECC_BCH_NUMOFSECTS_3  -- For 3 sectors. \n
 *                         GPMC_ECC_BCH_NUMOFSECTS_4  -- For 4 sectors. \n
@@ -2244,7 +2244,7 @@ void GPMCECCResultRegClear(unsigned int baseAddr)
 *                         This can take one of the following values :\n
 *                         GPMC_ECCPOINTER_RESULT_1 -- ECC pointer for result 1
 *                                                     register.\n
-*                         GPMC_ECCPOINTER_RESULT_2 -- ECC pointer for result 2 
+*                         GPMC_ECCPOINTER_RESULT_2 -- ECC pointer for result 2
 *                                                     register.\n
 *                         GPMC_ECCPOINTER_RESULT_3 -- ECC pointer for result 3
 *                                                     register.\n
@@ -2412,7 +2412,7 @@ void GPMCECCResultSizeSelect(unsigned int baseAddr,unsigned int eccResReg,
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
-* \param   eccResReg      ECC result register for from which ECC value has to 
+* \param   eccResReg      ECC result register for from which ECC value has to
 *                         retrive.\n
 *                         This can take one of the following values :\n
 *                         GPMC_ECC_RESULT_1 -- For ECC result 1 register.\n
@@ -2442,7 +2442,7 @@ unsigned int GPMCECCResultGet(unsigned int baseAddr,unsigned int eccResReg)
 *
 * \param   baseAddr       Memory address of GPMC.\n
 *
-* \param   resIndex       BCH ECC result index.\n 
+* \param   resIndex       BCH ECC result index.\n
 *                         This can take one of the following values :\n
 *                         GPMC_BCH_RESULT_0 -- For BCH result 0.\n
 *                         GPMC_BCH_RESULT_1 -- For BCH result 1.\n
@@ -2502,7 +2502,7 @@ unsigned int GPMCECCBCHResultGet(unsigned int baseAddr,unsigned int resIndex,
 }
 
 /**
-* \brief   This function write the data to BCH_SWDATA register. This is used 
+* \brief   This function write the data to BCH_SWDATA register. This is used
 *          to directly padd data to the BCH ECC calculator without accessing
 *          the actual NAND flash interface.\n
 *
@@ -2522,7 +2522,7 @@ void GPMCECCBCHSWDataWrite(unsigned int baseAddr,unsigned int bchData)
 }
 
 /**
-* \brief   This function read the data to BCH_SWDATA register. This is used 
+* \brief   This function read the data to BCH_SWDATA register. This is used
 *          to directly padd data to the BCH ECC calculator without accessing
 *          the actual NAND flash interface.\n
 *
diff --git a/lib/tiam1808/drivers/hsi2c.c b/lib/tiam1808/drivers/hsi2c.c
index 26fa1d9c2..26682f482 100644
--- a/lib/tiam1808/drivers/hsi2c.c
+++ b/lib/tiam1808/drivers/hsi2c.c
@@ -61,7 +61,7 @@
  * \param   outputClk   It is the required I2C bus speed or frequency.
  *
  * \return  None.
- **/ 
+ **/
 void I2CMasterInitExpClk(unsigned int baseAdd, unsigned int sysClk,
                          unsigned int internalClk, unsigned int outputClk)
 {
@@ -79,7 +79,7 @@ void I2CMasterInitExpClk(unsigned int baseAdd, unsigned int sysClk,
 
     HWREG(baseAdd + I2C_SCLL) = divider - 7;
 
-    HWREG(baseAdd + I2C_SCLH) = divider - 5; 
+    HWREG(baseAdd + I2C_SCLH) = divider - 5;
 }
 
 /**
@@ -135,7 +135,7 @@ unsigned int I2CMasterBusBusy(unsigned int baseAdd)
          status = 0;
     }
 
-    return status; 
+    return status;
 }
 
 /**
@@ -159,7 +159,7 @@ unsigned int I2CMasterBusy(unsigned int baseAdd)
  * \param   baseAdd   It is the Memory address of the I2C instance used.
  *
  * \returns error status.If error has occured it returns a non zero value.
- *          If no error has occured then return status will be zero.       
+ *          If no error has occured then return status will be zero.
  *
  * Error may occur during I2C operation due to arbitration lost,access error,
  * receive overrun and transmit underrun.
@@ -182,12 +182,12 @@ unsigned int I2CMasterErr(unsigned int baseAdd)
  * \param   baseAdd   It is the Memory address of the I2C instance used.
  * \param   cmd       It is the value which configures I2C in different mode's
  *                    of operation.\n
- * 
+ *
  *          cmd can take follwing macros.\n
  *
  *          I2C_CFG_MST_TX             - Configure's I2C as Master-Transmitter.\n
  *          I2C_CFG_MST_RX             - Configure's I2C as Master-Receiver.\n
- *          I2C_CFG_STOP               - Configure's I2C to generate stop 
+ *          I2C_CFG_STOP               - Configure's I2C to generate stop
  *                                       condition when DCOUNT counts down to
  *                                       zero.\n
  *          I2C_CFG_N0RMAL_MODE        - Configure's I2C in normal mode.\n
@@ -195,7 +195,7 @@ unsigned int I2CMasterErr(unsigned int baseAdd)
  *          I2C_CFG_7BIT_SLAVE_ADDR    - Configure's I2C to address seven bit
  *                                       addressed slave.\n
  *          I2C_CFG_10BIT_SLAVE_ADDR   - Configure's I2C to address ten bit
- *                                       addressed slave.\n 
+ *                                       addressed slave.\n
  *          I2C_CFG_10BIT_OWN_ADDR_0   - Enable 10bit addressing mode for own
  *                                       address 0.\n
  *          I2C_CFG_10BIT_OWN_ADDR_1   - Enable 10bit addressing mode for own
@@ -222,7 +222,7 @@ void I2CMasterControl(unsigned int baseAdd, unsigned int cmd)
 
 /**
  * \brief   This API start's a I2C transaction on the bus. This API must
- *          be called after all the configuration for the i2c module is 
+ *          be called after all the configuration for the i2c module is
  *          done and after bringing I2C out of local reset
  *
  * \param   baseAdd  It is the Memory address of the I2C instance used.
@@ -255,7 +255,7 @@ void I2CMasterStop(unsigned int baseAdd)
  * \param  intFlag   It specifies the interrupts that are rquired to be enabled.\n
  *
  *         intFlag can take following values.\n
- *         
+ *
  *         I2C_INT_ARBITRATION_LOST     - Arbitration-lost interrupt.\n
  *         I2C_INT_NO_ACK               - No-acknowledgment interrupt.\n
  *         I2C_INT_ADRR_READY_ACESS     - I2C registers are ready to access.\n
@@ -269,7 +269,7 @@ void I2CMasterStop(unsigned int baseAdd)
  *         I2C_INT_TRANSMIT_UNDER_FLOW  - Transmit under flow interrupt.\n
  *         I2C_INT_RECV_OVER_RUN        - Receive overrun interrupt.\n
  *         I2C_INT_RECV_DRAIN           - Receive drain interrupt.\n
- *         I2C_INT_TRANSMIT_DRAIN       - Transmit drain interrupt.\n   
+ *         I2C_INT_TRANSMIT_DRAIN       - Transmit drain interrupt.\n
  *
  * \return None.
  **/
@@ -285,7 +285,7 @@ void I2CMasterIntEnableEx(unsigned int baseAdd, unsigned int intFlag)
  * \param  intFlag   It specifies the interrupts that are rquired to be enabled.\n
  *
  *         intFlag can take following values.\n
- *         
+ *
  *         I2C_INT_NO_ACK               - No-acknowledgment interrupt.\n
  *         I2C_INT_ADRR_READY_ACESS     - I2C registers are ready to access.\n
  *         I2C_INT_RECV_READY           - Receive-data-ready interrupt.\n
@@ -297,7 +297,7 @@ void I2CMasterIntEnableEx(unsigned int baseAdd, unsigned int intFlag)
  *         I2C_INT_TRANSMIT_UNDER_FLOW  - Transmit under flow interrupt.\n
  *         I2C_INT_RECV_OVER_RUN        - Receive overrun interrupt.\n
  *         I2C_INT_RECV_DRAIN           - Receive drain interrupt.\n
- *         I2C_INT_TRANSMIT_DRAIN       - Transmit drain interrupt.\n   
+ *         I2C_INT_TRANSMIT_DRAIN       - Transmit drain interrupt.\n
  *
  * \return None.
  **/
@@ -313,7 +313,7 @@ void I2CSlaveIntEnableEx(unsigned int baseAdd, unsigned int intFlag)
  * \param  intFlag   It specifies the interrupts that are rquired to be disabled\n
  *
  *         intFlag can take following values.\n
- *         
+ *
  *         I2C_INT_ARBITRATION_LOST     - Arbitration-lost interrupt.\n
  *         I2C_INT_NO_ACK               - No-acknowledgment interrupt.\n
  *         I2C_INT_ADRR_READY_ACESS     - I2C registers are ready to access.\n
@@ -327,7 +327,7 @@ void I2CSlaveIntEnableEx(unsigned int baseAdd, unsigned int intFlag)
  *         I2C_INT_TRANSMIT_UNDER_FLOW  - Transmit under flow interrupt.\n
  *         I2C_INT_RECV_OVER_RUN        - Receive overrun interrupt.\n
  *         I2C_INT_RECV_DRAIN           - Receive drain interrupt.\n
- *         I2C_INT_TRANSMIT_DRAIN       - Transmit drain interrupt.\n   
+ *         I2C_INT_TRANSMIT_DRAIN       - Transmit drain interrupt.\n
  *
  * \return None.
  **/
@@ -343,7 +343,7 @@ void I2CMasterIntDisableEx(unsigned int baseAdd, unsigned int intFlag)
  * \param  intFlag   It specifies the interrupts that are rquired to be disabled\n
  *
  *         intFlag can take following values.\n
- *         
+ *
  *         I2C_INT_NO_ACK               - No-acknowledgment interrupt.\n
  *         I2C_INT_ADRR_READY_ACESS     - I2C registers are ready to access.\n
  *         I2C_INT_RECV_READY           - Receive-data-ready interrupt.\n
@@ -355,7 +355,7 @@ void I2CMasterIntDisableEx(unsigned int baseAdd, unsigned int intFlag)
  *         I2C_INT_TRANSMIT_UNDER_FLOW  - Transmit under flow interrupt.\n
  *         I2C_INT_RECV_OVER_RUN        - Receive overrun interrupt.\n
  *         I2C_INT_RECV_DRAIN           - Receive drain interrupt.\n
- *         I2C_INT_TRANSMIT_DRAIN       - Transmit drain interrupt.\n   
+ *         I2C_INT_TRANSMIT_DRAIN       - Transmit drain interrupt.\n
  *
  * \return None.
  **/
@@ -399,7 +399,7 @@ unsigned int I2CSlaveIntStatus(unsigned int baseAdd)
  *                  returned.\n
  *
  *         intFlag can take following macros.\n
- *         
+ *
  *         I2C_INT_ARBITRATION_LOST     - Arbitration-lost interrupt.\n
  *         I2C_INT_NO_ACK               - No-acknowledgment interrupt.\n
  *         I2C_INT_ADRR_READY_ACESS     - I2C register ready to access.\n
@@ -432,7 +432,7 @@ unsigned int I2CMasterIntStatusEx(unsigned int baseAdd, unsigned int intFlag)
  *                  returned.\n
  *
  *         intFlag can take following macros.\n
- *         
+ *
  *         I2C_INT_NO_ACK               - No-acknowledgment interrupt.\n
  *         I2C_INT_ADRR_READY_ACESS     - I2C registers are ready to access.\n
  *         I2C_INT_RECV_READY           - Receive-data-ready interrupt.\n
@@ -490,7 +490,7 @@ unsigned int I2CSlaveIntRawStatus(unsigned int baseAdd)
  *                  returned.\n
  *
  *         intFlag can take following macros.\n
- *         
+ *
  *         I2C_INT_ARBITRATION_LOST     - Arbitration-lost interrupt.\n
  *         I2C_INT_NO_ACK               - No-acknowledgment interrupt.\n
  *         I2C_INT_ADRR_READY_ACESS     - I2C registers are ready to access.\n
@@ -523,7 +523,7 @@ unsigned int I2CMasterIntRawStatusEx(unsigned int baseAdd, unsigned int intFlag)
  *                   returned.\n
  *
  *         intFlag can take following macros.\n
- *         
+ *
  *         I2C_INT_NO_ACK               - No-acknowledgment interrupt.\n
  *         I2C_INT_ADRR_READY_ACESS     - I2C registers are ready to access.\n
  *         I2C_INT_RECV_READY           - Receive-data-ready interrupt.\n
@@ -554,7 +554,7 @@ unsigned int I2CSlaveIntRawStatusEx(unsigned int baseAdd, unsigned int intFlag)
  * \param  intFlag  It specifies the interrupts whose status needs to be cleared\n
  *
  *         intFlag can take following macros.\n
- *         
+ *
  *         I2C_INT_ARBITRATION_LOST     - Arbitration-lost interrupt.\n
  *         I2C_INT_NO_ACK               - No-acknowledgment interrupt.\n
  *         I2C_INT_ADRR_READY_ACESS     - I2C registers ready to access.\n
@@ -567,13 +567,13 @@ unsigned int I2CSlaveIntRawStatusEx(unsigned int baseAdd, unsigned int intFlag)
  *         I2C_INT_ADRR_SLAVE           - Address-as-slave interrupt.\n
  *         I2C_INT_TRANSMIT_UNDER_FLOW  - Transmit under flow interrupt.\n
  *         I2C_INT_RECV_DRAIN           - Receive drain interrupt.\n
- *         I2C_INT_TRANSMIT_DRAIN       - Transmit drain interrupt.\n   
+ *         I2C_INT_TRANSMIT_DRAIN       - Transmit drain interrupt.\n
  *
  * \returns None
  **/
 void I2CMasterIntClearEx(unsigned int baseAdd, unsigned int intFlag)
 {
-    HWREG(baseAdd + I2C_IRQSTATUS) = intFlag; 
+    HWREG(baseAdd + I2C_IRQSTATUS) = intFlag;
 }
 
 /**
@@ -584,7 +584,7 @@ void I2CMasterIntClearEx(unsigned int baseAdd, unsigned int intFlag)
  * \param  intFlag  It specifies the interrupts whose status needs to be cleared\n
  *
  *         intFlag can take following macros.\n
- *         
+ *
  *         I2C_INT_NO_ACK               - No-acknowledgment interrupt.\n
  *         I2C_INT_ADRR_READY_ACESS     - No-acknowledgment interrupt.\n
  *         I2C_INT_RECV_READY           - Receive-data-ready interrupt.\n
@@ -596,13 +596,13 @@ void I2CMasterIntClearEx(unsigned int baseAdd, unsigned int intFlag)
  *         I2C_INT_ADRR_SLAVE           - Address-as-slave interrupt.\n
  *         I2C_INT_TRANSMIT_UNDER_FLOW  - Transmit under flow interrupt.\n
  *         I2C_INT_RECV_DRAIN           - Receive drain interrupt.\n
- *         I2C_INT_TRANSMIT_DRAIN       - Transmit drain interrupt.\n   
+ *         I2C_INT_TRANSMIT_DRAIN       - Transmit drain interrupt.\n
  *
  * \returns None
  **/
 void I2CSlaveIntClearEx(unsigned int baseAdd, unsigned int intFlag)
 {
-    HWREG(baseAdd + I2C_IRQSTATUS) = intFlag; 
+    HWREG(baseAdd + I2C_IRQSTATUS) = intFlag;
 }
 
 /**
@@ -613,7 +613,7 @@ void I2CSlaveIntClearEx(unsigned int baseAdd, unsigned int intFlag)
  * \param  intFlag  It specifies the interrupts whose status needs to be cleared\n
  *
  *         intFlag can take following macros.\n
- *         
+ *
  *         I2C_INT_NO_ACK               - No-acknowledgment interrupt.\n
  *         I2C_INT_ADRR_READY_ACESS     - I2C registers are ready to access.\n
  *         I2C_INT_RECV_READY           - Receive-data-ready interrupt.\n
@@ -624,7 +624,7 @@ void I2CSlaveIntClearEx(unsigned int baseAdd, unsigned int intFlag)
  **/
 void I2CMasterIntRawStatusClearEx(unsigned int baseAdd, unsigned int intFlag)
 {
-    HWREG(baseAdd + I2C_IRQSTATUS_RAW) = intFlag; 
+    HWREG(baseAdd + I2C_IRQSTATUS_RAW) = intFlag;
 }
 
 /**
@@ -635,7 +635,7 @@ void I2CMasterIntRawStatusClearEx(unsigned int baseAdd, unsigned int intFlag)
  * \param  intFlag   It specifies the interrupts whose status needs to be cleared\n
  *
  *         intFlag can take following macros.\n
- *         
+ *
  *         I2C_INT_NO_ACK               - No-acknowledgment interrupt.\n
  *         I2C_INT_ADRR_READY_ACESS     - I2C register are ready to access.\n
  *         I2C_INT_RECV_READY           - Receive-data-ready interrupt.\n
@@ -646,7 +646,7 @@ void I2CMasterIntRawStatusClearEx(unsigned int baseAdd, unsigned int intFlag)
  **/
 void I2CSlaveIntRawStatusClearEx(unsigned int baseAdd, unsigned int intFlag)
 {
-    HWREG(baseAdd + I2C_IRQSTATUS_RAW) = intFlag; 
+    HWREG(baseAdd + I2C_IRQSTATUS_RAW) = intFlag;
 }
 
 /**
@@ -680,7 +680,7 @@ unsigned int I2CMasterSlaveAddrGet(unsigned int baseAdd, unsigned int slaveAdd)
 }
 
 /**
- * \brief   This API configure I2C data count register with a value. 
+ * \brief   This API configure I2C data count register with a value.
  *          The value in the I2C data count register indicate how many data
  *          words to transfer when the I2C is configured as a  master-transmitter
  *          and repeat mode is off.
@@ -697,7 +697,7 @@ void I2CSetDataCount(unsigned int baseAdd, unsigned int count)
 
 
 /**
- * \brief   This API configure I2C data count register with a value. 
+ * \brief   This API configure I2C data count register with a value.
  *          The value in the I2C data count register indicate how many data
  *          words to transfer when the I2C is configured as a  master-transmitter
  *          and repeat mode is off.
@@ -715,11 +715,11 @@ unsigned int I2CDataCountGet(unsigned int baseAdd)
  * \brief   This API configure's the threshold value for FIFO buffer.
  *
  * \param   baseAdd     It is the Memory address of the I2C instance used.
- * \param   thresholdVal It is the threshold value for FIFO buffer.Which is 
+ * \param   thresholdVal It is the threshold value for FIFO buffer.Which is
  *                       used to specify the trigger level for data transfer or
  *                       data receive transfers.
  * \param   flag         It specifies FIFO buffer in TX mode or RX mode.\n
- *     
+ *
  *          flag can take following macros.\n
  *
  *          I2C_TX_MODE.\n
@@ -749,7 +749,7 @@ void I2CFIFOThresholdConfig(unsigned int baseAdd, unsigned int threshlodVal,
  *
  * \param   baseAdd     It is the Memory address of the I2C instance used..
  * \param   flag        It specifies Transmit FIFO or Receive FIFO.\n
- *     
+ *
  *         flag can take following macros.\n
  *
  *         I2C_TX_MODE - .\n
@@ -797,7 +797,7 @@ void I2CDMARxEventEnable(unsigned int baseAdd)
 {
     HWREG(baseAdd + I2C_BUF) |= (I2C_BUF_RDMA_EN);
 
-    HWREG(baseAdd + I2C_DMARXENABLE_SET) =   
+    HWREG(baseAdd + I2C_DMARXENABLE_SET) =
                                        (I2C_DMARXENABLE_SET_DMARX_ENABLE_SET);
 }
 
@@ -812,7 +812,7 @@ void I2CDMATxEventDisable(unsigned int baseAdd)
 {
     HWREG(baseAdd + I2C_BUF) &= ~(I2C_BUF_XDMA_EN);
 
-    HWREG(baseAdd + I2C_DMATXENABLE_CLR) =   
+    HWREG(baseAdd + I2C_DMATXENABLE_CLR) =
                                     (I2C_DMATXENABLE_CLR_DMATX_ENABLE_CLEAR);
 }
 
@@ -827,7 +827,7 @@ void I2CDMARxEventDisable(unsigned int baseAdd)
 {
     HWREG(baseAdd + I2C_BUF) &= ~(I2C_BUF_RDMA_EN);
 
-    HWREG(baseAdd + I2C_DMARXENABLE_CLR) =  
+    HWREG(baseAdd + I2C_DMARXENABLE_CLR) =
                                      (I2C_DMARXENABLE_CLR_DMARX_ENABLE_CLEAR);
 }
 
@@ -836,7 +836,7 @@ void I2CDMARxEventDisable(unsigned int baseAdd)
  *
  * \param   baseAdd     It is the Memory address of the I2C instance used..
  * \param   flag        It specifies required status field.\n
- *     
+ *
  *          flag can take following macros.\n
  *
  *          I2C_TX_BUFFER_STATUS - Indicates the number of data bytes still.
@@ -859,12 +859,12 @@ unsigned int I2CBufferStatus(unsigned int baseAdd, unsigned int flag)
                break;
 
          case 1:
-               status = (HWREG(baseAdd + I2C_BUFSTAT) & I2C_BUFSTAT_RXSTAT) 
+               status = (HWREG(baseAdd + I2C_BUFSTAT) & I2C_BUFSTAT_RXSTAT)
                         >> I2C_BUFSTAT_RXSTAT_SHIFT;
                break;
 
          case 2:
-               status = (HWREG(baseAdd + I2C_BUFSTAT) & I2C_BUFSTAT_FIFODEPTH) 
+               status = (HWREG(baseAdd + I2C_BUFSTAT) & I2C_BUFSTAT_FIFODEPTH)
                         >> I2C_BUFSTAT_FIFODEPTH_SHIFT;
                break;
 
@@ -881,7 +881,7 @@ unsigned int I2CBufferStatus(unsigned int baseAdd, unsigned int flag)
  *
  * \param   baseAdd  It is the Memory address of the I2C instance used.
  *
- * \returns one of the module's four own address the external master used 
+ * \returns one of the module's four own address the external master used
  *          when addressing the module.
  **/
 unsigned int I2CActiveOwnAddressGet(unsigned int baseAdd)
@@ -905,29 +905,29 @@ unsigned int I2CActiveOwnAddressGet(unsigned int baseAdd)
 
     return 0;
 }
-    
+
 /**
  * \brief   This API blocks or unblocks the clock for any of the module's four own
  *          addresses.
  *
  * \param   baseAdd  It is the Memory address of the I2C instance used.
  *
- * \param   ownAdd0  It is value which blocks or unblocks clock to i2c if 
+ * \param   ownAdd0  It is value which blocks or unblocks clock to i2c if
  *                   an external master using own address 0.
  *
- * \param   ownAdd1  It is value which blocks or unblocks clock to i2c if 
+ * \param   ownAdd1  It is value which blocks or unblocks clock to i2c if
  *                   an external master using own address 1.
  *
- * \param   ownAdd2  It is value which blocks or unblocks clock to i2c if 
+ * \param   ownAdd2  It is value which blocks or unblocks clock to i2c if
  *                   an external master using own address 2.
  *
- * \param   ownAdd3  It is value which blocks or unblocks clock to i2c if 
+ * \param   ownAdd3  It is value which blocks or unblocks clock to i2c if
  *                   an external master using own address 0.
  *
  *                   0 - Unblocks clock to i2c
  *                   1 - Blocks clock to i2c
  * \returns None.
- *          
+ *
  **/
 void I2CClockBlockingControl(unsigned int baseAdd, unsigned int ownAdd0,
                              unsigned int ownAdd1, unsigned int ownAdd2,
@@ -956,27 +956,27 @@ void I2CClockBlockingControl(unsigned int baseAdd, unsigned int ownAdd0,
  *                    out of four.\n
  *
  *          flag can take following values.\n
- *      
+ *
  *          I2C_OWN_ADDR_0.\n
  *          I2C_OWN_ADDR_1.\n
  *          I2C_OWN_ADDR_2.\n
  *          I2C_OWN_ADDR_3.\n
  *
  * \returns None.
- *          
+ *
  **/
 void I2COwnAddressSet(unsigned int baseAdd, unsigned int slaveAdd,
                         unsigned int flag)
 {
     switch(flag)
     {
-         case 0 : 
+         case 0 :
                HWREG(baseAdd + I2C_OA) = slaveAdd;
                return;
-         case 1 : 
+         case 1 :
                HWREG(baseAdd + I2C_OAn(0)) = slaveAdd;
                return;
-         case 2 : 
+         case 2 :
                HWREG(baseAdd + I2C_OAn(1)) = slaveAdd;
                return;
          case 3 :
@@ -992,7 +992,7 @@ void I2COwnAddressSet(unsigned int baseAdd, unsigned int slaveAdd,
  * \param   baseAdd  It is the Memory address of the I2C instance used.
  *
  * \returns None.
- *          
+ *
  **/
 void I2CSoftReset(unsigned int baseAdd)
 {
@@ -1005,7 +1005,7 @@ void I2CSoftReset(unsigned int baseAdd)
  * \param   baseAdd  It is the Memory address of the I2C instance used.
  *
  * \returns None.
- *          
+ *
  **/
 void I2CAutoIdleEnable(unsigned int baseAdd)
 {
@@ -1018,7 +1018,7 @@ void I2CAutoIdleEnable(unsigned int baseAdd)
  * \param   baseAdd  It is the Memory address of the I2C instance used.
  *
  * \returns None.
- *          
+ *
  **/
 void I2CAutoIdleDisable(unsigned int baseAdd)
 {
@@ -1031,7 +1031,7 @@ void I2CAutoIdleDisable(unsigned int baseAdd)
  * \param   baseAdd  It is the Memory address of the I2C instance used.
  *
  * \returns None.
- *          
+ *
  **/
 void I2CGlobalWakeUpEnable(unsigned int baseAdd)
 {
@@ -1044,7 +1044,7 @@ void I2CGlobalWakeUpEnable(unsigned int baseAdd)
  * \param   baseAdd  It is the Memory address of the I2C instance used.
  *
  * \returns None.
- *          
+ *
  **/
 void I2CGlobalWakeUpDisable(unsigned int baseAdd)
 {
@@ -1066,7 +1066,7 @@ void I2CGlobalWakeUpDisable(unsigned int baseAdd)
  *                                         of operation.\n
  *
  * \returns None.
- *          
+ *
  **/
 void I2CIdleModeSelect(unsigned int baseAdd, unsigned int flag)
 {
@@ -1092,7 +1092,7 @@ void I2CIdleModeSelect(unsigned int baseAdd, unsigned int flag)
  *          I2C_KEEP_ALIVE_BOTH_CLK     - BOTH OCP and SYS Clk are kept alive.\n
  *
  * \returns None.
- *          
+ *
  **/
 void I2CClockActivitySelect(unsigned int baseAdd, unsigned int flag)
 {
@@ -1108,11 +1108,11 @@ void I2CClockActivitySelect(unsigned int baseAdd, unsigned int flag)
  *         the I2C controller.
  *
  * \param  baseAdd    It is the Memory address of the I2C instance used.
- * \param  eventFlag   It specifies for which event wakeup sinal has to 
+ * \param  eventFlag   It specifies for which event wakeup sinal has to
  *                     Enable.\n
  *
  *         intFlag can take following values.\n
- *         
+ *
  *         I2C_WAKE_UP_ARBITRATION_LOST    - Arbitration-lost wakeup signal.\n
  *         I2C_WAKE_UP_NO_ACK              - No-acknowledgment wakeup signal.\n
  *         I2C_WAKE_UP_ADRR_READY_ACCESS   - No-acknowledgment wakeup signal.\n
@@ -1123,11 +1123,11 @@ void I2CClockActivitySelect(unsigned int baseAdd, unsigned int flag)
  *         I2C_WAKE_UP_TX_UNDER_FLOW       - Transmit under flow wakeup siganl.\n
  *         I2C_WAKE_UP_RECV_OVER_RUN       - Receive overrun wakeup signal.\n
  *         I2C_WAKE_UP_RECV_DRAIN          - Receive drain wakeup signal.\n
- *         I2C_WAKE_UP_TRANSMIT_DRAIN      - Transmit drain wakeup siganl.\n   
+ *         I2C_WAKE_UP_TRANSMIT_DRAIN      - Transmit drain wakeup siganl.\n
  *         I2C_WAKE_UP_DATA_RECV_TX_RDY    - Receive-data-ready
  *                                                  wakeup signal.\n
  *
- * \param  flag        It specifies IRQ or DMA Transmit or DMA receive 
+ * \param  flag        It specifies IRQ or DMA Transmit or DMA receive
  *                     request source to generate asynchronous wake up
  *                     signal.\n
  *
@@ -1154,7 +1154,7 @@ void I2CWakeUpEnable(unsigned int baseAdd, unsigned int eventFlag,
     {
          HWREG(baseAdd + I2C_DMATXWAKE_EN) |= eventFlag;
     }
-     
+
 }
 
 /**
@@ -1164,11 +1164,11 @@ void I2CWakeUpEnable(unsigned int baseAdd, unsigned int eventFlag,
  *         the I2C controller.
  *
  * \param  baseAdd    It is the Memory address of the I2C instance used.
- * \param  eventflag   It specifies for which event wakeup sinal has to 
+ * \param  eventflag   It specifies for which event wakeup sinal has to
  *                     disabled.\n
  *
  *         intFlag can take following macros.\n
- *         
+ *
  *         I2C_WAKE_UP_ARBITRATION_LOST    - Arbitration-lost wakeup signal.\n
  *         I2C_WAKE_UP_NO_ACK              - No-acknowledgment wakeup signal.\n
  *         I2C_WAKE_UP_ADRR_RDY_ACCESS     - No-acknowledgment wakeup signal.\n
@@ -1179,11 +1179,11 @@ void I2CWakeUpEnable(unsigned int baseAdd, unsigned int eventFlag,
  *         I2C_WAKE_UP_TX_UNDER_FLOW       - Transmit under flow wakeup siganl.\n
  *         I2C_WAKE_UP_RECV_OVER_RUN       - Receive overrun wakeup signal.\n
  *         I2C_WAKE_UP_RECV_DRAIN          - Receive drain wakeup signal.\n
- *         I2C_WAKE_UP_TRANSMIT_DRAIN      - Transmit drain wakeup siganl.\n   
+ *         I2C_WAKE_UP_TRANSMIT_DRAIN      - Transmit drain wakeup siganl.\n
  *         I2C_WAKE_UP_DATA_RECV_TX_RDY    - Receive-data-ready
  *                                              wakeup signal.\n
  *
- * \param  flag        It specifies IRQ or DMA Transmit or DMA receive 
+ * \param  flag        It specifies IRQ or DMA Transmit or DMA receive
  *                     request source to generate asynchronous wake up
  *                     signal.\n
  *
@@ -1218,9 +1218,9 @@ void I2CWakeUpDisable(unsigned int baseAdd, unsigned int eventFlag,
  *
  * \param   baseAdd  It is the Memory address of the I2C instance used.
  *
- * \returns returns "1" if reset is completed. 
+ * \returns returns "1" if reset is completed.
  *          returns "0" if internal module reset is ongoing.
- *          
+ *
  **/
 unsigned int I2CSystemStatusGet(unsigned int baseAdd)
 {
@@ -1229,10 +1229,10 @@ unsigned int I2CSystemStatusGet(unsigned int baseAdd)
 
 /**
  * \brief  This function Transmits a byte from the I2C in Master mode.
- * 
+ *
  * \param  baseAdd is the Memory address of the I2C instance used.
  * \param  data data to be transmitted from the I2C Master.
- * 
+ *
  * \return None.\n
  *
  **/
@@ -1244,9 +1244,9 @@ void I2CMasterDataPut(unsigned int baseAdd, unsigned char data)
 
 /**
  *  \brief  This Receives a byte that has been sent to the I2C in Master mode.
- * 
+ *
  *  \param  baseAdd is the Memory address of the I2C instance used.
- * 
+ *
  *  \return Returns the byte received from by the I2C in Master mode.
  *
  **/
@@ -1260,10 +1260,10 @@ unsigned char I2CMasterDataGet(unsigned int baseAdd)
 
 /**
  * \brief  This Transmits a byte from the I2C in Slave mode.
- * 
+ *
  * \param  baseAdd is the Memory address of the I2C Slave module.
  * \param  data data to be transmitted from the I2C in Slave mode.
- * 
+ *
  * \return None.
  *
  **/
@@ -1275,11 +1275,11 @@ void I2CSlaveDataPut(unsigned int baseAdd,unsigned int data)
 /**
  * \brief  This function Receives a byte that has been sent to the I2C in Slave
  *         mode.
- * 
+ *
  * \param  baseAdd is the Memory address of the I2C instace used.
- * 
+ *
  * \return Returns the byte received from by the I2C in Slave mode.
- * 
+ *
  **/
 unsigned int I2CSlaveDataGet(unsigned int baseAdd)
 {
@@ -1292,11 +1292,11 @@ unsigned int I2CSlaveDataGet(unsigned int baseAdd)
 
 
 /**
- * \brief  This function Acknowledges interrupt. 
- * 
+ * \brief  This function Acknowledges interrupt.
+ *
  * \param  baseAdd is the Memory address of the I2C instace used.
  * \param  flag    is value which acknowledges the asserted interrupt.
- * 
+ *
  **/
 void I2CEndOfInterrupt(unsigned int baseAdd, unsigned int flag)
 {
@@ -1342,8 +1342,8 @@ void I2CContextRestore(unsigned int i2cBase, I2CCONTEXT *contextPtr)
     HWREG(i2cBase + I2C_SCLL)	=	contextPtr->lowdivider;
     HWREG(i2cBase + I2C_SCLH)	=	contextPtr->highdivider;
     HWREG(i2cBase + I2C_OA)		=	contextPtr->ownaddr;
-	
-	HWREG(i2cBase + I2C_CON) |= I2C_CON_I2C_EN; 	// Enable 
+
+	HWREG(i2cBase + I2C_CON) |= I2C_CON_I2C_EN; 	// Enable
 	while((!HWREG(i2cBase + I2C_SYSS) & I2C_SYSS_RDONE)); 	// reset complete...?
 }
 
diff --git a/lib/tiam1808/drivers/i2c.c b/lib/tiam1808/drivers/i2c.c
index e0260af0c..4b35e9fb7 100644
--- a/lib/tiam1808/drivers/i2c.c
+++ b/lib/tiam1808/drivers/i2c.c
@@ -1,6 +1,6 @@
 /**
  * \file  i2c.c
- *    
+ *
  * \brief I2C device abstraction layer APIs
  */
 
@@ -76,7 +76,7 @@ void I2CMasterInitExpClk(unsigned int baseAdd, unsigned int inputClk,
 
     HWREG(baseAdd + I2C_ICPSC) = prescale;
 
-    switch (prescale) 
+    switch (prescale)
     {
         case 0:
             dValue = 7;
@@ -94,16 +94,16 @@ void I2CMasterInitExpClk(unsigned int baseAdd, unsigned int inputClk,
 
     HWREG(baseAdd + I2C_ICCLKL)= div/2;
     HWREG(baseAdd + I2C_ICCLKH) = div - HWREG(baseAdd + I2C_ICCLKL);
-    
+
     return;
 }
 
 /**
-* \brief   Enables the I2C module.This will bring the I2C module out of local 
+* \brief   Enables the I2C module.This will bring the I2C module out of local
 *           reset.\n
 *
 * \param  baseAddr Base Address is the Memory address of the I2C instance used\n
-* 
+*
 * \return None.\n
 *
 **/
@@ -120,7 +120,7 @@ void I2CMasterEnable(unsigned int baseAddr)
 * \brief  Disables the I2C Module.This will put the I2C module in local reset.
 *
 * \param  baseAddr Base Address is the Memory address of the I2C instance used
-* 
+*
 *  \return None.
 *
 **/
@@ -132,7 +132,7 @@ void I2CMasterDisable(unsigned int baseAddr)
 
 /**
 * \brief  Enables the interrupt when I2C is in Master mode.Enables the indicated
-*          I2C interrupt sources.Only the sources that are enabled can be 
+*          I2C interrupt sources.Only the sources that are enabled can be
 *          reflected to the processor interrupt; disabled sources have no effect on
 *          the processor.\n
 *
@@ -142,19 +142,19 @@ void I2CMasterDisable(unsigned int baseAddr)
 *        intFlag can take following values.\n
 *
 *               I2C_INT_ARBITRATION_LOST     - Arbitration-lost interrupt\n
-*                                              
+*
 *               I2C_INT_NO_ACK               - No-acknowledgment interrupt\n
-*                                              
+*
 *               I2C_INT_ADRR_READY_ACESS     - No-acknowledgment interrupt\n
-*                                              
+*
 *               I2C_INT_DATA_RECV_READY      - Receive-data-ready interrupt\n
-*                                              
+*
 *               I2C_INT_DATA_TRANSMIT_READY  - Transmit-data-ready interrupt\n
-*                                              
+*
 *               I2C_INT_STOP_CONDITION       - Stop condition interrupt\n
-*                                              
+*
 *               I2C_INT_ADRR_SLAVE            -Address-as-slave interrupt\n
-*                                              
+*
 *
 * \return None.\n
 *
@@ -162,35 +162,35 @@ void I2CMasterDisable(unsigned int baseAddr)
 void I2CMasterIntEnableEx(unsigned int baseAddr, unsigned int intFlag)
 {
     /*Enable the master interrupt.*/
-    HWREG(baseAddr + I2C_ICIMR) |= intFlag; 
+    HWREG(baseAddr + I2C_ICIMR) |= intFlag;
 }
 /**
 * \brief  Enables individual interrupt sources when I2C is in Slave mode.
 *          Enables the indicated I2C interrupt sources.  Only the sources that
 *          are enabled can be reflected to the processor interrupt; disabled sources
 *          have no effect on the processor\n
-* 
+*
 * \param baseAddr is the Memory address of the I2C instance used\n
 * \param intFlag is the bit mask of the interrupt sources to be enabled.\n
-* 
+*
 *        intFlag can take following values\n
-*                        
+*
 *               I2C_INT_ARBITRATION_LOST     - Arbitration-lost interrupt\n
-*                                              
+*
 *               I2C_INT_NO_ACK               - No-acknowledgment interrupt\n
-*                                              
+*
 *               I2C_INT_ADRR_READY_ACESS     - No-acknowledgment interrupt\n
-*                                              
+*
 *               I2C_INT_DATA_RECV_READY      - Receive-data-ready interrupt\n
-*                                              
+*
 *               I2C_INT_DATA_TRANSMIT_READY  - Transmit-data-ready interrupt\n
-*                                              
+*
 *               I2C_INT_STOP_CONDITION       - Stop condition interrupt \n
-*                                             
+*
 *               I2C_INT_ADRR_SLAVE           - Address-as-slave interrupt\n
-* 
+*
 *\return None.
-* 
+*
 **/
 void I2CSlaveIntEnableEx(unsigned int baseAddr, unsigned int intFlag)
 {
@@ -198,29 +198,29 @@ void I2CSlaveIntEnableEx(unsigned int baseAddr, unsigned int intFlag)
 }
 
 /**
-* \brief  Disables the interrupt when I2C is in Master mode.Disables the 
-*          indicated I2C interrupt sources.  Only the sources that are 
+* \brief  Disables the interrupt when I2C is in Master mode.Disables the
+*          indicated I2C interrupt sources.  Only the sources that are
 *          enabled can be reflected to the processor interrupt;disabled sources
 *          have no effect on the processor.\n
 *
 *
 * \param baseAddr is the Memory address of the I2C instance used\n
 * \param intFlag is the bit mask of the interrupt sources to be dislabled.\n
-*  
+*
 * intFlag can take follwing values\n
 *
 *                I2C_INT_ARBITRATION_LOST      - Arbitration-lost interrupt\n
-*                                               
+*
 *                I2C_INT_NO_ACK                - No-acknowledgment interrupt\n
-*                                               
+*
 *                I2C_INT_ADRR_READY_ACESS      - No-acknowledgment interrupt\n
-*                                               
+*
 *                I2C_INT_DATA_RECV_READY       - Receive-data-ready interrupt\n
-*                                                
+*
 *                I2C_INT_DATA_TRANSMIT_READY   - Transmit-data-ready interrupt\n
-*                                               
+*
 *                I2C_INT_STOP_CONDITION        - Stop condition interrupt \n
-*                                                
+*
 *                I2C_INT_ADRR_SLAVE            - Address-as-slave interrupt\n
 * \return None.\n
 *
@@ -232,28 +232,28 @@ void I2CMasterIntDisableEx(unsigned int baseAddr, unsigned int intFlag)
 /**
 * \brief  Disables individual interrupt sources when I2C is in Slave mode.
 *`          Disables the indicated I2C Slave interrupt sources.  Only the sources
-*          that are enabled can be reflected to the processor interrupt; 
+*          that are enabled can be reflected to the processor interrupt;
 *          disabled sources have no effect on the processor.\n
 *
 * \param baseAddr is the Memory address of the I2C instance used \n
 * \param intFlag is the bit mask of the interrupt sources to be disabled.\n
 *
 * intFlag is can take following values.\n
-*                        
+*
 *               I2C_INT_ARBITRATION_LOST     - Arbitration-lost interrupt\n
-*                                              
+*
 *               I2C_INT_NO_ACK               - No-acknowledgment interrupt\n
-*                                              
+*
 *               I2C_INT_ADRR_READY_ACESS     - No-acknowledgment interrupt\n
-*                                              
+*
 *               I2C_INT_DATA_RECV_READY      - Receive-data-ready interrupt\n
-*                                              
+*
 *               I2C_INT_DATA_TRANSMIT_READY  - Transmit-data-ready interrupt\n
-*                                              
+*
 *               I2C_INT_STOP_CONDITION       - Stop condition interrupt\n
-*                                              
+*
 *               I2C_INT_ADRR_SLAVE           - Address-as-slave interrupt\n
-*                                              
+*
 * \return None.\n
 *
 **/
@@ -268,7 +268,7 @@ void I2CSlaveIntDisableEx(unsigned int baseAddr, unsigned int intFlag)
 *          For more information on ICSTR refer to SPRUFV4.\n
 *
 * \param baseAddr is the Memory address of the I2C instance used \n
-* 
+*
 * \returns the interrupt status when I2C is in Master Mode.\n
 *
 **/
@@ -287,7 +287,7 @@ unsigned int I2CMasterIntStatus(unsigned int baseAddr)
 *         on ICSTR refer to SPRUFV4.\n
 *
 * \param baseAddr is the Memory address of the I2C instance used \n
-*  
+*
 * \returns the interrupt status for the when I2C is in Slave mode.\n
 *
 **/
@@ -303,7 +303,7 @@ unsigned int I2CSlaveIntStatus(unsigned int baseAddr)
 /**
 * \brief  This API determine the status of any one of the bit in interrupt \n
 *          status register.where intFlag is Mask of status bit needs to read.\n
-* 
+*
 * \param baseAddr is the Memory address of the I2C instance used\n
 * \param intFlag is Mask of status bit needs to read.\n
 *
@@ -312,7 +312,7 @@ unsigned int I2CSlaveIntStatus(unsigned int baseAddr)
 unsigned int I2CSlaveIntStatusEx(unsigned int baseAddr, unsigned int intFlag)
 {
     intFlag &= HWREG(baseAddr + I2C_ICSTR);
-        
+
     return intFlag;
 }
 
@@ -324,7 +324,7 @@ unsigned int I2CSlaveIntStatusEx(unsigned int baseAddr, unsigned int intFlag)
 * \intFlag is the mask of status bit to be cleared.\n
 *
 *        intFlag can take following values\n
-*        
+*
 *                I2C_CLEAR_NO_ACK          - No-acknowledgment interrupt
 *                                            flag bit.\n
 *                I2C_CLEAR_ADDR_READY      - Register-access-ready interrupt
@@ -364,7 +364,7 @@ void I2CMasterIntClearEx(unsigned int baseAddr, unsigned int intFlag)
 *               I2C_CLEAR_NO_ACK_SENT   - No-acknowledgment sent bit\n
 *               I2C_CLEAR_ARBITARTION_LOST-Arbitration-lost interrupt flag \n
 *
-* 
+*
 * \return None.\n
 *
 **/
@@ -391,9 +391,9 @@ void I2CMasterSlaveAddrSet(unsigned int baseAddr, unsigned int slaveAddr)
 * \brief   This function returns the indication of whether or not I2c bus is busy
 *
 * \param   baseAddr is the Memory address of the I2C instance used
-*   
-* \return  non zero of  the bus is busy, zero otherwise 
-* 
+*
+* \return  non zero of  the bus is busy, zero otherwise
+*
 **/
 unsigned int  I2CMasterBusBusy(unsigned int baseAddr)
 {
@@ -404,11 +404,11 @@ unsigned int  I2CMasterBusBusy(unsigned int baseAddr)
 * \brief   This function checks if indeed I2c operation has completed.
 *
 * \param   baseAddr is the Memory address of the I2C instance used\n
-*   
+*
 * \return   Non-Zero if the I2C peripheral operation is not complete
 *           0 if complete
-* 
-* \note    This is different from bus busy. This API checks if the peripheral is 
+*
+* \note    This is different from bus busy. This API checks if the peripheral is
 *          ready to be used for next transaction.
 **/
 unsigned int  I2CMasterIsBusy(unsigned int baseAddr)
@@ -423,7 +423,7 @@ unsigned int  I2CMasterIsBusy(unsigned int baseAddr)
 *         I2c Mode register i.e ICMDR referto SPRUFV4 document,which is a I2C
 *         peripheral manual.\n
 *
-* 
+*
 * \param baseAddr is the Memory address of the I2C instance used.\n
 * \param cmd is the command to be issued to the I2C Master module\n
 *
@@ -433,7 +433,7 @@ unsigned int  I2CMasterIsBusy(unsigned int baseAddr)
 *
 *               I2C_CFG_MAST_STOP_TX      -     This command configures I2C to
 *                                               Master-trasmiter generates stop
-*                                               conditon when internal data 
+*                                               conditon when internal data
 *                                               counts to 0 \n
 *
 *               I2C_CFG_MST_RX            -     This command configuers I2C to
@@ -441,7 +441,7 @@ unsigned int  I2CMasterIsBusy(unsigned int baseAddr)
 *
 *               I2C_CFG_NACKMOD           -     This command set the NACKMOD bit
 *                                               in ICMDR to send NACK bit to
-*                                               slave device to stop 
+*                                               slave device to stop
                                                 transmission of data.\n
 *
 *               I2C_CFG_STOP              -     This command sets STP bit in
@@ -451,16 +451,16 @@ unsigned int  I2CMasterIsBusy(unsigned int baseAddr)
 *
 *               I2C_CFG_7BIT_ADDR_MODE    -     This command configures I2C in
 *                                               to 7 bit addressing mode.\n
-* 
+*
 *               I2C_CFG_10BIT_ADDR_MODE   -     This command configures I2C in
 *                                               to 10 bit addressing mode.\n
-* 
+*
 *               I2C_CFG_FREE_FORMAT_DATA  -     This command configures I2C in
 *                                               to free format addressing mode.\n
 *
 *               I2C_CFG_SLAVE_STT         -     This command configures I2C to
 *                                               Slave mode and sets STT bit in
-*                                               ICSTR,if STT bit is not set 
+*                                               ICSTR,if STT bit is not set
 *                                               slave not responds to commands
 *                                               from master. \n
 *
@@ -486,7 +486,7 @@ void I2CMasterControl(unsigned int baseAddr, unsigned int cmd)
 * \brief  This API is used to start a I2C transaction on the bus. This API must
 *         be called after all the configuration for the i2c module is done and after
 *        bringing I2C out of local reset
-* 
+*
 * \param baseAddr is the Memory address of the I2C instance used.\n
 *
 * \return None
@@ -500,7 +500,7 @@ void I2CMasterStart(unsigned int baseAddr)
 * \brief  This API is used to stop a I2C transaction on the bus.\n
 *         This API must be used in case a deliberate STOP needs to be sent
 *         on the bus
-* 
+*
 * \param baseAddr is the Memory address of the I2C instance used.\n
 *
 * \return None
@@ -512,7 +512,7 @@ void I2CMasterStop(unsigned int baseAddr)
 
 /**
 * \brief  This API is used to clear a specific status bit(s).\n
-* 
+*
 * \param  baseAddr is the Memory address of the I2C instance used.\n
 * \param  status   contains mask of status bit(s) to be cleared.\n
 *
@@ -530,7 +530,7 @@ void I2CStatusClear(unsigned int baseAddr, unsigned int status)
 * \brief  This function indicates error if occured in I2C operation.\n
 *
 * \param  baseAddr is the Memory address of the I2C instance used.\n
-*  
+*
 * \returns 1 is error has because of above reasons,otherwise;return 0
 * i.e (error has not occured);\n
 *
@@ -546,10 +546,10 @@ unsigned int I2CMasterErr(unsigned int baseAddr)
 
 /**
 * \brief  This function Transmits a byte from the I2C in Master mode.\n
-* 
+*
 * \param baseAddr is the Memory address of the I2C instance used.\n
 * \param data data to be transmitted from the I2C Master\n
-* 
+*
 * \return None.\n
 *
 **/
@@ -561,9 +561,9 @@ void I2CMasterDataPut(unsigned int baseAddr, unsigned char data)
 
 /**
 *  \brief  This Receives a byte that has been sent to the I2C in Master mode.\n
-* 
+*
 *  \param baseAddr is the Memory address of the I2C instance used.\n
-* 
+*
 *  \return Returns the byte received from by the I2C in Master mode.\n
 *
 **/
@@ -576,10 +576,10 @@ unsigned int I2CMasterDataGet(unsigned int baseAddr)
 }
 /**
 * \brief This Transmits a byte from the I2C in Slave mode.\n
-* 
+*
 * \param baseAddr is the Memory address of the I2C Slave module.\n
 * \param data data to be transmitted from the I2C in Slave mode.\n
-* 
+*
 * \return None.\n
 *
 **/
@@ -592,11 +592,11 @@ void I2CSlaveDataPut(unsigned int baseAddr, unsigned char data)
 /**
 * \brief  This function Receives a byte that has been sent to the I2C in Slave
 *          mode.\n
-* 
+*
 * \param baseAddr is the Memory address of the I2C instace used.\n
-* 
+*
 * \return Returns the byte received from by the I2C in Slave mode\n
-* 
+*
 **/
 unsigned int I2CSlaveDataGet(unsigned int baseAddr)
 {
@@ -678,7 +678,7 @@ void I2CDMATxRxEventDisable(unsigned int baseAddr)
 **/
 void I2CDMATxEventEnable(unsigned int baseAddr)
 {
-    HWREG(baseAddr + I2C_ICDMAC) |= I2C_ICDMAC_TXDMAEN; 
+    HWREG(baseAddr + I2C_ICDMAC) |= I2C_ICDMAC_TXDMAEN;
 }
 
 /**
@@ -700,7 +700,7 @@ void I2CDMARxEventEnable(unsigned int baseAddr)
 * \param baseAddr is the Memory address of the instance used.
 *
 * \param flag     is the value which disables the transmit event of I2C
-* 
+*
 * \return None.
 *
 **/
@@ -715,7 +715,7 @@ void I2CDMATxEventDisable(unsigned int baseAddr)
 * \param baseAddr is the Memory address of the instance used.
 *
 * \param flag     is the value which disables the receiption event of I2C
-* 
+*
 * \return None.
 *
 **/
diff --git a/lib/tiam1808/drivers/mcasp.c b/lib/tiam1808/drivers/mcasp.c
index ca7b707dd..35b967520 100644
--- a/lib/tiam1808/drivers/mcasp.c
+++ b/lib/tiam1808/drivers/mcasp.c
@@ -83,16 +83,16 @@ void McASPRxReset(unsigned int baseAddr)
  *
  * \param   baseAddr      Base Address of the McASP FIFO Registers.
  * \param   numTxSer      Number of Transmit Serializers to be used.
- * \param   minWdPerSer   The minimum number of words per serializer 
+ * \param   minWdPerSer   The minimum number of words per serializer
  *                        to be available in FIFO to issue a DMA event.
  *
  * \return  None.
  *
  **/
-void McASPWriteFifoEnable(unsigned int baseAddr, unsigned int numTxSer, 
+void McASPWriteFifoEnable(unsigned int baseAddr, unsigned int numTxSer,
                           unsigned int minWdPerSer)
 {
-    HWREG(baseAddr + MCASP_FIFO_WFIFOCTL) = numTxSer | 
+    HWREG(baseAddr + MCASP_FIFO_WFIFOCTL) = numTxSer |
                                             ((minWdPerSer * numTxSer)
                                              << AFIFO_WFIFOCTL_WNUMEVT_SHIFT);
 
@@ -107,16 +107,16 @@ void McASPWriteFifoEnable(unsigned int baseAddr, unsigned int numTxSer,
  *
  * \param   baseAddr      Base Address of the McASP FIFO Registers.
  * \param   numRxSer      Number of Receive Serializers to be used.
- * \param   minWdPerSer   The minimum number of words per serializer 
+ * \param   minWdPerSer   The minimum number of words per serializer
  *                        to be available in FIFO to issue a DMA event.
  *
  * \return  None.
  *
  **/
-void McASPReadFifoEnable(unsigned int baseAddr, unsigned int numRxSer, 
+void McASPReadFifoEnable(unsigned int baseAddr, unsigned int numRxSer,
                          unsigned int minWdPerSer)
 {
-    HWREG(baseAddr + MCASP_FIFO_RFIFOCTL) = numRxSer | 
+    HWREG(baseAddr + MCASP_FIFO_RFIFOCTL) = numRxSer |
                                             ((minWdPerSer * numRxSer)
                                              << AFIFO_RFIFOCTL_RNUMEVT_SHIFT);
 
@@ -160,7 +160,7 @@ void McASPRxFmtMaskSet(unsigned int baseAddr, unsigned int mask)
 
 /**
  * \brief   Sets the format for Transmit section of McASP with the format value
- *          input.  
+ *          input.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
  * \param   formatVal     The format to be written to the transmit section
@@ -178,7 +178,7 @@ void McASPRxFmtMaskSet(unsigned int baseAddr, unsigned int mask)
  *     3. Padding Options, which can take one of the values \n
  *            MCASP_TX_PAD_WITH_0 \n
  *            MCASP_TX_PAD_WITH_1 \n
- *            MCASP_TX_PAD_WITH_PBIT(n) - pad the extra bytes with the 
+ *            MCASP_TX_PAD_WITH_PBIT(n) - pad the extra bytes with the
  *                                        n-th pad bit \n
  *
  *     4. Transmit Slot Size, which can take one of the values \n
@@ -204,8 +204,8 @@ void McASPRxFmtMaskSet(unsigned int baseAddr, unsigned int mask)
  *            MCASP_TX_ROT_RIGHT_24BITS \n
  *            MCASP_TX_ROT_RIGHT_28BITS \n
  *
- *     For example, the reset value is 
- *      (MCASP_TX_SYNC_DELAY_0BIT | MCASP_TX_BITSTREAM_LSB_FIRST | 
+ *     For example, the reset value is
+ *      (MCASP_TX_SYNC_DELAY_0BIT | MCASP_TX_BITSTREAM_LSB_FIRST |
  *       MCASP_TX_PAD_WITH_0 | MCASP_TX_SLOTSIZE_8BITS | MCASP_TX_BUF_DMAPORT |
  *       MCASP_TX_ROT_RIGHT_NONE)
  *
@@ -215,11 +215,11 @@ void McASPRxFmtMaskSet(unsigned int baseAddr, unsigned int mask)
 void McASPTxFmtSet(unsigned int baseAddr, unsigned int formatVal)
 {
     HWREG(baseAddr + MCASP_XFMT) = formatVal;
-} 
+}
 
 /**
  * \brief   Sets the format for Receive section of McASP with the format value
- *          input.  
+ *          input.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
  * \param   formatVal     The format to be written to the Receive section
@@ -237,7 +237,7 @@ void McASPTxFmtSet(unsigned int baseAddr, unsigned int formatVal)
  *     3. Padding Options, which can take one of the values \n
  *            MCASP_RX_PAD_WITH_0 \n
  *            MCASP_RX_PAD_WITH_1 \n
- *            MCASP_RX_PAD_WITH_RPBIT(n) - pad the extra bytes with the 
+ *            MCASP_RX_PAD_WITH_RPBIT(n) - pad the extra bytes with the
  *                                         n-th pad bit \n
  *
  *     4. Receive Slot Size, which can take one of the values \n
@@ -263,8 +263,8 @@ void McASPTxFmtSet(unsigned int baseAddr, unsigned int formatVal)
  *            MCASP_RX_ROT_RIGHT_24BITS \n
  *            MCASP_RX_ROT_RIGHT_28BITS \n
  *
- *     For example, the reset value is 
- *      (MCASP_RX_SYNC_DELAY_0BIT | MCASP_RX_BITSTREAM_LSB_FIRST | 
+ *     For example, the reset value is
+ *      (MCASP_RX_SYNC_DELAY_0BIT | MCASP_RX_BITSTREAM_LSB_FIRST |
  *       MCASP_RX_PAD_WITH_0 | MCASP_RX_SLOTSIZE_8BITS | MCASP_RX_BUF_DMAPORT |
  *       MCASP_RX_ROT_RIGHT_NONE)
  *
@@ -274,10 +274,10 @@ void McASPTxFmtSet(unsigned int baseAddr, unsigned int formatVal)
 void McASPRxFmtSet(unsigned int baseAddr, unsigned int formatVal)
 {
     HWREG(baseAddr + MCASP_RFMT) = formatVal;
-} 
+}
 
 /**
- * \brief   Sets the I2S format in the Transmit Format unit. 
+ * \brief   Sets the I2S format in the Transmit Format unit.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
  * \param   wordSize      The word size in bits.
@@ -285,29 +285,29 @@ void McASPRxFmtSet(unsigned int baseAddr, unsigned int formatVal)
  * \param   txMode        The mode of Transmission.
  *             txMode can take one of the values \n
  *                  MCASP_TX_MODE_NON_DMA - transmission without using DMA \n
- *                  MCASP_TX_MODE_DMA - DMA is used for transmission 
+ *                  MCASP_TX_MODE_DMA - DMA is used for transmission
  *
  * \return  None.
- * 
+ *
  *  Note : The Frame Sync shall be separately configured for I2S.
  *         It is assumed that the word size is a multiple of 8.
  *
  **/
-void McASPTxFmtI2SSet(unsigned int baseAddr, unsigned int wordSize, 
+void McASPTxFmtI2SSet(unsigned int baseAddr, unsigned int wordSize,
                       unsigned int slotSize, unsigned int txMode)
-{  
+{
     /* Set the mask assuming integer format */
     McASPTxFmtMaskSet(baseAddr, (1 << wordSize) - 1);
 
     /* Set the transmit format unit for I2S */
-    McASPTxFmtSet(baseAddr, (MCASP_TX_PAD_WITH_0 | MCASP_TX_BITSTREAM_MSB_FIRST 
+    McASPTxFmtSet(baseAddr, (MCASP_TX_PAD_WITH_0 | MCASP_TX_BITSTREAM_MSB_FIRST
                              | MCASP_TX_SYNC_DELAY_1BIT | (wordSize >> 2)
                              | ((slotSize/2 -1) << MCASP_XFMT_XSSZ_SHIFT)
                              | txMode));
 }
 
 /**
- * \brief   Sets the I2S format in the Receive Format unit. 
+ * \brief   Sets the I2S format in the Receive Format unit.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
  * \param   wordSize      The word size in bits.
@@ -318,19 +318,19 @@ void McASPTxFmtI2SSet(unsigned int baseAddr, unsigned int wordSize,
  *                  MCASP_RX_MODE_DMA - DMA is used for reception
  *
  * \return  None.
- * 
+ *
  *  Note : The Frame Sync shall be separately configured for I2S.
  *         It is assumed that the word size is a multiple of 8.
  *
  **/
-void McASPRxFmtI2SSet(unsigned int baseAddr, unsigned int wordSize, 
+void McASPRxFmtI2SSet(unsigned int baseAddr, unsigned int wordSize,
                       unsigned int slotSize, unsigned int rxMode)
-{  
+{
     /* Set the mask assuming integer format */
     McASPRxFmtMaskSet(baseAddr, (1 << wordSize) - 1);
 
     /* Set the receive format unit for I2S */
-    McASPRxFmtSet(baseAddr, (MCASP_RX_PAD_WITH_0 | MCASP_RX_BITSTREAM_MSB_FIRST 
+    McASPRxFmtSet(baseAddr, (MCASP_RX_PAD_WITH_0 | MCASP_RX_BITSTREAM_MSB_FIRST
                              | MCASP_RX_SYNC_DELAY_1BIT | (wordSize >> 2)
                              | ((slotSize/2 -1) << MCASP_RFMT_RSSZ_SHIFT)
                              | rxMode));
@@ -358,14 +358,14 @@ void McASPRxFmtI2SSet(unsigned int baseAddr, unsigned int wordSize,
  *         MCASP_TX_FS_INT_BEGIN_ON_FALL_EDGE - fs source is internal \n
  *         MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE - fs source is external \n
  *         MCASP_TX_FS_EXT_BEGIN_ON_FALL_EDGE - fs source is external \n
- *   
+ *
  * \return  None.
  *
  **/
-void McASPTxFrameSyncCfg(unsigned int baseAddr, unsigned int fsMode, 
+void McASPTxFrameSyncCfg(unsigned int baseAddr, unsigned int fsMode,
                          unsigned int fsWidth, unsigned int fsSetting)
 {
-    HWREG(baseAddr + MCASP_AFSXCTL) = ((fsMode << MCASP_AFSXCTL_XMOD_SHIFT) 
+    HWREG(baseAddr + MCASP_AFSXCTL) = ((fsMode << MCASP_AFSXCTL_XMOD_SHIFT)
                                        | fsWidth | fsSetting);
 }
 
@@ -391,23 +391,23 @@ void McASPTxFrameSyncCfg(unsigned int baseAddr, unsigned int fsMode,
  *         MCASP_RX_FS_INT_BEGIN_ON_FALL_EDGE - fs source is internal \n
  *         MCASP_RX_FS_EXT_BEGIN_ON_RIS_EDGE - fs source is external \n
  *         MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE - fs source is external \n
- *   
+ *
  * \return  None.
  *
  **/
-void McASPRxFrameSyncCfg(unsigned int baseAddr, unsigned int fsMode, 
+void McASPRxFrameSyncCfg(unsigned int baseAddr, unsigned int fsMode,
                          unsigned int fsWidth, unsigned int fsSetting)
 {
-    HWREG(baseAddr + MCASP_AFSRCTL) = ((fsMode << MCASP_AFSRCTL_RMOD_SHIFT) 
+    HWREG(baseAddr + MCASP_AFSRCTL) = ((fsMode << MCASP_AFSRCTL_RMOD_SHIFT)
                                        | fsWidth | fsSetting);
 }
 
 /**
  * \brief   Configures the clock for the Transmit Section for outputing bits.
- *          The source and divide values shall be pre-determined. 
+ *          The source and divide values shall be pre-determined.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
- * \param   clkSrc        The source of the clock 
+ * \param   clkSrc        The source of the clock
  * \param   mixClkDiv     Value which divides the mixed clock
  * \param   auxClkDiv     Value which divides the internal high frequency clock
  *
@@ -419,7 +419,7 @@ void McASPRxFrameSyncCfg(unsigned int baseAddr, unsigned int fsMode,
  * \return  None.
  *
  * Note: If external clock is selected, the divide values will not be used. \n
- *       If mixed clock is selected, the clock divide mixClkDiv only 
+ *       If mixed clock is selected, the clock divide mixClkDiv only
  *       will be used. \n
  *       If internal clock is selected, both the divide values will be used.
  *
@@ -427,11 +427,11 @@ void McASPRxFrameSyncCfg(unsigned int baseAddr, unsigned int fsMode,
 void McASPTxClkCfg(unsigned int baseAddr, unsigned int clkSrc,
                    unsigned int mixClkDiv, unsigned int auxClkDiv)
 {
-    HWREG(baseAddr + MCASP_ACLKXCTL) &= ~(MCASP_ACLKXCTL_CLKXM 
+    HWREG(baseAddr + MCASP_ACLKXCTL) &= ~(MCASP_ACLKXCTL_CLKXM
                                           | MCASP_ACLKXCTL_CLKXDIV);
     HWREG(baseAddr + MCASP_AHCLKXCTL) &= ~(MCASP_AHCLKXCTL_HCLKXM
                                            | MCASP_AHCLKXCTL_HCLKXDIV);
- 
+
     /* Set the clock source to chose internal/external with clkdiv */
     HWREG(baseAddr + MCASP_ACLKXCTL) |= ((clkSrc & MCASP_ACLKXCTL_CLKXM)
                                           | mixClkDiv);
@@ -441,10 +441,10 @@ void McASPTxClkCfg(unsigned int baseAddr, unsigned int clkSrc,
 
 /**
  * \brief   Configures the clock for the Receive Section for receiving bits.
- *          The source and divide values shall be pre-determined. 
+ *          The source and divide values shall be pre-determined.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
- * \param   clkSrc        The source of the clock 
+ * \param   clkSrc        The source of the clock
  * \param   mixClkDiv     Value which divides the mixed clock
  * \param   auxClkDiv     Value which divides the internal high frequency clock
  *
@@ -456,7 +456,7 @@ void McASPTxClkCfg(unsigned int baseAddr, unsigned int clkSrc,
  * \return  None.
  *
  * Note: If external clock is selected, the divide values will not be used. \n
- *       If mixed clock is selected, the clock divide mixClkDiv only 
+ *       If mixed clock is selected, the clock divide mixClkDiv only
  *       will be used. \n
  *       If internal clock is selected, both the divide values will be used.
  *
@@ -464,11 +464,11 @@ void McASPTxClkCfg(unsigned int baseAddr, unsigned int clkSrc,
 void McASPRxClkCfg(unsigned int baseAddr, unsigned int clkSrc,
                    unsigned int mixClkDiv, unsigned int auxClkDiv)
 {
-    HWREG(baseAddr + MCASP_ACLKRCTL) &= ~(MCASP_ACLKRCTL_CLKRM 
+    HWREG(baseAddr + MCASP_ACLKRCTL) &= ~(MCASP_ACLKRCTL_CLKRM
                                           | MCASP_ACLKRCTL_CLKRDIV);
     HWREG(baseAddr + MCASP_AHCLKRCTL) &= ~(MCASP_AHCLKRCTL_HCLKRM
                                            | MCASP_AHCLKRCTL_HCLKRDIV);
- 
+
     /* Set the clock source to chose internal/external with clkdiv */
     HWREG(baseAddr + MCASP_ACLKRCTL) |= ((clkSrc & MCASP_ACLKRCTL_CLKRM)
                                           | mixClkDiv);
@@ -478,8 +478,8 @@ void McASPRxClkCfg(unsigned int baseAddr, unsigned int clkSrc,
 
 /**
  * \brief   Sets the polarity of the Transmitter Clock. If an external receiver
- *          samples data on the falling edge of the serial clock,  the 
- *          transmitter  must shift data out on the rising edge of the 
+ *          samples data on the falling edge of the serial clock,  the
+ *          transmitter  must shift data out on the rising edge of the
  *          serial clock and vice versa.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
@@ -500,8 +500,8 @@ void McASPTxClkPolaritySet(unsigned int baseAddr, unsigned int polarity)
 
 /**
  * \brief   Sets the polarity of the Rceiver Clock. If an external receiver
- *          shifts data on the falling edge of the serial clock,  the 
- *          receiver  must sample the data on the rising edge of the 
+ *          shifts data on the falling edge of the serial clock,  the
+ *          receiver  must sample the data on the rising edge of the
  *          serial clock and vice versa.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
@@ -530,7 +530,7 @@ void McASPRxClkPolaritySet(unsigned int baseAddr, unsigned int polarity)
  *    polarity can take the values \n
  *         MCASP_TX_HI_FREQ_CLK_INVERT \n
  *         MCASP_TX_HI_FREQ_CLK_NO_INVERT \n
- *     
+ *
  * \return  None.
  *
  **/
@@ -550,7 +550,7 @@ void McASPTxHFClkPolaritySet(unsigned int baseAddr, unsigned int polarity)
  *    polarity can take the values \n
  *         MCASP_RX_HI_FREQ_CLK_INVERT \n
  *         MCASP_RX_HI_FREQ_CLK_NO_INVERT \n
- *     
+ *
  * \return  None.
  *
  **/
@@ -561,7 +561,7 @@ void McASPRxHFClkPolaritySet(unsigned int baseAddr, unsigned int polarity)
 }
 
 /**
- * \brief   Synchronizes the transmitter and receiver Clocks 
+ * \brief   Synchronizes the transmitter and receiver Clocks
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
  *
@@ -599,7 +599,7 @@ void McASPSerializerTxSet(unsigned int baseAddr, unsigned int serNum)
 {
     HWREG(baseAddr + MCASP_SRCTL(serNum)) &=  ~MCASP_SRCTL0_SRMOD;
     HWREG(baseAddr + MCASP_SRCTL(serNum)) |=  MCASP_SRCTL_SRMOD_TX;
- 
+
 }
 
 /**
@@ -639,20 +639,20 @@ void McASPSerializerInactivate(unsigned int baseAddr, unsigned int serNum)
  * \param   pinMask       Mask of the pins to be configured as GPIO.
  *            pinMask can be a combination of the below values \n
  *                MCASP_PIN_AFSR  \n
- *                MCASP_PIN_AHCLKR \n                                       
- *                MCASP_PIN_ACLKR \n                                       
- *                MCASP_PIN_AFSX \n                                       
- *                MCASP_PIN_AHCLKX \n                                       
- *                MCASP_PIN_ACLKX \n                                        
- *                MCASP_PIN_AMUTE \n                                       
- *                MCASP_PIN_AXR(n) - For serializer 'n'           
- *    
+ *                MCASP_PIN_AHCLKR \n
+ *                MCASP_PIN_ACLKR \n
+ *                MCASP_PIN_AFSX \n
+ *                MCASP_PIN_AHCLKX \n
+ *                MCASP_PIN_ACLKX \n
+ *                MCASP_PIN_AMUTE \n
+ *                MCASP_PIN_AXR(n) - For serializer 'n'
+ *
  * \return  None.
  *
  **/
 void McASPPinGPIOSet(unsigned int baseAddr, unsigned int pinMask)
 {
-     HWREG(baseAddr + MCASP_PFUNC) |= pinMask; 
+     HWREG(baseAddr + MCASP_PFUNC) |= pinMask;
 }
 
 /**
@@ -662,20 +662,20 @@ void McASPPinGPIOSet(unsigned int baseAddr, unsigned int pinMask)
  * \param   pinMask       Mask of the pins to be configured for McASP.
  *            pinMask can be a combination of the below values \n
  *                MCASP_PIN_AFSR  \n
- *                MCASP_PIN_AHCLKR \n                                       
- *                MCASP_PIN_ACLKR \n                                       
- *                MCASP_PIN_AFSX \n                                       
- *                MCASP_PIN_AHCLKX \n                                       
- *                MCASP_PIN_ACLKX \n                                        
- *                MCASP_PIN_AMUTE \n                                       
- *                MCASP_PIN_AXR(n) - For serializer 'n'           
+ *                MCASP_PIN_AHCLKR \n
+ *                MCASP_PIN_ACLKR \n
+ *                MCASP_PIN_AFSX \n
+ *                MCASP_PIN_AHCLKX \n
+ *                MCASP_PIN_ACLKX \n
+ *                MCASP_PIN_AMUTE \n
+ *                MCASP_PIN_AXR(n) - For serializer 'n'
  *
  * \return  None.
  *
  **/
 void McASPPinMcASPSet(unsigned int baseAddr, unsigned int pinMask)
 {
-     HWREG(baseAddr + MCASP_PFUNC) &= ~pinMask; 
+     HWREG(baseAddr + MCASP_PFUNC) &= ~pinMask;
 }
 
 /**
@@ -685,20 +685,20 @@ void McASPPinMcASPSet(unsigned int baseAddr, unsigned int pinMask)
  * \param   pinMask       Mask of the pins to be configured as output
  *            pinMask can be a combination of the below values \n
  *                MCASP_PIN_AFSR  \n
- *                MCASP_PIN_AHCLKR \n                                       
- *                MCASP_PIN_ACLKR \n                                       
- *                MCASP_PIN_AFSX \n                                       
- *                MCASP_PIN_AHCLKX \n                                       
- *                MCASP_PIN_ACLKX \n                                        
- *                MCASP_PIN_AMUTE \n                                       
- *                MCASP_PIN_AXR(n) - For serializer 'n'           
+ *                MCASP_PIN_AHCLKR \n
+ *                MCASP_PIN_ACLKR \n
+ *                MCASP_PIN_AFSX \n
+ *                MCASP_PIN_AHCLKX \n
+ *                MCASP_PIN_ACLKX \n
+ *                MCASP_PIN_AMUTE \n
+ *                MCASP_PIN_AXR(n) - For serializer 'n'
  *
  * \return  None.
  *
  **/
 void McASPPinDirOutputSet(unsigned int baseAddr, unsigned int pinMask)
 {
-     HWREG(baseAddr + MCASP_PDIR) |= pinMask; 
+     HWREG(baseAddr + MCASP_PDIR) |= pinMask;
 }
 
 /**
@@ -708,52 +708,52 @@ void McASPPinDirOutputSet(unsigned int baseAddr, unsigned int pinMask)
  * \param   pinMask       Mask of the pins to be configured as input
  *            pinMask can be a combination of the below values \n
  *                MCASP_PIN_AFSR  \n
- *                MCASP_PIN_AHCLKR \n                                       
- *                MCASP_PIN_ACLKR \n                                       
- *                MCASP_PIN_AFSX \n                                       
- *                MCASP_PIN_AHCLKX \n                                       
- *                MCASP_PIN_ACLKX \n                                        
- *                MCASP_PIN_AMUTE \n                                       
- *                MCASP_PIN_AXR(n) - For serializer 'n'           
+ *                MCASP_PIN_AHCLKR \n
+ *                MCASP_PIN_ACLKR \n
+ *                MCASP_PIN_AFSX \n
+ *                MCASP_PIN_AHCLKX \n
+ *                MCASP_PIN_ACLKX \n
+ *                MCASP_PIN_AMUTE \n
+ *                MCASP_PIN_AXR(n) - For serializer 'n'
  *
  * \return  None.
  *
  **/
 void McASPPinDirInputSet(unsigned int baseAddr, unsigned int pinMask)
 {
-     HWREG(baseAddr + MCASP_PDIR) &= ~pinMask; 
+     HWREG(baseAddr + MCASP_PDIR) &= ~pinMask;
 }
 
 /**
  * \brief   Sets the active time slot for the Transmitter section. The
  *          bit which is set in the mask will indicate that data will be
- *          transmitted during that time slot. 
+ *          transmitted during that time slot.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
- * \param   slotMask      The time slot mask. 
+ * \param   slotMask      The time slot mask.
  *
  * \return  None.
  *
  **/
 void McASPTxTimeSlotSet(unsigned int baseAddr, unsigned int slotMask)
 {
-     HWREG(baseAddr + MCASP_XTDM) = slotMask; 
+     HWREG(baseAddr + MCASP_XTDM) = slotMask;
 }
 
 /**
  * \brief   Sets the active time slot for the receiver section. The
  *          bit which is set in the mask will indicate that data will be
- *          shifted in during that time slot. 
+ *          shifted in during that time slot.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
- * \param   slotMask      The time slot mask. 
+ * \param   slotMask      The time slot mask.
  *
  * \return  None.
  *
  **/
 void McASPRxTimeSlotSet(unsigned int baseAddr, unsigned int slotMask)
 {
-     HWREG(baseAddr + MCASP_RTDM) = slotMask; 
+     HWREG(baseAddr + MCASP_RTDM) = slotMask;
 }
 
 
@@ -774,7 +774,7 @@ void McASPRxTimeSlotSet(unsigned int baseAddr, unsigned int slotMask)
  *                MCASP_AMUTE_RX_OVERRUN \n
  *            pinState can take one of the values \n
  *                MCASP_AMUTE_PIN_HIGH \n
- *                MCASP_AMUTE_PIN_LOW 
+ *                MCASP_AMUTE_PIN_LOW
  *
  * \return  None.
  *
@@ -782,7 +782,7 @@ void McASPRxTimeSlotSet(unsigned int baseAddr, unsigned int slotMask)
 void McASPAMuteEnable(unsigned int baseAddr, unsigned int errFlags,
                         unsigned int pinState)
 {
-    HWREG(baseAddr + MCASP_AMUTE) = errFlags | (MCASP_AMUTE_MUTEN & pinState); 
+    HWREG(baseAddr + MCASP_AMUTE) = errFlags | (MCASP_AMUTE_MUTEN & pinState);
 }
 
 /**
@@ -808,15 +808,15 @@ void McASPAMuteDisable(unsigned int baseAddr)
  * \param   boundMin      Transmit clock minimum boundary
  * \param   boundMax      Transmit clock maximum boundary
  *            clkDiv can take one of the following values \n
- *               MCASP_TX_CLKCHCK_DIV1 \n  
- *               MCASP_TX_CLKCHCK_DIV2 \n  
- *               MCASP_TX_CLKCHCK_DIV4 \n  
- *               MCASP_TX_CLKCHCK_DIV8 \n  
- *               MCASP_TX_CLKCHCK_DIV16 \n  
- *               MCASP_TX_CLKCHCK_DIV32 \n  
- *               MCASP_TX_CLKCHCK_DIV64 \n  
- *               MCASP_TX_CLKCHCK_DIV128 \n  
- *               MCASP_TX_CLKCHCK_DIV256  
+ *               MCASP_TX_CLKCHCK_DIV1 \n
+ *               MCASP_TX_CLKCHCK_DIV2 \n
+ *               MCASP_TX_CLKCHCK_DIV4 \n
+ *               MCASP_TX_CLKCHCK_DIV8 \n
+ *               MCASP_TX_CLKCHCK_DIV16 \n
+ *               MCASP_TX_CLKCHCK_DIV32 \n
+ *               MCASP_TX_CLKCHCK_DIV64 \n
+ *               MCASP_TX_CLKCHCK_DIV128 \n
+ *               MCASP_TX_CLKCHCK_DIV256
  *
  * \return  None.
  *
@@ -825,7 +825,7 @@ void McASPTxClkCheckConfig(unsigned int baseAddr, unsigned int clkDiv,
                            unsigned char boundMin, unsigned char boundMax)
 {
     HWREG(baseAddr + MCASP_XCLKCHK) = clkDiv
-                                      | boundMin << MCASP_XCLKCHK_XMIN_SHIFT 
+                                      | boundMin << MCASP_XCLKCHK_XMIN_SHIFT
                                       | boundMax << MCASP_XCLKCHK_XMAX_SHIFT ;
 }
 
@@ -839,15 +839,15 @@ void McASPTxClkCheckConfig(unsigned int baseAddr, unsigned int clkDiv,
  * \param   boundMin      Receive clock minimum boundary
  * \param   boundMax      Receive clock maximum boundary
  *            clkDiv can take one of the following values \n
- *               MCASP_RX_CLKCHCK_DIV1 \n  
- *               MCASP_RX_CLKCHCK_DIV2 \n  
- *               MCASP_RX_CLKCHCK_DIV4 \n  
- *               MCASP_RX_CLKCHCK_DIV8 \n  
- *               MCASP_RX_CLKCHCK_DIV16 \n  
- *               MCASP_RX_CLKCHCK_DIV32 \n  
- *               MCASP_RX_CLKCHCK_DIV64 \n  
- *               MCASP_RX_CLKCHCK_DIV128 \n  
- *               MCASP_RX_CLKCHCK_DIV256  
+ *               MCASP_RX_CLKCHCK_DIV1 \n
+ *               MCASP_RX_CLKCHCK_DIV2 \n
+ *               MCASP_RX_CLKCHCK_DIV4 \n
+ *               MCASP_RX_CLKCHCK_DIV8 \n
+ *               MCASP_RX_CLKCHCK_DIV16 \n
+ *               MCASP_RX_CLKCHCK_DIV32 \n
+ *               MCASP_RX_CLKCHCK_DIV64 \n
+ *               MCASP_RX_CLKCHCK_DIV128 \n
+ *               MCASP_RX_CLKCHCK_DIV256
  *
  * \return  None.
  *
@@ -856,7 +856,7 @@ void McASPRxClkCheckConfig(unsigned int baseAddr, unsigned int clkDiv,
                            unsigned char boundMin, unsigned char boundMax)
 {
     HWREG(baseAddr + MCASP_RCLKCHK) = clkDiv
-                                      | boundMin << MCASP_RCLKCHK_RMIN_SHIFT 
+                                      | boundMin << MCASP_RCLKCHK_RMIN_SHIFT
                                       | boundMax << MCASP_RCLKCHK_RMAX_SHIFT ;
 }
 
@@ -864,12 +864,12 @@ void McASPRxClkCheckConfig(unsigned int baseAddr, unsigned int clkDiv,
  * \brief   Activates the AMUTEIN pin and drives the AMUTE active.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
- * \param   polarity      polarity of AMUTEIN which shall drive the 
- *                        AMUTE active. 
+ * \param   polarity      polarity of AMUTEIN which shall drive the
+ *                        AMUTE active.
  *            polarity can take one of the following values. \n
  *                MCASP_AMUTEIN_POL_HIGH - high on AMUTEIN pin  \n
- *                MCASP_AMUTEIN_POL_LOW - low on AMUTEIN pin 
- *             
+ *                MCASP_AMUTEIN_POL_LOW - low on AMUTEIN pin
+ *
  * \return  None.
  *
  **/
@@ -878,14 +878,14 @@ void McASPAMUTEINActivate(unsigned int baseAddr, unsigned int polarity)
     HWREG(baseAddr + MCASP_AMUTE) &= ~MCASP_AMUTE_INPOL;
 
     HWREG(baseAddr + MCASP_AMUTE) |= (MCASP_AMUTE_INSTAT | MCASP_AMUTE_INEN
-                                      |(polarity & MCASP_AMUTE_INPOL)); 
+                                      |(polarity & MCASP_AMUTE_INPOL));
 }
 
 /**
  * \brief   Enables the specified Transmitter interrupts.
  *
  * \param   baseAddr     Base Address of the McASP Module Registers.
- * \param   intMask      The transmitter interrupts to be enabled 
+ * \param   intMask      The transmitter interrupts to be enabled
  *            intMask can be a logical OR combination of the values \n
  *                 MCASP_TX_STARTOFFRAME \n
  *                 MCASP_TX_DATAREADY \n
@@ -900,14 +900,14 @@ void McASPAMUTEINActivate(unsigned int baseAddr, unsigned int polarity)
  **/
 void McASPTxIntEnable(unsigned int baseAddr, unsigned int intMask)
 {
-    HWREG(baseAddr + MCASP_XINTCTL) |= intMask; 
+    HWREG(baseAddr + MCASP_XINTCTL) |= intMask;
 }
 
 /**
  * \brief   Enables the specified Receiver interrupts.
  *
  * \param   baseAddr     Base Address of the McASP Module Registers.
- * \param   intMask      The receive interrupts to be enabled 
+ * \param   intMask      The receive interrupts to be enabled
  *            intMask can be a logical OR combination of the values \n
  *                 MCASP_RX_STARTOFFRAME \n
  *                 MCASP_RX_DATAREADY \n
@@ -922,14 +922,14 @@ void McASPTxIntEnable(unsigned int baseAddr, unsigned int intMask)
  **/
 void McASPRxIntEnable(unsigned int baseAddr, unsigned int intMask)
 {
-    HWREG(baseAddr + MCASP_RINTCTL) |= intMask; 
+    HWREG(baseAddr + MCASP_RINTCTL) |= intMask;
 }
 
 /**
  * \brief   Disables the specified Transmitter interrupts.
  *
  * \param   baseAddr     Base Address of the McASP Module Registers.
- * \param   intMask      The transmitter interrupts to be disabled 
+ * \param   intMask      The transmitter interrupts to be disabled
  *            intMask can be a logical OR combination of the values \n
  *                 MCASP_TX_STARTOFFRAME \n
  *                 MCASP_TX_DATAREADY \n
@@ -944,14 +944,14 @@ void McASPRxIntEnable(unsigned int baseAddr, unsigned int intMask)
  **/
 void McASPTxIntDisable(unsigned int baseAddr, unsigned int intMask)
 {
-    HWREG(baseAddr + MCASP_XINTCTL) &= ~intMask; 
+    HWREG(baseAddr + MCASP_XINTCTL) &= ~intMask;
 }
 
 /**
  * \brief   Disables the specified Receiver interrupts.
  *
  * \param   baseAddr     Base Address of the McASP Module Registers.
- * \param   intMask      The receive interrupts to be disabled 
+ * \param   intMask      The receive interrupts to be disabled
  *            intMask can be a logical OR combination of the values \n
  *                 MCASP_RX_STARTOFFRAME \n
  *                 MCASP_RX_DATAREADY \n
@@ -966,7 +966,7 @@ void McASPTxIntDisable(unsigned int baseAddr, unsigned int intMask)
  **/
 void McASPRxIntDisable(unsigned int baseAddr, unsigned int intMask)
 {
-    HWREG(baseAddr + MCASP_RINTCTL) &= ~intMask; 
+    HWREG(baseAddr + MCASP_RINTCTL) &= ~intMask;
 }
 
 /**
@@ -982,8 +982,8 @@ void McASPTxSerActivate(unsigned int baseAddr)
     HWREG(baseAddr + MCASP_XSTAT) = 0xFFFF;
 
     /* Release transmit serializers from reset*/
-    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XSRCLR; 
-    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XSRCLR) 
+    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XSRCLR;
+    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XSRCLR)
           != MCASP_GBLCTL_XSRCLR) ;
 }
 
@@ -1000,13 +1000,13 @@ void McASPRxSerActivate(unsigned int baseAddr)
     HWREG(baseAddr + MCASP_RSTAT) = 0xFFFF;
 
     /* Release transmit serializers from reset*/
-    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_RSRCLR; 
-    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_RSRCLR) 
+    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_RSRCLR;
+    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_RSRCLR)
           != MCASP_GBLCTL_RSRCLR) ;
 }
 
 /**
- * \brief   Starts the McASP Transmitter Clock. 
+ * \brief   Starts the McASP Transmitter Clock.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
  * \param   clkSrc        The transmitter clock source.
@@ -1022,21 +1022,21 @@ void McASPRxSerActivate(unsigned int baseAddr)
 void McASPTxClkStart(unsigned int baseAddr, unsigned int clkSrc)
 {
     /* Release the high frequency clock from reset*/
-    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XHCLKRST; 
-    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XHCLKRST) 
+    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XHCLKRST;
+    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XHCLKRST)
           != MCASP_GBLCTL_XHCLKRST) ;
-     
+
     if(clkSrc != MCASP_TX_CLK_EXTERNAL)
     {
        /* Release the clock from reset*/
-        HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XCLKRST; 
-        while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XCLKRST) 
+        HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XCLKRST;
+        while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XCLKRST)
               != MCASP_GBLCTL_XCLKRST) ;
     }
 }
 
 /**
- * \brief   Starts the McASP Receiver Clock. 
+ * \brief   Starts the McASP Receiver Clock.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
  * \param   clkSrc        The receiver clock source.
@@ -1052,22 +1052,22 @@ void McASPTxClkStart(unsigned int baseAddr, unsigned int clkSrc)
 void McASPRxClkStart(unsigned int baseAddr, unsigned int clkSrc)
 {
     /* Release the high frequency clock from reset*/
-    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_RHCLKRST; 
-    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_RHCLKRST) 
+    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_RHCLKRST;
+    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_RHCLKRST)
           != MCASP_GBLCTL_RHCLKRST) ;
-     
+
     if(clkSrc != MCASP_RX_CLK_EXTERNAL)
     {
         /* Release the clock from reset*/
-        HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_RCLKRST; 
+        HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_RCLKRST;
         while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_RCLKRST)
               != MCASP_GBLCTL_RCLKRST) ;
     }
 }
 
 /**
- * \brief   Enables the McASP Transmission. When this API is called, 
- *          The transmit state machine and the frame sync generators are 
+ * \brief   Enables the McASP Transmission. When this API is called,
+ *          The transmit state machine and the frame sync generators are
  *          released from reset. The McASP starts transmission on the
  *          first frame sync after this.
  *
@@ -1079,19 +1079,19 @@ void McASPRxClkStart(unsigned int baseAddr, unsigned int clkSrc)
 void McASPTxEnable(unsigned int baseAddr)
 {
     /* Release the Transmit State machine from reset*/
-    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XSMRST; 
-    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XSMRST) 
+    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XSMRST;
+    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XSMRST)
           != MCASP_GBLCTL_XSMRST) ;
-     
+
     /* Release the frame sync generator from reset*/
-    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XFRST; 
-    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XFRST) 
+    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_XFRST;
+    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XFRST)
           != MCASP_GBLCTL_XFRST) ;
 }
 
 /**
- * \brief   Enables the McASP Reception. When this API is called, 
- *          The receive state machine and the frame sync generators are 
+ * \brief   Enables the McASP Reception. When this API is called,
+ *          The receive state machine and the frame sync generators are
  *          released from reset. The McASP starts reception on the
  *          first frame sync after this.
  *
@@ -1103,18 +1103,18 @@ void McASPTxEnable(unsigned int baseAddr)
 void McASPRxEnable(unsigned int baseAddr)
 {
     /* Release the Receive State machine from reset*/
-    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_RSMRST; 
-    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_RSMRST) 
+    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_RSMRST;
+    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_RSMRST)
           != MCASP_GBLCTL_RSMRST) ;
-     
+
     /* Release the frame sync generator from reset*/
-    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_RFRST; 
-    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_RFRST) 
+    HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_RFRST;
+    while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_RFRST)
           != MCASP_GBLCTL_RFRST) ;
 }
 
 /**
- * \brief   Reads a receive buffer through peripheral configuration port. 
+ * \brief   Reads a receive buffer through peripheral configuration port.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
  * \param   serNum        Serializer number
@@ -1128,7 +1128,7 @@ unsigned int McASPRxBufRead(unsigned int baseAddr, unsigned int serNum)
 }
 
 /**
- * \brief   Writes to a transmit buffer through peripheral configuration port. 
+ * \brief   Writes to a transmit buffer through peripheral configuration port.
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
  * \param   serNum        Serializer number
@@ -1137,7 +1137,7 @@ unsigned int McASPRxBufRead(unsigned int baseAddr, unsigned int serNum)
  * \return  None.
  *
  **/
-void McASPTxBufWrite(unsigned int baseAddr, unsigned int serNum, 
+void McASPTxBufWrite(unsigned int baseAddr, unsigned int serNum,
                      unsigned int data)
 {
     HWREG(baseAddr + MCASP_XBUF(serNum)) = data;
@@ -1151,9 +1151,9 @@ void McASPTxBufWrite(unsigned int baseAddr, unsigned int serNum,
  *                        time slots.
  *             vBit can take one of the following values \n
  *                MCASP_DIT_VBIT_ODD_0_EVEN_1 - V bit is 0 for odd slots
- *                                              and 1 for even slots  \n    
+ *                                              and 1 for even slots  \n
  *                MCASP_DIT_VBIT_ODD_1_EVEN_0 - V bit is 1 for odd slots
- *                                              and 0 for even slots  \n    
+ *                                              and 0 for even slots  \n
  *                MCASP_DIT_VBIT_BOTHSLOTS_0 - V bit is 0 for both slots \n
  *                MCASP_DIT_VBIT_BOTHSLOTS_1 - V bit is 1 for both slots
  * \return  None.
@@ -1185,22 +1185,22 @@ void McASPDITDisable(unsigned int baseAddr)
  * \param   channel       Channel of which status bits to be written
  * \param   data          Data to be written
  *            chStatBits can take one of the following values \n
- *                MCASP_DIT_CHSTAT_BITS_0_31 \n 
- *                MCASP_DIT_CHSTAT_BITS_32_63 \n 
- *                MCASP_DIT_CHSTAT_BITS_64_95 \n 
- *                MCASP_DIT_CHSTAT_BITS_96_127 \n 
- *                MCASP_DIT_CHSTAT_BITS_128_159 \n 
+ *                MCASP_DIT_CHSTAT_BITS_0_31 \n
+ *                MCASP_DIT_CHSTAT_BITS_32_63 \n
+ *                MCASP_DIT_CHSTAT_BITS_64_95 \n
+ *                MCASP_DIT_CHSTAT_BITS_96_127 \n
+ *                MCASP_DIT_CHSTAT_BITS_128_159 \n
  *                MCASP_DIT_CHSTAT_BITS_160_191 \n
  *
  *           channel can take the following values \n
  *                MCASP_DIT_CHANNEL_LEFT - for left channel only \n
  *                MCASP_DIT_CHANNEL_RIGHT - for right channel only \n
- *                MCASP_DIT_CHANNEL_BOTH - for both channels 
+ *                MCASP_DIT_CHANNEL_BOTH - for both channels
  *
  * \return  None.
  *
  **/
-void McASPDITChanStatWrite(unsigned int baseAddr, unsigned int chStatBits, 
+void McASPDITChanStatWrite(unsigned int baseAddr, unsigned int chStatBits,
                            unsigned int channel,  unsigned int data)
 {
     /* Write for the left channel */
@@ -1224,22 +1224,22 @@ void McASPDITChanStatWrite(unsigned int baseAddr, unsigned int chStatBits,
  * \param   channel       Channel of which user data bits to be written
  * \param   data          Data to be written
  *            chStatBits can take one of the following values \n
- *                MCASP_DIT_USRDATA_BITS_0_31 \n 
- *                MCASP_DIT_USRDATA_BITS_32_63 \n 
- *                MCASP_DIT_USRDATA_BITS_64_95 \n 
- *                MCASP_DIT_USRDATA_BITS_96_127 \n 
- *                MCASP_DIT_USRDATA_BITS_128_159 \n 
+ *                MCASP_DIT_USRDATA_BITS_0_31 \n
+ *                MCASP_DIT_USRDATA_BITS_32_63 \n
+ *                MCASP_DIT_USRDATA_BITS_64_95 \n
+ *                MCASP_DIT_USRDATA_BITS_96_127 \n
+ *                MCASP_DIT_USRDATA_BITS_128_159 \n
  *                MCASP_DIT_USRDATA_BITS_160_191 \n
  *
  *           channel can take the following values \n
  *                MCASP_DIT_CHANNEL_LEFT - for left channel only \n
  *                MCASP_DIT_CHANNEL_RIGHT - for right channel only \n
- *                MCASP_DIT_CHANNEL_BOTH - for both channels 
+ *                MCASP_DIT_CHANNEL_BOTH - for both channels
  *
  * \return  None.
  *
  **/
-void McASPDITChanUsrDataWrite(unsigned int baseAddr, unsigned int chUsrDataBits, 
+void McASPDITChanUsrDataWrite(unsigned int baseAddr, unsigned int chUsrDataBits,
                               unsigned int channel,  unsigned int data)
 {
     /* Write for the left channel */
@@ -1262,22 +1262,22 @@ void McASPDITChanUsrDataWrite(unsigned int baseAddr, unsigned int chUsrDataBits,
  * \param   chStatBits    Channel status bits to be read
  * \param   channel       Channel of which status bits to be read
  *            chStatBits can take one of the following values \n
- *                MCASP_DIT_CHSTAT_BITS_0_31 \n 
- *                MCASP_DIT_CHSTAT_BITS_32_63 \n 
- *                MCASP_DIT_CHSTAT_BITS_64_95 \n 
- *                MCASP_DIT_CHSTAT_BITS_96_127 \n 
- *                MCASP_DIT_CHSTAT_BITS_128_159 \n 
+ *                MCASP_DIT_CHSTAT_BITS_0_31 \n
+ *                MCASP_DIT_CHSTAT_BITS_32_63 \n
+ *                MCASP_DIT_CHSTAT_BITS_64_95 \n
+ *                MCASP_DIT_CHSTAT_BITS_96_127 \n
+ *                MCASP_DIT_CHSTAT_BITS_128_159 \n
  *                MCASP_DIT_CHSTAT_BITS_160_191 \n
  *
  *           channel can take the following values \n
  *                MCASP_DIT_CHANNEL_LEFT  \n
- *                MCASP_DIT_CHANNEL_RIGHT 
+ *                MCASP_DIT_CHANNEL_RIGHT
  *
  * \return  DIT channel status.
  *
  **/
-unsigned int McASPDITChanStatRead(unsigned int baseAddr, 
-                                  unsigned int chStatBits, 
+unsigned int McASPDITChanStatRead(unsigned int baseAddr,
+                                  unsigned int chStatBits,
                                   unsigned int channel)
 {
     unsigned int retVal = 0;
@@ -1304,11 +1304,11 @@ unsigned int McASPDITChanStatRead(unsigned int baseAddr,
  * \param   chStatBits    Channel user data bits to be read
  * \param   channel       Channel of which user data bits to be read
  *            chStatBits can take one of the following values \n
- *                MCASP_DIT_USRDATA_BITS_0_31 \n 
- *                MCASP_DIT_USRDATA_BITS_32_63 \n 
- *                MCASP_DIT_USRDATA_BITS_64_95 \n 
- *                MCASP_DIT_USRDATA_BITS_96_127 \n 
- *                MCASP_DIT_USRDATA_BITS_128_159 \n 
+ *                MCASP_DIT_USRDATA_BITS_0_31 \n
+ *                MCASP_DIT_USRDATA_BITS_32_63 \n
+ *                MCASP_DIT_USRDATA_BITS_64_95 \n
+ *                MCASP_DIT_USRDATA_BITS_96_127 \n
+ *                MCASP_DIT_USRDATA_BITS_128_159 \n
  *                MCASP_DIT_USRDATA_BITS_160_191 \n
  *
  *           channel can take the following values \n
@@ -1318,8 +1318,8 @@ unsigned int McASPDITChanStatRead(unsigned int baseAddr,
  * \return  DIT channel user data.
  *
  **/
-unsigned int McASPDITChanUsrDataRead(unsigned int baseAddr, 
-                                     unsigned int chUsrDataBits, 
+unsigned int McASPDITChanUsrDataRead(unsigned int baseAddr,
+                                     unsigned int chUsrDataBits,
                                      unsigned int channel)
 {
     unsigned int retVal = 0;
@@ -1335,7 +1335,7 @@ unsigned int McASPDITChanUsrDataRead(unsigned int baseAddr,
     {
         retVal = HWREG(baseAddr + MCASP_DITUDRB(chUsrDataBits));
     }
-     
+
     return retVal;
 }
 
@@ -1344,19 +1344,19 @@ unsigned int McASPDITChanUsrDataRead(unsigned int baseAddr,
  *
  * \param   baseAddr      Base Address of the McASP Module Registers.
  *
- * \return  Status of McASP Transmission. This is the contents of the 
+ * \return  Status of McASP Transmission. This is the contents of the
  *          register XSTAT. \n
  *          The below tokens can be used for each status bits returned. \n
- *              MCASP_TX_STAT_ERR  \n                    
- *              MCASP_TX_STAT_DMAERR \n                  
- *              MCASP_TX_STAT_STARTOFFRAME \n             
- *              MCASP_TX_STAT_DATAREADY \n            
- *              MCASP_TX_STAT_LASTSLOT \n                
- *              MCASP_TX_STAT_CURRSLOT_EVEN \n           
- *              MCASP_TX_STAT_CURRSLOT_ODD \n             
- *              MCASP_TX_STAT_CLKFAIL \n                 
- *              MCASP_TX_STAT_SYNCERR \n                
- *              MCASP_TX_STAT_UNDERRUN               
+ *              MCASP_TX_STAT_ERR  \n
+ *              MCASP_TX_STAT_DMAERR \n
+ *              MCASP_TX_STAT_STARTOFFRAME \n
+ *              MCASP_TX_STAT_DATAREADY \n
+ *              MCASP_TX_STAT_LASTSLOT \n
+ *              MCASP_TX_STAT_CURRSLOT_EVEN \n
+ *              MCASP_TX_STAT_CURRSLOT_ODD \n
+ *              MCASP_TX_STAT_CLKFAIL \n
+ *              MCASP_TX_STAT_SYNCERR \n
+ *              MCASP_TX_STAT_UNDERRUN
  *
  **/
 unsigned int McASPTxStatusGet(unsigned int baseAddr)
@@ -1413,7 +1413,7 @@ void McASPContextSave(unsigned int baseAddrCtrl, unsigned int baseAddrFifo,
     /* Check if Transmit section context needs to be saved */
     if(McASP_CONTEXT_TX & sectFlag)
     {
-        contextPtr->fifoWfifoCtl = HWREG(baseAddrFifo + MCASP_FIFO_WFIFOCTL); 
+        contextPtr->fifoWfifoCtl = HWREG(baseAddrFifo + MCASP_FIFO_WFIFOCTL);
         contextPtr->xmask = HWREG(baseAddrCtrl + MCASP_XMASK);
         contextPtr->xfmt = HWREG(baseAddrCtrl + MCASP_XFMT);
         contextPtr->afsxctl = HWREG(baseAddrCtrl + MCASP_AFSXCTL);
@@ -1426,7 +1426,7 @@ void McASPContextSave(unsigned int baseAddrCtrl, unsigned int baseAddrFifo,
     /* Check if receive section context needs to be saved */
     if(McASP_CONTEXT_RX & sectFlag)
     {
-        contextPtr->fifoRfifoCtl = HWREG(baseAddrFifo + MCASP_FIFO_RFIFOCTL); 
+        contextPtr->fifoRfifoCtl = HWREG(baseAddrFifo + MCASP_FIFO_RFIFOCTL);
         contextPtr->rmask = HWREG(baseAddrCtrl + MCASP_RMASK);
         contextPtr->rfmt = HWREG(baseAddrCtrl + MCASP_RFMT);
         contextPtr->afsrctl = HWREG(baseAddrCtrl + MCASP_AFSRCTL);
@@ -1449,8 +1449,8 @@ void McASPContextSave(unsigned int baseAddrCtrl, unsigned int baseAddrFifo,
 /**
 * \brief  This function restores the context of McASP registers.
 *         This is useful in power management, where the power supply to McASP
-*         controller will be cut off. Note that this API does not enable McASP 
-*         clocks. Also McASP state machine shall be brought out of reset 
+*         controller will be cut off. Note that this API does not enable McASP
+*         clocks. Also McASP state machine shall be brought out of reset
 *         separately.
 *
 * \param  baseAddrCtrl     Base Address of the McASP Module Control Registers.
diff --git a/lib/tiam1808/drivers/mcspi.c b/lib/tiam1808/drivers/mcspi.c
index a4506a4e1..df08e0754 100644
--- a/lib/tiam1808/drivers/mcspi.c
+++ b/lib/tiam1808/drivers/mcspi.c
@@ -53,14 +53,14 @@
 *******************************************************************************/
 
 /**
-* \brief  This API will configure the clkD and extClk fields to generate 
-*         required spi clock depending on the type of granularity. It will 
+* \brief  This API will configure the clkD and extClk fields to generate
+*         required spi clock depending on the type of granularity. It will
 *         also set the phase and polarity of spiClk by the clkMode field.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
 * \param  spiInClk       Clock frequency given to the McSPI module.
 * \param  spiOutClk      Clock frequency on the McSPI bus.
-* \param  chNum          Channel number of the McSPI instance used. 
+* \param  chNum          Channel number of the McSPI instance used.
 * \param  clkMode        Clock mode used.\n
 *
 *         'chNum' can take the following values.\n
@@ -76,27 +76,27 @@
 * \return none.
 *
 * \note:  1) clkMode depends on phase and polarity of McSPI clock.\n
-*         2) To pass the desired value for clkMode please refer the 
+*         2) To pass the desired value for clkMode please refer the
 *            McSPI_CH(i)CONF register.\n
-*         3) Please understand the polarity and phase of the slave device 
+*         3) Please understand the polarity and phase of the slave device
 *            connected and accordingly set the clkMode.\n
-*         4) McSPIClkConfig does not have any significance in slave mode 
-*            because the clock signal required for communication is generated 
+*         4) McSPIClkConfig does not have any significance in slave mode
+*            because the clock signal required for communication is generated
 *            by the master device.
 **/
-void McSPIClkConfig(unsigned int baseAdd, unsigned int spiInClk, 
-                    unsigned int spiOutClk, unsigned int chNum, 
+void McSPIClkConfig(unsigned int baseAdd, unsigned int spiInClk,
+                    unsigned int spiOutClk, unsigned int chNum,
                     unsigned int clkMode)
 {
-    unsigned int fRatio = 0;    
+    unsigned int fRatio = 0;
     unsigned int extClk = 0;
     unsigned int clkD = 0;
 
     /* Calculate the value of fRatio. */
     fRatio = (spiInClk / spiOutClk);
- 
+
     /* If fRatio is not a power of 2, set granularity of 1 clock cycle */
-    if(0 != (fRatio & (fRatio - 1))) 
+    if(0 != (fRatio & (fRatio - 1)))
     {
         /* Set the clock granularity to 1 clock cycle.*/
         HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= MCSPI_CH0CONF_CLKG;
@@ -109,7 +109,7 @@ void McSPIClkConfig(unsigned int baseAdd, unsigned int spiInClk,
         HWREG(baseAdd + MCSPI_CHCTRL(chNum)) &= ~MCSPI_CH0CTRL_EXTCLK;
 
         /* Set the extClk field of MCSPI_CHCTRL register.*/
-        HWREG(baseAdd + MCSPI_CHCTRL(chNum)) |= (extClk << 
+        HWREG(baseAdd + MCSPI_CHCTRL(chNum)) |= (extClk <<
                                                  MCSPI_CH0CTRL_EXTCLK_SHIFT);
     }
     else
@@ -129,19 +129,19 @@ void McSPIClkConfig(unsigned int baseAdd, unsigned int spiInClk,
 
     /* Configure the clkD field of MCSPI_CHCONF register.*/
     HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (clkD << MCSPI_CH0CONF_CLKD_SHIFT);
-         
+
     /*Clearing the clkMode field of MCSPI_CHCONF register.*/
-    HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~(MCSPI_CH0CONF_PHA | 
+    HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~(MCSPI_CH0CONF_PHA |
                                                MCSPI_CH0CONF_POL);
 
     /* Configure the clkMode of MCSPI_CHCONF register.*/
-    HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (clkMode & (MCSPI_CH0CONF_PHA | 
+    HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (clkMode & (MCSPI_CH0CONF_PHA |
                                                          MCSPI_CH0CONF_POL));
 }
 
 /**
-* \brief  This API will configure the length of McSPI word used for 
-*         communication. 
+* \brief  This API will configure the length of McSPI word used for
+*         communication.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
 * \param  wordLength     Length of a data word used for McSPI communication.
@@ -160,7 +160,7 @@ void McSPIClkConfig(unsigned int baseAdd, unsigned int spiInClk,
 * \return none.
 *
 * \note:  wordLength can vary from 4-32 bits length. To program the
-*         required value of wordLength please refer the MCSPI_CH(i)CONF 
+*         required value of wordLength please refer the MCSPI_CH(i)CONF
 *         register.\n
 **/
 void McSPIWordLengthSet(unsigned int baseAdd, unsigned int wordLength,
@@ -180,13 +180,13 @@ void McSPIWordLengthSet(unsigned int baseAdd, unsigned int wordLength,
 *
 * \return none.
 *
-* \note:  Modification of CS polarity, SPI clock phase and polarity 
+* \note:  Modification of CS polarity, SPI clock phase and polarity
           is not allowed when CS is enabled.
 **/
 void McSPICSEnable(unsigned int baseAdd)
 {
     /* CLear PIN34 of MCSPI_MODULCTRL register. */
-    HWREG(baseAdd + MCSPI_MODULCTRL) &= ~MCSPI_MODULCTRL_PIN34;                 
+    HWREG(baseAdd + MCSPI_MODULCTRL) &= ~MCSPI_MODULCTRL_PIN34;
 }
 
 /**
@@ -199,7 +199,7 @@ void McSPICSEnable(unsigned int baseAdd)
 void McSPICSDisable(unsigned int baseAdd)
 {
     /* Set PIN34 of MCSPI_MODULCTRL register.*/
-    HWREG(baseAdd + MCSPI_MODULCTRL) |= MCSPI_MODULCTRL_PIN34;             
+    HWREG(baseAdd + MCSPI_MODULCTRL) |= MCSPI_MODULCTRL_PIN34;
 }
 
 /**
@@ -221,7 +221,7 @@ void McSPICSDisable(unsigned int baseAdd)
 * \return none.
 **/
 void McSPICSPolarityConfig(unsigned int baseAdd, unsigned int spiEnPol,
-                           unsigned int chNum) 
+                           unsigned int chNum)
 {
     /* Clear the EPOL field of MCSPI_CHCONF register. */
     HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~MCSPI_CH0CONF_EPOL;
@@ -256,7 +256,7 @@ void McSPICSTimeControlSet(unsigned int baseAdd, unsigned int csTimeControl,
     HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~MCSPI_CH0CONF_TCS0;
 
     /* Set the TCS field with the user sent value. */
-    HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (csTimeControl & 
+    HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (csTimeControl &
                                               MCSPI_CH0CONF_TCS0);
 }
 
@@ -307,14 +307,14 @@ void McSPICSDeAssert(unsigned int baseAdd, unsigned int chNum)
 *         'chNum' can take the following values.\n
 *         MCSPI_CHANNEL_n - Channel n is used for communication.\n
 *
-*         For chNum 0 <= n <= 3.\n  
+*         For chNum 0 <= n <= 3.\n
 *
 * \return none.
 **/
 void McSPIStartBitEnable(unsigned int baseAdd, unsigned int chNum)
 {
     /* Set the SBE bit of MCSPI_CHCONF register. */
-    HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= MCSPI_CH0CONF_SBE; 
+    HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= MCSPI_CH0CONF_SBE;
 }
 
 /**
@@ -337,14 +337,14 @@ void McSPIStartBitEnable(unsigned int baseAdd, unsigned int chNum)
 *
 * \return none.
 **/
-void McSPIStartBitPolarityConfig(unsigned int baseAdd, unsigned int startBitPol, 
+void McSPIStartBitPolarityConfig(unsigned int baseAdd, unsigned int startBitPol,
                                  unsigned int chNum)
 {
     /* Clear the SBE field of MCSPI_CHCONF register. */
-    HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~MCSPI_CH0CONF_SBPOL;     
-   
+    HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~MCSPI_CH0CONF_SBPOL;
+
     /* Set the user sent value */
-    HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (startBitPol & 
+    HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (startBitPol &
                                               MCSPI_CH0CONF_SBPOL);
 }
 
@@ -364,11 +364,11 @@ void McSPIStartBitPolarityConfig(unsigned int baseAdd, unsigned int startBitPol,
 void McSPIStartBitDisable(unsigned int baseAdd, unsigned int chNum)
 {
     /* Clear the SBE field of MCSPI_CHCONF register. */
-    HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~MCSPI_CH0CONF_SBE; 
+    HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~MCSPI_CH0CONF_SBE;
 }
 
 /**
-* \brief  This API will enable the McSPI controller in master mode.  
+* \brief  This API will enable the McSPI controller in master mode.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
 *
@@ -377,11 +377,11 @@ void McSPIStartBitDisable(unsigned int baseAdd, unsigned int chNum)
 void McSPIMasterModeEnable(unsigned int baseAdd)
 {
     /* Clear the MS field of MCSPI_MODULCTRL register. */
-    HWREG(baseAdd + MCSPI_MODULCTRL) &= ~MCSPI_MODULCTRL_MS; 
+    HWREG(baseAdd + MCSPI_MODULCTRL) &= ~MCSPI_MODULCTRL_MS;
 }
 
 /**
-* \brief  This API will enable the McSPI controller in slave mode.  
+* \brief  This API will enable the McSPI controller in slave mode.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
 *
@@ -390,18 +390,18 @@ void McSPIMasterModeEnable(unsigned int baseAdd)
 void McSPISlaveModeEnable(unsigned int baseAdd)
 {
     /* Set the MS field of MCSPI_MODULCTRL register. */
-    HWREG(baseAdd + MCSPI_MODULCTRL) |= MCSPI_MODULCTRL_MS; 
+    HWREG(baseAdd + MCSPI_MODULCTRL) |= MCSPI_MODULCTRL_MS;
 }
 
 /**
-* \brief  This API will enable the McSPI controller in master mode and 
+* \brief  This API will enable the McSPI controller in master mode and
 *         configure other parameters required for master mode.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
 * \param  channelMode    Single/Multi channel.
-* \param  trMode         Transmit/Receive mode used in master 
+* \param  trMode         Transmit/Receive mode used in master
 *                        configuration.
-* \param  pinMode        Interface mode and pin assignment.                                
+* \param  pinMode        Interface mode and pin assignment.
 * \param  chNum          Channel number of the McSPI instance used.\n
 *
 *         'channelMode' can take the following values.\n
@@ -423,22 +423,22 @@ void McSPISlaveModeEnable(unsigned int baseAdd)
 *
 *         For chNum 0 <= n <= 3.\n
 *
-* \return 'retVal' which states if the combination of trMode and pinMode chosen 
+* \return 'retVal' which states if the combination of trMode and pinMode chosen
 *          by the user is supported for communication on SPIDAT[1:0] pins.\n
 *          TRUE  - Communication supported by SPIDAT[1:0].\n
 *          FALSE - Communication not supported by SPIDAT[1:0].\n
 *
-* \note   Please refer the description about IS,DPE1,DPE0 and TRM bits for 
+* \note   Please refer the description about IS,DPE1,DPE0 and TRM bits for
 *         proper configuration of SPIDAT[1:0].\n
 **/
 unsigned int McSPIMasterModeConfig(unsigned int baseAdd,
-                                   unsigned int channelMode, 
-                                   unsigned int trMode, 
+                                   unsigned int channelMode,
+                                   unsigned int trMode,
                                    unsigned int pinMode,
                                    unsigned int chNum)
 {
     unsigned int retVal = FALSE;
-    
+
     /* Clear the MS field of MCSPI_MODULCTRL register. */
     HWREG(baseAdd + MCSPI_MODULCTRL) &= ~MCSPI_MODULCTRL_SINGLE;
 
@@ -451,27 +451,27 @@ unsigned int McSPIMasterModeConfig(unsigned int baseAdd,
     /* Set the TRM field with the user sent value. */
     HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (trMode & MCSPI_CH0CONF_TRM);
 
-    if(((MCSPI_TX_RX_MODE == trMode) && 
-       (MCSPI_DATA_LINE_COMM_MODE_3 == pinMode)) || 
-       ((MCSPI_TX_ONLY_MODE == trMode) && 
-       (MCSPI_DATA_LINE_COMM_MODE_3 == pinMode)) || 
-       ((MCSPI_TX_RX_MODE == trMode) && 
-       (MCSPI_DATA_LINE_COMM_MODE_7 == pinMode)) || 
-       ((MCSPI_TX_ONLY_MODE == trMode) && 
+    if(((MCSPI_TX_RX_MODE == trMode) &&
+       (MCSPI_DATA_LINE_COMM_MODE_3 == pinMode)) ||
+       ((MCSPI_TX_ONLY_MODE == trMode) &&
+       (MCSPI_DATA_LINE_COMM_MODE_3 == pinMode)) ||
+       ((MCSPI_TX_RX_MODE == trMode) &&
+       (MCSPI_DATA_LINE_COMM_MODE_7 == pinMode)) ||
+       ((MCSPI_TX_ONLY_MODE == trMode) &&
        (MCSPI_DATA_LINE_COMM_MODE_7 == pinMode)))
     {
         retVal = FALSE;
     }
-    else 
+    else
     {
         /* Clear the IS, DPE0, DPE1 fields of MCSPI_CHCONF register. */
-        HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~(MCSPI_CH0CONF_IS | 
-                                                   MCSPI_CH0CONF_DPE1 | 
+        HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~(MCSPI_CH0CONF_IS |
+                                                   MCSPI_CH0CONF_DPE1 |
                                                    MCSPI_CH0CONF_DPE0);
-  
+
         /* Set the IS, DPE0, DPE1 fields with the user sent values. */
         HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (pinMode & (MCSPI_CH0CONF_IS |
-                                                            MCSPI_CH0CONF_DPE1 | 
+                                                            MCSPI_CH0CONF_DPE1 |
                                                             MCSPI_CH0CONF_DPE0));
 
         retVal = TRUE;
@@ -485,9 +485,9 @@ unsigned int McSPIMasterModeConfig(unsigned int baseAdd,
 *         operation and certain configurations required for slave mode.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
-* \param  trMode         Transmit/Receive mode used in slave 
+* \param  trMode         Transmit/Receive mode used in slave
 *                        configuration.
-* \param  pinMode        Interface mode and pin assignment.\n                           
+* \param  pinMode        Interface mode and pin assignment.\n
 *
 *         'trMode' can take the following values.\n
 *         MCSPI_TX_RX_MODE   - Enable McSPI in TX and RX modes.\n
@@ -499,14 +499,14 @@ unsigned int McSPIMasterModeConfig(unsigned int baseAdd,
 *
 *         For pinMode 0 <= n <= 7.\n
 *
-* \return 'retVal' which states if the combination of trMode and pinMode chosen 
+* \return 'retVal' which states if the combination of trMode and pinMode chosen
 *         by the user are supported for communication on SPIDAT[1:0] pins.\n
 *         TRUE  - Communication supported by SPIDAT[1:0].\n
 *         FALSE - Communication not supported by SPIDAT[1:0].\n
 *
-* \note   Please refer to the description about IS,DPE1,DPE0 and TRM bits for 
+* \note   Please refer to the description about IS,DPE1,DPE0 and TRM bits for
 *         proper configuration of SPIDAT[1:0].\n
-*         Also ensure to use only channel 0 for communication in 
+*         Also ensure to use only channel 0 for communication in
 *         slave mode. Communication using channels other than zero
 *         is not valid in slave mode.\n
 **/
@@ -521,28 +521,28 @@ unsigned int McSPISlaveModeConfig(unsigned int baseAdd, unsigned int trMode,
     /* Set the TRM field with the user sent value. */
     HWREG(baseAdd + MCSPI_CHCONF(MCSPI_CH_NUM_0)) |= (trMode & MCSPI_CH0CONF_TRM);
 
-    if(((MCSPI_TX_RX_MODE == trMode) && 
-       (MCSPI_DATA_LINE_COMM_MODE_3 == pinMode)) || 
-       ((MCSPI_TX_ONLY_MODE == trMode) && 
-       (MCSPI_DATA_LINE_COMM_MODE_3 == pinMode)) || 
-       ((MCSPI_TX_RX_MODE == trMode) && 
-       (MCSPI_DATA_LINE_COMM_MODE_7 == pinMode)) || 
-       ((MCSPI_TX_ONLY_MODE == trMode) && 
+    if(((MCSPI_TX_RX_MODE == trMode) &&
+       (MCSPI_DATA_LINE_COMM_MODE_3 == pinMode)) ||
+       ((MCSPI_TX_ONLY_MODE == trMode) &&
+       (MCSPI_DATA_LINE_COMM_MODE_3 == pinMode)) ||
+       ((MCSPI_TX_RX_MODE == trMode) &&
+       (MCSPI_DATA_LINE_COMM_MODE_7 == pinMode)) ||
+       ((MCSPI_TX_ONLY_MODE == trMode) &&
        (MCSPI_DATA_LINE_COMM_MODE_7 == pinMode)))
     {
         retVal = FALSE;
     }
-    else 
+    else
     {
         /*Clear the IS, DPE0, DPE1 fields of MCSPI_CHCONF register. */
         HWREG(baseAdd + MCSPI_CHCONF(MCSPI_CH_NUM_0)) &= ~(MCSPI_CH0CONF_IS |
-                                                            MCSPI_CH0CONF_DPE1 | 
+                                                            MCSPI_CH0CONF_DPE1 |
                                                             MCSPI_CH0CONF_DPE0);
 
         /*Set the IS, DPE0, DPE1 fields with the user sent values. */
-        HWREG(baseAdd + MCSPI_CHCONF(MCSPI_CH_NUM_0)) |= (pinMode & 
-                                                          (MCSPI_CH0CONF_IS | 
-                                                           MCSPI_CH0CONF_DPE1 | 
+        HWREG(baseAdd + MCSPI_CHCONF(MCSPI_CH_NUM_0)) |= (pinMode &
+                                                          (MCSPI_CH0CONF_IS |
+                                                           MCSPI_CH0CONF_DPE1 |
                                                            MCSPI_CH0CONF_DPE0));
     }
 
@@ -568,7 +568,7 @@ unsigned int McSPISlaveModeConfig(unsigned int baseAdd, unsigned int trMode,
 void McSPIChannelEnable(unsigned int baseAdd, unsigned int chNum)
 {
     /* Set the EN field of MCSPI_CHCTRL register. */
-    HWREG(baseAdd + MCSPI_CHCTRL(chNum)) |= MCSPI_CH0CTRL_EN_ACTIVE;                        
+    HWREG(baseAdd + MCSPI_CHCTRL(chNum)) |= MCSPI_CH0CTRL_EN_ACTIVE;
 }
 
 /**
@@ -587,7 +587,7 @@ void McSPIChannelEnable(unsigned int baseAdd, unsigned int chNum)
 void McSPIChannelDisable(unsigned int baseAdd, unsigned int chNum)
 {
     /* Clear the EN field of MCSPI_CHCTRL register. */
-    HWREG(baseAdd + MCSPI_CHCTRL(chNum)) &= ~MCSPI_CH0CTRL_EN_ACTIVE;                   
+    HWREG(baseAdd + MCSPI_CHCTRL(chNum)) &= ~MCSPI_CH0CTRL_EN_ACTIVE;
 }
 
 /**
@@ -600,15 +600,15 @@ void McSPIChannelDisable(unsigned int baseAdd, unsigned int chNum)
 void McSPIReset(unsigned int baseAdd)
 {
     /* Set the SOFTRESET field of MCSPI_SYSCONFIG register. */
-    HWREG(baseAdd + MCSPI_SYSCONFIG) |= MCSPI_SYSCONFIG_SOFTRESET; 
-    
+    HWREG(baseAdd + MCSPI_SYSCONFIG) |= MCSPI_SYSCONFIG_SOFTRESET;
+
     /* Stay in the loop until reset is done. */
-    while(!(MCSPI_SYSSTATUS_RESETDONE_COMPLETED & 
-            HWREG(baseAdd + MCSPI_SYSSTATUS))); 
+    while(!(MCSPI_SYSSTATUS_RESETDONE_COMPLETED &
+            HWREG(baseAdd + MCSPI_SYSSTATUS)));
 }
 
 /**
-* \brief  This API will enable the McSPI turbo mode of operation. 
+* \brief  This API will enable the McSPI turbo mode of operation.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
 * \param  chNum          Channel number of the McSPI instance used.
@@ -620,16 +620,16 @@ void McSPIReset(unsigned int baseAdd)
 *
 * \return none.
 *
-* \note   
+* \note
 **/
 void McSPITurboModeEnable(unsigned int baseAdd, unsigned int chNum)
 {
     /* Set the TURBO field on MCSPI_CHCONF register. */
-    HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= MCSPI_CH0CONF_TURBO; 
+    HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= MCSPI_CH0CONF_TURBO;
 }
 
 /**
-* \brief  This API will disable the McSPI turbo mode of operation. 
+* \brief  This API will disable the McSPI turbo mode of operation.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
 * \param  chNum          Channel number of the McSPI instance used.
@@ -662,14 +662,14 @@ void McSPITurboModeDisable(unsigned int baseAdd, unsigned int chNum)
 *
 * \return none.
 **/
-void McSPIDataPinDirectionConfig(unsigned int baseAdd, 
+void McSPIDataPinDirectionConfig(unsigned int baseAdd,
                                  unsigned int datDirection)
 {
     /* Clear the SPIDATDIR1 and SPIDATDIR0 fields of MCSPI_SYST register. */
-    HWREG(baseAdd + MCSPI_SYST) &= ~(MCSPI_SYST_SPIDATDIR1 | 
+    HWREG(baseAdd + MCSPI_SYST) &= ~(MCSPI_SYST_SPIDATDIR1 |
                                      MCSPI_SYST_SPIDATDIR0);
     /* Set the SPIDATDIR1 and SPIDATDIR0 fields with the user sent value. */
-    HWREG(baseAdd + MCSPI_SYST) |= (datDirection & (MCSPI_SYST_SPIDATDIR0 | 
+    HWREG(baseAdd + MCSPI_SYST) |= (datDirection & (MCSPI_SYST_SPIDATDIR0 |
                                                     MCSPI_SYST_SPIDATDIR1));
 }
 
@@ -693,14 +693,14 @@ void McSPIDataPinDirectionConfig(unsigned int baseAdd,
 *
 * \note:  Enabling FIFO is restricted to only 1 channel.
 **/
-void McSPITxFIFOConfig(unsigned int baseAdd, unsigned int txFifo, 
+void McSPITxFIFOConfig(unsigned int baseAdd, unsigned int txFifo,
                        unsigned int chNum)
 {
     /* Clear the FFEW field of MCSPI_CHCONF register. */
     HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~MCSPI_CH0CONF_FFEW;
 
     /* Set the FFEW field with user sent value. */
-    HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (txFifo & MCSPI_CH0CONF_FFEW); 
+    HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (txFifo & MCSPI_CH0CONF_FFEW);
 }
 
 /**
@@ -723,7 +723,7 @@ void McSPITxFIFOConfig(unsigned int baseAdd, unsigned int txFifo,
 *
 * \note:  Enabling FIFO is restricted to only 1 channel.
 **/
-void McSPIRxFIFOConfig(unsigned int baseAdd, unsigned int rxFifo, 
+void McSPIRxFIFOConfig(unsigned int baseAdd, unsigned int rxFifo,
                        unsigned int chNum)
 {
     /* Clear the FFER field of MCSPI_CHCONF register. */
@@ -734,51 +734,51 @@ void McSPIRxFIFOConfig(unsigned int baseAdd, unsigned int rxFifo,
 }
 
 /**
-* \brief  This API will set the transfer levels used by FIFO depending on 
-*         the various McSPI transmit/receive modes. 
+* \brief  This API will set the transfer levels used by FIFO depending on
+*         the various McSPI transmit/receive modes.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
 * \param  afl            Buffer almost full value.
 * \param  ael            Buffer almost empty value.
-* \param  trMode         Transmit/Receive modes used.\n 
+* \param  trMode         Transmit/Receive modes used.\n
 *
 *         'trMode' can take the following values.\n
 *         MCSPI_TX_RX_MODE   - Enable McSPI in TX and RX modes.\n
 *         MCSPI_RX_ONLY_MODE - Enable McSPI only in RX mode.\n
 *         MCSPI_TX_ONLY_MODE - Enable McSPI only in TX mode.\n
-*      
+*
 * \return none.
 *
 * \note   Values for afl and ael will have varying values depending on
-*         trMode. If trMode is MCSPI_TX_RX_MODE then afl and ael can take 
+*         trMode. If trMode is MCSPI_TX_RX_MODE then afl and ael can take
 *         values ranging from 0-19. If trMode is MCSPI_RX_ONLY_MODE/
 *         MCSPI_TX_ONLY_MODE then afl and ael can take values from 0-39.\n
 *
-*         While configuring mode of operation using trMode please ensure the 
+*         While configuring mode of operation using trMode please ensure the
 *         same value of trMode is used while using API's McSPIMasterModeConfig
-*         and McSPISlaveModeConfig. Mismatch while using trMode for different 
-*         APIs can result in unpredictable behaviour.\n 
+*         and McSPISlaveModeConfig. Mismatch while using trMode for different
+*         APIs can result in unpredictable behaviour.\n
 *
 *         For 'ael' and 'afl' please send level values for both of the fields
-*         and do not send the value which has to be written into the register 
+*         and do not send the value which has to be written into the register
 *         for the corresponding level value.
-*         For e.g. if 'ael' or 'afl' has to be 1 byte, then pass the parameter 
-*         'ael' or 'afl' as 1 and not 0 because the value which has to be 
+*         For e.g. if 'ael' or 'afl' has to be 1 byte, then pass the parameter
+*         'ael' or 'afl' as 1 and not 0 because the value which has to be
 *         written into register is manipulated inside the driver itself.\n
 **/
-void McSPIFIFOTrigLvlSet(unsigned int baseAdd, unsigned char afl, 
+void McSPIFIFOTrigLvlSet(unsigned int baseAdd, unsigned char afl,
                          unsigned char ael, unsigned int trMode)
 {
     if(MCSPI_TX_RX_MODE == trMode)
     {
         /* Clear the AFL and AEL fields of MCSPI_XFERLEVEL register. */
-        HWREG(baseAdd + MCSPI_XFERLEVEL) &= ~(MCSPI_XFERLEVEL_AFL | 
+        HWREG(baseAdd + MCSPI_XFERLEVEL) &= ~(MCSPI_XFERLEVEL_AFL |
                                               MCSPI_XFERLEVEL_AEL);
 
         /* Set the AFL and AEL fields with the user sent value. */
-        HWREG(baseAdd + MCSPI_XFERLEVEL) |= ((((afl-1) << 
-                                             MCSPI_XFERLEVEL_AFL_SHIFT) & 
-                                             MCSPI_XFERLEVEL_AFL) | 
+        HWREG(baseAdd + MCSPI_XFERLEVEL) |= ((((afl-1) <<
+                                             MCSPI_XFERLEVEL_AFL_SHIFT) &
+                                             MCSPI_XFERLEVEL_AFL) |
                                              ((ael - 1) & MCSPI_XFERLEVEL_AEL));
     }
     else if(MCSPI_TX_ONLY_MODE == trMode)
@@ -795,8 +795,8 @@ void McSPIFIFOTrigLvlSet(unsigned int baseAdd, unsigned char afl,
         HWREG(baseAdd + MCSPI_XFERLEVEL) &= ~MCSPI_XFERLEVEL_AFL;
 
         /* Set the AFL field with the user sent value. */
-        HWREG(baseAdd + MCSPI_XFERLEVEL) |= (((afl - 1) << 
-                                               MCSPI_XFERLEVEL_AFL_SHIFT) & 
+        HWREG(baseAdd + MCSPI_XFERLEVEL) |= (((afl - 1) <<
+                                               MCSPI_XFERLEVEL_AFL_SHIFT) &
                                                MCSPI_XFERLEVEL_AFL);
     }
     else
@@ -806,7 +806,7 @@ void McSPIFIFOTrigLvlSet(unsigned int baseAdd, unsigned char afl,
 }
 
 /**
-* \brief  This API will set the McSPI word counter value. 
+* \brief  This API will set the McSPI word counter value.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
 * \param  wCnt           Word count.
@@ -826,7 +826,7 @@ void McSPIWordCountSet(unsigned int baseAdd, unsigned short wCnt)
 * \brief  This API will enable the DMA read/write events of McSPI.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
-* \param  dmaFlags       Variable used to enable DMA mode for 
+* \param  dmaFlags       Variable used to enable DMA mode for
 *                        Rx/Tx events.
 * \param  chNum          Channel number of the McSPI instance used.\n
 *
@@ -846,7 +846,7 @@ void McSPIDMAEnable(unsigned int baseAdd, unsigned int dmaFlags,
 {
     /* Enable the DMA events. */
     HWREG(baseAdd + MCSPI_CHCONF(chNum)) |= (dmaFlags & (MCSPI_CH0CONF_DMAR |
-                                                          MCSPI_CH0CONF_DMAW)); 
+                                                          MCSPI_CH0CONF_DMAW));
 }
 
 /**
@@ -872,7 +872,7 @@ void McSPIDMADisable(unsigned int baseAdd, unsigned int dmaFlags,
                      unsigned int chNum)
 {
     /* Disable the DMA events. */
-    HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~(dmaFlags & (MCSPI_CH0CONF_DMAR | 
+    HWREG(baseAdd + MCSPI_CHCONF(chNum)) &= ~(dmaFlags & (MCSPI_CH0CONF_DMAR |
                                                            MCSPI_CH0CONF_DMAW));
 }
 
@@ -885,13 +885,13 @@ void McSPIDMADisable(unsigned int baseAdd, unsigned int dmaFlags,
 *
 *         'intFlags' can take the following values.\n
 *         MCSPI_INT_TX_EMPTY(chan) - Transmitter register empty interrupt.\n
-*         MCSPI_INT_TX_UNDERFLOW(chan) - Transmitter register underflow 
+*         MCSPI_INT_TX_UNDERFLOW(chan) - Transmitter register underflow
 *                                        interrupt.\n
 *         MCSPI_INT_RX_FULL(chan) - Receiver register full interrupt.\n
 *         MCSPI_INT_RX0_OVERFLOW - Receiver register 0 overflow interrupt.\n
 *         MCSPI_INT_EOWKE - End of word count interrupt.\n
 *
-*         'chan' stands for channel number. 
+*         'chan' stands for channel number.
 *         Please specify the proper channel number while passing the macros.
 *         0 <= chan <= 3 \n
 *
@@ -902,7 +902,7 @@ void McSPIDMADisable(unsigned int baseAdd, unsigned int dmaFlags,
 *
 * \return none.
 *
-* \note   Please ensure the proper channel number is passed while using the 
+* \note   Please ensure the proper channel number is passed while using the
 *         macros.
 **/
 void McSPIIntEnable(unsigned int baseAdd, unsigned int intFlags)
@@ -919,7 +919,7 @@ void McSPIIntEnable(unsigned int baseAdd, unsigned int intFlags)
 *
 *         'intFlags' can take the following values.\n
 *         MCSPI_INT_TX_EMPTY(chan) - Transmitter register empty interrupt.\n
-*         MCSPI_INT_TX_UNDERFLOW(chan) - Transmitter register underflow 
+*         MCSPI_INT_TX_UNDERFLOW(chan) - Transmitter register underflow
 *                                        interrupt.\n
 *         MCSPI_INT_RX_FULL(chan) - Receiver register full interrupt.\n
 *         MCSPI_INT_RX0_OVERFLOW - Receiver register 0 overflow interrupt.\n
@@ -946,7 +946,7 @@ void McSPIIntDisable(unsigned int baseAdd, unsigned int intFlags)
 }
 
 /**
-* \brief  This API will set initial delay for first transfer from McSPI 
+* \brief  This API will set initial delay for first transfer from McSPI
 *         peripheral.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
@@ -976,7 +976,7 @@ void McSPIInitDelayConfig(unsigned int baseAdd, unsigned int initDelay)
 * \brief  This API will enable/disable the SYSTEST mode of McSPI peripheral\n.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
-* \param  sysTest        Value to enable or disable the SYSTEST mode of 
+* \param  sysTest        Value to enable or disable the SYSTEST mode of
 *                        operation.\n
 *
 *         'sysTest' can take the following values.\n
@@ -999,15 +999,15 @@ void McSPISysTestModeConfig(unsigned int baseAdd, unsigned int sysTest)
 *         By using this bit we can accordingly configure the SPIEN pin for
 *         slave detection.
 *
-* \param  baseAdd        Memory Address of the McSPI instance used.          
-* \param  slaveSelect    Will configure the SPIEN[0:3] pin for slave 
+* \param  baseAdd        Memory Address of the McSPI instance used.
+* \param  slaveSelect    Will configure the SPIEN[0:3] pin for slave
 *                        detection.\n
 *
 *         'slaveSelect' can take the following values.\n
 *         MCSPI_SLAVE_DETECT_n - Detection enabled on SPIEN[n].\n
 *
 *         For slaveSelect n can range from 0-3.\n
-*             
+*
 * \return none.
 *
 * \note: This API does not have any significance in master mode.
@@ -1018,16 +1018,16 @@ void McSPISlaveSelect(unsigned int baseAdd, unsigned int slaveSelect)
     HWREG(baseAdd + MCSPI_CHCONF(MCSPI_CH_NUM_0)) &= ~MCSPI_CH0CONF_SPIENSLV;
 
     /* Set the SPIENSLV field with the user sent value. */
-    HWREG(baseAdd + MCSPI_CHCONF(MCSPI_CH_NUM_0)) |= (slaveSelect & 
+    HWREG(baseAdd + MCSPI_CHCONF(MCSPI_CH_NUM_0)) |= (slaveSelect &
                                                        MCSPI_CH0CONF_SPIENSLV);
 }
 
 /**
-* \brief  This API will put the data on to the McSPI Channel 
+* \brief  This API will put the data on to the McSPI Channel
 *         transmit register.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
-* \param  txData         32 bit data sent by the user which is put on 
+* \param  txData         32 bit data sent by the user which is put on
 *                        to the MCSPI_TX register.
 * \param  chNum          Channel number of the McSPI instance used.\n
 *
@@ -1072,7 +1072,7 @@ unsigned int McSPIReceiveData(unsigned int baseAdd, unsigned int chNum)
 * \return This API will return the status of the McSPI peripheral interrupts.
 *         User can use the following macros to check the status \n
 *         MCSPI_INT_TX_EMPTY(chan) - Transmitter register empty for channel n \n
-*         MCSPI_INT_TX_UNDERFLOW(chan) - Transmitter register underflow for 
+*         MCSPI_INT_TX_UNDERFLOW(chan) - Transmitter register underflow for
 *                                        channel n \n
 *         MCSPI_INT_RX_FULL(chan) - Receiver register full for channel n \n
 *         MCSPI_INT_RX0_OVERFLOW - Receiver register overflow for channel 0 \n
@@ -1084,7 +1084,7 @@ unsigned int McSPIIntStatusGet(unsigned int baseAdd)
 {
     /* Return the interrupt status present in the MCSPI_IRQSTATUS register. */
     return(HWREG(baseAdd + MCSPI_IRQSTATUS));
-} 
+}
 
 /**
 * \brief  This API will clear the status of McSPI Interrupts.
@@ -1095,13 +1095,13 @@ unsigned int McSPIIntStatusGet(unsigned int baseAdd)
 *
 *         intFlags can take the following values.\n
 *         MCSPI_INT_TX_EMPTY(chan) - Transmitter register empty interrupt.\n
-*         MCSPI_INT_TX_UNDERFLOW(chan) - Transmitter register underflow 
+*         MCSPI_INT_TX_UNDERFLOW(chan) - Transmitter register underflow
 *                                        interrupt.\n
 *         MCSPI_INT_RX_FULL(chan) - Receiver register full interrupt.\n
 *         MCSPI_INT_RX0_OVERFLOW - Receiver register 0 overflow interrupt.\n
 *         MCSPI_INT_EOW - End of word count interrupt.\n
 *
-*         'chan' stands for channel number. Please ensure proper channel 
+*         'chan' stands for channel number. Please ensure proper channel
 *         number is used while passing the macros.
 *         0 <= chan <= 3 \n
 *
@@ -1112,26 +1112,26 @@ unsigned int McSPIIntStatusGet(unsigned int baseAdd)
 *
 * \return none.
 *
-* \note   Please ensure the proper channel number is used while passing the 
+* \note   Please ensure the proper channel number is used while passing the
 *         macros passed.\n
 **/
 void McSPIIntStatusClear(unsigned int baseAdd, unsigned int intFlags)
 {
     /* Clear the SSB bit in the MCSPI_SYST register. */
-    HWREG(baseAdd + MCSPI_SYST) &= ~MCSPI_SET_STATUS_BIT;        
-        
+    HWREG(baseAdd + MCSPI_SYST) &= ~MCSPI_SET_STATUS_BIT;
+
     /* Clear the interrupt status. */
     HWREG(baseAdd + MCSPI_IRQSTATUS) = intFlags;
 }
 
 /**
-* \brief  This API will store the value of CLKSPI line into memory location 
+* \brief  This API will store the value of CLKSPI line into memory location
 *         pointed by spiClk when McSPI peripheral is in slave mode.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.\n
 * \param  spiClk         Will hold the value of spiClk.\n
 *
-* \return This API will return TRUE if McSPI peripheral is in Slave mode and 
+* \return This API will return TRUE if McSPI peripheral is in Slave mode and
 *         FALSE if peripheral is in Master mode.
 *
 * \note   This API will be applicable if McSPI is used in Slave mode only\n.
@@ -1140,7 +1140,7 @@ unsigned int McSPIClkRead(unsigned int baseAdd, unsigned int *spiClk)
 {
     unsigned int retVal = FALSE;
 
-    /* Check whether SPIENDIR is used as input. */ 
+    /* Check whether SPIENDIR is used as input. */
     if(HWREG(baseAdd + MCSPI_SYST) & MCSPI_SYST_SPIENDIR)
     {
         retVal = TRUE;
@@ -1151,8 +1151,8 @@ unsigned int McSPIClkRead(unsigned int baseAdd, unsigned int *spiClk)
 }
 
 /**
-* \brief  This API will change the value of McSPI clock to high or low, as 
-*         programmed by the user when McSPI peripheral is in master mode only\n. 
+* \brief  This API will change the value of McSPI clock to high or low, as
+*         programmed by the user when McSPI peripheral is in master mode only\n.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used\n.
 * \param  spiClk         Will hold the value of spiClk \n.
@@ -1162,7 +1162,7 @@ unsigned int McSPIClkRead(unsigned int baseAdd, unsigned int *spiClk)
 *         MCSPI_CLK_HIGH - Will drive the McSPI clk line high.\n
 *         MCSPI_CLK_LOW  - Will drive the McSPI clk line low.\n
 *
-* \return This API will return TRUE if McSPI peripheral is in Master mode and 
+* \return This API will return TRUE if McSPI peripheral is in Master mode and
 *         FALSE if peripheral is in Slave mode.
 *
 * \note   This API will be applicable if McSPI is used in Master mode.
@@ -1183,15 +1183,15 @@ unsigned int McSPIClkWrite(unsigned int baseAdd, unsigned int spiClk)
     }
 
     return retVal;
-} 
+}
 
 /**
-* \brief  This API will read the values of SPIDAT_0 or SPIDAT_1 depending on 
-*         dataDir and provided SPIDAT[0:1] is used only for input. 
+* \brief  This API will read the values of SPIDAT_0 or SPIDAT_1 depending on
+*         dataDir and provided SPIDAT[0:1] is used only for input.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.\n
 * \param  dataPinDir     Direction of SPIDAT[1:0] pins.\n
-* \param  spiDat         Memory location at which data pin data has to be 
+* \param  spiDat         Memory location at which data pin data has to be
 *                        placed.
 *
 *         'dataPinDir' can take the following values.\n
@@ -1201,10 +1201,10 @@ unsigned int McSPIClkWrite(unsigned int baseAdd, unsigned int spiClk)
 * \return This API will return TRUE if SPIDAT[1:0] pins are used as input
 *         else FALSE.
 *
-* \note   This API will be applicable if SPIDAT[1:0] pins are used only 
+* \note   This API will be applicable if SPIDAT[1:0] pins are used only
 *         as input.
 **/
-unsigned int McSPIDataPinRead(unsigned int baseAdd, unsigned int dataPinDir, 
+unsigned int McSPIDataPinRead(unsigned int baseAdd, unsigned int dataPinDir,
                               unsigned int *spiDat)
 {
     unsigned int retVal = FALSE;
@@ -1234,7 +1234,7 @@ unsigned int McSPIDataPinRead(unsigned int baseAdd, unsigned int dataPinDir,
 }
 
 /**
-* \brief  This API will write spiDat into SPIDAT_0 or SPIDAT_1 field of 
+* \brief  This API will write spiDat into SPIDAT_0 or SPIDAT_1 field of
 *         MCSPI_SYST register depending on the dataDir values.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
@@ -1252,7 +1252,7 @@ unsigned int McSPIDataPinRead(unsigned int baseAdd, unsigned int dataPinDir,
 * \return This API will return TRUE if SPIDAT[1:0] pins are used as output
 *         else FALSE.
 *
-* \note   This API will be applicable if SPIDAT[1:0] pins are used only 
+* \note   This API will be applicable if SPIDAT[1:0] pins are used only
 *         as output.
 **/
 unsigned int McSPIDataPinWrite(unsigned int baseAdd, unsigned int dataPinDir,
@@ -1291,7 +1291,7 @@ unsigned int McSPIDataPinWrite(unsigned int baseAdd, unsigned int dataPinDir,
 }
 
 /**
-* \brief  This API will read the data present on the SPIEN line. 
+* \brief  This API will read the data present on the SPIEN line.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
 * \param  spiEn          Memory location at which read value is stored.
@@ -1302,13 +1302,13 @@ unsigned int McSPIDataPinWrite(unsigned int baseAdd, unsigned int dataPinDir,
 *
 *         For spiEnNum n can range from 0-3.\n
 *
-* \return This API will return TRUE if direction of SPIEN is used as input 
+* \return This API will return TRUE if direction of SPIEN is used as input
 *         else FALSE.
 *
 * \note   This API will be applicable if SPIENDIR is configured as input.
-* 
+*
 **/
-unsigned int McSPICSRead(unsigned int baseAdd, unsigned int *spiEn, 
+unsigned int McSPICSRead(unsigned int baseAdd, unsigned int *spiEn,
                          unsigned int spiEnNum)
 {
     unsigned int retVal = FALSE;
@@ -1329,7 +1329,7 @@ unsigned int McSPICSRead(unsigned int baseAdd, unsigned int *spiEn,
 *         n can be 0-3 when SPIENDIR is configured as output.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
-* \param  spiEnLvl       Value to be written into SPIEN_n field where 
+* \param  spiEnLvl       Value to be written into SPIEN_n field where
 *                        n is 0-3.
 * \param  spiEnNum       The instance of SPIEN used.\n
 *
@@ -1337,17 +1337,17 @@ unsigned int McSPICSRead(unsigned int baseAdd, unsigned int *spiEn,
 *
 *         MCSPI_SPIEN_HIGH - SPIEN is driven high.\n
 *         MCSPI_SPIEN_LOW - SPIEN is driven low.\n
-*  
+*
 *         'spiEnNum' can take the following values.\n
 *         MCSPI_SPIEN_n - SPIEN_n is used.\n
 *
 *         For spiEnNum n can range from 0-3.\n
 *
-* \return This API will return TRUE if direction of SPIEN is used as output 
+* \return This API will return TRUE if direction of SPIEN is used as output
 *         else FALSE.
 *
 * \note   This API will be applicable if SPIENDIR is configured as output.
-* 
+*
 **/
 unsigned int McSPICSWrite(unsigned int baseAdd, unsigned int spiEnLvl,
                           unsigned int spiEnNum)
@@ -1373,8 +1373,8 @@ unsigned int McSPICSWrite(unsigned int baseAdd, unsigned int spiEnLvl,
             HWREG(baseAdd + MCSPI_SYST) &= ~MCSPI_SYST_SPIEN_1;
 
             /* Set the SPIEN_1 field with the user sent value. */
-            HWREG(baseAdd + MCSPI_SYST) |= ((spiEnLvl << 
-                                             MCSPI_SYST_SPIEN_1_SHIFT) & 
+            HWREG(baseAdd + MCSPI_SYST) |= ((spiEnLvl <<
+                                             MCSPI_SYST_SPIEN_1_SHIFT) &
                                              MCSPI_SYST_SPIEN_1);
         }
 
@@ -1384,8 +1384,8 @@ unsigned int McSPICSWrite(unsigned int baseAdd, unsigned int spiEnLvl,
             HWREG(baseAdd + MCSPI_SYST) &= ~MCSPI_SYST_SPIEN_2;
 
             /* Set the SPIEN_2 field with the user sent value. */
-            HWREG(baseAdd + MCSPI_SYST) |= ((spiEnLvl << 
-                                             MCSPI_SYST_SPIEN_2_SHIFT) & 
+            HWREG(baseAdd + MCSPI_SYST) |= ((spiEnLvl <<
+                                             MCSPI_SYST_SPIEN_2_SHIFT) &
                                              MCSPI_SYST_SPIEN_2);
         }
 
@@ -1395,8 +1395,8 @@ unsigned int McSPICSWrite(unsigned int baseAdd, unsigned int spiEnLvl,
             HWREG(baseAdd + MCSPI_SYST) &= ~MCSPI_SYST_SPIEN_3;
 
             /* Set the SPIEN_3 field with the user sent value. */
-            HWREG(baseAdd + MCSPI_SYST) |= ((spiEnLvl << 
-                                             MCSPI_SYST_SPIEN_3_SHIFT) & 
+            HWREG(baseAdd + MCSPI_SYST) |= ((spiEnLvl <<
+                                             MCSPI_SYST_SPIEN_3_SHIFT) &
                                              MCSPI_SYST_SPIEN_3);
         }
 
@@ -1407,10 +1407,10 @@ unsigned int McSPICSWrite(unsigned int baseAdd, unsigned int spiEnLvl,
     }
 
     return retVal;
-} 
+}
 
 /**
-* \brief  This API will return the status of the McSPI channel currently in 
+* \brief  This API will return the status of the McSPI channel currently in
 *         use.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
@@ -1419,7 +1419,7 @@ unsigned int McSPICSWrite(unsigned int baseAdd, unsigned int spiEnLvl,
 *         'chNum' can take the following values.\n
 *         MCSPI_CHANNEL_n - Channel n is used for communication.\n
 *
-* \return This API will return the status of the McSPI channel status 
+* \return This API will return the status of the McSPI channel status
 *         register.
 *         User can use the following macros to check the status \n
 *         MCSPI_CH_STAT_RXS_FULL - Receiver register is full \n
@@ -1428,7 +1428,7 @@ unsigned int McSPICSWrite(unsigned int baseAdd, unsigned int spiEnLvl,
 *         MCSPI_CH_TXFFE - FIFO transmit buffer empty status \n
 *         MCSPI_CH_TXFFF - FIFO transmit buffer full status \n
 *         MCSPI_CH_RXFFE - FIFO receive buffer empty status \n
-*         MCSPI_CH_RXFFF - FIFO receive buffer full status \n 
+*         MCSPI_CH_RXFFF - FIFO receive buffer full status \n
 **/
 unsigned int McSPIChannelStatusGet(unsigned int baseAdd, unsigned int chNum)
 {
@@ -1437,7 +1437,7 @@ unsigned int McSPIChannelStatusGet(unsigned int baseAdd, unsigned int chNum)
 }
 
 /**
-* \brief  This API will enable/disable multiple word OCP access for McSPI 
+* \brief  This API will enable/disable multiple word OCP access for McSPI
 *         peripheral.
 *
 * \param  baseAdd        Memory Address of the McSPI instance used.
@@ -1447,19 +1447,19 @@ unsigned int McSPIChannelStatusGet(unsigned int baseAdd, unsigned int chNum)
 *         MCSPI_MOA_ENABLE  - Enable MOA.\n
 *         MCSPI_MOA_DISABLE - Disable MOA.\n
 *
-* \return none. 
+* \return none.
 **/
 void McSPIMultipleWordAccessConfig(unsigned int baseAdd, unsigned int moa)
 {
     /* Clear the MOA field of MCSPI_MODULCTRL register. */
     HWREG(baseAdd + MCSPI_MODULCTRL) &= ~MCSPI_MODULCTRL_MOA;
 
-    /* Set the MOA fields with the user sent value. */    
+    /* Set the MOA fields with the user sent value. */
     HWREG(baseAdd + MCSPI_MODULCTRL) |= (moa & MCSPI_MODULCTRL_MOA);
 }
 
 /**
-* \brief  This API will enable/disable the FIFO DMA address 256-bit aligned 
+* \brief  This API will enable/disable the FIFO DMA address 256-bit aligned
 *         feature of McSPI peripheral.
 *
 * \param  baseAdd       Memory Address of the McSPI instance used.
@@ -1469,7 +1469,7 @@ void McSPIMultipleWordAccessConfig(unsigned int baseAdd, unsigned int moa)
 *        MCSPI_FDAA_ENABLE  - Enable FDAA.\n
 *        MCSPI_FDAA_DISABLE - Disable FDAA.\n
 *
-* \return none. 
+* \return none.
 **/
 void McSPIFIFODatManagementConfig(unsigned int baseAdd, unsigned int fdaa)
 {
@@ -1491,7 +1491,7 @@ void McSPIFIFODatManagementConfig(unsigned int baseAdd, unsigned int fdaa)
 *         MCSPI_AUTO_IDLE_ENABLE  - Enable AUTOIDLE.\n
 *         MCSPI_AUTO_IDLE_DISABLE - Disable AUTOIDLE.\n
 *
-* \return none. 
+* \return none.
 **/
 void McSPIAutoIdleConfig(unsigned int baseAdd, unsigned int autoIdle)
 {
@@ -1503,18 +1503,18 @@ void McSPIAutoIdleConfig(unsigned int baseAdd, unsigned int autoIdle)
 }
 
 /**
-* \brief  This API will enable/disable multiple word access for McSPI 
+* \brief  This API will enable/disable multiple word access for McSPI
 *         peripheral.
 *
 * \param  baseAdd       Memory Address of the McSPI instance used.
 * \param  smartIdle     Used to set modes for smart idle mode.\n
- 
+
 *         'smartIdle' can take the following values.\n
 *         MCSPI_SIDLE_MODE_FORCE - Inactive or Force mode.\n
 *         MCSPI_SIDLE_MODE_NOIDLE - No Idle mode.\n
 *         MCSPI_SIDLE_MODE_SMART - Smart Idle mode.\n
 *
-* \return none. 
+* \return none.
 **/
 void McSPISmartIdleConfig(unsigned int baseAdd, unsigned int smartIdle)
 {
@@ -1530,14 +1530,14 @@ void McSPISmartIdleConfig(unsigned int baseAdd, unsigned int smartIdle)
 *
 * \param  baseAdd      Memory Address of the McSPI instance used.
 * \param  clkAct       Clock activity used.\n
-* 
+*
 *         'clkAct' can take the following values.\n
 *         MCSPI_CLK_ACTIVITY_NONE - OCP and functional clocks not used.\n
 *         MCSPI_CLK_ACTIVITY_OCP  - OCP clock only may be used.\n
 *         MCSPI_CLK_ACTIVITY_FUNC - Functional clock only may be used.\n
 *         MCSPI_CLK_ACTIVITY_BOTH - OCP and Functional clocks are used.\n
 *
-* \return none. 
+* \return none.
 **/
 void McSPIClkActivityConfig(unsigned int baseAdd, unsigned int clkAct)
 {
diff --git a/lib/tiam1808/drivers/mdio.c b/lib/tiam1808/drivers/mdio.c
index 9c6c18e85..519c6985c 100644
--- a/lib/tiam1808/drivers/mdio.c
+++ b/lib/tiam1808/drivers/mdio.c
@@ -170,17 +170,17 @@ void MDIOInit(unsigned int baseAddr, unsigned int mdioInputFreq,
    unsigned int clkDiv = (mdioInputFreq/mdioOutputFreq) - 1;
 
    HWREG(baseAddr + MDIO_CONTROL) = ((clkDiv & MDIO_CONTROL_CLKDIV)
-                                     | MDIO_CONTROL_ENABLE 
+                                     | MDIO_CONTROL_ENABLE
                                      | MDIO_CONTROL_PREAMBLE
                                      | MDIO_CONTROL_FAULTENB);
 }
 
 /**
- * \brief   Saves the MDIO register context. Note that only MDIO control 
+ * \brief   Saves the MDIO register context. Note that only MDIO control
  *          register context is saved here.
  *
  * \param   baseAddr       Base Address of the MDIO Module Registers.
- * \param   contextPtr     Pointer to the structure where MDIO context 
+ * \param   contextPtr     Pointer to the structure where MDIO context
  *                         needs to be saved.
  * \return  None
  *
@@ -191,12 +191,12 @@ void MDIOContextSave(unsigned int baseAddr, MDIOCONTEXT *contextPtr)
 }
 
 /**
- * \brief   Restores the MDIO register context. Note that only MDIO control 
+ * \brief   Restores the MDIO register context. Note that only MDIO control
  *          register context is restored here. Hence enough delay shall be
  *          given after this API
  *
  * \param   baseAddr       Base Address of the MDIO Module Registers.
- * \param   contextPtr     Pointer to the structure where MDIO context 
+ * \param   contextPtr     Pointer to the structure where MDIO context
  *                         needs to be restored from
  * \return  None
  *
diff --git a/lib/tiam1808/drivers/psc.c b/lib/tiam1808/drivers/psc.c
index 8d0a18267..8b59a9b8d 100644
--- a/lib/tiam1808/drivers/psc.c
+++ b/lib/tiam1808/drivers/psc.c
@@ -2,7 +2,7 @@
  * \file      psc.c
  *
  * \brief     This file contains the device abstraction layer APIs for the
- *            PSC module. There are APIs here to enable power domain, 
+ *            PSC module. There are APIs here to enable power domain,
  *            transitions for a particular module
  */
 
@@ -66,7 +66,7 @@
  *                            the commands that can be given to a module.
  *
  * \return                    0 in case of successful transition, -1 otherwise.
- *            
+ *
  */
 
 int PSCModuleControl (unsigned int baseAdd, unsigned int moduleId,
@@ -103,10 +103,10 @@ int PSCModuleControl (unsigned int baseAdd, unsigned int moduleId,
     if (timeout != 0)
     {
         timeout = 0xFFFFFF;
-        status = flags & PSC_MDCTL_NEXT; 
+        status = flags & PSC_MDCTL_NEXT;
         do {
             timeout--;
-        } while(timeout && 
+        } while(timeout &&
                 (HWREG(baseAdd + PSC_MDSTAT(moduleId)) & PSC_MDSTAT_STATE) != status);
     }
 
diff --git a/lib/tiam1808/drivers/rtc.c b/lib/tiam1808/drivers/rtc.c
index 6312b55f2..0a8f32adb 100644
--- a/lib/tiam1808/drivers/rtc.c
+++ b/lib/tiam1808/drivers/rtc.c
@@ -44,7 +44,7 @@
 #include "rtc.h"
 
 /******************************************************************************
-**                 LOCAL MACRO DEFINITIONS                                   
+**                 LOCAL MACRO DEFINITIONS
 ******************************************************************************/
 
 #define IS_RTC_BUSY             (HWREG(baseAdd + RTC_STATUS) & (RTC_STATUS_BUSY))
@@ -96,7 +96,7 @@
 
 /**
  * \brief    This function sets the 32KHz counter to run.\n
- * 
+ *
  * \param    baseAdd   The base address of the RTC instance being used.\n
  *
  * \return   None.\n
@@ -115,10 +115,10 @@ void RTCRun(unsigned int baseAdd)
     ** only when RTC is running. The current function is invoked when
     ** RTC is stopped. Thus, BUSY status need not be checked.
     */
-    
+
     /* Setting the RUN bit in CTRL register.*/
     HWREG(baseAdd + RTC_CTRL) |= (RTC_CTRL_RUN | splitPower);
-} 
+}
 
 
 /**
@@ -128,13 +128,13 @@ void RTCRun(unsigned int baseAdd)
  *
  * \return  None. \n
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
  *
  */
 void RTCStop(unsigned int baseAdd)
 {
-   
+
     volatile unsigned int splitPower = 0;
 
     if(RTC_REV_AM1808 == RtcVersionGet())
@@ -147,8 +147,8 @@ void RTCStop(unsigned int baseAdd)
     ** is low.
     */
     while(IS_RTC_BUSY);
-     
-      /* Clearing the RUN bit in CTRL register. */    
+
+      /* Clearing the RUN bit in CTRL register. */
     HWREG(baseAdd + RTC_CTRL) &= ~(RTC_CTRL_RUN);
     HWREG(baseAdd + RTC_CTRL) |= splitPower;
 }
@@ -159,7 +159,7 @@ void RTCStop(unsigned int baseAdd)
  * \param   baseAdd  The base address of the RTC instance being used.\n
  *
  * \return  None.\n
- * 
+ *
  * \note    To enable write-protection for RTC registers, the KICK registers
  *          have to be programmed with any value other than their key values.\n
  */
@@ -179,11 +179,11 @@ void RTCWriteProtectEnable(unsigned int baseAdd)
  * \return  None.\n
  *
  * \note    To disable write-protection for RTC registers, the KICK registers
- *          namely KICK0R and KICK1R have to be programmed with specific key 
+ *          namely KICK0R and KICK1R have to be programmed with specific key
  *          values .\n
- *          The pre-requisite to write to any RTC registers except KICK  
+ *          The pre-requisite to write to any RTC registers except KICK
  *          registers is that the KICK registers have to be programmed with
- *          specific key values mentioned in the RTC peripheral user manual. 
+ *          specific key values mentioned in the RTC peripheral user manual.
  */
 
 
@@ -199,9 +199,9 @@ void RTCWriteProtectDisable(unsigned int baseAdd)
  *
  * \param   baseAdd  The base address of the RTC instance being used.\n
  *
- * \return  None. \n 
+ * \return  None. \n
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
  *          By ALARM, the functional specification effectively means ALARM1,
  *          although it does not use the name ALARM1. This comes into context
@@ -215,7 +215,7 @@ void RTCIntAlarmEnable(unsigned int baseAdd)
     ** is low.
     */
     while(IS_RTC_BUSY);
-        
+
     HWREG(baseAdd + RTC_INTERRUPT) |= RTC_INTERRUPTS_ALARM;
 }
 
@@ -226,7 +226,7 @@ void RTCIntAlarmEnable(unsigned int baseAdd)
  *
  * \return  None. \n
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
  *
  */
@@ -238,13 +238,13 @@ void RTCIntAlarmDisable(unsigned int baseAdd)
     */
     while(IS_RTC_BUSY);
     HWREG(baseAdd + RTC_INTERRUPT) &= ~(RTC_INTERRUPTS_ALARM);
-}   
+}
 
 /**
  * \brief   This function enables the periodic timer interrupt.\n
  *
  * \param   baseAdd     The base address of the RTC instance being used.\n
- * \param   timerPeriod  This specifies the period between two consecutive 
+ * \param   timerPeriod  This specifies the period between two consecutive
  *                       interrupts. This can take one of the following values:\n
  *                       RTC_INT_EVERY_SECOND \n
  *                       RTC_INT_EVERY_MINUTE \n
@@ -253,16 +253,16 @@ void RTCIntAlarmDisable(unsigned int baseAdd)
  *
  * \return  None. \n
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
- * 
+ *
  */
 
 void RTCIntTimerEnable(unsigned int baseAdd, unsigned int timerPeriod)
 {
     /*
     ** Writing to INTERRUPT register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
 
@@ -277,9 +277,9 @@ void RTCIntTimerEnable(unsigned int baseAdd, unsigned int timerPeriod)
  *
  * \return  None. \n
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
- * 
+ *
  */
 
 void RTCIntTimerDisable(unsigned int baseAdd)
@@ -288,8 +288,8 @@ void RTCIntTimerDisable(unsigned int baseAdd)
     ** Writing to INTERRUPT register requires that BUSY bit in STATUS register
     ** is low.
     */
-    while(IS_RTC_BUSY); 
-    HWREG(baseAdd + RTC_INTERRUPT) &= ~(RTC_INTERRUPTS_TIMER);    
+    while(IS_RTC_BUSY);
+    HWREG(baseAdd + RTC_INTERRUPT) &= ~(RTC_INTERRUPTS_TIMER);
 }
 
 
@@ -310,7 +310,7 @@ unsigned int  RTCBusyStatusGet(unsigned int baseAdd)
 }
 
 /**
- * \brief   This function indicates whether RTC is currently running or 
+ * \brief   This function indicates whether RTC is currently running or
  *          stopped.\n
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
@@ -318,7 +318,7 @@ unsigned int  RTCBusyStatusGet(unsigned int baseAdd)
  * \return  This function returns either of the following two values:\n
  *          1> RTC_STATUS_RUNNING - indicating that RTC is in running state.\n
  *          2> RTC_STATUS_STOPPED - indicating that RTC is in stopped state.\n
- * 
+ *
  */
 
 unsigned int RTCRunStatusGet(unsigned int baseAdd)
@@ -337,12 +337,12 @@ unsigned int RTCRunStatusGet(unsigned int baseAdd)
  *          has been generated.\n
  *          RTC_NO_NEW_ALARM_INTERRUPT - indicating that no new ALARM interrupt
  *          has been generated. \n
- * 
+ *
  * \note    It is important to invoke the function RTCSAlarmIntStatusClear()
  *          to clear the ALARM interrupt status whenever an ALARM interrupt is \n
- *          generated. Otherwise, there is a possibility of the interrupt 
+ *          generated. Otherwise, there is a possibility of the interrupt
  *          handler being entered again since the previous interrupt's status
- *          was not cleared. \n 
+ *          was not cleared. \n
  */
 unsigned int RTCAlarmIntStatusGet(unsigned int baseAdd)
 {
@@ -368,21 +368,21 @@ void RTCAlarmIntStatusClear(unsigned int baseAdd)
 }
 
 /**
- * \brief   This function determines what registers have been incremented in 
+ * \brief   This function determines what registers have been incremented in
  *          the latest time update.\n
  *
  * \param    baseAdd  The base address of the RTC instance being used.\n
  *
  * \return  This function can return one of the following four values:\n
- *          1> RTC_SECOND_EVENT - when only SECOND register has incremented.\n 
- *          2> (RTC_SECOND_EVENT | RTC_MINUTE_EVENT) - when both SECOND and 
+ *          1> RTC_SECOND_EVENT - when only SECOND register has incremented.\n
+ *          2> (RTC_SECOND_EVENT | RTC_MINUTE_EVENT) - when both SECOND and
  *             MINUTE registers have been incremented.\n
- *          3> (RTC_SECOND_EVENT | RTC_MINUTE_EVENT | RTC_HOUR_EVENT) - when 
+ *          3> (RTC_SECOND_EVENT | RTC_MINUTE_EVENT | RTC_HOUR_EVENT) - when
  *              SECOND, MINUTE and HOUR register have been incremented.\n
- *          4> (RTC_SECOND_EVENT | RTC_MINUTE_EVENT | RTC_HOUR_EVENT | 
- *              RTC_DAY_EVENT) - when SECOND, MINUTE, HOUR and DAY registers 
+ *          4> (RTC_SECOND_EVENT | RTC_MINUTE_EVENT | RTC_HOUR_EVENT |
+ *              RTC_DAY_EVENT) - when SECOND, MINUTE, HOUR and DAY registers
  *              have been incremented.\n
- * 
+ *
  */
 unsigned int RTCEventUpdateGet(unsigned int baseAdd)
 {
@@ -394,11 +394,11 @@ unsigned int RTCEventUpdateGet(unsigned int baseAdd)
 }
 
 /**
- * \brief   This function enables the rounding feature on the current time to 
+ * \brief   This function enables the rounding feature on the current time to
  *          the nearest minute.\n
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
- * 
+ *
  * \return  None.
  *
  */
@@ -412,7 +412,7 @@ void RTCMinRoundingEnable(unsigned int baseAdd)
     }
 
     /*
-    ** Writing to any bit in CTRL register except for SET32COUNTER bit does 
+    ** Writing to any bit in CTRL register except for SET32COUNTER bit does
     ** not require BUSY bit in STATUS register to be low.
     */
     HWREG(baseAdd + RTC_CTRL) |= (RTC_CTRL_ROUNDMIN | splitPower);
@@ -451,7 +451,7 @@ void RTCMinRoundingDisable(unsigned int baseAdd)
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
  *
- * \return  None. 
+ * \return  None.
  *
  */
 
@@ -495,7 +495,7 @@ void RTCAutoCompDisable(unsigned int baseAdd)
     ** Writing to any bit in CTRL register except for SET32COUNTER bit does
     ** not require BUSY bit in STATUS register to be low.
     */
-    
+
     HWREG(baseAdd + RTC_CTRL) &= ~(RTC_CTRL_AUTOCOMP);
     HWREG(baseAdd + RTC_CTRL) |= splitPower;
 }
@@ -504,13 +504,13 @@ void RTCAutoCompDisable(unsigned int baseAdd)
 /**
  * \brief   This function configures the representation type for hours for the
  *          RTC as either being 24 hour type or 12 hour type. \n
- * 
+ *
  * \param   baseAdd   The base address of the RTC instance being used.\n
- * \param   hourType   Represents the hour mode representation type. This can 
+ * \param   hourType   Represents the hour mode representation type. This can
  *                     take one of the two below values: \n
  *                     RTC_12HOUR_MODE - for 12 hour mode representation.\n
  *                     RTC_24HOUR_MODE - for 24 hour mode representation.\n
- * 
+ *
  * \return  None. \n
  */
 
@@ -525,12 +525,12 @@ void RTCHourModeSet(unsigned int baseAdd, unsigned int hourType)
 
     switch(hourType)
     {
-        case RTC_12HOUR_MODE:            
+        case RTC_12HOUR_MODE:
              HWREG(baseAdd + RTC_CTRL) |= (RTC_12HOUR_MODE | splitPower);
         break;
-   
+
         case RTC_24HOUR_MODE:
-        default:    
+        default:
              HWREG(baseAdd + RTC_CTRL) |= (RTC_24HOUR_MODE | splitPower);
         break;
 
@@ -539,8 +539,8 @@ void RTCHourModeSet(unsigned int baseAdd, unsigned int hourType)
 
 
 /**
- * \brief  This function reads the hour mode representation currently used in RTC. 
- *         The hour mode representation used could either be a 12 hour mode or 
+ * \brief  This function reads the hour mode representation currently used in RTC.
+ *         The hour mode representation used could either be a 12 hour mode or
  *         24 hour mode representation.
  *
  * \param  baseAdd  The base address of the RTC instance being used.\n
@@ -554,7 +554,7 @@ unsigned int RTCHourModeGet(unsigned int baseAdd)
 {
 
     return(HWREG(baseAdd + RTC_CTRL) & (RTC_12HOUR_MODE));
-} 
+}
 
 /**
  * \brief   This function sets the SET32COUNTER bit in CTRL register.
@@ -634,7 +634,7 @@ void RTCSet32CounterDisable(unsigned int baseAdd)
  * \brief   This function is used to disable the RTC instance. Disabling the
  *          RTC would gate the 32KHz reference clock to the RTC.\n
  *
- * \param   baseAdd   The base address of the RTC instance being used.\n  
+ * \param   baseAdd   The base address of the RTC instance being used.\n
  *
  * \return  None.
  *
@@ -689,15 +689,15 @@ void RTCEnable(unsigned int baseAdd)
     HWREG(baseAdd + RTC_CTRL) &= ~(RTC_CTRL_RTCDISABLE);
     HWREG(baseAdd + RTC_CTRL) |= splitPower;
 }
- 
+
 /**
- * \brief   This function indicates whether RTC is disabled or is enabled 
+ * \brief   This function indicates whether RTC is disabled or is enabled
  *          and functional.\n
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
  *
  * \return  This can return one of the two below values:
- *          RTC_ENABLED - indicating that RTC is enabled and is 
+ *          RTC_ENABLED - indicating that RTC is enabled and is
  *                        functional.
  *          RTC_DISABLED - indicating that RTC is disabled.
  */
@@ -707,7 +707,7 @@ unsigned int RTCEnableStatus(unsigned int baseAdd)
 }
 
 /**
- *  \brief  This function enables the split power feature of RTC and 
+ *  \brief  This function enables the split power feature of RTC and
  *          in turn enabling the leakage isolation circuitry.
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
@@ -722,7 +722,7 @@ void RTCSplitPwrEnable(unsigned int baseAdd)
 }
 
 /**
- * \brief   This function disables the split power feature of RTC and 
+ * \brief   This function disables the split power feature of RTC and
  *          in turn disabling the leakage isolation circuitry. \n
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
@@ -738,68 +738,68 @@ void RTCSplitPwrDisable(unsigned int baseAdd)
 
 /**
  * \brief   This function sets the SECOND register with the specified value.\n
- 
+
  * \param   baseAdd   The base address of the RTC instance being used.\n
- * \param   secValue   The value of 'seconds' to be written to SECOND 
+ * \param   secValue   The value of 'seconds' to be written to SECOND
  *                     register.\n
  * \return  None.
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
- * 
+ *
  */
 void RTCSecondSet(unsigned int baseAdd, unsigned int secValue)
 {
-    
+
     /*
     ** Writing to SECOND register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
- 
-    while(IS_RTC_BUSY); 
-    
+
+    while(IS_RTC_BUSY);
+
     /* Writing least 7 bits of 'secValue' into SECOND register.*/
-    HWREG(baseAdd + RTC_SECOND) = (secValue & (RTC_SECOND_SEC1 | 
-                                               RTC_SECOND_SEC0));        
+    HWREG(baseAdd + RTC_SECOND) = (secValue & (RTC_SECOND_SEC1 |
+                                               RTC_SECOND_SEC0));
 }
 
 /**
  * \brief   This function determines the 'second' value of the current time.\n
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
- *        
- * \return  The value in the SECOND register. 
+ *
+ * \return  The value in the SECOND register.
  */
 unsigned int RTCSecondGet(unsigned int baseAdd)
 {
-    return(HWREG(baseAdd + RTC_SECOND) & (RTC_SECOND_SEC1 | RTC_SECOND_SEC0)); 
+    return(HWREG(baseAdd + RTC_SECOND) & (RTC_SECOND_SEC1 | RTC_SECOND_SEC0));
 }
 
 /**
  * \brief   This function sets the MINUTE register with the specified value.\n
  *
  * \param   baseAdd  The base address of the RTC instance being used.\n
- * \param   minValue  The value of 'minutes' to be written to MINUTE 
- *                    register.\n  
+ * \param   minValue  The value of 'minutes' to be written to MINUTE
+ *                    register.\n
  *
  * \return  None.
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
- *  
+ *
  */
 
 void RTCMinuteSet(unsigned int baseAdd, unsigned int minValue)
 {
     /*
     ** Writing to MINUTE register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
- 
+
     while(IS_RTC_BUSY);
 
     /* Writing least 7 bits of 'minValue' into MINUTE register.*/
-    HWREG(baseAdd + RTC_MINUTE) = (minValue & (RTC_MINUTE_MIN1 | 
+    HWREG(baseAdd + RTC_MINUTE) = (minValue & (RTC_MINUTE_MIN1 |
                                                 RTC_MINUTE_MIN0));
 }
 
@@ -813,7 +813,7 @@ void RTCMinuteSet(unsigned int baseAdd, unsigned int minValue)
 
 unsigned int RTCMinuteGet(unsigned int baseAdd)
 {
-    return(HWREG(baseAdd + RTC_MINUTE) & (RTC_MINUTE_MIN1 | 
+    return(HWREG(baseAdd + RTC_MINUTE) & (RTC_MINUTE_MIN1 |
                                            RTC_MINUTE_MIN0));
 }
 
@@ -822,16 +822,16 @@ unsigned int RTCMinuteGet(unsigned int baseAdd)
  *
  * \param  baseAdd   The base address of the RTC instance being used.\n
  * \param  hourValue  The value of 'hours' to be written into HOURS register.\n
- * 
+ *
  * \return None.
  *
  * \note   Programming the HOUR register with the hours value will also modify
  *         the MERIDIEM bit present in the HOUR register. Thus, invoke the \n
- *         API \RTCMeridiemSet after invoking this API to set the meridiem 
+ *         API \RTCMeridiemSet after invoking this API to set the meridiem
  *         type. \n
- *         If the RTC is busy in updating its registers, then this API waits 
+ *         If the RTC is busy in updating its registers, then this API waits
  *         until this update is complete. \n
- * 
+ *
  */
 
 
@@ -840,12 +840,12 @@ void RTCHourSet(unsigned int baseAdd, unsigned int hourValue)
 
     /*
     ** Writing to HOUR register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
 
     /* Writing least 6 bits of 'hourValue' into HOUR register.*/
-    HWREG(baseAdd + RTC_HOUR) = (hourValue & (RTC_HOUR_HOUR1 | 
+    HWREG(baseAdd + RTC_HOUR) = (hourValue & (RTC_HOUR_HOUR1 |
                                               RTC_HOUR_HOUR0));
 }
 
@@ -856,7 +856,7 @@ void RTCHourSet(unsigned int baseAdd, unsigned int hourValue)
  *
  * \param  baseAdd   The base address of the RTC instance being used.\n
  *
- * \return The value in the HOUR register. 
+ * \return The value in the HOUR register.
  */
 unsigned int RTCHourGet(unsigned int baseAdd)
 {
@@ -864,8 +864,8 @@ unsigned int RTCHourGet(unsigned int baseAdd)
 }
 
 /**
- * \brief  This function sets the meridiem type for the time that is 
- *         programmed. 
+ * \brief  This function sets the meridiem type for the time that is
+ *         programmed.
  *
  * \param   baseAdd      The base address of the RTC instance being used.\n
  * \param   meridiemType  This specifies the meridiem type. This can take one
@@ -877,10 +877,10 @@ unsigned int RTCHourGet(unsigned int baseAdd)
  *
  * \note    Programming the type of meridiem is meaningful only when 12-hour
  *          mode of time representation has been opted for. Use RTCHourModeSet()
- *          to do this. 
- *          If the RTC is busy in updating its registers, then this API waits 
+ *          to do this.
+ *          If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
- */                        
+ */
 
 
 
@@ -888,10 +888,10 @@ void RTCMeridiemSet(unsigned int baseAdd, unsigned int meridiemType)
 {
     /*
     ** Writing to HOUR register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
-    
+
     /* Set the MERIDIEM bit in HOUR register.*/
     HWREG(baseAdd + RTC_HOUR) |= (meridiemType & RTC_HOUR_MERIDIEM);
 
@@ -902,12 +902,12 @@ void RTCMeridiemSet(unsigned int baseAdd, unsigned int meridiemType)
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
  *
- * \return  The meridiem type of the current time. This will be one of the 
+ * \return  The meridiem type of the current time. This will be one of the
  *          two below values:
  *          RTC_ANTE_MERIDIEM - indicating ante-meridiem(AM).
  *          RTC_POST_MERIDIEM - indicating post-meridiem(PM).
  *
- * \note    The meridiem type of the current time should be ignored if the 
+ * \note    The meridiem type of the current time should be ignored if the
  *          time representation is in 24 hour mode format.
  */
 
@@ -917,14 +917,14 @@ unsigned int RTCMeridiemGet(unsigned int baseAdd)
 }
 
 /**
- * \brief  This function sets the day of the month in the relevant register.  
+ * \brief  This function sets the day of the month in the relevant register.
  *
  * \param  baseAdd  The base address of the RTC instance being used.\n
  * \param  dayValue  The 'day' value to be written to DAY register.\n
  *
  * \return None.\n
  *
- * \note   If the RTC is busy in updating its registers, then this API waits 
+ * \note   If the RTC is busy in updating its registers, then this API waits
  *         until this update is complete. \n
  *
  */
@@ -933,17 +933,17 @@ void RTCDayOfMonthSet(unsigned int baseAdd, unsigned int dayValue)
 {
     /*
     ** Writing to DAY register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
 
     /* Writing least 6 bits of 'dayValue' to DAY register.*/
-    HWREG(baseAdd + RTC_DAY) = (dayValue & (RTC_DAY_DAY1 | RTC_DAY_DAY0));    
+    HWREG(baseAdd + RTC_DAY) = (dayValue & (RTC_DAY_DAY1 | RTC_DAY_DAY0));
 
 }
 
 /**
- * \brief  This function determines the day of the month currently held by 
+ * \brief  This function determines the day of the month currently held by
  *         relevant RTC register.
  *
  * \param  baseAdd  The base address of the RTC instance being used.\n
@@ -959,35 +959,35 @@ unsigned int RTCDayOfMonthGet(unsigned int baseAdd)
 
 /**
  * \brief   This function sets the month of the year in the relevant RTC
- *          register. 
+ *          register.
  *
  * \param   baseAdd    The base address of the RTC instance being used.\n
  * \param   monthValue  The 'month' value to be written to MONTH regsiter.\n
  *
  * \return  None.\n
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
- 
+
  */
 
 void RTCMonthSet(unsigned int baseAdd, unsigned int monthValue)
 {
     /*
     ** Writing to MONTH register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
 
     /* Writing least 5 bits of 'monthValue' into MONTH register.*/
-    HWREG(baseAdd + RTC_MONTH) = (monthValue & (RTC_MONTH_MONTH1 | 
+    HWREG(baseAdd + RTC_MONTH) = (monthValue & (RTC_MONTH_MONTH1 |
                                                 RTC_MONTH_MONTH0));
 
 }
 
 /**
- * \brief  This function determines the month of the year from the relevant 
- *         RTC register. 
+ * \brief  This function determines the month of the year from the relevant
+ *         RTC register.
  *
  * \param   baseAdd    The base address of the RTC instance being used.\n
  *
@@ -1001,7 +1001,7 @@ unsigned int RTCMonthGet(unsigned int baseAdd)
 }
 
 /**
- * \brief   This function sets the year value in the relevant RTC register. 
+ * \brief   This function sets the year value in the relevant RTC register.
  *
  * \param   baseAdd  The base address of the RTC instance being used.\n
  * \param   yearValue  The 'year' value to be written to YEAR register. \n
@@ -1010,9 +1010,9 @@ unsigned int RTCMonthGet(unsigned int baseAdd)
  *
  * \note    We can program only the last two digits of the four digit year
  *          value. Ex: 87 is programmed for year being 1987. \n
- *          If the RTC is busy in updating its registers, then this API waits 
+ *          If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
- * 
+ *
  */
 
 
@@ -1020,7 +1020,7 @@ void RTCYearSet(unsigned int baseAdd, unsigned int yearValue)
 {
     /*
     ** Writing to YEAR register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
 
@@ -1031,10 +1031,10 @@ void RTCYearSet(unsigned int baseAdd, unsigned int yearValue)
 
 /**
  * \brief  This function determines the current year value from the relevant
- *         RTC register. 
+ *         RTC register.
  *
  * \param  baseAdd  The base address of the RTC instance being used.\n
- * 
+ *
  * \return  The 'year' value in the YEAR register.\n
  */
 
@@ -1044,7 +1044,7 @@ unsigned int RTCYearGet(unsigned int baseAdd)
 }
 
 /**
- * \brief   This function sets the day of the week in the relevant RTC register. 
+ * \brief   This function sets the day of the week in the relevant RTC register.
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
  * \param   weekValue  The 'day of the week' value to be written to DOTW
@@ -1056,22 +1056,22 @@ unsigned int RTCYearGet(unsigned int baseAdd)
  *                     RTC_DOTW_WED - indicating Wednesday. \n
  *                     RTC_DOTW_THU - indicating Thursday. \n
  *                     RTC_DOTW_FRI - indicating Friday. \n
- *                     RTC_DOTW_SAT - indicating Saturday. \n                     
+ *                     RTC_DOTW_SAT - indicating Saturday. \n
  *
  * \return  None.
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
- * 
+ *
  */
 void RTCDayOfTheWeekSet(unsigned int baseAdd, unsigned int dotwValue)
 {
     /*
     ** Writing to DOTW register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
-    
+
     /* Write least 3 bits of 'weekValue' to DOTW register.*/
     HWREG(baseAdd + RTC_DOTW) = (dotwValue & RTC_DOTW_DOTW);
 }
@@ -1082,7 +1082,7 @@ void RTCDayOfTheWeekSet(unsigned int baseAdd, unsigned int dotwValue)
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
  *
- * \return  The 'day of the week' value in the DOTW register. 
+ * \return  The 'day of the week' value in the DOTW register.
  *          This returns one of the seven values mentioned in the API
  *          \RTCDayOfTheWeekSet. \n
  */
@@ -1139,11 +1139,11 @@ void RTCTimeSet(unsigned int baseAdd, unsigned int time)
     HWREG(baseAdd + RTC_HOUR) = (((time & HOUR_MASK) >> HOUR_SHIFT) |
                                  (time & MERIDIEM_MASK));
 
-}  
+}
 
 
 /**
- * \brief   This function reads the current time from the registers holding 
+ * \brief   This function reads the current time from the registers holding
  *          time information. \n
  *
  * \param   baseAdd  The base address of the RTC instance being used.\n
@@ -1168,20 +1168,20 @@ unsigned int RTCTimeGet(unsigned int baseAdd)
     hour = (hour & (RTC_HOUR_HOUR1 | RTC_HOUR_HOUR0)) << HOUR_SHIFT;
 
     /* Reading MERIDIEM bit in HOUR register.*/
-    mer = (HWREG(baseAdd + RTC_HOUR) & RTC_HOUR_MERIDIEM);      
-          
- 
-    return ( sec | min | hour | mer);  
+    mer = (HWREG(baseAdd + RTC_HOUR) & RTC_HOUR_MERIDIEM);
+
+
+    return ( sec | min | hour | mer);
 }
 
 /**
- * \brief  This function sets the specified calendar information in registers 
+ * \brief  This function sets the specified calendar information in registers
  *         holding calendar settings. \n
- *          
+ *
  *
  * \param   baseAdd  The base address of the RTC instance being used.\n
  * \param   calendar  This parameter includes values for day of the month,
- *                    month, year and day of the week. The format is:  
+ *                    month, year and day of the week. The format is:
  *                    <day of the month><month><year><day of the week>
  *
  *                    For example, if the date is: 29 November,2010,Monday,then
@@ -1190,9 +1190,9 @@ unsigned int RTCTimeGet(unsigned int baseAdd)
  *
  * \return  None.
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
- * 
+ *
  */
 
 void RTCCalendarSet(unsigned int baseAdd, unsigned int calendar)
@@ -1227,17 +1227,17 @@ void RTCCalendarSet(unsigned int baseAdd, unsigned int calendar)
 unsigned int RTCCalendarGet(unsigned int baseAdd)
 {
     unsigned int calVal = 0;
-    
+
     /* Reading from the DAY register.*/
     calVal = (HWREG(baseAdd + RTC_DAY) & (RTC_DAY_DAY1 | RTC_DAY_DAY0)) <<  \
                                              DAY_SHIFT;
 
     /* Reading from MONTH register.*/
-    calVal |= (HWREG(baseAdd + RTC_MONTH) & (RTC_MONTH_MONTH1 | 
+    calVal |= (HWREG(baseAdd + RTC_MONTH) & (RTC_MONTH_MONTH1 |
                                               RTC_MONTH_MONTH0)) << MONTH_SHIFT;
 
     /* Reading from YEAR register.*/
-    calVal |= (HWREG(baseAdd + RTC_YEAR) & (RTC_YEAR_YEAR1 | 
+    calVal |= (HWREG(baseAdd + RTC_YEAR) & (RTC_YEAR_YEAR1 |
                                              RTC_YEAR_YEAR0))  << YEAR_SHIFT;
 
     /* Reading from DOTW register.*/
@@ -1251,20 +1251,20 @@ unsigned int RTCCalendarGet(unsigned int baseAdd)
  *
  * \param  baseAdd  The base address of the RTC instance being used.\n
  * \param  alarmsecValue  The seconds value to be set in the ALARMSECOND
- *                        registers. \n 
+ *                        registers. \n
  *
  * \return None.
  *
- * \note   If the RTC is busy in updating its registers, then this API waits 
+ * \note   If the RTC is busy in updating its registers, then this API waits
  *         until this update is complete. \n
- * 
+ *
  */
 
 void RTCAlarmSecondSet(unsigned int baseAdd, unsigned int alarmSecValue)
-{    
+{
     /*
     ** Writing to ALARMSECOND register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
 
@@ -1286,7 +1286,7 @@ void RTCAlarmSecondSet(unsigned int baseAdd, unsigned int alarmSecValue)
 
 unsigned int RTCAlarmSecondGet(unsigned int baseAdd)
 {
-    return(HWREG(baseAdd + RTC_ALARMSECOND) & (RTC_ALARMSECOND_SEC1 | 
+    return(HWREG(baseAdd + RTC_ALARMSECOND) & (RTC_ALARMSECOND_SEC1 |
                                                 RTC_ALARMSECOND_SEC0));
 }
 
@@ -1294,12 +1294,12 @@ unsigned int RTCAlarmSecondGet(unsigned int baseAdd)
  * \brief   This configures the minutes value in the ALARM registers. \n
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
- * \param   alarmminValue  The minutes value to be written to 
+ * \param   alarmminValue  The minutes value to be written to
  *                         ALARMMINUTES register. \n
  * \return  None.
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
- *          until this update is complete. \n 
+ * \note    If the RTC is busy in updating its registers, then this API waits
+ *          until this update is complete. \n
  *
  */
 
@@ -1308,9 +1308,9 @@ void RTCAlarmMinuteSet(unsigned int baseAdd, unsigned int alrmMinValue)
 {
     /*
     ** Writing to ALARMMINUTE register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
-    
+
     while(IS_RTC_BUSY);
 
     /* Write least 7 bits to ALARMMINUTE register.*/
@@ -1330,7 +1330,7 @@ void RTCAlarmMinuteSet(unsigned int baseAdd, unsigned int alrmMinValue)
 
 unsigned int RTCAlarmMinuteGet(unsigned int baseAdd)
 {
-    return(HWREG(baseAdd + RTC_ALARMMINUTE) & (RTC_ALARMMINUTE_MIN1 | 
+    return(HWREG(baseAdd + RTC_ALARMMINUTE) & (RTC_ALARMMINUTE_MIN1 |
                                                 RTC_ALARMMINUTE_MIN0));
 }
 
@@ -1338,32 +1338,32 @@ unsigned int RTCAlarmMinuteGet(unsigned int baseAdd)
  * \brief  This sets the value of hours in the ALARM registers. \n
  *
  * \param  baseAdd  The base address of the RTC instance being used.\n
- * \param  alarmhourValue  The value of hours to be written to 
+ * \param  alarmhourValue  The value of hours to be written to
  *                         ALARMHOUR register. \n
  * \return None.
- * 
- * \note   Programming the ALARMHOUR register with the hours value will also 
+ *
+ * \note   Programming the ALARMHOUR register with the hours value will also
  *         modify the MERIDIEM bit present in the ALARMHOUR register.
  *         Thus, invoke the API RTCAlarmHourMeridiemSet() after invoking
  *         the current API to configure the MERIDIEM bit. \n
- *         If the RTC is busy in updating its registers, then this API waits 
+ *         If the RTC is busy in updating its registers, then this API waits
  *         until this update is complete. \n
- * 
+ *
  */
 
 void RTCAlarmHourSet(unsigned int baseAdd, unsigned int alrmHourVal)
 {
     /*
     ** Writing to ALARMHOUR register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
 
     /*
-    ** Writing the least 6 bits of 'alrmHourVal' to the ALARMHOUR 
+    ** Writing the least 6 bits of 'alrmHourVal' to the ALARMHOUR
     ** register.
     */
-    HWREG(baseAdd + RTC_ALARMHOUR) = (alrmHourVal & (RTC_ALARMHOUR_HOUR1 | 
+    HWREG(baseAdd + RTC_ALARMHOUR) = (alrmHourVal & (RTC_ALARMHOUR_HOUR1 |
                                                       RTC_ALARMHOUR_HOUR0));
 }
 
@@ -1378,7 +1378,7 @@ void RTCAlarmHourSet(unsigned int baseAdd, unsigned int alrmHourVal)
 
 unsigned int RTCAlarmHourGet(unsigned int baseAdd)
 {
-    return(HWREG(baseAdd + RTC_ALARMHOUR) & (RTC_ALARMHOUR_HOUR1 | 
+    return(HWREG(baseAdd + RTC_ALARMHOUR) & (RTC_ALARMHOUR_HOUR1 |
                                               RTC_ALARMHOUR_HOUR0));
 }
 
@@ -1397,7 +1397,7 @@ unsigned int RTCAlarmHourGet(unsigned int baseAdd)
  * \note    Programming the type of meridiem is meaningful only when 12-hour
  *          mode of time representation has been opted for. Use RTCHourModeSet()
  *          to do this.
- *          If the RTC is busy in updating its registers, then this API waits 
+ *          If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
  */
 
@@ -1406,7 +1406,7 @@ void RTCAlarmHourMeridiemSet(unsigned int baseAdd, unsigned int meridiemType)
 {
     /*
     ** Writing to YEAR register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
 
@@ -1427,7 +1427,7 @@ void RTCAlarmHourMeridiemSet(unsigned int baseAdd, unsigned int meridiemType)
  * \note    The meridiem type of the ALARM time should be ignored if the
  *          time representation is in 24 hour mode format.
  */
- 
+
 unsigned int RTCAlarmHourMeridiemGet(unsigned int baseAdd)
 {
     return(HWREG(baseAdd + RTC_ALARMHOUR) & RTC_HOUR_MERIDIEM);
@@ -1437,7 +1437,7 @@ unsigned int RTCAlarmHourMeridiemGet(unsigned int baseAdd)
  * \brief  This function sets the ALARM time regiters with the specified
  *         ALARM time value. \n
  *
- * \param  baseAdd   The base address of the RTC instance being used.\n  
+ * \param  baseAdd   The base address of the RTC instance being used.\n
  * \param  alarmTime  The time is specified here and should be in the
  *                    following format: <hours><minutes><seconds><meridiem>.\n
  *                    Example - For 12-hour mode representation:\n
@@ -1448,9 +1448,9 @@ unsigned int RTCAlarmHourMeridiemGet(unsigned int baseAdd)
  *                    If the time is 17 hours, 36 minutes, 41 seconds, then
  *                    'alarmTime' should be (0x17364100).\n
  *
- * \note   If the RTC is busy in updating its registers, then this API waits 
+ * \note   If the RTC is busy in updating its registers, then this API waits
  *         until this update is complete. \n
- * 
+ *
  */
 
 
@@ -1472,7 +1472,7 @@ void RTCAlarmTimeSet(unsigned int baseAdd, unsigned int alarmTime)
 
 
 
-/**  
+/**
  * \brief   This function reads the programmed ALARM time from the ALARM
  *          registers.
  *
@@ -1481,9 +1481,9 @@ void RTCAlarmTimeSet(unsigned int baseAdd, unsigned int alarmTime)
  * \return  The ALARM time is returned in the format:
  *          <hour><minute><second><meridiem>.
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
- * 
+ *
  */
 unsigned int RTCAlarmTimeGet(unsigned int baseAdd)
 {
@@ -1504,10 +1504,10 @@ unsigned int RTCAlarmTimeGet(unsigned int baseAdd)
     alrmHour = (alrmHour & (RTC_HOUR_HOUR1 | RTC_HOUR_HOUR0)) << HOUR_SHIFT;
 
     /* Reading MERIDIEM bit in ALARMHOUR register.*/
-    alrmMer = (HWREG(baseAdd + RTC_ALARMHOUR) & RTC_HOUR_MERIDIEM);      
-          
- 
-    return ( alrmSec | alrmMin | alrmHour | alrmMer);  
+    alrmMer = (HWREG(baseAdd + RTC_ALARMHOUR) & RTC_HOUR_MERIDIEM);
+
+
+    return ( alrmSec | alrmMin | alrmHour | alrmMer);
 }
 
  /**
@@ -1519,21 +1519,21 @@ unsigned int RTCAlarmTimeGet(unsigned int baseAdd)
  *
  * \return None.
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
- * 
+ *
  */
 
 void RTCAlarmDayOfMonthSet(unsigned int baseAdd, unsigned int alarmDayValue)
 {
     /*
     ** Writing to YEAR register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
- 
+
     /* Writing the least 6 bits of 'alarmDayValue' to ALARMHOUR register.*/
-    HWREG(baseAdd + RTC_ALARMDAY) = (alarmDayValue & (RTC_ALARMDAY_DAY1 | 
+    HWREG(baseAdd + RTC_ALARMDAY) = (alarmDayValue & (RTC_ALARMDAY_DAY1 |
                                                   RTC_ALARMDAY_DAY0));
 
 }
@@ -1555,25 +1555,25 @@ unsigned int RTCAlarmDayOfMonthGet(unsigned int baseAdd)
  * \brief   This function sets the value of the month in the ALARM registers.\n
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
- * \param   alarmmonthValue  The value of the month to be written to 
+ * \param   alarmmonthValue  The value of the month to be written to
  *                           ALARMMONTH register. \n
  * \return  None.
  *
- * \note    If the RTC is busy in updating its registers, then this API waits 
+ * \note    If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
- * 
+ *
  */
 
 void RTCAlarmMonthSet(unsigned int baseAdd, unsigned int alrmMnthVal)
 {
     /*
     ** Writing to YEAR register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
-   
+
     /* Writing the least 6 bits of 'alrmMnthVal' to ALARMHOUR register.*/
-    HWREG(baseAdd + RTC_ALARMMONTH) = (alrmMnthVal & (RTC_ALARMMONTH_MONTH1 | 
+    HWREG(baseAdd + RTC_ALARMMONTH) = (alrmMnthVal & (RTC_ALARMMONTH_MONTH1 |
                                                        RTC_ALARMMONTH_MONTH0));
 }
 
@@ -1582,13 +1582,13 @@ void RTCAlarmMonthSet(unsigned int baseAdd, unsigned int alrmMnthVal)
  *         ALARM registers. \n
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
- * 
+ *
  * \return  The value of month being set in the ALARMMONTH register. \n
  */
 
 unsigned int RTCAlarmMonthGet(unsigned int baseAdd)
 {
-    return(HWREG(baseAdd + RTC_ALARMMONTH) & (RTC_ALARMMONTH_MONTH1 | 
+    return(HWREG(baseAdd + RTC_ALARMMONTH) & (RTC_ALARMMONTH_MONTH1 |
                                                RTC_ALARMMONTH_MONTH0));
 }
 
@@ -1598,12 +1598,12 @@ unsigned int RTCAlarmMonthGet(unsigned int baseAdd)
  * \param   baseAdd   The base address of the RTC instance being used.\n
  * \param   alarmyearValue  The value of year to be written to ALARMYEAR
  *                          register. \n
- * 
+ *
  * \return  None.
  *
  * \note    We can program only the last two digits of the four digit year
  *          value. Ex: 87 is programmed for year being 1987.
- *          If the RTC is busy in updating its registers, then this API waits 
+ *          If the RTC is busy in updating its registers, then this API waits
  *          until this update is complete. \n
  *
  */
@@ -1612,17 +1612,17 @@ void RTCAlarmYearSet(unsigned int baseAdd, unsigned int alrmYrVal)
 {
     /*
     ** Writing to YEAR register requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
     while(IS_RTC_BUSY);
-    
+
     /* Writing the least 8 bits of 'alrmYrVal' to ALARMYEAR register.*/
-    HWREG(baseAdd + RTC_ALARMYEAR) = (alrmYrVal & (RTC_ALARMYEAR_YEAR1 | 
+    HWREG(baseAdd + RTC_ALARMYEAR) = (alrmYrVal & (RTC_ALARMYEAR_YEAR1 |
                                                     RTC_ALARMYEAR_YEAR0));
 }
 
 /**
- * \brief  This function determines the value of the year being set in the 
+ * \brief  This function determines the value of the year being set in the
  *         ALARM registers. \n
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
@@ -1633,7 +1633,7 @@ void RTCAlarmYearSet(unsigned int baseAdd, unsigned int alrmYrVal)
 
 unsigned int RTCAlarmYearGet(unsigned int baseAdd)
 {
-    return(HWREG(baseAdd + RTC_ALARMYEAR) & (RTC_ALARMYEAR_YEAR1 | 
+    return(HWREG(baseAdd + RTC_ALARMYEAR) & (RTC_ALARMYEAR_YEAR1 |
                                               RTC_ALARMYEAR_YEAR0));
 }
 
@@ -1643,17 +1643,17 @@ unsigned int RTCAlarmYearGet(unsigned int baseAdd)
  *
  * \param  baseAdd  The base address of the RTC instance being used.\n
  * \param  calVal    This parameter includes values for day of the month,
- *                   month and  year. The format is:  
+ *                   month and  year. The format is:
  *                   <day of the month><month><year>.
  *                   For example, if the ALARM calendar registers are to be
- *                   loaded with a date namely 24 February, 2003, then 
+ *                   loaded with a date namely 24 February, 2003, then
  *                   'calVal' should be 0x24020300(February=0x02, 2003=0x03)
  *
  * \return None. \n
- * 
- * \note   If the RTC is busy in updating its registers, then this API waits 
+ *
+ * \note   If the RTC is busy in updating its registers, then this API waits
  *         until this update is complete. \n
- * 
+ *
  */
 void RTCAlarmCalendarSet(unsigned int baseAdd, unsigned int calVal)
 {
@@ -1679,23 +1679,23 @@ void RTCAlarmCalendarSet(unsigned int baseAdd, unsigned int calVal)
  *          registers. The format of this information is:
  *          <day of the week><month><year>.
  *
- * 
+ *
  */
 unsigned int RTCAlarmCalendarGet(unsigned int baseAdd)
 {
     unsigned int calVal = 0;
-    
+
     /* Reading from the ALARMDAY register.*/
-    calVal = (HWREG(baseAdd + RTC_ALARMDAY) & (RTC_DAY_DAY1 | 
+    calVal = (HWREG(baseAdd + RTC_ALARMDAY) & (RTC_DAY_DAY1 |
                                                 RTC_DAY_DAY0)) << DAY_SHIFT;
 
     /* Reading from ALARMMONTH register.*/
-    calVal |= (HWREG(baseAdd + RTC_ALARMMONTH) & (RTC_MONTH_MONTH1 | 
+    calVal |= (HWREG(baseAdd + RTC_ALARMMONTH) & (RTC_MONTH_MONTH1 |
                                                    RTC_MONTH_MONTH0)) <<   \
                                                    MONTH_SHIFT;
 
     /* Reading from ALARMYEAR register.*/
-    calVal |= (HWREG(baseAdd + RTC_ALARMYEAR) & (RTC_YEAR_YEAR1 | 
+    calVal |= (HWREG(baseAdd + RTC_ALARMYEAR) & (RTC_YEAR_YEAR1 |
                                                   RTC_YEAR_YEAR0))  <<     \
                                                   YEAR_SHIFT;
 
@@ -1712,21 +1712,21 @@ unsigned int RTCAlarmCalendarGet(unsigned int baseAdd)
  *
  * \return None. \n
  *
- * \note   Compensation value is subtracted from the 32KHz period. The 
+ * \note   Compensation value is subtracted from the 32KHz period. The
  *         subtraction here is accomplished by two's complement
- *         addititon. Thus the application should pass the two's 
+ *         addititon. Thus the application should pass the two's
  *         complement value of the value to be subtracted.\n
- *         If the RTC is busy in updating its registers, then this API waits 
+ *         If the RTC is busy in updating its registers, then this API waits
  *         until this update is complete. \n
- * 
+ *
  */
 void RTCCompensationSet(unsigned int baseAdd, unsigned int compVal)
 {
     /*
     ** Writing to COMPENSATION registers requires that BUSY bit in STATUS register
-    ** is low.    
+    ** is low.
     */
-    while(IS_RTC_BUSY);  
+    while(IS_RTC_BUSY);
 
     /* Writing the lower 8 bits of 'compVal' to COMPLSB register.*/
     HWREG(baseAdd + RTC_COMPLSB) = (compVal & COMP_LOW_MASK);
@@ -1736,15 +1736,15 @@ void RTCCompensationSet(unsigned int baseAdd, unsigned int compVal)
 }
 
 /**
- * \brief   This function reads the compensation value being set in the 
+ * \brief   This function reads the compensation value being set in the
  *          compensation registers. \n
  *
  * \param   baseAdd   The base address of the RTC instance being used.\n
  *
  * \return  The value in the compensation registers COMPMSB and COMPLSB.
  *
- * \note    This returns the two's complement value of the number to be 
- *          subtracted from 32KHz period. Refer to \note of 
+ * \note    This returns the two's complement value of the number to be
+ *          subtracted from 32KHz period. Refer to \note of
  *          \RTCCompensationSet  API for more details.
  */
 
@@ -1770,14 +1770,14 @@ unsigned int RTCCompensationGet(unsigned int baseAdd)
  * \param   baseAdd       The base address of the RTC instance being used.\n
  * \param   regNumber     This specifies the scratch register number to be
  *                        accessed. This can take the values: 0, 1 or 2. \n
- * \param   scratchValue  Refers to the value to be written to the scratch 
+ * \param   scratchValue  Refers to the value to be written to the scratch
  *                        registers. \n
  *
  * \return  None.
  *
  */
 
-void RTCScratchPadSet(unsigned int baseAdd, unsigned int regNumber, 
+void RTCScratchPadSet(unsigned int baseAdd, unsigned int regNumber,
                       unsigned int scratchValue)
 {
     unsigned int offset = 0;
@@ -1789,7 +1789,7 @@ void RTCScratchPadSet(unsigned int baseAdd, unsigned int regNumber,
 /**
  * \brief   This function reads the value stored in a specified scratch
  *          register. \n
- * 
+ *
  * \param   baseAdd  The base address of the RTC instance being used.\n
  * \param   regNumber Specifies the scratch register number to be accessed.
  *                    This can take the values: 0, 1 or 2. \n
@@ -1800,7 +1800,7 @@ void RTCScratchPadSet(unsigned int baseAdd, unsigned int regNumber,
 unsigned int RTCScratchPadGet(unsigned int baseAdd, unsigned int regNumber)
 {
     unsigned int offset = 0;
- 
+
     offset = regNumber * 4;
     return(HWREG(baseAdd + RTC_SCRATCH0 + offset));
 }
@@ -1921,7 +1921,7 @@ void RTCWakeUpAlarmEventControl(unsigned int baseAdd, unsigned int controlFlag)
  *   event\n
  *
  * \return  None
- */ 
+ */
 
 void RTCWakeUpTimerEventControl(unsigned int baseAdd, unsigned int controlFlag)
 {
@@ -2220,7 +2220,7 @@ void RTCAlarm2CalendarSet(unsigned int baseAdd, unsigned int calVal)
 }
 
 /*****************************************************************************
-**                      End of APIs specific to AM335x                       
+**                      End of APIs specific to AM335x
 *****************************************************************************/
 
 /************************* End of file ***************************************/
diff --git a/lib/tiam1808/drivers/spi.c b/lib/tiam1808/drivers/spi.c
index e91d6b951..880f95a2e 100644
--- a/lib/tiam1808/drivers/spi.c
+++ b/lib/tiam1808/drivers/spi.c
@@ -1,6 +1,6 @@
 /**
 *  \file spi.c
-*    
+*
 *  \brief SPI device abstraction layer APIs
 */
 
@@ -68,12 +68,12 @@ void SPIClkConfigure(unsigned int baseAdd, unsigned int moduleClk,
 * \brief - It will Enable SPI module\n.
 *
 * \param - baseAdd  is the Memory Address of the SPI instance used\n.
-*    
+*
 * \return none.
-**/    
+**/
 void SPIEnable(unsigned int baseAdd)
 {
-    HWREG(baseAdd + SPI_SPIGCR1) |= SPI_SPIGCR1_ENABLE;           
+    HWREG(baseAdd + SPI_SPIGCR1) |= SPI_SPIGCR1_ENABLE;
 }
 /**
 * \brief - It will put SPI in to reset state.\n
@@ -95,8 +95,8 @@ void SPIReset(unsigned int baseAdd)
 **/
 void SPIOutOfReset(unsigned int baseAdd)
 {
-    HWREG(baseAdd + SPI_SPIGCR0) =  SPI_SPIGCR0_RESET; 
-}      
+    HWREG(baseAdd + SPI_SPIGCR0) =  SPI_SPIGCR0_RESET;
+}
 /**
 * \brief - Configures SPI to master or slave mode.
 *
@@ -110,32 +110,37 @@ void SPIModeConfigure(unsigned int baseAdd, unsigned int flag)
 }
 
 /**
-* \brief - Configures SPI Pin Control Registers.\n
+* \brief - Get SPI Pin Control Register value.\n
 *
 * \param - baseAdd is the Memory Address of the SPI instance used.\n
 * \param - idx     is the Pin Control register number.It can take
 *                  any integer value between 0 and 5.\n
 *
-* \param - flag    is to indicate to whether to (1)read from Pin Control
-*                  Register or to (0)write to Pin Control Register.\n
+* \param - val     the value read
 *
-* \param - val     is a value/return argument which has the value to be written
-*                  in case of writes or the value read in case of reads
+* \return none.\n
+**/
+void SPIPinControlGet(unsigned int baseAdd, unsigned int idx, unsigned int *val)
+{
+    *val = HWREG(baseAdd + SPI_SPIPC(idx));
+}
+
+/**
+* \brief - Set SPI Pin Control Register value.\n
+*
+* \param - baseAdd is the Memory Address of the SPI instance used.\n
+* \param - idx     is the Pin Control register number.It can take
+*                  any integer value between 0 and 5.\n
+*
+* \param - val     the value to be written
 *
 * \return none.\n
 **/
-void SPIPinControl(unsigned int baseAdd, unsigned int idx,
-                           unsigned int flag, unsigned int *val)
+void SPIPinControlSet(unsigned int baseAdd, unsigned int idx, unsigned int val)
 {
-    if (0 == flag)
-    {
-        HWREG(baseAdd + SPI_SPIPC(idx)) = *val;
-    }
-    else
-    {
-        *val = HWREG(baseAdd + SPI_SPIPC(idx));
-    }
+    HWREG(baseAdd + SPI_SPIPC(idx)) = val;
 }
+
 /**
 * \brief - Configures SPI CS and ENA Delay in SPIDELAY Register.\n
 *
@@ -159,7 +164,7 @@ void SPIDelayConfigure(unsigned int baseAdd, unsigned int c2edelay,
 {
     HWREG(baseAdd + SPI_SPIDELAY) |= (c2edelay & SPI_SPIDELAY_C2EDELAY);
 
-    HWREG(baseAdd + SPI_SPIDELAY) |= (SPI_SPIDELAY_T2EDELAY & 
+    HWREG(baseAdd + SPI_SPIDELAY) |= (SPI_SPIDELAY_T2EDELAY &
                                      (t2edelay << SPI_SPIDELAY_T2EDELAY_SHIFT));
 
     HWREG(baseAdd + SPI_SPIDELAY) |= (SPI_SPIDELAY_T2CDELAY &
@@ -167,7 +172,7 @@ void SPIDelayConfigure(unsigned int baseAdd, unsigned int c2edelay,
 
     HWREG(baseAdd + SPI_SPIDELAY) |= (SPI_SPIDELAY_C2TDELAY &
                                      (c2tdelay << SPI_SPIDELAY_C2TDELAY_SHIFT));
-}  
+}
 /**
 * \brief - Sets the default value for CS pin(line)  when no transmission is
 *            is performed by writing to SPIDEF Reg.\n
@@ -187,20 +192,20 @@ void SPIDefaultCSSet(unsigned int baseAdd, unsigned char dcsval)
 *            of the SPIDat1 Register.\n
 *
 * \param - baseAdd  is the Memory Address of the SPI data instance used.\n
-* \param - flag is value to Configure CSHOL,Wait Delay Conter Enable bit  
+* \param - flag is value to Configure CSHOL,Wait Delay Conter Enable bit
 *          and to select the appropriate DataFormat register.\n
 *
 *         flag can take following values.\n
-*               
+*
 *         SPI_CSHOLD            - To Hold the CS line active after data Transfer
 *                                 untill new data and Control information is
 *                                 loaded.\n
-*             
+*
 *         SPI_DELAY_COUNTER_ENA - Enables Delay Counter.\n
 *
-*         SPI_DATA_FORMAT0      - To select DataFormat Register 0.\n            
-*         SPI_DATA_FORMAT1      - To select DataFormat Register 1.\n            
-*         SPI_DATA_FORMAT2      - To select DataFormat Register 2.\n            
+*         SPI_DATA_FORMAT0      - To select DataFormat Register 0.\n
+*         SPI_DATA_FORMAT1      - To select DataFormat Register 1.\n
+*         SPI_DATA_FORMAT2      - To select DataFormat Register 2.\n
 *         SPI_DATA_FORMAT3      - To select DataFormat Register 3.\n
 *
 * \param - cs is the value to driven on CS pin(line).\n
@@ -212,10 +217,10 @@ void SPIDat1Config(unsigned int baseAdd, unsigned int flag, unsigned char cs)
     unsigned char *ptr = (unsigned char*)(baseAdd + SPI_SPIDAT1);
     unsigned char dcs;
 
-    *(ptr+3) = (char)((flag >> 24) | (flag & (SPI_SPIDAT1_DFSEL >> 
+    *(ptr+3) = (char)((flag >> 24) | (flag & (SPI_SPIDAT1_DFSEL >>
                                       SPI_SPIDAT1_DFSEL_SHIFT)));
 
-    dcs = HWREG(baseAdd + SPI_SPIDEF ) & (SPI_SPIDEF_CSDEF);          
+    dcs = HWREG(baseAdd + SPI_SPIDEF ) & (SPI_SPIDEF_CSDEF);
 
     *(ptr+2) = cs ^ dcs;
 }
@@ -240,14 +245,14 @@ void SPITransmitData1(unsigned int baseAdd, unsigned int data)
 * \param - dataFormat is the value to select the Format register.\n
 *
 *            dataFormat can take following value.\n
-*         
+*
 *            SPI_DATA_FORMAT0      - To select DataFormat Register 0.\n
 *            SPI_DATA_FORMAT1      - To select DataFormat Register 1.\n
 *            SPI_DATA_FORMAT2      - To select DataFormat Register 2.\n
 *            SPI_DATA_FORMAT3      - To select DataFormat Register 3.\n
 *
 * \return none.
-**/            
+**/
 void SPICSTimerDisable(unsigned int baseAdd, unsigned int dataFormat)
 {
     HWREG(baseAdd + SPI_SPIFMT(dataFormat)) |= SPI_SPIFMT_DISCSTIMERS;
@@ -373,7 +378,7 @@ void SPIShiftLsbFirst(unsigned int baseAdd, unsigned int dataFormat)
 * \param - flag    is the value determines whether odd or even Parity.\n
 *
 *            flag can take following values.\n
-*          
+*
 *            SPI_ODD_PARITY   -  selects odd parity
 *            SPI_EVEN_PARITY  -  selects even parity
 *
@@ -453,7 +458,7 @@ void SPIWdelaySet(unsigned int baseAdd, unsigned int flag,
 *
 * \return none.
 *
-* Note:It is applicable only in SPI Master Mode.SPIx_ENA is a active 
+* Note:It is applicable only in SPI Master Mode.SPIx_ENA is a active
 *      low signal
 **/
 void SPIWaitEnable(unsigned int baseAdd, unsigned int dataFormat)
@@ -501,7 +506,7 @@ void SPIWaitDisable(unsigned int baseAdd, unsigned int dataFormat)
 *
 * \return none.
 *
-**/    
+**/
 void SPIIntLevelSet(unsigned int baseAdd, unsigned int flag)
 {
     HWREG(baseAdd + SPI_SPILVL) |= flag;
@@ -625,10 +630,10 @@ unsigned int SPIDataReceive(unsigned int baseAdd)
 * \param - baseAdd is the memory instance to be used.\n
 *
 * \returns vector of the pending interrupt at interrupt line INT1.
-**/  
+**/
 unsigned int  SPIInterruptVectorGet(unsigned int baseAdd)
 {
-   unsigned int intVectorCode; 
+   unsigned int intVectorCode;
    intVectorCode = HWREG(baseAdd + SPI_INTVEC1);
 
    return (intVectorCode >> 1);
diff --git a/lib/tiam1808/drivers/syscfg.c b/lib/tiam1808/drivers/syscfg.c
index 5988eca1d..771dc5ccd 100644
--- a/lib/tiam1808/drivers/syscfg.c
+++ b/lib/tiam1808/drivers/syscfg.c
@@ -2,7 +2,7 @@
  * \file  syscfg.c
  *
  * \brief This file contains APIs to lock and unlock the System Configuration
- *        (SYSCFG) module registers by appropriately programming the Kick 
+ *        (SYSCFG) module registers by appropriately programming the Kick
  *        Registers.
  */
 
@@ -44,19 +44,19 @@
 #include "hw_types.h"
 
 /**
- * \brief   This function unlocks the write-protection of the SYSCFG module. 
- * 
+ * \brief   This function unlocks the write-protection of the SYSCFG module.
+ *
  * \return  None.
- * 
- * \note    The other registers of the SYSCFG module can be programmed only 
- *          when an unlock sequence has been written to the Kick Regsiters. 
+ *
+ * \note    The other registers of the SYSCFG module can be programmed only
+ *          when an unlock sequence has been written to the Kick Regsiters.
  */
 
 void SysCfgRegistersUnlock(void)
 {
      /* Unlocking Kick Registers before pinmux configuration */
      HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_KICK0R) = SYSCFG_KICK0R_UNLOCK;
-     HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_KICK1R) = SYSCFG_KICK1R_UNLOCK; 
+     HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_KICK1R) = SYSCFG_KICK1R_UNLOCK;
 
 }
 
@@ -65,8 +65,8 @@ void SysCfgRegistersUnlock(void)
  *
  * \return  None.
  *
- * \note    On programming the Kick Registers with any value other than the 
- *          unlock sequence, the SYSCFG module gets locked and its registers 
+ * \note    On programming the Kick Registers with any value other than the
+ *          unlock sequence, the SYSCFG module gets locked and its registers
  *          cannot be accessed.
  */
 
diff --git a/lib/tiam1808/drivers/timer.c b/lib/tiam1808/drivers/timer.c
index 037bf2122..a92a48848 100644
--- a/lib/tiam1808/drivers/timer.c
+++ b/lib/tiam1808/drivers/timer.c
@@ -61,7 +61,7 @@
 *******************************************************************************/
 
 /**
- * \brief   Enables the timer in the specified mode. The timer must be 
+ * \brief   Enables the timer in the specified mode. The timer must be
  *          configured before it is enabled. The timer starts running when this
  *          API is called
  *
@@ -82,7 +82,7 @@
  * \return  None.
  *
  **/
-void TimerEnable(unsigned int baseAddr, unsigned int timer, 
+void TimerEnable(unsigned int baseAddr, unsigned int timer,
                  unsigned int enaMode)
 {
     /* Clear the enable bits of both timers; the timers stops couting */
@@ -118,7 +118,7 @@ void TimerDisable(unsigned int baseAddr, unsigned int timer)
  * \brief   Configures the timer. The timer can be configured in 64 bit mode
  *          32 bit chained/unchained mode, or as a watchdog timer. The timer
  *          can be given external clock input or internal clock input. When
- *          this API is called,\n  
+ *          this API is called,\n
  *          > The Timer counters are cleared \n
  *          > Both the timers are disabled from Reset. Hence, both the timers
  *            will start counting when enabled. \n
@@ -126,19 +126,19 @@ void TimerDisable(unsigned int baseAddr, unsigned int timer)
  * \param   baseAddr      Base Address of the Timer Module Registers.
  * \param   config        Configuration of the Timer Module.
  *
- * config can take the values \n 
+ * config can take the values \n
  *     TMR_CFG_64BIT_CLK_INT - 64 bit mode with internal clock \n
  *     TMR_CFG_64BIT_CLK_EXT - 64 bit mode with external clock \n
  *     TMR_CFG_64BIT_WATCHDOG - 64 bit watchdog timer mode \n
  *     TMR_CFG_32BIT_CH_CLK_INT - 32 bit chained mode with internal clock \n
  *     TMR_CFG_32BIT_CH_CLK_EXT - 32 bit chained mode with external clock \n
- *     TMR_CFG_32BIT_UNCH_CLK_BOTH_INT - 32 bit unchained mode; Both timers 
+ *     TMR_CFG_32BIT_UNCH_CLK_BOTH_INT - 32 bit unchained mode; Both timers
  *                                       clock sources are internal \n
  *     TMR_CFG_32BIT_UNCH_CLK_12INT_34EXT - 32 bit unchained mode; Clock source
- *                       for Timer12 is internal and for Timer34 is external \n 
+ *                       for Timer12 is internal and for Timer34 is external \n
  *     TMR_CFG_32BIT_UNCH_CLK_12EXT_34INT - 32 bit unchained mode; Clock source
  *                       for Timer12 is external and for Timer34 is internal \n
- *     TMR_CFG_32BIT_UNCH_CLK_BOTH_EXT - 32 bit unchained  mode; Both timers 
+ *     TMR_CFG_32BIT_UNCH_CLK_BOTH_EXT - 32 bit unchained  mode; Both timers
  *                                       clock sources are external
  *
  * \return  None.
@@ -166,7 +166,7 @@ void TimerConfigure(unsigned int baseAddr, unsigned int config)
     ** Select the timer mode and disable the timer module from Reset
     ** Timer Plus features are enabled.
     */
-    HWREG(baseAddr + TMR_TGCR) |= (config & 
+    HWREG(baseAddr + TMR_TGCR) |= (config &
                                    (TMR_TGCR_TIMMODE | TMR_TGCR_TIM34RS |
                                     TMR_TGCR_TIM12RS | TMR_TGCR_PLUSEN));
 }
@@ -190,7 +190,7 @@ void TimerWatchdogActivate(unsigned int baseAddr)
     HWREG(baseAddr + TMR_WDTCR) = ((HWREG(baseAddr + TMR_WDTCR) &
                                     (~TMR_WDTCR_WDKEY)) |
                                    (WDT_KEY_ACTIVE << TMR_WDTCR_WDKEY_SHIFT));
-                                        
+
 }
 
 /**
@@ -212,7 +212,7 @@ void TimerWatchdogReactivate(unsigned int baseAddr)
     HWREG(baseAddr + TMR_WDTCR) = ((HWREG(baseAddr + TMR_WDTCR) &
                                     (~TMR_WDTCR_WDKEY)) |
                                    (WDT_KEY_ACTIVE << TMR_WDTCR_WDKEY_SHIFT));
- 
+
 }
 
 /**
@@ -225,12 +225,12 @@ void TimerWatchdogReactivate(unsigned int baseAddr)
  * timer can take the values \n
  *     TMR_TIMER34 - Timer34 only \n
  *     TMR_TIMER12 - Timer12 only \n
- *     TMR_TIMER_BOTH - Both timers 
+ *     TMR_TIMER_BOTH - Both timers
  *
  * \return  None.
  *
  **/
-void TimerPeriodSet(unsigned int baseAddr, unsigned int timer, 
+void TimerPeriodSet(unsigned int baseAddr, unsigned int timer,
                     unsigned int period)
 {
     if(TMR_TIMER12 & timer)
@@ -254,7 +254,7 @@ void TimerPeriodSet(unsigned int baseAddr, unsigned int timer,
  *
  * timer can take the values \n
  *     TMR_TIMER34 - Timer34 \n
- *     TMR_TIMER12 - Timer12 
+ *     TMR_TIMER12 - Timer12
  *
  * \return  Period Value
  *
@@ -281,7 +281,7 @@ unsigned int TimerPeriodGet(unsigned int baseAddr, unsigned int timer)
  * \return  None.
  *
  **/
-void TimerCounterSet(unsigned int baseAddr, unsigned int timer, 
+void TimerCounterSet(unsigned int baseAddr, unsigned int timer,
                      unsigned int counter)
 {
     if(TMR_TIMER12 & timer)
@@ -333,7 +333,7 @@ unsigned int TimerCounterGet(unsigned int baseAddr, unsigned int timer)
  * \return  None.
  *
  **/
-void TimerReloadSet(unsigned int baseAddr, unsigned int timer, 
+void TimerReloadSet(unsigned int baseAddr, unsigned int timer,
                     unsigned int reload)
 {
     if(TMR_TIMER12 & timer)
@@ -402,7 +402,7 @@ unsigned int TimerCaptureGet(unsigned int baseAddr, unsigned int timer)
  * \return  None.
  *
  **/
-void TimerCompareSet(unsigned int baseAddr, unsigned int regIndex, 
+void TimerCompareSet(unsigned int baseAddr, unsigned int regIndex,
                      unsigned int compare)
 {
     /* Write only to the desired Compare register according to the index */
@@ -486,9 +486,9 @@ void TimerIntDisable(unsigned int baseAddr, unsigned int intFlags)
  * \return  Status of Interrupt. Returns all the fields of which status is set
  *
  * Note : This API will return the same fields which is passed as parameter, if
- * all the specified interrupt status is set. The return value will be 0 if 
- * none of the interrupt status in the parameter passed is set. 
- *     
+ * all the specified interrupt status is set. The return value will be 0 if
+ * none of the interrupt status in the parameter passed is set.
+ *
  **/
 unsigned int TimerIntStatusGet(unsigned int baseAddr, unsigned int statFlag)
 {
@@ -510,7 +510,7 @@ unsigned int TimerIntStatusGet(unsigned int baseAddr, unsigned int statFlag)
  *    TMR_INTSTAT34_TIMER_CAPT - Timer34 interrupt status in capture mode \n
  *
  * \return  None
- *     
+ *
  **/
 unsigned int TimerIntStatusClear(unsigned int baseAddr, unsigned int statFlag)
 {
@@ -533,10 +533,10 @@ unsigned int TimerIntStatusClear(unsigned int baseAddr, unsigned int statFlag)
  **/
 void TimerPreScalarCount34Set(unsigned int baseAddr, unsigned int psc34)
 {
-    HWREG(baseAddr + TMR_TGCR) &= ~(PRESCALE_MASK << TMR_TGCR_PSC34_SHIFT); 
+    HWREG(baseAddr + TMR_TGCR) &= ~(PRESCALE_MASK << TMR_TGCR_PSC34_SHIFT);
 
     /* Set the Prescalar value. This is applicable only for Timer34 */
-    HWREG(baseAddr + TMR_TGCR) |= ((psc34 & PRESCALE_MASK) << 
+    HWREG(baseAddr + TMR_TGCR) |= ((psc34 & PRESCALE_MASK) <<
                                    TMR_TGCR_PSC34_SHIFT);
 }
 
@@ -551,11 +551,11 @@ void TimerPreScalarCount34Set(unsigned int baseAddr, unsigned int psc34)
  **/
 unsigned int TimerPreScalarCount34Get(unsigned int baseAddr)
 {
-    /* 
-    ** Return the prescalar value. This is only for Timer34 in 32 bit 
+    /*
+    ** Return the prescalar value. This is only for Timer34 in 32 bit
     ** unchained mode.
-    */ 
-    return((HWREG(baseAddr + TMR_TGCR) & TMR_TGCR_PSC34) >> 
+    */
+    return((HWREG(baseAddr + TMR_TGCR) & TMR_TGCR_PSC34) >>
            TMR_TGCR_PSC34_SHIFT);
 }
 
@@ -574,7 +574,7 @@ void TimerDivDwnRatio34Set(unsigned int baseAddr, unsigned int tddr34)
     HWREG(baseAddr + TMR_TGCR) &= ~(TDDR_MASK << TMR_TGCR_TDDR34_SHIFT);
 
     /* Set the TDDR. This is only for Timer34  in unchained mode */
-    HWREG(baseAddr + TMR_TGCR) |= ((tddr34 & TDDR_MASK) << 
+    HWREG(baseAddr + TMR_TGCR) |= ((tddr34 & TDDR_MASK) <<
                                    TMR_TGCR_TDDR34_SHIFT);
 }
 
@@ -589,7 +589,7 @@ void TimerDivDwnRatio34Set(unsigned int baseAddr, unsigned int tddr34)
 unsigned int TimerDivDwnRatio34Get(unsigned int baseAddr)
 {
     /* Return the TDDR value. Only applicable in unchained mode for Timer34 */
-    return((HWREG(baseAddr + TMR_TGCR) & TMR_TGCR_TDDR34) >> 
+    return((HWREG(baseAddr + TMR_TGCR) & TMR_TGCR_TDDR34) >>
             TMR_TGCR_TDDR34_SHIFT);
 }
 
@@ -610,12 +610,12 @@ unsigned int TimerDivDwnRatio34Get(unsigned int baseAddr)
  *     TMR_CAPT_DISABLE - Capture Mode disable \n
  *     TMR_CAPT_ENABLE_RIS_EDGE - Capture enable at rising edge \n
  *     TMR_CAPT_ENABLE_FALL_EDGE - Capture enable at falling edge \n
- *     TMR_CAPT_ENABLE_BOTH_EDGE - Capture enable at both edges 
+ *     TMR_CAPT_ENABLE_BOTH_EDGE - Capture enable at both edges
  *
  * \return  None.
  *
  **/
-void TimerCaptureConfigure(unsigned int baseAddr, unsigned int timer, 
+void TimerCaptureConfigure(unsigned int baseAddr, unsigned int timer,
                            unsigned int cfgCap)
 {
     /* Clear the bits CAPTEN and edge selection bits */
@@ -632,7 +632,7 @@ void TimerCaptureConfigure(unsigned int baseAddr, unsigned int timer,
 /**
  * \brief   Enables the timer(s) for read reset mode. The timer shall be
  *          Configured in 32 bit unchained mode before this API is called.
- *          Read reset determines the effect of timer counter read on TIMn. 
+ *          Read reset determines the effect of timer counter read on TIMn.
  *          If Read reset is enabled, the timer counter will be reset when
  *          the timer counter register TIMn is read.
  *
@@ -649,7 +649,7 @@ void TimerCaptureConfigure(unsigned int baseAddr, unsigned int timer,
  **/
 void TimerReadResetEnable(unsigned int baseAddr, unsigned int timer)
 {
-    /* 
+    /*
     ** Enable the read reset mode for the specified timers; The timer counter
     ** for the corresponding timer will be reset for further TIMn reads
     */
@@ -746,7 +746,7 @@ void TimerInputGateDisable(unsigned int baseAddr, unsigned int timer)
  * \return  None.
  *
  **/
-void TimerPulseWidthSet(unsigned int baseAddr, unsigned int timer, 
+void TimerPulseWidthSet(unsigned int baseAddr, unsigned int timer,
                         unsigned int pulseWidth)
 {
     /* Clear the bits for Pulse width selection */
@@ -823,7 +823,7 @@ void TimerPulseModeSet(unsigned int baseAddr, unsigned int timer)
  * \return  Status of the timer. Returns the following values or the
  *          combination of both. \n
  *          TMR_OUT12_ASSERTED - TMR64P_OUT12 is asserted \n
- *          TMR_OUT34_ASSERTED - TMR64P_OUT34 is asserted 
+ *          TMR_OUT34_ASSERTED - TMR64P_OUT34 is asserted
  *
  **/
 unsigned int TimerOUTStatusGet(unsigned int baseAddr, unsigned int timer)
@@ -859,7 +859,7 @@ void TimerInvertINEnable(unsigned int baseAddr, unsigned int timer)
  *
  * \param   baseAddr      Base Address of the Timer Module Registers.
  * \param   timer         The timer, of which inversion to be disabled.
- * 
+ *
  *  timer can take the values \n
  *     TMR_TIMER34 - TMR64P_INT34 inversion will be disabled \n
  *     TMR_TIMER12 - TMR64P_IN12 inversion will be disabled \n
diff --git a/lib/tiam1808/drivers/uart.c b/lib/tiam1808/drivers/uart.c
index 25017b62b..4dbaa4b64 100644
--- a/lib/tiam1808/drivers/uart.c
+++ b/lib/tiam1808/drivers/uart.c
@@ -1,8 +1,8 @@
 /**
  * \file      uart.c
  *
- * \brief     This file contains device abstraction layer APIs for the 
- *            UART device. There are APIs here to enable the UART instance, 
+ * \brief     This file contains device abstraction layer APIs for the
+ *            UART device. There are APIs here to enable the UART instance,
  *            set the required configurations for communication, transmit
  *            or receive data and also to disable the UART instance.
  */
@@ -62,25 +62,25 @@
  * \param     baseAdd         Memory address of the UART instance used.\n
  * \param     uartClk         Frequency of the clock supplied to the UART module.\n
  * \param     baudrate        Required baud rate of communication.\n
- * \param     config          Logical OR of the appropriate macros related to 
- *                            parity, number of stop bits and number of data 
+ * \param     config          Logical OR of the appropriate macros related to
+ *                            parity, number of stop bits and number of data
  *                            bits per frame.\n
  * \param     overSampRate    Over-sampling rate(either 13x or 16x).\n
  *
  * \return                    None.\n
- *            
- * \note     The baud rate is configured by setting the divisor values derived 
- *           from the module input clock \uartClk and the over sampling rate 
- *           \overSampleRate. The module input clock depends on the PLL 
- *           configurations and the system clock tree. 
+ *
+ * \note     The baud rate is configured by setting the divisor values derived
+ *           from the module input clock \uartClk and the over sampling rate
+ *           \overSampleRate. The module input clock depends on the PLL
+ *           configurations and the system clock tree.
  */
 
-void UARTConfigSetExpClk (unsigned int baseAdd, unsigned int uartClk, 
-                          unsigned int baudrate, unsigned int config, 
-                          unsigned int overSampRate) 
-{                                         
+void UARTConfigSetExpClk (unsigned int baseAdd, unsigned int uartClk,
+                          unsigned int baudrate, unsigned int config,
+                          unsigned int overSampRate)
+{
     unsigned int divisor = 0;
-    
+
     /* Calculating the divisor value */
     switch (overSampRate)
     {
@@ -88,14 +88,14 @@ void UARTConfigSetExpClk (unsigned int baseAdd, unsigned int uartClk,
             divisor = uartClk/(baudrate * 13);
             HWREG(baseAdd + UART_MDR) = UART_OVER_SAMP_RATE;
         break;
-        
+
         case UART_OVER_SAMP_RATE_16:
-        default: 
+        default:
             divisor = uartClk/(baudrate * 16);
             HWREG(baseAdd + UART_MDR) &= ~UART_OVER_SAMP_RATE;
         break;
     }
-    
+
     /*
     ** Writing the divisor value onto the Divisor Latch registers.
     ** Programming the divisor latch registers with an appropriate value sets
@@ -107,7 +107,7 @@ void UARTConfigSetExpClk (unsigned int baseAdd, unsigned int uartClk,
     /*
     ** Write only relevant values to the LCR. LCR controls the number of data
     ** bits and stop bits per frame, parity enable feature, type of parity
-    ** (even of odd), stick parity enable feature, Break control and DLAB 
+    ** (even of odd), stick parity enable feature, Break control and DLAB
     ** selection bits.
     */
 
@@ -127,7 +127,7 @@ void UARTConfigSetExpClk (unsigned int baseAdd, unsigned int uartClk,
  * \param    baseAdd      Memory address of the UART instance used.\n
  * \param    uartClk      Frequency of clock supplied to the UART module.\n
  * \param    pBaud        Pointer to the storage of the UART baud rate.\n
- * \param    pConfig      Pointer to the storage of the configuration 
+ * \param    pConfig      Pointer to the storage of the configuration
  *                        parameters.\n
  *
  * \return   None.\n
@@ -147,7 +147,7 @@ void UARTConfigGetExpClk (unsigned int baseAdd, unsigned int uartClk,
    {
       overSampRate = 13;
    }
-   else 
+   else
    {
       overSampRate = 16;
    }
@@ -176,9 +176,9 @@ void UARTConfigGetExpClk (unsigned int baseAdd, unsigned int uartClk,
  *                        3> UART_RX_TRIG_LEVEL_8
  *                        4> UART_RX_TRIG_LEVEL_14
  *  \return   None.\n
- * 
- *  \note   This API needs needs to be called to configure the FIFO without 
- *          enabling the DMA mode. If DMA mode is being used, the 
+ *
+ *  \note   This API needs needs to be called to configure the FIFO without
+ *          enabling the DMA mode. If DMA mode is being used, the
  *          UARTDMAEnable() should be used to configure the FIFO.
  *
  * \note    FIFO Control Register(FCR) and the Interrupt Identification Register
@@ -189,7 +189,7 @@ void UARTConfigGetExpClk (unsigned int baseAdd, unsigned int uartClk,
  *          Since these share the same address, the integrity of bits in FCR \n
  *          register are at risk if we read from IIR register, modify this value
  *          and write the new value into the FCR register. Thus, we retain the \n
- *          status of the FIFOEN bit and the RXFIFTL bit in the FCR register by 
+ *          status of the FIFOEN bit and the RXFIFTL bit in the FCR register by
  *          reinstating them to their previous values.\n
 
 
@@ -210,16 +210,16 @@ void UARTFIFOLevelSet (unsigned int baseAdd, unsigned int rxLevel)
  *                      macros:
  *                      UART_FIFO_MODE - which enables the FIFO mode of operation,
  *                      UART_DMAMODE - which enables the DMA mode of operation.
- * 
+ *
  *                      This can also contain the Rx FIFO threshold value.\n
  *                      This can take any one of the four following values:
  *                      1> UART_RX_TRIG_LEVEL_1 - one byte trigger level.\n
  *                      2> UART_RX_TRIG_LEVEL_4 - 4 bytes trigger level. \n
  *                      3> UART_RX_TRIG_LEVEL_8 - 8 bytes trigger level. \n
  *                      4> UART_RX_TRIG_LEVEL_14 - 14 bytes trigger level.\n
- *                      
+ *
  * \return   None.\n
- *                 
+ *
  * \note    FIFO Control Register(FCR) and the Interrupt Identification Regsiter
  *          (IIR) share a common offset address. FCR register has write-only \n
  *          permissions and IIR register has read-only permissions. Therefore,
@@ -228,7 +228,7 @@ void UARTFIFOLevelSet (unsigned int baseAdd, unsigned int rxLevel)
  *          Since these share the same address, the integrity of bits in FCR \n
  *          register are at risk if we read from IIR register, modify this value
  *          and write the new value into the FCR register. Thus, we retain the \n
- *          status of the FIFOEN bit and the RXFIFTL bit in the FCR register by 
+ *          status of the FIFOEN bit and the RXFIFTL bit in the FCR register by
  *          reinstating them to their previous values. Also, since the DMA mode \n
  *          requires that the FIFO be enabled, FIFO is enabled here. \n
  */
@@ -254,7 +254,7 @@ void UARTDMAEnable (unsigned int baseAdd, unsigned int flags)
  *                        2> UART_RX_TRIG_LEVEL_4 - 4 bytes trigger level. \n
  *                        3> UART_RX_TRIG_LEVEL_8 - 8 bytes trigger level. \n
  *                        4> UART_RX_TRIG_LEVEL_14 - 14 bytes trigger level.\n
- * 
+ *
  *
  * \return    None.\n
  *
@@ -265,7 +265,7 @@ void UARTDMAEnable (unsigned int baseAdd, unsigned int flags)
 
 void UARTDMADisable (unsigned int baseAdd, unsigned int flags)
 {
-    /* Enabling the FIFO mode of operation.*/   
+    /* Enabling the FIFO mode of operation.*/
     HWREG(baseAdd + UART_FCR) = (flags & (UART_FIFO_MODE | UART_RX_TRIG_LEVEL));
 }
 
@@ -282,10 +282,10 @@ void UARTDMADisable (unsigned int baseAdd, unsigned int flags)
 
 void UARTParityModeSet(unsigned int baseAdd, unsigned int parityMode)
 {
-    /* Clearing the Parity related bits.*/ 
-    HWREG(baseAdd + UART_LCR) &= ~(UART_PARITY  | UART_SET_PARITY_TYPE | 
+    /* Clearing the Parity related bits.*/
+    HWREG(baseAdd + UART_LCR) &= ~(UART_PARITY  | UART_SET_PARITY_TYPE |
                                    UART_STICK_PARITY);
-    /* Setting the Parity related bits depending upon 'parityMode'.*/ 
+    /* Setting the Parity related bits depending upon 'parityMode'.*/
     HWREG(baseAdd + UART_LCR) |= (parityMode & (UART_PARITY |
                                                 UART_SET_PARITY_TYPE |
                                                 UART_STICK_PARITY));
@@ -296,7 +296,7 @@ void UARTParityModeSet(unsigned int baseAdd, unsigned int parityMode)
  * \brief    This function gets the parity mode currently being used.\n
  *
  * \param    baseAdd   Memory address of the UART instance used.\n
- * 
+ *
  * \return   A value which when appropriately decoded in the application
  *           program would tell whether: \n
  *           a> No, odd or even parity is selected.\n
@@ -308,7 +308,7 @@ unsigned int UARTParityModeGet(unsigned int baseAdd)
     unsigned int mask;
 
     mask = (UART_PARITY | UART_SET_PARITY_TYPE | UART_STICK_PARITY);
-    
+
     return (HWREG(baseAdd + UART_LCR)& mask);
 }
 
@@ -337,8 +337,8 @@ void UARTEnable (unsigned int baseAdd)
  * \brief     This function does the following operations.\n
  *            1> Disables and resets the transmitter.\n
  *            2> Disables the resets the receiver.\n
- *            3> Disables the FREE running mode of operation of the UART. \n   
- *           
+ *            3> Disables the FREE running mode of operation of the UART. \n
+ *
  * \param    baseAdd     Memory address of the UART instance used.
  *
  * \return   None.
@@ -365,9 +365,9 @@ void UARTDisable (unsigned int baseAdd)
  *
  * \return  None.
  *
- * \note    This enable the FIFO and the trigger levels are set to the default 
+ * \note    This enable the FIFO and the trigger levels are set to the default
  *          values. The TX and the RX FIFO are also cleared. If the FIFO needs
- *          to be enabled, with different settings then one should call 
+ *          to be enabled, with different settings then one should call
  *          \UARTFIFOLevelSet after this API call.
  *
  */
@@ -388,7 +388,7 @@ void UARTFIFOEnable(unsigned int baseAdd)
  *
  * \note     This clears all the settings of the FIFO control Register(FCR)
  *           and disables the FIFO.
- *          
+ *
  */
 
 void UARTFIFODisable(unsigned int baseAdd)
@@ -399,10 +399,10 @@ void UARTFIFODisable(unsigned int baseAdd)
 
 /**
  * \brief   This function checks if the transmitter is empty by checking for
- *          the emptiness of Transmitter Holding Register(THR) and the 
+ *          the emptiness of Transmitter Holding Register(THR) and the
  *          Transmit Shift regsiter(TSR).
- *          
- *                               
+ *
+ *
  * \param   baseAdd   Memory address of the UART instance used.
  *
  * \return            Returns TRUE if Transmitter FIFO(or THR register
@@ -412,18 +412,18 @@ void UARTFIFODisable(unsigned int baseAdd)
 unsigned int UARTSpaceAvail(unsigned int baseAdd)
 {
     unsigned int retVal = FALSE;
-     
+
     /*
-    ** Checking if THRE or TEMT bits in Line Status Register (LSR) are set. 
-    ** THRE bit is set when the Transmitter FIFO is empty( THR register in 
+    ** Checking if THRE or TEMT bits in Line Status Register (LSR) are set.
+    ** THRE bit is set when the Transmitter FIFO is empty( THR register in
     ** non-FIFO mode). TEMT bit is set when both Transmitter FIFO and the
-    ** Transmitter Shift Register(TSR)are empty(THR and TSR registers in 
+    ** Transmitter Shift Register(TSR)are empty(THR and TSR registers in
     ** non-FIFO mode).
     */
-      
+
     if (HWREG(baseAdd + UART_LSR) & (UART_THR_TSR_EMPTY | UART_THR_EMPTY))
-    {                                         
-        retVal = TRUE;                                              
+    {
+        retVal = TRUE;
     }
 
     return retVal;
@@ -432,27 +432,27 @@ unsigned int UARTSpaceAvail(unsigned int baseAdd)
 
 /**
  * \brief   This function checks if: \n
- *          a> the Receiver Buffer Register(RBR) has data and it is ready to 
+ *          a> the Receiver Buffer Register(RBR) has data and it is ready to
  *             be read (for non-FIFO mode) or\n
  *          b> the Receiver FIFO has atleast one byte of data to be read
  *             (FIFO mode). \n
  *
  * \param     baseAdd   Memory address of the UART instance used.
  *
- * \return    Returns TRUE if there is atleast one byte to be read. 
+ * \return    Returns TRUE if there is atleast one byte to be read.
  *            Else it returns FALSE.
  *
  */
 
 unsigned int UARTCharsAvail(unsigned int baseAdd)
 {
-    unsigned int retVal = FALSE;    
+    unsigned int retVal = FALSE;
 
     if (HWREG(baseAdd + UART_LSR) & UART_DATA_READY)
-    {                                         
-        retVal = TRUE;                                              
+    {
+        retVal = TRUE;
     }
-    
+
     return retVal;
 }
 
@@ -467,7 +467,7 @@ unsigned int UARTCharsAvail(unsigned int baseAdd)
  *                      UART_OVERRUN_ERROR - indicating an Overrun Error.
  *                      UART_PARITY_ERROR - indicating a Parity Error.
  *                      UART_FRAME_ERROR - indicating a Frame Error.
- *                      UART_BREAK_IND - indicating a Break Indicator 
+ *                      UART_BREAK_IND - indicating a Break Indicator
  *                                       has been generated.
  */
 
@@ -479,7 +479,7 @@ unsigned int UARTRxErrorGet(unsigned int baseAdd)
 
 
 /**
- * \brief    This function attempts to write a byte into Transmitter Holding 
+ * \brief    This function attempts to write a byte into Transmitter Holding
  *           Register (THR). This API checks only once if the transmitter
  *           is empty. If yes, it puts the byte, else it returns FALSE.
  *
@@ -490,28 +490,28 @@ unsigned int UARTRxErrorGet(unsigned int baseAdd)
  *           is empty and the character was written. Else it returns FALSE.
  */
 
-unsigned int UARTCharPutNonBlocking(unsigned int baseAdd, 
+unsigned int UARTCharPutNonBlocking(unsigned int baseAdd,
                                     unsigned char byteWrite)
 {
     unsigned int retVal = FALSE;
-    
+
     if (HWREG(baseAdd + UART_LSR) & (UART_THR_TSR_EMPTY | UART_THR_EMPTY))
     {
        HWREG(baseAdd + UART_THR) = byteWrite;
        retVal = TRUE;
     }
-    
+
     return retVal;
  }
 
- 
+
 /**
  * \brief    This function reads a byte from the Receiver Buffer Register
  *           (RBR). This API checks if any character is ready to be read.
  *            If ready then returns the read byte, else it returns -1.
  *
  * \param    baseAdd   Memory address of the UART instance being used.
- * 
+ *
  * \return   The character in the RBR register typecasted as integer.
  *           If no character is found in the RBR register, -1
  *           is returned.
@@ -525,14 +525,14 @@ int UARTCharGetNonBlocking(unsigned int baseAdd)
     {
        retVal = HWREG(baseAdd + UART_RBR);
     }
-    
+
     return retVal;
 }
 
 
 /**
- * \brief      This function waits indefinitely for the arrival of a byte in   
- *             the receiver FIFO. Once a byte has arrived, it returns that 
+ * \brief      This function waits indefinitely for the arrival of a byte in
+ *             the receiver FIFO. Once a byte has arrived, it returns that
  *             byte typecasted as integer.
  *
  * \param      baseAdd     Memory address of the UART instance being used.
@@ -544,13 +544,13 @@ int UARTCharGetNonBlocking(unsigned int baseAdd)
 int UARTCharGet(unsigned int baseAdd)
 {
     int data = 0;
-    
+
     /*
     ** Busy check if data is available in receiver FIFO(RBR regsiter in non-FIFO
     ** mode) so that data could be read from the RBR register.
     */
     while ((HWREG(baseAdd + UART_LSR) & UART_DATA_READY) == 0);
-    
+
     data = (int)HWREG(baseAdd + UART_RBR);
 
     return data;
@@ -580,9 +580,9 @@ void UARTCharPut(unsigned int baseAdd, unsigned char byteTx)
    ** Register(THR) and Transmitter Shift Register(TSR) before writing
    ** data into the Transmitter FIFO(THR for non-FIFO mode).
    */
-   
+
    while (txEmpty != (HWREG(baseAdd + UART_LSR) & txEmpty));
-   
+
    /*
    ** Transmitter FIFO(THR register in non-FIFO mode) is empty.
    ** Write the byte onto the THR register.
@@ -594,7 +594,7 @@ void UARTCharPut(unsigned int baseAdd, unsigned char byteTx)
 /**
  * \brief   This function enables the specified interrupts of the UART module.
  *          The interrupts that can be enabled are the receive interrupt,
- *          transmit interrupt, line status interrupt and the modem status 
+ *          transmit interrupt, line status interrupt and the modem status
  *          interrupt.
  *
  * \param   baseAdd    Memory address of the UART instance being used.
@@ -607,7 +607,7 @@ void UARTCharPut(unsigned int baseAdd, unsigned char byteTx)
 
 void UARTIntEnable(unsigned int baseAdd, unsigned int intFlags)
 {
-    HWREG(baseAdd + UART_IER) |= 
+    HWREG(baseAdd + UART_IER) |=
             (intFlags & (UART_INT_MODEM_STAT | UART_INT_LINE_STAT |
                          UART_INT_TX_EMPTY | UART_INT_RXDATA_CTI));
 }
@@ -617,16 +617,16 @@ void UARTIntEnable(unsigned int baseAdd, unsigned int intFlags)
  * \brief   This function disables the specified interrupts of the UART module.
  *
  * \param   baseAdd    Memory address of the UART instance being used.
- * \param   intFlags   This is bitwise OR of interrupts that need to be 
+ * \param   intFlags   This is bitwise OR of interrupts that need to be
  *                     disabled.
  *
  * \return  None.
- * 
+ *
  */
 
 void UARTIntDisable(unsigned int baseAdd, unsigned int intFlags)
 {
-    HWREG(baseAdd + UART_IER) &= ~(intFlags & (UART_INT_MODEM_STAT | 
+    HWREG(baseAdd + UART_IER) &= ~(intFlags & (UART_INT_MODEM_STAT |
                                                UART_INT_LINE_STAT |
                                                UART_INT_TX_EMPTY |
                                                UART_INT_RXDATA_CTI));
@@ -637,8 +637,8 @@ void UARTIntDisable(unsigned int baseAdd, unsigned int intFlags)
  * \brief   This function returns highest priority UART interrupt for service
  *
  * \param   baseAdd    Memory address of the UART instance being used.
- * 
- * \return  Contents of the Interrupt Type field of IIR register. 
+ *
+ * \return  Contents of the Interrupt Type field of IIR register.
  *          This function returns one of the following macros:
  *          1> UART_INTID_TX_EMPTY.
  *          2> UART_INTID_RX_DATA.
@@ -659,29 +659,29 @@ unsigned int UARTIntStatus(unsigned int baseAdd)
 }
 
 /**
- * \brief   This function is used to transmit Break condition to the receiving 
+ * \brief   This function is used to transmit Break condition to the receiving
  *          UART and also to release the Break condition depending on the value
  *          of the 'breakState' variable
  *
  * \param   baseAdd      Memory address of the UART instance being used.
  * \param   BreakState   TRUE for transmitting the Break condition to the
  *                       receiving UART.
- *                       FALSE for releasing the receiver from the Break 
+ *                       FALSE for releasing the receiver from the Break
  *                       condition.
  *
  * \return  None.
  *
- */ 
- 
+ */
+
 void UARTBreakCtl(unsigned int baseAdd, unsigned int breakState)
 {
    if(TRUE == breakState)
    {
         HWREG(baseAdd + UART_LCR) |= UART_BREAK_CTRL;
    }
-   else 
+   else
    {
-       HWREG(baseAdd + UART_LCR) &= ~UART_BREAK_CTRL; 
+       HWREG(baseAdd + UART_LCR) &= ~UART_BREAK_CTRL;
    }
 
    return;
@@ -692,7 +692,7 @@ void UARTBreakCtl(unsigned int baseAdd, unsigned int breakState)
  *         bit and Request To Send(RTS) bit in the Modem Control Register(MCR).
  *
  * \param  baseAdd      Memory address of the UART instance being used.
- * \param  ctrlFlags    This contains bitwise OR of the AFE enable  bit and 
+ * \param  ctrlFlags    This contains bitwise OR of the AFE enable  bit and
  *                      RTS bit in the MCR register.
  *
  * \return  None.
@@ -703,7 +703,7 @@ void UARTModemControlSet(unsigned int baseAdd, unsigned int ctrlFlags)
 {
    /* Reading the Modem Control Register(MCR).*/
    HWREG(baseAdd + UART_MCR) &= ~(UART_AUTOFLOW | UART_RTS);
-   
+
    HWREG(baseAdd + UART_MCR) |= (ctrlFlags & (UART_AUTOFLOW | UART_RTS));
 }
 
@@ -733,7 +733,7 @@ void UARTModemControlClear(unsigned int baseAdd, unsigned int ctrlFlags)
  *
  * \return  The status of RTS and AFE bits if MCR
  *
- */ 
+ */
 unsigned int UARTModemControlGet(unsigned int baseAdd)
 {
    return HWREG(baseAdd + UART_MCR) & (UART_AUTOFLOW | UART_RTS);
@@ -744,14 +744,14 @@ unsigned int UARTModemControlGet(unsigned int baseAdd)
  *
  * \param   baseAdd    Memory address of the UART instance being used.
  *
- * \return  This function returns the status of DCD, CTS, DSR and RI 
+ * \return  This function returns the status of DCD, CTS, DSR and RI
  *          bits of the Modem Status Register(MSR).
  */
 unsigned int UARTModemStatusGet(unsigned int baseAdd)
 {
    return HWREG(baseAdd + UART_MSR) & (UART_RI | UART_DSR |
                                        UART_CTS | UART_DCD);
-                                     
+
 }
 
 /*****************************END OF FILE************************************/
diff --git a/lib/tiam1808/drivers/usb.c b/lib/tiam1808/drivers/usb.c
index aec16ed89..bca3c3a24 100644
--- a/lib/tiam1808/drivers/usb.c
+++ b/lib/tiam1808/drivers/usb.c
@@ -795,13 +795,13 @@ USBIntRegister(unsigned int ulBase, void(*pfnHandler)(void))
 
     /* Register the interrupt handler. */
     IntRegister(INT_USB0, pfnHandler);
-    
+
     /* Enable the USB interrupt. */
     IntEnable(INT_USB0);
 #else
     /* Register the interrupt handler. */
     IntRegister(INT_USB0, pfnHandler);
-    
+
     /* Enable the USB interrupt. */
     IntSystemEnable(INT_USB0);
 #endif
@@ -1327,7 +1327,7 @@ USBDevDisconnect(unsigned int ulBase)
     ASSERT(ulBase == USB0_BASE);
 
     /* Disable connection to the USB bus. */
-    HWREGB(ulBase + USB_O_POWER) &= (~USB_POWER_SOFTCONN);	 
+    HWREGB(ulBase + USB_O_POWER) &= (~USB_POWER_SOFTCONN);
 }
 
 /**
@@ -1478,12 +1478,12 @@ USBHostEndpointConfig(unsigned int ulBase, unsigned int ulEndpoint,
 		}
 		else if(ulFlags & USB_EP_SPEED_FULL)
 		{
-			 HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TYPE0) = 
+			 HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TYPE0) =
 			 			USB_TYPE0_SPEED_FULL;
 		}
 		else
 		{
-			 HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TYPE0) = 
+			 HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TYPE0) =
 			 			USB_TYPE0_SPEED_LOW;
 		}
     }
@@ -2431,7 +2431,7 @@ USBEndpointDataSend(unsigned int ulBase, unsigned int ulEndpoint,
     {
         ulTxPktRdy = (ulTransType >> 8) & 0xff;
     }
-	
+
     /* Don't allow transmit of data if the TxPktRdy bit is already set. */
     if(HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) & USB_CSRL0_TXRDY)
     {
@@ -3154,9 +3154,9 @@ void USBEnableOtgIntr(unsigned int ulBase)
 	reg &= 0xFFFFFFF7;
 	HWREG(ulBase + USB_0_CTRL) = reg;
 
-	/* This API  enables the USB Interrupts through subsystem specific wrapper 
+	/* This API  enables the USB Interrupts through subsystem specific wrapper
 	registers*/
-	USBEnableInt(ulBase); 
+	USBEnableInt(ulBase);
 }
 
 /**
@@ -3175,7 +3175,7 @@ void USBReset(unsigned int ulBase)
 
 	/* Set the Reset Bit */
 	HWREG(ulBase + USB_0_CTRL) = reg;
-	 
+
 	/* Wait till Reset bit is cleared */
 	while(((HWREG(ulBase + USB_0_CTRL)) & 0x1 )== 1);
 
diff --git a/lib/tiam1808/drivers/usbphyGS60.c b/lib/tiam1808/drivers/usbphyGS60.c
index ac9ec017c..1ca22fa0d 100644
--- a/lib/tiam1808/drivers/usbphyGS60.c
+++ b/lib/tiam1808/drivers/usbphyGS60.c
@@ -53,8 +53,8 @@
 #endif
 
 /**
- * \brief This function will switch on the USB Phy  
- *          
+ * \brief This function will switch on the USB Phy
+ *
  *
  * \param    None
  *
@@ -66,9 +66,9 @@ void UsbPhyOn()
 
     unsigned int  reg = 0;
 
-	reg = HWREG(CFGCHIP2_USBPHYCTRL); 
+	reg = HWREG(CFGCHIP2_USBPHYCTRL);
 
-    reg &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);   
+    reg &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
 
     reg |= CFGCHIP2_PHY_PLLON;
 
@@ -78,14 +78,14 @@ void UsbPhyOn()
 
     HWREG(CFGCHIP2_USBPHYCTRL) = reg;
 
-    while (!(HWREG(CFGCHIP2_USBPHYCTRL) & CFGCHIP2_PHYCLKGD)); 
-	
+    while (!(HWREG(CFGCHIP2_USBPHYCTRL) & CFGCHIP2_PHYCLKGD));
+
 }
 
 
 /**
- * \brief This function will switch off  the USB Phy  
- *          
+ * \brief This function will switch off  the USB Phy
+ *
  *
  * \param    None
  *
@@ -95,12 +95,12 @@ void UsbPhyOn()
 void UsbPhyOff()
 {
 	unsigned int  reg = 0;
-	reg = HWREG(CFGCHIP2_USBPHYCTRL); 
-	
-	/** Ensure that USB 1.1 reference clock is not being sourced from	
+	reg = HWREG(CFGCHIP2_USBPHYCTRL);
+
+	/** Ensure that USB 1.1 reference clock is not being sourced from
 			* USB 2.0 PHY.	Otherwise do not power down the PHY.*/
-	
-	if (!( reg & CFGCHIP2_USB1PHYCLKMUX) && ( reg & CFGCHIP2_USB1SUSPENDM)) 
+
+	if (!( reg & CFGCHIP2_USB1PHYCLKMUX) && ( reg & CFGCHIP2_USB1SUSPENDM))
 	{
 	   return;
 	}
diff --git a/lib/tiam1808/drivers/watchdog.c b/lib/tiam1808/drivers/watchdog.c
index c0eceb915..aafaf4b0e 100644
--- a/lib/tiam1808/drivers/watchdog.c
+++ b/lib/tiam1808/drivers/watchdog.c
@@ -56,7 +56,7 @@
 *******************************************************************************/
 
 /**
- * \brief   Starts/Enables the watchdog timer. 
+ * \brief   Starts/Enables the watchdog timer.
  *
  * \param   baseAdd       Base Address of the Watchdog Timer Module Registers.
  *
@@ -69,14 +69,14 @@ void WatchdogTimerEnable(unsigned int baseAdd)
     HWREG(baseAdd + WDT_WSPR) = WDT_ENABLE_SEQ1;
 
     /* Wait until write is successful to WDT_WSPR register */
-    while(WatchdogTimerWritePostedStatusGet(baseAdd, 
+    while(WatchdogTimerWritePostedStatusGet(baseAdd,
                                             WDT_WRITE_PENDING_WSPR));
 
     /* Write the second value of the watchdog timer enabling sequence */
     HWREG(baseAdd + WDT_WSPR) = WDT_ENABLE_SEQ2;
 
     /* Wait until write is successful to WDT_WSPR register */
-    while(WatchdogTimerWritePostedStatusGet(baseAdd, 
+    while(WatchdogTimerWritePostedStatusGet(baseAdd,
                                             WDT_WRITE_PENDING_WSPR));
 }
 
@@ -183,15 +183,15 @@ void WatchdogTimerPreScalerClkEnable(unsigned int baseAdd, unsigned int ptv)
     HWREG(baseAdd + WDT_WCLR) &= ~WDT_WCLR_PTV;
 
     /* Wait until write is successful to WDT_WCLR register */
-    while(WatchdogTimerWritePostedStatusGet(baseAdd, 
+    while(WatchdogTimerWritePostedStatusGet(baseAdd,
                                               WDT_WRITE_PENDING_WCLR));
 
-    /* 
-    ** Set the ptv field of WDT_WCLR register with the ptv value and also 
-    ** enable the pre-scaler clock 
-    */                
-    HWREG(baseAdd + WDT_WCLR) |= ((ptv & WDT_WCLR_PTV) | 
-                                              WDT_WCLR_PRE);               
+    /*
+    ** Set the ptv field of WDT_WCLR register with the ptv value and also
+    ** enable the pre-scaler clock
+    */
+    HWREG(baseAdd + WDT_WCLR) |= ((ptv & WDT_WCLR_PTV) |
+                                              WDT_WCLR_PRE);
 
     /* Wait until write is successful to WDT_WCLR register */
     while(WatchdogTimerWritePostedStatusGet(baseAdd,
@@ -231,7 +231,7 @@ void WatchdogTimerCounterSet(unsigned int baseAdd, unsigned int countVal)
     HWREG(baseAdd + WDT_WCRR) = countVal;
 
     /* Wait until write is successful to WDT_WCRR register */
-    while(WatchdogTimerWritePostedStatusGet(baseAdd, 
+    while(WatchdogTimerWritePostedStatusGet(baseAdd,
                                             WDT_WRITE_PENDING_WCRR));
 }
 
@@ -240,7 +240,7 @@ void WatchdogTimerCounterSet(unsigned int baseAdd, unsigned int countVal)
  *
  * \param   baseAdd       Base Address of the Watchdog Timer Module Register.
  *
- * \return  This API returns the count value present in the Watchdog Timer 
+ * \return  This API returns the count value present in the Watchdog Timer
  *            Counter register.
  *
  **/
@@ -258,7 +258,7 @@ unsigned int WatchdogTimerCounterGet(unsigned int baseAdd)
  *
  * \return  None.
  *
- * \note:   It is recommended to not use reload value as 0xFFFFFFFF. 
+ * \note:   It is recommended to not use reload value as 0xFFFFFFFF.
  *
  **/
 void WatchdogTimerReloadSet(unsigned int baseAdd, unsigned int reloadVal)
@@ -292,11 +292,11 @@ unsigned int WatchdogTimerReloadGet(unsigned int baseAdd)
  *
  * \return  None.
  *
- * \note    This API should be called if the Watchdog timer WDT_WCRR 
- *          register has to be loaded with the WDT_WLDR register before 
+ * \note    This API should be called if the Watchdog timer WDT_WCRR
+ *          register has to be loaded with the WDT_WLDR register before
  *          overflow occurs. If this API has to be called more than once in an
- *          application then ensure each time this API is called, pass a 
- *          different value to the parameter 'trigVal' to ensure proper working. 
+ *          application then ensure each time this API is called, pass a
+ *          different value to the parameter 'trigVal' to ensure proper working.
  *
  **/
 void WatchdogTimerTriggerSet(unsigned int baseAdd, unsigned int trigVal)
@@ -305,7 +305,7 @@ void WatchdogTimerTriggerSet(unsigned int baseAdd, unsigned int trigVal)
     HWREG(baseAdd + WDT_WTGR) = trigVal;
 
     /* Wait till write is successful to WDT_WTGR register */
-    while(WatchdogTimerWritePostedStatusGet(baseAdd, 
+    while(WatchdogTimerWritePostedStatusGet(baseAdd,
                                                   WDT_WRITE_PENDING_WTGR));
 }
 
@@ -313,7 +313,7 @@ void WatchdogTimerTriggerSet(unsigned int baseAdd, unsigned int trigVal)
  * \brief   Load the delay register of Watchdog timer with the delay value.
  *
  * \param   baseAdd       Base Address of the Watchdog Timer Module Register.
- * \param   delayVal      Delay value. 
+ * \param   delayVal      Delay value.
  *
  * \return  None.
  *
@@ -324,7 +324,7 @@ void WatchdogTimerDelaySet(unsigned int baseAdd, unsigned int delayVal)
     HWREG(baseAdd + WDT_WDLY) = delayVal;
 
     /* Wait until write is successful to the WDT_WDLY register */
-    while(WatchdogTimerWritePostedStatusGet(baseAdd, 
+    while(WatchdogTimerWritePostedStatusGet(baseAdd,
           WDT_WRITE_PENDING_WDLY));
 }
 
@@ -333,7 +333,7 @@ void WatchdogTimerDelaySet(unsigned int baseAdd, unsigned int delayVal)
  *
  * \param   baseAdd       Base Address of the Watchdog Timer Module Register.
  *
- * \return  This API returns the delay register(WDT_WDLY) value of Watchdog 
+ * \return  This API returns the delay register(WDT_WDLY) value of Watchdog
  *          timer.
  *
  **/
@@ -359,8 +359,8 @@ unsigned int WatchdogTimerDelayGet(unsigned int baseAdd)
 void WatchdogTimerIntRawStatusSet(unsigned int baseAdd, unsigned int intFlags)
 {
     /* Set the status in the WDT_WIRQSTATRAW register */
-    HWREG(baseAdd + WDT_WIRQSTATRAW) = (intFlags & 
-                                            (WDT_INT_OVERFLOW | 
+    HWREG(baseAdd + WDT_WIRQSTATRAW) = (intFlags &
+                                            (WDT_INT_OVERFLOW |
                                              WDT_INT_DELAY));
 }
 
@@ -408,8 +408,8 @@ unsigned int WatchdogTimerIntStatusGet(unsigned int baseAdd)
 void WatchdogTimerIntStatusClear(unsigned int baseAdd, unsigned int intFlags)
 {
     /* Clear the status in the WDT_WIRQSTAT register */
-    HWREG(baseAdd + WDT_WIRQSTAT) = (intFlags & 
-                                         (WDT_INT_OVERFLOW | 
+    HWREG(baseAdd + WDT_WIRQSTAT) = (intFlags &
+                                         (WDT_INT_OVERFLOW |
                                           WDT_INT_DELAY));
 }
 
@@ -429,13 +429,13 @@ void WatchdogTimerIntStatusClear(unsigned int baseAdd, unsigned int intFlags)
 void WatchdogTimerIntEnable(unsigned int baseAdd, unsigned int intFlags)
 {
     /* Enable the watchdog timer interrupts */
-    HWREG(baseAdd + WDT_WIRQENSET) = (intFlags & 
-                                          (WDT_INT_ENABLE_OVRFLW | 
-                                           WDT_INT_ENABLE_DELAY)); 
+    HWREG(baseAdd + WDT_WIRQENSET) = (intFlags &
+                                          (WDT_INT_ENABLE_OVRFLW |
+                                           WDT_INT_ENABLE_DELAY));
 }
 
 /**
- * \brief   Used to check whether interrupts of Watchdog timer are enabled 
+ * \brief   Used to check whether interrupts of Watchdog timer are enabled
  *          or disabled.
  *
  * \param   baseAdd       Base Address of the Watchdog Timer Module Register.
@@ -465,8 +465,8 @@ unsigned int WatchdogTimerIntEnableStatusGet(unsigned int baseAdd)
 void WatchdogTimerIntDisable(unsigned int baseAdd, unsigned int intFlags)
 {
     /* Disable the Watchdog timer interrupts */
-    HWREG(baseAdd + WDT_WIRQENCLR) = (intFlags & 
-                                          (WDT_INT_DISABLE_DELAY | 
+    HWREG(baseAdd + WDT_WIRQENCLR) = (intFlags &
+                                          (WDT_INT_DISABLE_DELAY |
                                            WDT_INT_DISABLE_OVRFLW));
 }
 
diff --git a/lib/tiam1808/system_config/armv5/am1808/gcc/exceptionhandler.S b/lib/tiam1808/system_config/armv5/am1808/gcc/exceptionhandler.S
index 8ceedab07..33fed07a6 100644
--- a/lib/tiam1808/system_config/armv5/am1808/gcc/exceptionhandler.S
+++ b/lib/tiam1808/system_config/armv5/am1808/gcc/exceptionhandler.S
@@ -2,7 +2,7 @@
 @
 @ exceptionhandler.S - Definitions of exception handlers
 @
-@ Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/  
+@ Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 @ All rights reserved.
 @
 @******************************************************************************
@@ -19,11 +19,11 @@
         .global SWIHandler
         .global UndefInstHandler
         .global CPUAbortHandler
-        
+
         .equ ADDR_HIPVR1, SOC_AINTC_0_REGS + AINTC_HIPVR(0)
         .equ ADDR_HIPVR2, SOC_AINTC_0_REGS + AINTC_HIPVR(1)
         .equ MASK_SWI_NUM, 0xFF000000
-  
+
 @**************************** Text Section ************************************
         .text
 
@@ -31,10 +31,10 @@
         .code 32
 @******************************************************************************
 @*                  Function Definition of SWI Handler
-@******************************************************************************    
+@******************************************************************************
 @
 @ The SWI Handler switches to system mode if the SWI number is 458752. If the
-@ SWI number is different, no mode switching will be done. No other SWI are 
+@ SWI number is different, no mode switching will be done. No other SWI are
 @ handled here
 @
 SWIHandler:
@@ -42,14 +42,14 @@ SWIHandler:
         LDR      r0, [r14, #-4]           @ R0 points to SWI instruction
         BIC      r0, r0, #MASK_SWI_NUM    @ Get the SWI number
         CMP      r0, #458752
-        MRSEQ    r1, spsr                 @ Copy SPSR  
+        MRSEQ    r1, spsr                 @ Copy SPSR
         ORREQ    r1, r1, #0x1F            @ Change the mode to System
         MSREQ    spsr_cf, r1              @ Restore SPSR
         LDMFD    r13!, {r0-r1, pc}^       @ Restore registers from IRQ stack
 
 @******************************************************************************
 @*                  Function Definition of IRQ Handler
-@******************************************************************************    
+@******************************************************************************
 @
 @ The IRQ handler jumps to the ISR of highest priority pending IRQ. The address
 @ is taken from the HIPVR2 register, which contains the ISR address of highest
@@ -59,14 +59,14 @@ IRQHandler:
         STMFD    r13!, {r0-r3, r12, r14}  @ Save context in IRQ stack
         LDR      r0, =ADDR_HIPVR2         @ R0 points to address of HIPVR2
         LDR      r1, [r0]                 @ R1 contains address of ISR
-        ADD      r14, pc, #0              @ Save return address in LR 
+        ADD      r14, pc, #0              @ Save return address in LR
         LDR      pc, [r1]                 @ Go to ISR (still in IRQ mode)
         LDMFD    r13!, {r0-r3, r12, r14}  @ Restore registers from IRQ stack
         SUBS     pc, r14, #0x4            @ Return to program before IRQ
-        
+
 @******************************************************************************
 @*                  Function Definition of FIQ Handler
-@******************************************************************************    
+@******************************************************************************
 @
 @ The FIQ Handler jumps to the ISR of the highest priority pending FIQ. The
 @ address is taken from HIPVR1, which contains the ISR address of the highest
@@ -74,19 +74,19 @@ IRQHandler:
 @
 FIQHandler:
 @
-@ Save the required context in FIQ stack. 
+@ Save the required context in FIQ stack.
 @
         STMFD    r13!, {r0-r3, r12, r14}  @ Save context in FIQ stack
         LDR      r0, =ADDR_HIPVR1         @ R0 points to address of HIPVR1
         LDR      r1, [r0]                 @ R1 contains address of ISR
-        ADD      r14, pc, #0              @ Save return address in LR 
+        ADD      r14, pc, #0              @ Save return address in LR
         LDR      pc, [r1]                 @ Go to ISR (still in FIQ mode)
         LDMFD    r13!, {r0-r3, r12, r14}  @ Restore registers from FIQ stack
-        SUBS     pc, r14, #0x4            @ Return to program state before FIQ 
-        
+        SUBS     pc, r14, #0x4            @ Return to program state before FIQ
+
 @******************************************************************************
 @*             Function Definition of Abort/Undef Handler
-@******************************************************************************    
+@******************************************************************************
 @
 @ The Abort handler goes to the C handler of abort mode. Note that the undefined
 @ instruction is not handled separately.
@@ -98,7 +98,7 @@ UndefInstHandler:
 @ Disable all the interrupts
 @
         MRS     r0, cpsr                  @ Read from CPSR
-        ORR     r0, r0, #0xC0             @ Clear the IRQ and FIQ bits    
+        ORR     r0, r0, #0xC0             @ Clear the IRQ and FIQ bits
         MSR     cpsr, r0                  @ Write to CPSR
         ADD     r14, pc, #0               @ Store the return address
         LDR     pc, =CPUAbortHandler      @ Go to C handler
@@ -106,13 +106,13 @@ UndefInstHandler:
 @ Go to infinite loop if returned from C handler
 @
 loop0:
-        B       loop0                      
+        B       loop0
 
 @*****************************************************************************
 @
 @ End of the file
 @
     .end
-    
-    
-    
+
+
+
diff --git a/lib/tiam1808/system_config/armv5/am1808/interrupt.c b/lib/tiam1808/system_config/armv5/am1808/interrupt.c
index 6010ac45e..ecfd2f5b8 100644
--- a/lib/tiam1808/system_config/armv5/am1808/interrupt.c
+++ b/lib/tiam1808/system_config/armv5/am1808/interrupt.c
@@ -66,7 +66,7 @@ static void IntDefaultHandler(void);
 
 /**
  *
- * The Default Interrupt Handler. 
+ * The Default Interrupt Handler.
  *
  * This is the default interrupt handler for all interrupts.  It simply loops
  * forever so that the system state is preserved for observation by a
@@ -86,14 +86,14 @@ static void IntDefaultHandler(void)
 
 /**
  * \brief    Registers an interrupt Handler in the interrupt vector table for
- *           system interrupts. 
- * 
+ *           system interrupts.
+ *
  * \param    intrNum - Interrupt Number
  * \param    fnHandler - Function pointer to the ISR
- * 
+ *
  * Note: When the interrupt occurs for the sytem interrupt number indicated,
  * the control goes to the ISR given as the parameter.
- * 
+ *
  * \return      None.
  **/
 void IntRegister(unsigned int intrNum, void (*fnHandler)(void))
@@ -104,12 +104,12 @@ void IntRegister(unsigned int intrNum, void (*fnHandler)(void))
 
 /**
  * \brief   Unregisters an interrupt
- * 
+ *
  * \param   intrNum - Interrupt Number
- * 
+ *
  * Note: Once an interrupt is unregistered it will enter infinite loop once
  * an interrupt occurs
- * 
+ *
  * \return      None.
  **/
 void IntUnRegister(unsigned int intrNum)
@@ -119,11 +119,11 @@ void IntUnRegister(unsigned int intrNum)
 }
 
 /**
- * \brief  Set the channel number for a system interrupt. Channel numbers 0-1 
+ * \brief  Set the channel number for a system interrupt. Channel numbers 0-1
  *         are mapped to FIQ and Channel numbers 2-31 are mapped to IRQ of ARM.
- *         One or more system interrupt can be mapped to one channel. However, 
+ *         One or more system interrupt can be mapped to one channel. However,
  *         one system interrupt can not be mapped to multiple channels.
- * 
+ *
  * \param   intrNum - Interrupt Number
  * \param   channel - Channel Number to be set
  *
@@ -131,10 +131,10 @@ void IntUnRegister(unsigned int intrNum)
  **/
 void IntChannelSet(unsigned int intrNum, unsigned char channel)
 {
-    volatile unsigned char *CMRByte = (unsigned char*)(SOC_AINTC_0_REGS + 
+    volatile unsigned char *CMRByte = (unsigned char*)(SOC_AINTC_0_REGS +
                                                        AINTC_CMR(0));
 
-    /* 
+    /*
     ** This function assumes that the CMRs are continuous in memory and are
     ** byte accessible. Also assumes that the architecture is little-endian
     */
@@ -148,17 +148,17 @@ void IntChannelSet(unsigned int intrNum, unsigned char channel)
 
 /**
  * \brief    Get the channel number for a system interrupt
- * 
+ *
  * \param    intrNum - Interrupt Number
- * 
+ *
  * \return   Channel Number.
  **/
 unsigned char IntChannelGet(unsigned int intrNum)
 {
-    volatile unsigned char *CMRByte = (unsigned char*)(SOC_AINTC_0_REGS + 
+    volatile unsigned char *CMRByte = (unsigned char*)(SOC_AINTC_0_REGS +
                                                        AINTC_CMR(0));
 
-    /* 
+    /*
     ** This function assumes that the CMRs are continuous in memory and are
     ** byte accessible. Also assumes that the architecture is little-endian
     */
@@ -172,9 +172,9 @@ unsigned char IntChannelGet(unsigned int intrNum)
 /**
  * \brief    Enables interrupts in GER register of AINTC. FIQ and IRQ will be
  *           signaled for processing.
- * 
+ *
  * \param    None
- * 
+ *
  * \return   None
  **/
 void IntGlobalEnable(void)
@@ -186,9 +186,9 @@ void IntGlobalEnable(void)
 /**
  * \brief    Disables interrupts in GER register of AINTC. No interrupts will
  *           be signaled by the AINTC to the ARM core.
- * 
+ *
  * \param    None
- * 
+ *
  * \return   None
  **/
 void IntGlobalDisable(void)
@@ -198,24 +198,24 @@ void IntGlobalDisable(void)
 }
 
 /**
- * \brief    Enables the sytem interrupt in AINTC. The interrupt will be 
+ * \brief    Enables the sytem interrupt in AINTC. The interrupt will be
  *           processed only if it is enabled in AINTC
- * 
+ *
  * \param    intrNum - Interrupt number
  *
  * \return   None.
  **/
 void IntSystemEnable(unsigned int intrNum)
 {
-    volatile unsigned char *ESRByte = (unsigned char*)(SOC_AINTC_0_REGS + 
+    volatile unsigned char *ESRByte = (unsigned char*)(SOC_AINTC_0_REGS +
                                                        AINTC_ESR(0));
     unsigned int bitNum;
-    
-    /* 
+
+    /*
     **  This function assumes that the ESRn are continuous in memory and are
     **  byte accessible. Also assumes that the architecture is little-endian
     */
-    
+
     /* Get the byte address corresponding to the system interrupt */
     ESRByte += (intrNum >> SYSTEM_INTR_BYTE_SHIFT);
 
@@ -228,22 +228,22 @@ void IntSystemEnable(unsigned int intrNum)
 
 /**
  * \brief   Disables the sytem interrupt in the AINTC
- * 
+ *
  * \param   intrNum - Interrupt number
- * 
+ *
  * \return  None
  **/
 void IntSystemDisable(unsigned int intrNum)
 {
-    volatile unsigned char *ECRByte = (unsigned char*)(SOC_AINTC_0_REGS + 
+    volatile unsigned char *ECRByte = (unsigned char*)(SOC_AINTC_0_REGS +
                                                        AINTC_ECR(0));
     unsigned int bitNum;
 
-    /* 
+    /*
     **  This function assumes that the ESRn are continuous in memory and are
     **  byte accessible. Also assumes that the architecture is little-endian
     */
-    
+
     /* Get the byte address corresponding to the system interrupt */
     ECRByte += (intrNum >> SYSTEM_INTR_BYTE_SHIFT);
 
@@ -256,7 +256,7 @@ void IntSystemDisable(unsigned int intrNum)
 
 /**
  * \brief    Clears a sytem interrupt status in AINTC
- * 
+ *
  * \param    intrNum - Interrupt number
  *
  * \return   None
@@ -264,10 +264,10 @@ void IntSystemDisable(unsigned int intrNum)
  **/
 void IntSystemStatusClear(unsigned int intrNum)
 {
-    volatile unsigned char *SECRByte = (unsigned char*)(SOC_AINTC_0_REGS + 
+    volatile unsigned char *SECRByte = (unsigned char*)(SOC_AINTC_0_REGS +
                                                         AINTC_SECR(0));
     unsigned int bitNum;
-    
+
     /* Get the byte address corresponding to the system interrupt */
     SECRByte += (intrNum >> SYSTEM_INTR_BYTE_SHIFT);
 
@@ -281,24 +281,24 @@ void IntSystemStatusClear(unsigned int intrNum)
 /**
  * \brief    Get the raw status of a system interrupt. This will return 1
  *           if the status is set and return 0 if the status is clear.
- * 
+ *
  * \param    intrNum - Interrupt number
- * 
- * \return   Raw Interrupt Status 
- * 
+ *
+ * \return   Raw Interrupt Status
+ *
  **/
 unsigned int IntSystemStatusRawGet(unsigned int intrNum)
 {
-    volatile unsigned char *SRSRByte = (unsigned char*)(SOC_AINTC_0_REGS + 
+    volatile unsigned char *SRSRByte = (unsigned char*)(SOC_AINTC_0_REGS +
                                                         AINTC_SRSR(0));
 
     unsigned int bitNum;
-    
+
     /*
     **  This function assumes that the SRSRn are continuous in memory
     **  are byte accessible; also that the architecture is little-endian
     */
- 
+
     /* Get the byte address corresponding to the system interrupt */
     SRSRByte += (intrNum >> SYSTEM_INTR_BYTE_SHIFT);
 
@@ -312,21 +312,21 @@ unsigned int IntSystemStatusRawGet(unsigned int intrNum)
 /**
  * \brief    Get the enabled status of a system interrupt. This will return
  *           1 if the status is set, and return 0 if the status is clear.
- * 
+ *
  * \param    intrNum - Interrupt Number
- *  
+ *
  * \return   Enabled Interrupt Status.
- * 
+ *
  **/
 unsigned int IntSystemStatusEnabledGet(unsigned int intrNum)
 {
-    volatile unsigned char *SECRByte = (unsigned char*)(SOC_AINTC_0_REGS + 
+    volatile unsigned char *SECRByte = (unsigned char*)(SOC_AINTC_0_REGS +
                                                         AINTC_SECR(0));
 
     unsigned int bitNum;
-   
+
     /*
-    **  This function assumes that the SECRn are continuous in memory 
+    **  This function assumes that the SECRn are continuous in memory
     **  are byte accessible; also that the architecture is little-endian
     */
 
@@ -342,9 +342,9 @@ unsigned int IntSystemStatusEnabledGet(unsigned int intrNum)
 
 /**
  * \brief    Enables IRQ in HIER register of AINTC
- * 
+ *
  * \param    None
- * 
+ *
  * \return   None.
  **/
 void IntIRQEnable(void)
@@ -355,9 +355,9 @@ void IntIRQEnable(void)
 
 /**
  * \brief    Disables IRQ in HIER register of AINTC
- * 
+ *
  * \param    None
- * 
+ *
  * \return   None.
  **/
 void IntIRQDisable(void)
@@ -368,9 +368,9 @@ void IntIRQDisable(void)
 
 /**
  * \brief    Enables FIQ in AINTC
- * 
+ *
  * \param    None
- * 
+ *
  * \return   None.
  **/
 void IntFIQEnable(void)
@@ -381,9 +381,9 @@ void IntFIQEnable(void)
 
 /**
  * \brief     Disables FIQ host interrupts in  AINTC
- * 
+ *
  * \param     None
- * 
+ *
  * \return    None
  **/
 void IntFIQDisable(void)
@@ -393,20 +393,20 @@ void IntFIQDisable(void)
 }
 
 /**
- * \brief   This API is used to setup the AINTC. This API shall be called 
+ * \brief   This API is used to setup the AINTC. This API shall be called
  *          before using the AINTC. All the host interruptsi will be disabled
  *          after calling this API. The user shall enable all the interrupts
- *          required for processing. 
+ *          required for processing.
  *
  * \param   None
- * 
+ *
  * \return  None.
  *
  **/
 void IntAINTCInit(void)
 {
     unsigned int cnt;
-  
+
     /* Reset AINTC */
     for(cnt = 0; cnt < 3; cnt++)
     {
@@ -428,8 +428,8 @@ void IntAINTCInit(void)
 }
 
 /**
- * \brief  Enables the processor IRQ only in CPSR. Makes the processor to 
- *         respond to IRQs.  This does not affect the set of interrupts 
+ * \brief  Enables the processor IRQ only in CPSR. Makes the processor to
+ *         respond to IRQs.  This does not affect the set of interrupts
  *         enabled/disabled in the AINTC.
  *
  * \param    None
@@ -446,8 +446,8 @@ void IntMasterIRQEnable(void)
 }
 
 /**
- * \brief  Disables the processor IRQ only in CPSR.Prevents the processor to 
- *         respond to IRQs.  This does not affect the set of interrupts 
+ * \brief  Disables the processor IRQ only in CPSR.Prevents the processor to
+ *         respond to IRQs.  This does not affect the set of interrupts
  *         enabled/disabled in the AINTC.
  *
  * \param    None
@@ -463,8 +463,8 @@ void IntMasterIRQDisable(void)
 }
 
 /**
- * \brief  Enables the processor FIQ only in CPSR. Makes the processor to 
- *         respond to FIQs.  This does not affect the set of interrupts 
+ * \brief  Enables the processor FIQ only in CPSR. Makes the processor to
+ *         respond to FIQs.  This does not affect the set of interrupts
  *         enabled/disabled in the AINTC.
  *
  * \param    None
@@ -480,8 +480,8 @@ void IntMasterFIQEnable(void)
 }
 
 /**
- * \brief  Disables the processor FIQ only in CPSR.Prevents the processor to 
- *         respond to FIQs.  This does not affect the set of interrupts 
+ * \brief  Disables the processor FIQ only in CPSR.Prevents the processor to
+ *         respond to FIQs.  This does not affect the set of interrupts
  *         enabled/disabled in the AINTC.
  *
  * \param    None
@@ -512,7 +512,7 @@ unsigned int IntMasterStatusGet(void)
 
 /**
  * \brief Read and save the stasus and Disables the processor IRQ .
- *         Prevents the processor to respond to IRQs.  
+ *         Prevents the processor to respond to IRQs.
  *
  * \param    None
  *
@@ -546,7 +546,7 @@ unsigned char IntDisable(void)
 }
 
 /**
- * \brief  Restore the processor IRQ only status. This does not affect 
+ * \brief  Restore the processor IRQ only status. This does not affect
  *          the set of interrupts enabled/disabled in the AINTC.
  *
  * \param    The status returned by the IntDisable fundtion.
@@ -561,10 +561,10 @@ void IntEnable(unsigned char  status)
 {
     // REVISIT: Why does original library version (above) not work?
 
-	// if((status & 0x80) == 0) 
+	// if((status & 0x80) == 0)
 	// {
 	// 	IntMasterIRQEnable();
-	// } 
+	// }
     __asm__ __volatile__ ("msr cpsr_c, %0" : : "r" (status));
 }
 
diff --git a/lib/tiam1808/system_config/armv5/am1808/startup.c b/lib/tiam1808/system_config/armv5/am1808/startup.c
index 4ca12ec37..af603a4ac 100644
--- a/lib/tiam1808/system_config/armv5/am1808/startup.c
+++ b/lib/tiam1808/system_config/armv5/am1808/startup.c
@@ -110,13 +110,13 @@ static unsigned int const vecTbl[14]=
  * \param   none
  *
  * \return  None.
- * 
+ *
  * This function is the first function that needs to be called in a system.
  * This should be set as the entry point in the linker script if loading the
  * elf binary via a debugger, on the target. This function never returns, but
  * gives control to the application entry point
  **/
-unsigned int start_boot(void) 
+unsigned int start_boot(void)
 {
 
     /* Enable write-protection for registers of SYSCFG module. */
diff --git a/lib/tiam1808/system_config/armv5/gcc/cp15.c b/lib/tiam1808/system_config/armv5/gcc/cp15.c
index 491ddd73a..b700a4229 100644
--- a/lib/tiam1808/system_config/armv5/gcc/cp15.c
+++ b/lib/tiam1808/system_config/armv5/gcc/cp15.c
@@ -91,7 +91,7 @@ void CP15ICacheEnable(void)
 * \param      None.
 *
 * \retiurn     None.
-* 
+*
 * Note: MMU shall be enabled before enabling D-Cache
 **/
 void CP15DCacheEnable(void)
@@ -111,7 +111,7 @@ void CP15DCacheEnable(void)
 **/
 void CP15DCacheFlush(void)
 {
-    __asm( "   mov     r0, #0\n\t"   
+    __asm( "   mov     r0, #0\n\t"
            "   mcr     p15, #0, r0, c7, c6, #0\n\t");
 }
 
@@ -154,7 +154,7 @@ void CP15DCacheCleanFlush(void)
 **/
 void CP15ICacheFlush(void)
 {
-    __asm("    mov     r0, #0\n\t" 
+    __asm("    mov     r0, #0\n\t"
           "    mcr     p15, #0, r0, c7, c5, #0\n\t");
 }
 
@@ -170,16 +170,16 @@ void CP15ICacheFlush(void)
 **/
 void CP15ICacheFlushBuff(unsigned int bufPtr, unsigned int size)
 {
-    unsigned int ptr;  
+    unsigned int ptr;
+
+    ptr = bufPtr & ~0x1f;
 
-    ptr = bufPtr & ~0x1f; 
-  
-    while(ptr < bufPtr + size) 
-    { 
+    while(ptr < bufPtr + size)
+    {
         __asm("    mcr p15, #0, %[value], c7, c6, #1":: [value] "r" (ptr));
 
         ptr += 32;
-    } 
+    }
 }
 
 /**
@@ -222,15 +222,15 @@ void CP15TtbSet(unsigned int ttb)
     * client by configuring domain access register,
     * in that case access controlled by permission value
     * set by page table entry
-    */  
+    */
     __asm("   mov r1, #0\n\t"
           "   mcr p15, #0, r1, c8, c7, #0\n\t"
           "   ldr r1, =0x55555555\n\t"
           "   mcr p15, #0, r1, c3, c0, #0\n\t");
-  
-   /* sets translation table base resgister with page table 
+
+   /* sets translation table base resgister with page table
     * starting address.
-    */ 
+    */
     __asm("   mcr p15, #0, %[value], c2, c0, 0":: [value] "r" (ttb));
 
 }
@@ -248,8 +248,8 @@ void CP15MMUDisable(void)
     __asm("    mov r0, #0\n\t"
           "    mcr p15, #0, r0, c8, c7, #0\n\t"
           "    mrc p15, #0, r0, c1, c0, #0\n\t"
-          "    mov r1, #0x1\n\t"       
-          "    bic r0, r0, r1\n\t"        
+          "    mov r1, #0x1\n\t"
+          "    bic r0, r0, r1\n\t"
           "    mcr p15, #0, r0, c1, c0, #0\n\t");
 }
 
diff --git a/lib/tiam1808/system_config/armv5/gcc/cpu.c b/lib/tiam1808/system_config/armv5/gcc/cpu.c
index 259b9687c..595c5d109 100644
--- a/lib/tiam1808/system_config/armv5/gcc/cpu.c
+++ b/lib/tiam1808/system_config/armv5/gcc/cpu.c
@@ -43,7 +43,7 @@
 ******************************************************************************/
 /**
  * \brief     This API can be used to switch from user mode to privileged mode
- *            The priviledge mode will be system mode. System mode will share 
+ *            The priviledge mode will be system mode. System mode will share
  *            the same resources as user mode, but with privileges.
  *
  * \param     None.
@@ -59,7 +59,7 @@ void CPUSwitchToPrivilegedMode(void)
 }
 
 /**
- * \brief     This API can be used to switch from any previleged mode of ARM to 
+ * \brief     This API can be used to switch from any previleged mode of ARM to
  *            user mode. After this API is called, the program will continue
  *            to operate in non-privileged mode, until any exception occurs.
  *            After the exception is serviced, execution will continue in user
@@ -83,13 +83,13 @@ void CPUSwitchToUserMode(void)
 /**
  * \brief     This API is called when the CPU is aborted or during execution
  *            of any undefined instruction. Both IRQ and FIQ will be disabled
- *            when the CPU gets an abort and calls this API. 
+ *            when the CPU gets an abort and calls this API.
  *
  * \param     None.
  *
  * \return    None.
  *
- * Note : The user can perform error handling such as an immediate reset 
+ * Note : The user can perform error handling such as an immediate reset
  *        inside this API if required.
  **/
 void CPUAbortHandler(void)
@@ -109,7 +109,7 @@ unsigned int CPUIntStatus(void)
     /* IRQ and FIQ in CPSR */
     __asm("    mrs     r0, CPSR\n\t"
           "    and     %[result], r0, #0xC0" : [result] "=r" (stat));
-    
+
     return stat;
 }
 
diff --git a/lib/tiam1808/system_config/armv5/gcc/init.S b/lib/tiam1808/system_config/armv5/gcc/init.S
index f38ee3df0..0145289ef 100644
--- a/lib/tiam1808/system_config/armv5/gcc/init.S
+++ b/lib/tiam1808/system_config/armv5/gcc/init.S
@@ -9,7 +9,7 @@
 
 @****************************** Global Symbols*********************************
         .global Entry
-        .global _stack                  
+        .global _stack
         .global _bss_start
         .global _bss_end
         .global start_boot
@@ -27,16 +27,16 @@
 
 @
 @ to set the mode bits in CPSR for different modes
-@        
-        .set  MODE_USR, 0x10            
+@
+        .set  MODE_USR, 0x10
         .set  MODE_FIQ, 0x11
         .set  MODE_IRQ, 0x12
         .set  MODE_SVC, 0x13
         .set  MODE_ABT, 0x17
         .set  MODE_UND, 0x1B
-        .set  MODE_SYS, 0x1F            
+        .set  MODE_SYS, 0x1F
 
-        .equ  I_F_BIT, 0xC0               
+        .equ  I_F_BIT, 0xC0
 
 @**************************** Code Seection ***********************************
         .text
@@ -52,7 +52,7 @@
 @
 @ The reset handler sets up the stack pointers for all the modes. The FIQ and
 @ IRQ shall be disabled during this. Then, clearthe BSS sections, switch to the
-@ main() function. 
+@ main() function.
 @
 Entry:
 @
@@ -64,31 +64,31 @@ Entry:
          SUB   r0, r0, #UND_STACK_SIZE         @ give stack space
 @
 @ Set up the Stack for abort mode
-@        
+@
          MSR   cpsr_c, #MODE_ABT|I_F_BIT       @ Change to abort mode
          MOV   sp, r0                          @ write the stack pointer
          SUB   r0,r0, #ABT_STACK_SIZE          @ give stack space
 @
 @ Set up the Stack for FIQ mode
-@       
+@
          MSR   cpsr_c, #MODE_FIQ|I_F_BIT       @ change to FIQ mode
          MOV   sp,r0                           @ write the stack pointer
          SUB   r0,r0, #FIQ_STACK_SIZE          @ give stack space
 @
 @ Set up the Stack for IRQ mode
-@       
+@
          MSR   cpsr_c, #MODE_IRQ|I_F_BIT       @ change to IRQ mode
          MOV   sp,r0                           @ write the stack pointer
          SUB   r0,r0, #IRQ_STACK_SIZE          @ give stack space
 @
 @ Set up the Stack for SVC mode
-@        
+@
          MSR   cpsr_c, #MODE_SVC|I_F_BIT       @ change to SVC mode
          MOV   sp,r0                           @ write the stack pointer
          SUB   r0,r0, #SVC_STACK_SIZE          @ give stack space
 @
 @ Set up the Stack for USer/System mode
-@      
+@
          MSR   cpsr_c, #MODE_SYS|I_F_BIT       @ change to system mode
          MOV   sp,r0                           @ write the stack pointer
 
@@ -99,8 +99,8 @@ Clear_Bss_Section:
 
          LDR   r0, =_bss_start                 @ Start address of BSS
          LDR   r1, =(_bss_end - 0x04)          @ End address of BSS
-         MOV   r2, #0  
-Loop: 
+         MOV   r2, #0
+Loop:
          STR   r2, [r0], #4                    @ Clear one word in BSS
          CMP   r0, r1
          BLE   Loop                            @ Clear till BSS end
@@ -110,16 +110,16 @@ Loop:
 @
 @Enter_main:
          LDR   r10,=start_boot                 @ Get the address of start_boot
-         MOV   lr,pc                           @ Dummy return 
+         MOV   lr,pc                           @ Dummy return
          BX    r10                             @ Branch to start_boot
-         SUB   pc, pc, #0x08                   @ looping   
+         SUB   pc, pc, #0x08                   @ looping
 
 @
 @ End of the file
 @
          .end
-    
-    
+
+
 
 
 
diff --git a/lib/tiam1808/tiam1808/armv5/am1808/edma_event.h b/lib/tiam1808/tiam1808/armv5/am1808/edma_event.h
index 91cfee8f1..8c55ab8dc 100644
--- a/lib/tiam1808/tiam1808/armv5/am1808/edma_event.h
+++ b/lib/tiam1808/tiam1808/armv5/am1808/edma_event.h
@@ -5,34 +5,34 @@
  */
 
 /*
-* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 
+* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
-*  Redistribution and use in source and binary forms, with or without 
-*  modification, are permitted provided that the following conditions 
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
 *  are met:
 *
-*    Redistributions of source code must retain the above copyright 
+*    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the 
-*    documentation and/or other materials provided with the   
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
diff --git a/lib/tiam1808/tiam1808/armv5/am1808/evmAM1808.h b/lib/tiam1808/tiam1808/armv5/am1808/evmAM1808.h
index 51119e2ff..1b50a453a 100644
--- a/lib/tiam1808/tiam1808/armv5/am1808/evmAM1808.h
+++ b/lib/tiam1808/tiam1808/armv5/am1808/evmAM1808.h
@@ -6,34 +6,34 @@
  */
 
 /*
-* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 
+* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
-*  Redistribution and use in source and binary forms, with or without 
-*  modification, are permitted provided that the following conditions 
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
 *  are met:
 *
-*    Redistributions of source code must retain the above copyright 
+*    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the 
-*    documentation and/or other materials provided with the   
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
@@ -53,7 +53,7 @@ extern void UARTPinMuxSetup(unsigned int instanceNum,
                             unsigned int modemCtrlChoice);
 extern void RTCPinMuxSetup(unsigned int alarmPinReqd);
 extern void SPI0CSPinMuxSetup(unsigned int csPinNum);
-extern void SPI1CSPinMuxSetup(unsigned int csPinNum); 
+extern void SPI1CSPinMuxSetup(unsigned int csPinNum);
 extern void I2CPinMuxSetup(unsigned int instanceNum);
 extern void SPIPinMuxSetup(unsigned int instanceNum);
 extern void ConfigRasterDisplayEnable(void);
diff --git a/lib/tiam1808/tiam1808/armv5/am1808/interrupt.h b/lib/tiam1808/tiam1808/armv5/am1808/interrupt.h
index f5e3d23c5..464b63d1e 100644
--- a/lib/tiam1808/tiam1808/armv5/am1808/interrupt.h
+++ b/lib/tiam1808/tiam1808/armv5/am1808/interrupt.h
@@ -7,34 +7,34 @@
 */
 
 /*
-* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 
+* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
-*  Redistribution and use in source and binary forms, with or without 
-*  modification, are permitted provided that the following conditions 
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
 *  are met:
 *
-*    Redistributions of source code must retain the above copyright 
+*    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the 
-*    documentation and/or other materials provided with the   
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
diff --git a/lib/tiam1808/tiam1808/armv5/cp15.h b/lib/tiam1808/tiam1808/armv5/cp15.h
index f876daa14..84ba4110e 100644
--- a/lib/tiam1808/tiam1808/armv5/cp15.h
+++ b/lib/tiam1808/tiam1808/armv5/cp15.h
@@ -7,34 +7,34 @@
 */
 
 /*
-* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 
+* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
-*  Redistribution and use in source and binary forms, with or without 
-*  modification, are permitted provided that the following conditions 
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
 *  are met:
 *
-*    Redistributions of source code must retain the above copyright 
+*    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the 
-*    documentation and/or other materials provided with the   
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
diff --git a/lib/tiam1808/tiam1808/armv5/cpu.h b/lib/tiam1808/tiam1808/armv5/cpu.h
index fd6f1ee63..3ec2febb9 100644
--- a/lib/tiam1808/tiam1808/armv5/cpu.h
+++ b/lib/tiam1808/tiam1808/armv5/cpu.h
@@ -7,34 +7,34 @@
 */
 
 /*
-* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 
+* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
-*  Redistribution and use in source and binary forms, with or without 
-*  modification, are permitted provided that the following conditions 
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
 *  are met:
 *
-*    Redistributions of source code must retain the above copyright 
+*    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the 
-*    documentation and/or other materials provided with the   
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
diff --git a/lib/tiam1808/tiam1808/cppi41dma.h b/lib/tiam1808/tiam1808/cppi41dma.h
index 7398b5eb5..9d9c7f849 100644
--- a/lib/tiam1808/tiam1808/cppi41dma.h
+++ b/lib/tiam1808/tiam1808/cppi41dma.h
@@ -117,8 +117,8 @@ extern "C"
 
 #if defined (am335x_15x15) || defined(am335x)
 //DMA registers
-#define CPDMA_TX_CHANNEL_CONFIG_REG		 	0x2800 
-#define CPDMA_RX_CHANNEL_CONFIG_REG 		0x2808 
+#define CPDMA_TX_CHANNEL_CONFIG_REG		 	0x2800
+#define CPDMA_RX_CHANNEL_CONFIG_REG 		0x2808
 #define CPDMA_RX_CHANNEL_REG_A      		0x280C
 #define CPDMA_RX_CHANNEL_REG_B      		0x2810
 #define CPDMA_SCHED_CONTROL_REG        		0x3000
@@ -126,8 +126,8 @@ extern "C"
 #define CPDMA_SCHED_TABLE_1            		0x3804
 #else
 //DMA registers
-#define CPDMA_TX_CHANNEL_CONFIG_REG		 	0x1800 
-#define CPDMA_RX_CHANNEL_CONFIG_REG 		0x1808 
+#define CPDMA_TX_CHANNEL_CONFIG_REG		 	0x1800
+#define CPDMA_RX_CHANNEL_CONFIG_REG 		0x1808
 #define CPDMA_RX_CHANNEL_REG_A      		0x180C
 #define CPDMA_RX_CHANNEL_REG_B      		0x1810
 #define CPDMA_SCHED_CONTROL_REG        		0x2000
@@ -330,11 +330,11 @@ typedef struct hostPacketDesc {
 	unsigned char devInst;
 	void * reqContext;
 	unsigned char reserved[18];
-	
+
 } hostPacketDesc ;
 
 // End point info structure for the application
-typedef struct  
+typedef struct
 {
 	 unsigned int endPoint;
 	 unsigned short direction;
@@ -373,9 +373,9 @@ typedef struct
 
 	//Pointers for BD Management
 	hostPacketDesc *tail_bd ;
-	hostPacketDesc *head_bd;	
+	hostPacketDesc *head_bd;
 	unsigned int *region0DescriptorAddress;
-	
+
 	//Array of USB Instances
 	usbInstance usbInst[NUMOF_USB_INSTANCE];
 }cppi41DmaInfo;
@@ -388,10 +388,10 @@ void Cppi41DmaInit(unsigned short usbDevInst, endpointInfo *epInfo, unsigned sho
 unsigned int dmaTxCompletion(unsigned short usbDevInst, unsigned int ulEndpoint);
 unsigned int  dmaRxCompletion(unsigned short usbDevInst, unsigned int ulEndpoint);
 
-void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff, 
+void doDmaTxTransfer(unsigned short usbDevInst, unsigned char *buff,
 								unsigned int length, unsigned int endPoint);
 
-void doDmaRxTransfer(unsigned short usbDevInst, unsigned int length, 
+void doDmaRxTransfer(unsigned short usbDevInst, unsigned int length,
 								unsigned char *buff, unsigned int endPoint);
 
 void enableCoreTxDMA(unsigned short usbDevInst, unsigned int ulEndpoint);
@@ -406,7 +406,7 @@ unsigned int * cppiDmaAllocBuffer();
 void cppiDmaFreeBuffer(unsigned int *dataBuffer);
 unsigned int * cppiDmaAllocnBuffer(unsigned int numOfBlocks);
 void cppiDmaFreenBuffer(unsigned int *dataBuffer);
-void cppiDmaHandleError(unsigned int usbDevInst); 
+void cppiDmaHandleError(unsigned int usbDevInst);
 
 
 #ifdef __cplusplus
diff --git a/lib/tiam1808/tiam1808/cpsw.h b/lib/tiam1808/tiam1808/cpsw.h
index 2de23fb97..05e384032 100644
--- a/lib/tiam1808/tiam1808/cpsw.h
+++ b/lib/tiam1808/tiam1808/cpsw.h
@@ -100,14 +100,14 @@ extern "C" {
 #define CPSW_RGMII1_LINK_STAT                  CPSW_WR_RGMII_CTL_RGMII1_LINK
 
 /* The values, one of which will be returned by CPSWWrRGMIIStatusGet */
-#define CPSW_RGMII2_DUPLEX_FULL                CPSW_WR_RGMII_CTL_RGMII2_FULLDUPLEX 
+#define CPSW_RGMII2_DUPLEX_FULL                CPSW_WR_RGMII_CTL_RGMII2_FULLDUPLEX
 #define CPSW_RGMII2_DUPLEX_HALF                (0x00u)
 #define CPSW_RGMII2_SPEED_10M                  (0x00u << CPSW_WR_RGMII_CTL_RGMII2_SPEED_SHIFT)
 #define CPSW_RGMII2_SPEED_100M                 (0x01u << CPSW_WR_RGMII_CTL_RGMII2_SPEED_SHIFT)
 #define CPSW_RGMII2_SPEED_1000M                (0x02u << CPSW_WR_RGMII_CTL_RGMII2_SPEED_SHIFT)
-#define CPSW_RGMII2_LINK_UP                    CPSW_WR_RGMII_CTL_RGMII2_LINK 
+#define CPSW_RGMII2_LINK_UP                    CPSW_WR_RGMII_CTL_RGMII2_LINK
 #define CPSW_RGMII2_LINK_DOWN                  (0x00u)
-#define CPSW_RGMII1_DUPLEX_FULL                CPSW_WR_RGMII_CTL_RGMII1_FULLDUPLEX 
+#define CPSW_RGMII1_DUPLEX_FULL                CPSW_WR_RGMII_CTL_RGMII1_FULLDUPLEX
 #define CPSW_RGMII1_DUPLEX_HALF                (0x00u)
 #define CPSW_RGMII1_SPEED_10M                  (0x00u << CPSW_WR_RGMII_CTL_RGMII1_SPEED_SHIFT)
 #define CPSW_RGMII1_SPEED_100M                 (0x01u << CPSW_WR_RGMII_CTL_RGMII1_SPEED_SHIFT)
@@ -116,10 +116,10 @@ extern "C" {
 #define CPSW_RGMII1_LINK_DOWN                  (0x00u)
 
 /*
-** Macros which can be passed as 'pacFlag' to the API CPSWWrIntPacingEnable 
+** Macros which can be passed as 'pacFlag' to the API CPSWWrIntPacingEnable
 ** CPSWWrIntPacingDisable
 */
-#define CPSW_INT_PACING_C0_RX_PULSE            (0x01 << CPSW_WR_INT_CONTROL_INT_PACE_EN_SHIFT) 
+#define CPSW_INT_PACING_C0_RX_PULSE            (0x01 << CPSW_WR_INT_CONTROL_INT_PACE_EN_SHIFT)
 #define CPSW_INT_PACING_C0_TX_PULSE            (0x02 << CPSW_WR_INT_CONTROL_INT_PACE_EN_SHIFT)
 #define CPSW_INT_PACING_C1_RX_PULSE            (0x04 << CPSW_WR_INT_CONTROL_INT_PACE_EN_SHIFT)
 #define CPSW_INT_PACING_C1_TX_PULSE            (0x08 << CPSW_WR_INT_CONTROL_INT_PACE_EN_SHIFT)
@@ -133,7 +133,7 @@ extern "C" {
 #define CPSW_ALE_PORT_STATE_LEARN              (0x02u)
 #define CPSW_ALE_PORT_STATE_BLOCKED            (0x01u)
 #define CPSW_ALE_PORT_STATE_DISABLED           (0x00u)
- 
+
 /*
 ** Macros which can be passed as 'eoiFlag' to CPSWCPDMAEndOfIntVectorWrite
 */
@@ -154,7 +154,7 @@ extern "C" {
 #define CPDMA_STAT_TX_HOST_ERR_CODE            (CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE)
 
 /* The return values for the above 'statFlag' */
-#define CPDMA_STAT_TX_NO_ERR                   (0x00u << CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT) 
+#define CPDMA_STAT_TX_NO_ERR                   (0x00u << CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT)
 #define CPDMA_STAT_TX_SOP_ERR                  (0x01u << CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT)
 #define CPDMA_STAT_TX_OWN_ERR                  (0x02u << CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT)
 #define CPDMA_STAT_TX_ZERO_DESC                (0x03u << CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT)
diff --git a/lib/tiam1808/tiam1808/dmtimer.h b/lib/tiam1808/tiam1808/dmtimer.h
index b12c752bb..6615e8d8c 100644
--- a/lib/tiam1808/tiam1808/dmtimer.h
+++ b/lib/tiam1808/tiam1808/dmtimer.h
@@ -105,7 +105,7 @@ extern "C" {
 
 /******************************************************************************/
 /*
-** Values that can be passed to DMTimerPWMEnable as ptMode. 
+** Values that can be passed to DMTimerPWMEnable as ptMode.
 */
 /* Value used to determine Pulse(Positive) mode for PORTTIMERPWM */
 #define DMTIMER_PWM_PULSE_MODE_POSITIVE	    (DMTIMER_TCLR_PT_PULSE | \
@@ -176,7 +176,7 @@ extern "C" {
 
 /******************************************************************************/
 /*
-** Values that can be passed to DMTimerEmulationModeConfigure as emuMode. 
+** Values that can be passed to DMTimerEmulationModeConfigure as emuMode.
 */
 /* Value used to signify that the Emulation mode is free */
 #define DMTIMER_EMUFREE_FREE		    (DMTIMER_TIOCP_CFG_EMUFREE)
@@ -186,7 +186,7 @@ extern "C" {
 
 /******************************************************************************/
 /*
-** Values that can be passed to DMTimerPwrMngmntConfigure as pwrMngMode. 
+** Values that can be passed to DMTimerPwrMngmntConfigure as pwrMngMode.
 */
 /* Value used to configure force-idle mode */
 #define DMTIMER_FORCE_IDLE_MODE		    (DMTIMER_TIOCP_CFG_IDLEMODE_FORCE)
@@ -206,7 +206,7 @@ extern "C" {
 /******************************************************************************/
 /*
 ** Values that can be passed to DMTimerIntStatusClear/DMTimerIntRawStatusSet/
-** as intFlags. Also these values can be used while checking the status got from 
+** as intFlags. Also these values can be used while checking the status got from
 ** DMTimerIntRawStatusGet/DMTimerIntStatusGet.
 ** Any combination is also followed.
 ** Example- (DMTIMER_INT_TCAR_IT_FLAG | DMTIMER_INT_OVF_IT_FLAG)
@@ -215,7 +215,7 @@ extern "C" {
 #define DMTIMER_INT_TCAR_IT_FLAG             (DMTIMER_IRQSTATUS_RAW_TCAR_IT_FLAG)
 
 /* Value used for overflow event of DMTimer */
-#define DMTIMER_INT_OVF_IT_FLAG              (DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG) 
+#define DMTIMER_INT_OVF_IT_FLAG              (DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG)
 
 /* Value used for Match event of DMTimer */
 #define DMTIMER_INT_MAT_IT_FLAG              (DMTIMER_IRQSTATUS_RAW_MAT_IT_FLAG)
@@ -223,7 +223,7 @@ extern "C" {
 /******************************************************************************/
 /*
 ** Values that can be passed to DMTimerIntEnable/DMTimerIntDisable as intFlags.
-** Also these values can be used while checking the status got from 
+** Also these values can be used while checking the status got from
 ** DMTimerIntEnableGet.
 ** Any combination is also followed.
 ** Example- (DMTIMER_INT_TCAR_EN_FLAG | DMTIMER_INT_OVF_EN_FLAG)
@@ -265,7 +265,7 @@ extern "C" {
 
 /******************************************************************************/
 /*
-** Values that can be used while checking status received from 
+** Values that can be used while checking status received from
 ** DMTimerWritePostedStatusGet.
 */
 /* Value used to check the write posted condition for TMAR register */
@@ -275,7 +275,7 @@ extern "C" {
 #define DMTIMER_WRITE_POST_TTGR              (DMTIMER_TWPS_W_PEND_TTGR)
 
 /* Value used to check the write posted condition for TLDR register */
-#define DMTIMER_WRITE_POST_TLDR              (DMTIMER_TWPS_W_PEND_TLDR) 
+#define DMTIMER_WRITE_POST_TLDR              (DMTIMER_TWPS_W_PEND_TLDR)
 
 /* Value used to check the write posted condition for TCRR register */
 #define DMTIMER_WRITE_POST_TCRR              (DMTIMER_TWPS_W_PEND_TCRR)
@@ -295,7 +295,7 @@ extern "C" {
 
 /******************************************************************************/
 /*
-** Values that can be used while checking the status received from 
+** Values that can be used while checking the status received from
 ** DMTimerIsResetDone.
 */
 /* Value used to check whether reset is done */
diff --git a/lib/tiam1808/tiam1808/ecap.h b/lib/tiam1808/tiam1808/ecap.h
index 68478f7f8..4883732e6 100644
--- a/lib/tiam1808/tiam1808/ecap.h
+++ b/lib/tiam1808/tiam1808/ecap.h
@@ -56,7 +56,7 @@ extern "C" {
 */
 
 #define  ECAP_CAPTURE_MODE               1
-#define  ECAP_APWM_MODE                  0 
+#define  ECAP_APWM_MODE                  0
 
 /****************************************************************************/
 /*
@@ -64,7 +64,7 @@ extern "C" {
 ** to determine for which capture event time-stamp has to be returned
 */
 
-#define  ECAP_CAPTURE_EVENT_1            0x08     
+#define  ECAP_CAPTURE_EVENT_1            0x08
 #define  ECAP_CAPTURE_EVENT_2            0x0c
 #define  ECAP_CAPTURE_EVENT_3            0x10
 #define  ECAP_CAPTURE_EVENT_4            0x14
@@ -76,8 +76,8 @@ extern "C" {
 ** Capture register(1-4) frozen.\n
 */
 
-#define  ECAP_CAPTURE_EVENT1_STOP        (0x00 << ECAP_ECCTL2_STOP_WRAP_SHIFT)  
-#define  ECAP_CAPTURE_EVENT2_STOP        (0x01 << ECAP_ECCTL2_STOP_WRAP_SHIFT) 
+#define  ECAP_CAPTURE_EVENT1_STOP        (0x00 << ECAP_ECCTL2_STOP_WRAP_SHIFT)
+#define  ECAP_CAPTURE_EVENT2_STOP        (0x01 << ECAP_ECCTL2_STOP_WRAP_SHIFT)
 #define  ECAP_CAPTURE_EVENT3_STOP        (0x02 << ECAP_ECCTL2_STOP_WRAP_SHIFT)
 #define  ECAP_CAPTURE_EVENT4_STOP        (0x03 << ECAP_ECCTL2_STOP_WRAP_SHIFT)
 
@@ -87,8 +87,8 @@ extern "C" {
 ** which determines the output polarity for APWM output
 */
 
-#define  ECAP_APWM_ACTIVE_HIGH           0 
-#define  ECAP_APWM_ACTIVE_LOW            1   
+#define  ECAP_APWM_ACTIVE_HIGH           0
+#define  ECAP_APWM_ACTIVE_LOW            1
 
 /****************************************************************************/
 /*
@@ -113,7 +113,7 @@ extern "C" {
 /****************************************************************************/
 /*
 ** Values that can be passed to ECAPSyncInOutSelect API  as syncOut
-** to select syncIn event to be the Sync-Out signal or select 
+** to select syncIn event to be the Sync-Out signal or select
 ** PRD_eq event to be Sync-Out signal or to disaqble syncOut
 ** signal
 */
@@ -121,20 +121,20 @@ extern "C" {
 #define  ECAP_SYNC_IN                    (00 << ECAP_ECCTL2_SYNCO_SEL_SHIFT)
 #define  ECAP_PRD_EQ                     (01 << ECAP_ECCTL2_SYNCO_SEL_SHIFT)
 #define  ECAP_SYNC_OUT_DISABLE           (10 << ECAP_ECCTL2_SYNCO_SEL_SHIFT)
- 
+
 /****************************************************************************/
 /*
-** Values that can be passed to ECAPIntEnable/Disable  API 
+** Values that can be passed to ECAPIntEnable/Disable  API
 ** to enable or disable interrupt or it can be passed
-** ECAPIntStatus to get the interrupt or it can be passed 
-** to ECAPIntStatusClear to clear the interrupt status 
+** ECAPIntStatus to get the interrupt or it can be passed
+** to ECAPIntStatusClear to clear the interrupt status
 */
 
-#define  ECAP_CEVT1_INT                  ECAP_ECEINT_CEVT1                   
+#define  ECAP_CEVT1_INT                  ECAP_ECEINT_CEVT1
 #define  ECAP_CEVT2_INT                  ECAP_ECEINT_CEVT2
 #define  ECAP_CEVT3_INT                  ECAP_ECEINT_CEVT3
 #define  ECAP_CEVT4_INT                  ECAP_ECEINT_CEVT4
-#define  ECAP_CNTOVF_INT                 ECAP_ECEINT_CTROVF 
+#define  ECAP_CNTOVF_INT                 ECAP_ECEINT_CTROVF
 #define  ECAP_PRDEQ_INT                  ECAP_ECEINT_CTR_PRD
 #define  ECAP_CMPEQ_INT                  ECAP_ECEINT_CTR_CMP
 
@@ -143,21 +143,21 @@ extern "C" {
 
 /****************************************************************************/
 /*
-** Values that can be passed to ECAPStandByModeConfig API 
+** Values that can be passed to ECAPStandByModeConfig API
 ** to configure ECAP module in different stand by mode.
-**  
+**
 */
 #define     ECAP_SMART_STAND_BY_WAKE_UP     3
-#define     ECAP_FORCE_STAND_BY             0  
+#define     ECAP_FORCE_STAND_BY             0
 #define     ECAP_SMART_STAND_BY             2
 #define     ECAP_NO_STAND_BY                1
 /****************************************************************************/
 /*
-** Values that can be passed to ECAPIdleModeConfig API 
+** Values that can be passed to ECAPIdleModeConfig API
 ** to configure ECAP module in different Idle mode.
-**  
+**
 */
-#define     ECAP_SMART_IDLE_WAKE_UP        3  
+#define     ECAP_SMART_IDLE_WAKE_UP        3
 #define     ECAP_SMART_IDLE_MODE           2
 #define     ECAP_FORCE_IDLE_MODE           0
 #define     ECAP_NO_IDLE_MODE              1
@@ -218,4 +218,4 @@ extern void EcapContextSave(unsigned int ecapBase, unsigned int pwmssBase,
 extern void EcapContextRestore(unsigned int ecapBase, unsigned int pwmssBase,
                                ECAPCONTEXT *contextPtr);
 
-#endif  
+#endif
diff --git a/lib/tiam1808/tiam1808/edma.h b/lib/tiam1808/tiam1808/edma.h
index c58a43c90..d775afb46 100644
--- a/lib/tiam1808/tiam1808/edma.h
+++ b/lib/tiam1808/tiam1808/edma.h
@@ -297,27 +297,27 @@ typedef struct EDMA3CCPaRAMEntry {
 typedef struct edmaContext {
     /* Channel mapping reg Val */
     unsigned int dchMap[64];
-    /* DMA Queue Number Register Val */    
-    unsigned int dmaQNum[8];    
-    
-    /* DMA Region Access Enable Register val */    
-    unsigned int regAccEnableLow;    
-    unsigned int regAccEnableHigh;        
-
-    /* Event Set Register value */    
+    /* DMA Queue Number Register Val */
+    unsigned int dmaQNum[8];
+
+    /* DMA Region Access Enable Register val */
+    unsigned int regAccEnableLow;
+    unsigned int regAccEnableHigh;
+
+    /* Event Set Register value */
     unsigned int eventSetRegLow;
-    unsigned int eventSetRegHigh;    
-    
-    /* Enable Event Set Register value */    
+    unsigned int eventSetRegHigh;
+
+    /* Enable Event Set Register value */
     unsigned int enableEvtSetRegLow;
     unsigned int enableEvtSetRegHigh;
-    
-    /* Interrupt Enable Set Register value */            
-    unsigned int intEnableSetRegLow;        
-    unsigned int intEnableSetRegHigh;    
-    
-    struct EDMA3CCPaRAMEntry dmaParEntry[512];    
-    
+
+    /* Interrupt Enable Set Register value */
+    unsigned int intEnableSetRegLow;
+    unsigned int intEnableSetRegHigh;
+
+    struct EDMA3CCPaRAMEntry dmaParEntry[512];
+
 } EDMACONTEXT;
 
 /****************************************************************************
diff --git a/lib/tiam1808/tiam1808/ehrpwm.h b/lib/tiam1808/tiam1808/ehrpwm.h
index d2c0b1f79..08fa40946 100644
--- a/lib/tiam1808/tiam1808/ehrpwm.h
+++ b/lib/tiam1808/tiam1808/ehrpwm.h
@@ -53,7 +53,7 @@ extern "C" {
 #define EHRPWM_PRD_LOAD_SHADOW_MASK		EHRPWM_TBCTL_PRDLD
 
 /* Counter mode */
-#define EHRPWM_COUNTER_MODE_MASK		EHRPWM_TBCTL_CTRMODE 
+#define EHRPWM_COUNTER_MODE_MASK		EHRPWM_TBCTL_CTRMODE
 #define EHRPWM_COUNT_UP				(EHRPWM_TBCTL_CTRMODE_UP << \
 	       						EHRPWM_TBCTL_CTRMODE_SHIFT)
 #define EHRPWM_COUNT_DOWN			(EHRPWM_TBCTL_CTRMODE_DOWN << \
@@ -66,7 +66,7 @@ extern "C" {
 #define EHRPWM_SYNC_ENABLE			EHRPWM_TBCTL_PHSEN
 //#define EHRPWM_SW_FORCED_SYNC			0x1
 
-#define EHRPWM_SYNCOUT_MASK			EHRPWM_TBCTL_SYNCOSEL   
+#define EHRPWM_SYNCOUT_MASK			EHRPWM_TBCTL_SYNCOSEL
 #define EHRPWM_SYNCOUT_SYNCIN			(EHRPWM_TBCTL_SYNCOSEL_EPWMXSYNCI << \
 							EHRPWM_TBCTL_SYNCOSEL_SHIFT)
 #define EHRPWM_SYNCOUT_COUNTER_EQUAL_ZERO	(EHRPWM_TBCTL_SYNCOSEL_TBCTRZERO << \
@@ -138,7 +138,7 @@ extern "C" {
 							EHRPWM_CMPCTL_LOADAMODE_SHIFT)
 #define EHRPWM_COMPA_LOAD_COUNT_EQUAL_ZERO_OR_PERIOD \
 						(EHRPWM_CMPCTL_LOADAMODE_ZEROORPRD << \
-							EHRPWM_CMPCTL_LOADAMODE_SHIFT)						 
+							EHRPWM_CMPCTL_LOADAMODE_SHIFT)
 #define EHRPWM_COMPA_NO_LOAD			(EHRPWM_CMPCTL_LOADAMODE_FREEZE << \
 							EHRPWM_CMPCTL_LOADAMODE_SHIFT)
 
@@ -167,15 +167,15 @@ extern "C" {
 //**********************************************************************/
 
 /* Timebase sub-module */
-void EHRPWMTimebaseClkConfig(unsigned int baseAddr, unsigned int tbClk, 
+void EHRPWMTimebaseClkConfig(unsigned int baseAddr, unsigned int tbClk,
 		unsigned int moduleClk);
 void EHRPWMPWMOpFreqSet(unsigned int baseAddr, unsigned int tbClk,
-		unsigned int pwmFreq,unsigned int counterDir, 
+		unsigned int pwmFreq,unsigned int counterDir,
 		bool enableShadowWrite);
 void EHRPWMTBEmulationModeSet(unsigned int baseAddr, unsigned int mode);
 void EHRPWMTimebaseSyncEnable(unsigned int baseAddr, unsigned int tbPhsValue,
 	       	unsigned int phsCountDir);
-void EHRPWMTimebaseSyncDisable(unsigned int baseAddr); 
+void EHRPWMTimebaseSyncDisable(unsigned int baseAddr);
 void EHRPWMTriggerSWSync(unsigned int baseAddr);
 void EHRPWMSyncOutModeSet(unsigned int baseAddr, unsigned int syncOutMode);
 void EHRPWMWriteTBCount(unsigned int baseAddr, unsigned int tbCount);
@@ -186,7 +186,7 @@ void EHRPWMTBClearStatus(unsigned int baseAddr, unsigned int tbStatusMask);
 
 /* Counter compare sub-module */
 bool EHRPWMLoadCMPA(unsigned int baseAddr, unsigned int CMPAVal,
-		bool enableShadowWrite, unsigned int ShadowToActiveLoadTrigger, 
+		bool enableShadowWrite, unsigned int ShadowToActiveLoadTrigger,
 		bool OverwriteShadowFull);
 
 bool EHRPWMLoadCMPB(unsigned int baseAddr, unsigned int CMPBVal,
@@ -194,19 +194,19 @@ bool EHRPWMLoadCMPB(unsigned int baseAddr, unsigned int CMPBVal,
 		bool OverwriteShadowFull);
 
 /* Action Qualifier sub-module */
-void EHRPWMConfigureAQActionOnA(unsigned int baseAddr, unsigned int zero, 
+void EHRPWMConfigureAQActionOnA(unsigned int baseAddr, unsigned int zero,
 		unsigned int period,
 		unsigned int CAUp,  unsigned int CADown,  unsigned int CBUp,
 		unsigned int CBDown, unsigned int SWForced);
-void EHRPWMConfigureAQActionOnB(unsigned int baseAddr, unsigned int zero, 
+void EHRPWMConfigureAQActionOnB(unsigned int baseAddr, unsigned int zero,
 		unsigned int period,
 		unsigned int CAUp,  unsigned int CADown,  unsigned int CBUp,
 		unsigned int CBDown, unsigned int SWForced);
 void EHRPWMSWForceA(unsigned int baseAddr);
 void EHRPWMSWForceB(unsigned int baseAddr);
-void EHRPWMAQContSWForceOnA(unsigned int baseAddr, unsigned int forceVal, 
+void EHRPWMAQContSWForceOnA(unsigned int baseAddr, unsigned int forceVal,
 		unsigned int activeRegReloadMode);
-void EHRPWMAQContSWForceOnB(unsigned int baseAddr, unsigned int forceVal, 
+void EHRPWMAQContSWForceOnB(unsigned int baseAddr, unsigned int forceVal,
 		unsigned int activeRegReloadMode);
 
 /* Dead Band Generator */
@@ -246,9 +246,9 @@ void EHRPWMETIntSWForce(unsigned int baseAddr);
 
 /* HEPWM sub-module */
 void EHRPWMLoadTBPHSHR(unsigned int baseAddr, unsigned int TBPHSHRVal);
-void EHRPWMLoadCMPAHR(unsigned int baseAddr, unsigned int CMPAHRVal, 
+void EHRPWMLoadCMPAHR(unsigned int baseAddr, unsigned int CMPAHRVal,
 		unsigned int ShadowToActiveLoadTrigger);
-void EHRPWMConfigHR(unsigned int baseAddr,unsigned int ctrlMode, 
+void EHRPWMConfigHR(unsigned int baseAddr,unsigned int ctrlMode,
 		unsigned int MEPCtrlEdge); /* also enables */
 void EHRPWMHRDisable(unsigned int baseAddr);
 void EHRPWMClockEnable(unsigned int baseAdd);
diff --git a/lib/tiam1808/tiam1808/emac.h b/lib/tiam1808/tiam1808/emac.h
index 884b236f4..18b121c49 100644
--- a/lib/tiam1808/tiam1808/emac.h
+++ b/lib/tiam1808/tiam1808/emac.h
@@ -56,14 +56,14 @@ extern "C" {
 #define EMAC_RMIISPEED_100MBPS                (0x00008000u)
 
 /*
-** Macros which can be used as duplexMode parameter to the API 
+** Macros which can be used as duplexMode parameter to the API
 ** EMACDuplexSet
 */
 #define EMAC_DUPLEX_FULL                      (0x00000001u)
 #define EMAC_DUPLEX_HALF                      (0x00000000u)
 
 /*
-** Macros which can be used as matchFilt  parameters to the API 
+** Macros which can be used as matchFilt  parameters to the API
 ** EMACMACAddrSet
 */
 /* Address not used to match/filter incoming packets */
diff --git a/lib/tiam1808/tiam1808/emifa.h b/lib/tiam1808/tiam1808/emifa.h
index e92362f9c..6d6f23f04 100644
--- a/lib/tiam1808/tiam1808/emifa.h
+++ b/lib/tiam1808/tiam1808/emifa.h
@@ -55,7 +55,7 @@ extern "C" {
 *******************************************************************************/
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFANandCSSet API as CSNum to select 
+** Values that can be passed to EMIFANandCSSet API as CSNum to select
 ** Chip Select.
 */
 
@@ -87,7 +87,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFACSWaitPinSelect API as pin to select 
+** Values that can be passed to EMIFACSWaitPinSelect API as pin to select
 ** EMA_WAIT Pin.
 */
 
@@ -98,7 +98,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFAWaitPinPolaritySet API as pinPolarity to 
+** Values that can be passed to EMIFAWaitPinPolaritySet API as pinPolarity to
 ** select Pin polarity.
 */
 
@@ -110,7 +110,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFADataBusWidthSelect API as width to set the 
+** Values that can be passed to EMIFADataBusWidthSelect API as width to set the
 ** bus width.
 */
 
@@ -119,7 +119,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFAOpModeSelect API as mode to set the 
+** Values that can be passed to EMIFAOpModeSelect API as mode to set the
 ** Asynchronous interface opmode.
 */
 
@@ -128,7 +128,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFAExtendedWaitEnable API as flag to select 
+** Values that can be passed to EMIFAExtendedWaitEnable API as flag to select
 ** or deselect the extended wait cycles.
 */
 
@@ -137,7 +137,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFANORPageSizeSet API as pagesize to set the  
+** Values that can be passed to EMIFANORPageSizeSet API as pagesize to set the
 ** page size for NOR.
 */
 
@@ -146,7 +146,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFANANDEccValGet API as eccValIndex to   
+** Values that can be passed to EMIFANANDEccValGet API as eccValIndex to
 ** specify the ecc value to read.
 */
 
@@ -161,7 +161,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFANAND4BitEccErrAddrGet API as    
+** Values that can be passed to EMIFANAND4BitEccErrAddrGet API as
 ** eccErrAddrIndex to specify the ecc error address to read.
 */
 
@@ -172,7 +172,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that define the state values in the ECC_STATE field of NANDFSR   
+** Values that define the state values in the ECC_STATE field of NANDFSR
 ** as returned by EMIFANAND4BitECCStateGet.
 */
 #define EMIFA_4BITECC_CORRECTION_ECCSTATE_0           (0u)
@@ -183,7 +183,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFANANDECCStart API as eccType to specify   
+** Values that can be passed to EMIFANANDECCStart API as eccType to specify
 ** specify the ecc type.
 */
 
@@ -192,7 +192,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFANAND4BitEccErrValGet API as eccErrValIndex 
+** Values that can be passed to EMIFANAND4BitEccErrValGet API as eccErrValIndex
 ** to specify the ecc error value to read.
 */
 
@@ -203,7 +203,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFASDRAMSelfRefModeConfig API as flag 
+** Values that can be passed to EMIFASDRAMSelfRefModeConfig API as flag
 ** to specify the selfrefresh mode to enter or exit.
 */
 
@@ -212,7 +212,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFASDRAMPowDownModeConfig API as flag 
+** Values that can be passed to EMIFASDRAMPowDownModeConfig API as flag
 ** to specify the powerdown mode ot enter or exit.
 */
 
@@ -221,7 +221,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFA_SDRAM_CONF macro as psize 
+** Values that can be passed to EMIFA_SDRAM_CONF macro as psize
 ** to specify the internal page size.
 */
 
@@ -232,7 +232,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFA_SDRAM_CONF macro as ibank 
+** Values that can be passed to EMIFA_SDRAM_CONF macro as ibank
 ** to specify the Internal SDRAM bank size.
 */
 
@@ -242,7 +242,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFA_SDRAM_CONF macro as bit11_9lock 
+** Values that can be passed to EMIFA_SDRAM_CONF macro as bit11_9lock
 ** to specify the CAS lat write lock flag.
 */
 
@@ -251,7 +251,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFA_SDRAM_CONF macro as nm 
+** Values that can be passed to EMIFA_SDRAM_CONF macro as nm
 ** to specify the Narrow mode bit.
 */
 
@@ -260,7 +260,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFA_SDRAM_CONF macro as caslat 
+** Values that can be passed to EMIFA_SDRAM_CONF macro as caslat
 ** to specify the CAS latency.
 */
 
@@ -269,7 +269,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be passed to EMIFANORPageModeConfig API as flag 
+** Values that can be passed to EMIFANORPageModeConfig API as flag
 ** to specify the page mode to enable or disable.
 */
 
@@ -290,7 +290,7 @@ extern "C" {
 /*****************************************************************************/
 /*
 * \brief  This macro used to make the conf value which is used to configure the
-*           async wait time.\n 
+*           async wait time.\n
 *
 * \param  wset      Write setup time or width in EMA_CLK cycles.\n
 *
@@ -320,7 +320,7 @@ extern "C" {
 /*****************************************************************************/
 /*
 * \brief  This macro used to make the conf value which is used to configure the
-*           SDRAM.\n 
+*           SDRAM.\n
 *
 * \param  psize       -- internal page size.It can take follwing values.
 *                           EMIFA_SDRAM_8COLUMN_ADDR_BITS
@@ -337,37 +337,37 @@ extern "C" {
 *         caslat      -- CAS latency. It can take following values.
 *                           EMIFA_SDRAM_CAS_LAT_2CYCLES
 *                           EMIFA_SDRAM_CAS_LAT_3CYCLES
-*         nm          -- Narrow mode bit.This defines whether a 16- or 
+*         nm          -- Narrow mode bit.This defines whether a 16- or
 *                        32-bit-wide SDRAM is connected to the EMIFA.It can
 *                        take following values.
 *                           EMIFA_SDRAM_32BIT
 *                           EMIFA_SDRAM_16BIT
 *
 */
-                               
+
 #define EMIFA_SDRAM_CONF(psize, ibank, bit11_9lock, caslat, nm )   ((unsigned int) \
                                                                     ((psize << EMIFA_SDCR_PAGESIZE_SHIFT) & EMIFA_SDCR_PAGESIZE) | \
                                                                     ((ibank << EMIFA_SDCR_IBANK_SHIFT) & EMIFA_SDCR_IBANK) | \
                                                                     ((bit11_9lock << EMIFA_SDCR_BIT11_9LOCK_SHIFT) & EMIFA_SDCR_BIT11_9LOCK) | \
                                                                     ((caslat << EMIFA_SDCR_CL_SHIFT) & EMIFA_SDCR_CL) | \
                                                                     ((nm << EMIFA_SDCR_NM_SHIFT) & EMIFA_SDCR_NM))
-                                                                    
+
 /*****************************************************************************/
 /*
 * \brief  This macro used to make the conf value which is used to configure the
-*           SDRAM.\n 
+*           SDRAM.\n
 *
 * \param  t_rrd   -- internal page size.It can take follwing values.
-*         t_rc    -- EMA_CLK clock cycles from Activate to Activate 
+*         t_rc    -- EMA_CLK clock cycles from Activate to Activate
 *         t_ras   -- EMA_CLK clock cycles from Activate(ACTV) to Precharge(PRE)
 *         t_wr    -- EMA_CLK cycles from last Write (WRT) to Precharge (PRE)
 *         t_rcd   -- EMA_CLK cycles from Active(ACTV) to Rd(READ) or Wr(WRT).
-*         t_rp    -- EMA_CLK cycles from Precharge (PRE) to Activate (ACTV) 
+*         t_rp    -- EMA_CLK cycles from Precharge (PRE) to Activate (ACTV)
 *                       or Refresh (REFR) command,
 *         t_rfc   -- EMA_CLK cycles from Refresh (REFR) to Refresh (REFR).
 *
-*/                                                                  
-                                                                                                                            
+*/
+
 #define EMIFA_SDRAM_TIMING_CONF(t_rrd, t_rc, t_ras, t_wr, t_rcd, t_rp, t_rfc )   ((unsigned int) \
                                                                                   ((t_rrd << EMIFA_SDTIMR_T_RRD_SHIFT) & EMIFA_SDTIMR_T_RRD) | \
                                                                                   ((t_rc << EMIFA_SDTIMR_T_RC_SHIFT) & EMIFA_SDTIMR_T_RC) | \
@@ -399,32 +399,32 @@ extern void EMIFANAND4BitECCSelect(unsigned int baseAddr, unsigned int CSNum);
 extern void EMIFAMaxExtWaitCycleSet(unsigned int baseAddr,
                                     unsigned int waitVal);
 extern void EMIFASDRAMSelfRefModeConfig(unsigned int baseAddr,
-                                        unsigned int flag);                                    
+                                        unsigned int flag);
 extern unsigned int EMIFARawIntStatusRead(unsigned int baseAddr,
-                                          unsigned int intFlag);                                    
+                                          unsigned int intFlag);
 extern unsigned int EMIFAMskedIntStatusRead(unsigned int baseAddr,
-                                            unsigned int intFlag);                                          
+                                            unsigned int intFlag);
 extern void EMIFASDRAMPowDownModeConfig(unsigned int baseAddr,
                                         unsigned int flag);
 extern unsigned int EMIFAWaitPinStatusGet(unsigned int baseAddr,
-                                              unsigned int pinNum);                                        
+                                              unsigned int pinNum);
 extern void EMIFASDRAMSelfRefExitTimeConfig(unsigned int baseAddr,
-                                            unsigned int exitTime);                                            
+                                            unsigned int exitTime);
 extern unsigned int EMIFANAND4BitEccErrAddrGet(unsigned int baseAddr,
                                                unsigned int eccErrAddrIndex);
 extern unsigned int EMIFANAND4BitEccErrValGet(unsigned int baseAddr,
-                                              unsigned int eccErrValIndex);                                            
+                                              unsigned int eccErrValIndex);
 extern void EMIFACSWaitPinSelect(unsigned int baseAddr,
-                                 unsigned int CSNum,unsigned int pin);                             
+                                 unsigned int CSNum,unsigned int pin);
 extern void EMIFAAsyncDevOpModeSelect(unsigned int baseAddr,unsigned int CSNum,
-                                      unsigned int mode);                             
+                                      unsigned int mode);
 extern void EMIFAExtendedWaitConfig(unsigned int baseAddr,unsigned int CSNum,
-                                    unsigned int flag);                                  
+                                    unsigned int flag);
 extern void EMIFAAsyncDevDataBusWidthSelect(unsigned int baseAddr,
                                             unsigned int CSNum,
-                                            unsigned int width);                                 
+                                            unsigned int width);
 extern void EMIFAWaitTimingConfig(unsigned int baseAddr,unsigned int csNum,
-                                  unsigned int conf);                                    
+                                  unsigned int conf);
 extern void EMIFAWaitPinPolaritySet(unsigned int baseAddr,unsigned int pin,
                                     unsigned int pinPolarity);
 extern void EMIFANORPageModeConfig(unsigned int baseAddr, unsigned int CSNum,
diff --git a/lib/tiam1808/tiam1808/epwm.h b/lib/tiam1808/tiam1808/epwm.h
index dd29ab7b0..a41ddb9f1 100644
--- a/lib/tiam1808/tiam1808/epwm.h
+++ b/lib/tiam1808/tiam1808/epwm.h
@@ -51,7 +51,7 @@ extern "C" {
 #define EHRPWM_PRD_LOAD_SHADOW_MASK		EHRPWM_TBCTL_PRDLD
 
 /* Counter mode */
-#define EHRPWM_COUNTER_MODE_MASK		EHRPWM_TBCTL_CTRMODE 
+#define EHRPWM_COUNTER_MODE_MASK		EHRPWM_TBCTL_CTRMODE
 #define EHRPWM_COUNT_UP				(EHRPWM_TBCTL_CTRMODE_UP << \
 	       						EHRPWM_TBCTL_CTRMODE_SHIFT)
 #define EHRPWM_COUNT_DOWN			(EHRPWM_TBCTL_CTRMODE_DOWN << \
@@ -64,7 +64,7 @@ extern "C" {
 #define EHRPWM_SYNC_ENABLE			EHRPWM_TBCTL_PHSEN
 //#define EHRPWM_SW_FORCED_SYNC			0x1
 
-#define EHRPWM_SYNCOUT_MASK			EHRPWM_TBCTL_SYNCOSEL   
+#define EHRPWM_SYNCOUT_MASK			EHRPWM_TBCTL_SYNCOSEL
 #define EHRPWM_SYNCOUT_SYNCIN			(EHRPWM_TBCTL_SYNCOSEL_EPWMXSYNCI << \
 							EHRPWM_TBCTL_SYNCOSEL_SHIFT)
 #define EHRPWM_SYNCOUT_COUNTER_EQUAL_ZERO	(EHRPWM_TBCTL_SYNCOSEL_TBCTRZERO << \
@@ -136,7 +136,7 @@ extern "C" {
 							EHRPWM_CMPCTL_LOADAMODE_SHIFT)
 #define EHRPWM_COMPA_LOAD_COUNT_EQUAL_ZERO_OR_PERIOD \
 						(EHRPWM_CMPCTL_LOADAMODE_ZEROORPRD << \
-							EHRPWM_CMPCTL_LOADAMODE_SHIFT)						 
+							EHRPWM_CMPCTL_LOADAMODE_SHIFT)
 #define EHRPWM_COMPA_NO_LOAD			(EHRPWM_CMPCTL_LOADAMODE_FREEZE << \
 							EHRPWM_CMPCTL_LOADAMODE_SHIFT)
 
@@ -163,15 +163,15 @@ typedef char bool;
 //**********************************************************************/
 
 /* Timebase sub-module */
-void EHRPWMTimebaseClkConfig(unsigned int baseAddr, unsigned int tbClk, 
+void EHRPWMTimebaseClkConfig(unsigned int baseAddr, unsigned int tbClk,
 		unsigned int moduleClk);
 void EHRPWMPWMOpFreqSet(unsigned int baseAddr, unsigned int tbClk,
-		unsigned int pwmFreq,unsigned int counterDir, 
+		unsigned int pwmFreq,unsigned int counterDir,
 		bool enableShadowWrite);
 void EHRPWMTBEmulationModeSet(unsigned int baseAddr, unsigned int mode);
 void EHRPWMTimebaseSyncEnable(unsigned int baseAddr, unsigned int tbPhsValue,
 	       	unsigned int phsCountDir);
-void EHRPWMTimebaseSyncDisable(unsigned int baseAddr); 
+void EHRPWMTimebaseSyncDisable(unsigned int baseAddr);
 void EHRPWMTriggerSWSync(unsigned int baseAddr);
 void EHRPWMSyncOutModeSet(unsigned int baseAddr, unsigned int syncOutMode);
 void EHRPWMWriteTBCount(unsigned int baseAddr, unsigned int tbCount);
@@ -182,7 +182,7 @@ void EHRPWMTBClearStatus(unsigned int baseAddr, unsigned int tbStatusMask);
 
 /* Counter compare sub-module */
 bool EHRPWMLoadCMPA(unsigned int baseAddr, unsigned int CMPAVal,
-		bool enableShadowWrite, unsigned int ShadowToActiveLoadTrigger, 
+		bool enableShadowWrite, unsigned int ShadowToActiveLoadTrigger,
 		bool OverwriteShadowFull);
 
 bool EHRPWMLoadCMPB(unsigned int baseAddr, unsigned int CMPBVal,
@@ -190,19 +190,19 @@ bool EHRPWMLoadCMPB(unsigned int baseAddr, unsigned int CMPBVal,
 		bool OverwriteShadowFull);
 
 /* Action Qualifier sub-module */
-void EHRPWMConfigureAQActionOnA(unsigned int baseAddr, unsigned int zero, 
+void EHRPWMConfigureAQActionOnA(unsigned int baseAddr, unsigned int zero,
 		unsigned int period,
 		unsigned int CAUp,  unsigned int CADown,  unsigned int CBUp,
 		unsigned int CBDown, unsigned int SWForced);
-void EHRPWMConfigureAQActionOnB(unsigned int baseAddr, unsigned int zero, 
+void EHRPWMConfigureAQActionOnB(unsigned int baseAddr, unsigned int zero,
 		unsigned int period,
 		unsigned int CAUp,  unsigned int CADown,  unsigned int CBUp,
 		unsigned int CBDown, unsigned int SWForced);
 void EHRPWMSWForceA(unsigned int baseAddr);
 void EHRPWMSWForceB(unsigned int baseAddr);
-void EHRPWMAQContSWForceOnA(unsigned int baseAddr, unsigned int forceVal, 
+void EHRPWMAQContSWForceOnA(unsigned int baseAddr, unsigned int forceVal,
 		unsigned int activeRegReloadMode);
-void EHRPWMAQContSWForceOnB(unsigned int baseAddr, unsigned int forceVal, 
+void EHRPWMAQContSWForceOnB(unsigned int baseAddr, unsigned int forceVal,
 		unsigned int activeRegReloadMode);
 
 /* Dead Band Generator */
@@ -242,9 +242,9 @@ void EHRPWMETIntSWForce(unsigned int baseAddr);
 
 /* HEPWM sub-module */
 void EHRPWMLoadTBPHSHR(unsigned int baseAddr, unsigned int TBPHSHRVal);
-void EHRPWMLoadCMPAHR(unsigned int baseAddr, unsigned int CMPAHRVal, 
+void EHRPWMLoadCMPAHR(unsigned int baseAddr, unsigned int CMPAHRVal,
 		unsigned int ShadowToActiveLoadTrigger);
-void EHRPWMConfigHR(unsigned int baseAddr,unsigned int ctrlMode, 
+void EHRPWMConfigHR(unsigned int baseAddr,unsigned int ctrlMode,
 		unsigned int MEPCtrlEdge); /* also enables */
 void EHRPWMHRDisable(unsigned int baseAddr);
 
diff --git a/lib/tiam1808/tiam1808/gpio.h b/lib/tiam1808/tiam1808/gpio.h
index 5db5ab8e5..3e3627189 100644
--- a/lib/tiam1808/tiam1808/gpio.h
+++ b/lib/tiam1808/tiam1808/gpio.h
@@ -38,7 +38,7 @@
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
- 
+
 #ifndef      __GPIO_H__
 #define      __GPIO_H__
 
@@ -86,10 +86,10 @@ extern "C" {
 
 
 /*****************Bit Mask values for banks.***************************/
-/* 
+/*
 ** The following macros are used by the application while invoking
-** the function 'GPIOBankPinsWrite'. Any one or a combination of 
-** the below macros is passed as 'setPins' and 'clrPins' to 
+** the function 'GPIOBankPinsWrite'. Any one or a combination of
+** the below macros is passed as 'setPins' and 'clrPins' to
 ** 'GPIOBankPinsWrite'.
 */
 #define GPIO_BANK_PIN_0              GPIO_DIR_DIR0
@@ -112,7 +112,7 @@ extern "C" {
 
 
 /*****************************************************************************
-**                   FUNCTION DECLARATIONS                                   
+**                   FUNCTION DECLARATIONS
 *****************************************************************************/
 
 
diff --git a/lib/tiam1808/tiam1808/gpio_v2.h b/lib/tiam1808/tiam1808/gpio_v2.h
index 18873f921..61b33cd55 100644
--- a/lib/tiam1808/tiam1808/gpio_v2.h
+++ b/lib/tiam1808/tiam1808/gpio_v2.h
@@ -50,7 +50,7 @@ extern "C" {
 #endif
 
 /*****************************************************************************
-**                       MACRO DEFINITIONS                                   
+**                       MACRO DEFINITIONS
 *****************************************************************************/
 
 /* Values used to configure the direction of GPIO pins. */
@@ -99,7 +99,7 @@ extern "C" {
 
 /* Values used to configure the Gating Ratio. */
 #define GPIO_GR_FUNC_CLK_INTER_CLK_BY_1  (GPIO_CTRL_GATINGRATIO_N_1 << \
-                                          GPIO_CTRL_GATINGRATIO_SHIFT)    
+                                          GPIO_CTRL_GATINGRATIO_SHIFT)
 #define GPIO_GR_FUNC_CLK_INTER_CLK_BY_2  (GPIO_CTRL_GATINGRATIO_N_2 << \
                                           GPIO_CTRL_GATINGRATIO_SHIFT)
 #define GPIO_GR_FUNC_CLK_INTER_CLK_BY_4  (GPIO_CTRL_GATINGRATIO_N_4 << \
@@ -121,7 +121,7 @@ typedef struct gpioContext{
 
 
 /*****************************************************************************
-**                       FUNCTION PROTOTYPES                                   
+**                       FUNCTION PROTOTYPES
 *****************************************************************************/
 
 extern void GPIOModuleReset(unsigned int baseAdd);
diff --git a/lib/tiam1808/tiam1808/gpmc.h b/lib/tiam1808/tiam1808/gpmc.h
index 627c1eb72..63dc90634 100644
--- a/lib/tiam1808/tiam1808/gpmc.h
+++ b/lib/tiam1808/tiam1808/gpmc.h
@@ -57,7 +57,7 @@ extern "C" {
 /*****************************************************************************/
 /*
 ** Macros which can be used as 'mode' parameter to GPMCIdleModeSelect API.
-** 
+**
 */
 #define GPMC_IDLEMODE_FORCEIDLE                       (0)
 #define GPMC_IDLEMODE_NOIDLE                          (1)
@@ -66,7 +66,7 @@ extern "C" {
 /*****************************************************************************/
 /*
 ** Macros which can be used as 'configVal' parameter to GPMCAutoIdleConfig API.
-** 
+**
 */
 #define GPMC_AUTOIDLE_FREERUN                         (0)
 #define GPMC_AUTOIDLE_AUTORUN                         (1)
@@ -166,7 +166,7 @@ extern "C" {
 ** GPMCycle2CycleAndTurnArndTimeTimingConfig, GPMCSNANDCmdWrite,
 ** GPMCNANDAddrWrite, GPMCNANDDataWrite, GPMCNANDDataRead, GPMCPrefetchCSSelect,
 ** GPMCECCCSSelect, GPMCECCBCHResultGet APIs.
-** 
+**
 */
 #define GPMC_CHIP_SELECT_0                            (0)
 #define GPMC_CHIP_SELECT_1                            (1)
@@ -179,9 +179,9 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Macros which can be used as 'divideVal' parameter to GPMCFclkDividerSelect 
+** Macros which can be used as 'divideVal' parameter to GPMCFclkDividerSelect
 ** API.
-** 
+**
 */
 #define GPMC_FCLK_DIV_BY_1                            (0)
 #define GPMC_FCLK_DIV_BY_2                            (1)
@@ -191,7 +191,7 @@ extern "C" {
 /*****************************************************************************/
 /*
 ** Macros which can be used as 'scaleftr' parameter to
-** GPMCTimeparaGranularitySelect API. 
+** GPMCTimeparaGranularitySelect API.
 **
 */
 #define GPMC_TIMEPARAGRANULARITY_X1                   (0)
@@ -199,8 +199,8 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Macros which can be used as 'protocol' parameter to 
-** GPMCAddrDataMuxProtocolSelect API. 
+** Macros which can be used as 'protocol' parameter to
+** GPMCAddrDataMuxProtocolSelect API.
 **
 */
 #define GPMC_MUXADDDATA_NOMUX                         (0)
@@ -235,7 +235,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Macros which can be used as 'mode' parameter to GPMCWaitPinMonitoringConfig 
+** Macros which can be used as 'mode' parameter to GPMCWaitPinMonitoringConfig
 ** API.
 **
 */
@@ -305,7 +305,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Macros which can be used as 'CSExtDelayFlag' parameter to 
+** Macros which can be used as 'CSExtDelayFlag' parameter to
 ** GPMC_CS_TIMING_CONFIG macro
 */
 #define GPMC_CS_EXTRA_DELAY                           (1)
@@ -313,21 +313,21 @@ extern "C" {
 
 /*
 * \brief  This macro used to make the conf value which is used to configure the
-*         CS signal timing configuration.\n 
+*         CS signal timing configuration.\n
 *
-* \param  CSWrOffTime    CS# de-assertion time from start cycle time for write 
+* \param  CSWrOffTime    CS# de-assertion time from start cycle time for write
 *                        accesses in GPMC_FCLK cycles.
 *
-*         CSRdOffTime    CS# de-assertion time from start cycle time for read 
+*         CSRdOffTime    CS# de-assertion time from start cycle time for read
 *                        accesses in GPMC_FCLK cycles
 *
 *         CSExtDelayFlag Flag to indicate whether to add half GPMC_FCLK delay to
 *                        CS or not.
 *                        This can take one of the following values :
-*                        GPMC_CS_EXTRA_DELAY --   CS# Timing control  
-*                                                 signal is delayed of          
+*                        GPMC_CS_EXTRA_DELAY --   CS# Timing control
+*                                                 signal is delayed of
 *                                                 half GPMC_FCLK cycle.
-*                        GPMC_CS_EXTRA_NODELAY -- CS# Timing control  
+*                        GPMC_CS_EXTRA_NODELAY -- CS# Timing control
 *                                                 signal is not delayed
 *
 *         CSOnTime       CS# assertion time from start cycle time in GPMC_FCLK
@@ -351,36 +351,36 @@ extern "C" {
 
 /*
 * \brief  This macro used to make the conf value which is used to configure the
-*         ADV# signal timing configuration.\n 
+*         ADV# signal timing configuration.\n
 *
-* \param  ADVAADMuxWrOffTime    ADV# de-assertion time in GPMC_FCLK cycles for 
+* \param  ADVAADMuxWrOffTime    ADV# de-assertion time in GPMC_FCLK cycles for
 *                               first address phase when using the AAD-Mux
 *                               prorocol.
 *
-*         ADVAADMuxRdOffTime    ADV# de-assertion time in GPMC_FCLK cycles for 
+*         ADVAADMuxRdOffTime    ADV# de-assertion time in GPMC_FCLK cycles for
 *                               first address phase when using the AAD-Mux
 *                               prorocol.
 *
-*         ADVWrOffTime          ADV# de-assertion time in GPMC_FCLK cycles from 
+*         ADVWrOffTime          ADV# de-assertion time in GPMC_FCLK cycles from
 *                               start cycle time for write accesses
 *
-*         ADVRdOffTime          ADV# de-assertion time in GPMC_FCLK cycles from 
+*         ADVRdOffTime          ADV# de-assertion time in GPMC_FCLK cycles from
 *                               start cycle time for write accesses
 *
-*         ADVExtDelayFlag       Flag to indicate whether to add half GPMC_FCLK 
+*         ADVExtDelayFlag       Flag to indicate whether to add half GPMC_FCLK
 *                               delay to ADV or not.
 *                               This can take one of the following values :
-*                               GPMC_ADV_EXTRA_DELAY --   ADV# Timing control  
-*                                                         signal is delayed of  
+*                               GPMC_ADV_EXTRA_DELAY --   ADV# Timing control
+*                                                         signal is delayed of
 *                                                         half GPMC_FCLK cycle.
-*                               GPMC_ADV_EXTRA_NODELAY -- ADV# Timing control  
+*                               GPMC_ADV_EXTRA_NODELAY -- ADV# Timing control
 *                                                         signal is not delayed.
 *
-*         ADVAADMuxOnTime       ADV# assertion time in GPMC_FCLK cycles for 
-*                               first address phase when using the 
-*                               AAD-Multiplexed protocol.   
+*         ADVAADMuxOnTime       ADV# assertion time in GPMC_FCLK cycles for
+*                               first address phase when using the
+*                               AAD-Multiplexed protocol.
 *
-*         ADVOnTime             ADV# assertion time from start cycle time in 
+*         ADVOnTime             ADV# assertion time from start cycle time in
 *                               GPMC_FCLK cycles.
 */
 
@@ -412,43 +412,43 @@ extern "C" {
 
 /*
 * \brief  This macro used to make the conf value which is used to configure the
-*         WE# and OE# signal timing configuration.\n 
+*         WE# and OE# signal timing configuration.\n
 *
-* \param  WEOffTime             WE# de-assertion time in GPMC_FCLK cycles from 
+* \param  WEOffTime             WE# de-assertion time in GPMC_FCLK cycles from
 *                               start cycle time.
 *
-*         WEExtDelayFlag        Flag to indicate whether to add half GPMC_FCLK 
+*         WEExtDelayFlag        Flag to indicate whether to add half GPMC_FCLK
 *                               delay to WE or not.
 *                               This can take one of the following values :
-*                               GPMC_WE_EXTRA_DELAY --   WE# Timing control  
-*                                                        signal is delayed of   
+*                               GPMC_WE_EXTRA_DELAY --   WE# Timing control
+*                                                        signal is delayed of
 *                                                        half GPMC_FCLK cycle.
-*                               GPMC_WE_EXTRA_NODELAY -- WE# Timing control  
+*                               GPMC_WE_EXTRA_NODELAY -- WE# Timing control
 *                                                        signal is not delayed
-*         WEOnTime              WE# assertion time in GPMC_FCLK cycles from 
+*         WEOnTime              WE# assertion time in GPMC_FCLK cycles from
 *                               start cycle time.
 *
-*         OEAADMuxOffTime       OE# de-assertion time in GPMC_FCLK cycles for 
+*         OEAADMuxOffTime       OE# de-assertion time in GPMC_FCLK cycles for
 *                               first address phase when using the AAD-Mux
 *                               prorocol.
 *
-*         OEOffTime             OE# de-assertion time in GPMC_FCLK cycles from 
+*         OEOffTime             OE# de-assertion time in GPMC_FCLK cycles from
 *                               start cycle time.
 *
-*         OEExtDelayFlag        Flag to indicate whether to add half GPMC_FCLK 
+*         OEExtDelayFlag        Flag to indicate whether to add half GPMC_FCLK
 *                               delay to OE or not.
 *                               This can take one of the following values :
-*                               GPMC_OE_EXTRA_DELAY --   OE# Timing control  
-*                                                        signal is delayed of   
+*                               GPMC_OE_EXTRA_DELAY --   OE# Timing control
+*                                                        signal is delayed of
 *                                                        half GPMC_FCLK cycle.
-*                               GPMC_OE_EXTRA_NODELAY -- OE# Timing control  
+*                               GPMC_OE_EXTRA_NODELAY -- OE# Timing control
 *                                                        signal is not delayed
 *
-*         OEAADMuxOnTime        OE# assertion time in GPMC_FCLK cycles for 
+*         OEAADMuxOnTime        OE# assertion time in GPMC_FCLK cycles for
 *                               first address phase when using the AAD-Mux
 *                               prorocol.
 *
-*         OEOnTime              OE# assertion time in GPMC_FCLK cycles from 
+*         OEOnTime              OE# assertion time in GPMC_FCLK cycles from
 *                               start cycle time.
 *
 */
@@ -465,7 +465,7 @@ extern "C" {
 
 /*
 * \brief  This macro used to make the conf value which is used to configure the
-*         read access and cycle time timing configuration.\n 
+*         read access and cycle time timing configuration.\n
 *
 * \param  rdCycleTime           Total read cycle time in GPMC_FCLK cycles.
 *
@@ -474,8 +474,8 @@ extern "C" {
 *         rdAccessTime          Read access time (Delay between start cycle time
 *                               and first data valid) in GPMC_FCLK cycles.
 *
-*         pageBurstAccessTime   Page burest access time (Delay between 
-*                               successive words in a multiple access)in 
+*         pageBurstAccessTime   Page burest access time (Delay between
+*                               successive words in a multiple access)in
 *                               GPMC_FCLK cycles.
 *
 */
@@ -504,31 +504,31 @@ extern "C" {
 
 /*
 * \brief  This macro used to make the conf value which is used to configure the
-*         cycle to cycle and bus turn around time timing configuration.\n 
+*         cycle to cycle and bus turn around time timing configuration.\n
 *
-* \param  cycle2CycleDelay       Cycle to cycle delay (Chip select high pulse 
-*                                delay between two successive accesses)in 
+* \param  cycle2CycleDelay       Cycle to cycle delay (Chip select high pulse
+*                                delay between two successive accesses)in
 *                                GPMC_FCLK cycles.
 *
 *      cycle2CycleDelaySameCSCfg Specified whether to add the cycle to cycle
 *                                delay between two successive accesses or not
 *                                (to the same chip-select).
 *                                This can take one of the following values :
-*                                GPMC_CYCLE2CYCLESAMECSEN_C2CDELAY   -- To add 
+*                                GPMC_CYCLE2CYCLESAMECSEN_C2CDELAY   -- To add
 *                                                                     the delay.
-*                                GPMC_CYCLE2CYCLESAMECSEN_NOC2CDELAY -- Don't 
+*                                GPMC_CYCLE2CYCLESAMECSEN_NOC2CDELAY -- Don't
 *                                                                 add the delay.
 *
 *      cycle2CycleDelayDiffCSCfg Specified whether to add the cycle to cycle
 *                                delay between two successive accesses or not
 *                                (to the diffrent chip-select).
 *                                This can take one of the following values :
-*                                GPMC_CYCLE2CYCLEDIFFCSEN_C2CDELAY   -- To add 
+*                                GPMC_CYCLE2CYCLEDIFFCSEN_C2CDELAY   -- To add
 *                                                                     the delay.
-*                                GPMC_CYCLE2CYCLEDIFFCSEN_NOC2CDELAY -- Don't 
+*                                GPMC_CYCLE2CYCLEDIFFCSEN_NOC2CDELAY -- Don't
 *                                                                 add the delay.
 *
-*         busTAtime             Bus turn aroung time between two successive 
+*         busTAtime             Bus turn aroung time between two successive
 *                               accesses to the same chip-select (read to write)
 *                               or to a diff chip-select in GPMC_FCLK cycles.
 *
@@ -599,7 +599,7 @@ extern "C" {
 /*****************************************************************************/
 /*
 ** Macros which can be used as 'configVal' GPMCPrefetchAccessCycleOptConfig API.
-** 
+**
 */
 #define GPMC_PREFETCH_OPTIMIZED_ACCESS_ENABLE         (1)
 #define GPMC_PREFETCH_OPTIMIZED_ACCESS_DISABLE        (0)
@@ -615,7 +615,7 @@ extern "C" {
 /*****************************************************************************/
 /*
 ** Macros which can be used as 'algo' parameter to GPMCECCAlgoSelect API.
-** 
+**
 */
 #define GPMC_ECC_ALGORITHM_HAMMINGCODE                (0)
 #define GPMC_ECC_ALGORITHM_BCH                        (1)
diff --git a/lib/tiam1808/tiam1808/hs_mmcsd.h b/lib/tiam1808/tiam1808/hs_mmcsd.h
index b0e6d287a..689f721cd 100644
--- a/lib/tiam1808/tiam1808/hs_mmcsd.h
+++ b/lib/tiam1808/tiam1808/hs_mmcsd.h
@@ -146,12 +146,12 @@ extern "C" {
 ** Macros that can be used for checking the present state of the host controller
 */
 #define HS_MMCSD_CARD_WRITEPROT        (MMCHS_PSTATE_WP)
-#define HS_MMCSD_CARD_INSERTED         (MMCHS_PSTATE_CINS)        
-#define HS_MMCSD_CARD_STABLE           (MMCHS_PSTATE_CSS)        
-#define HS_MMCSD_BUFFER_READABLE       (MMCHS_PSTATE_BRE)        
-#define HS_MMCSD_BUFFER_WRITEABLE      (MMCHS_PSTATE_BWE)        
-#define HS_MMCSD_READ_INPROGRESS       (MMCHS_PSTATE_RTA)        
-#define HS_MMCSD_WRITE_INPROGRESS      (MMCHS_PSTATE_WTA)        
+#define HS_MMCSD_CARD_INSERTED         (MMCHS_PSTATE_CINS)
+#define HS_MMCSD_CARD_STABLE           (MMCHS_PSTATE_CSS)
+#define HS_MMCSD_BUFFER_READABLE       (MMCHS_PSTATE_BRE)
+#define HS_MMCSD_BUFFER_WRITEABLE      (MMCHS_PSTATE_BWE)
+#define HS_MMCSD_READ_INPROGRESS       (MMCHS_PSTATE_RTA)
+#define HS_MMCSD_WRITE_INPROGRESS      (MMCHS_PSTATE_WTA)
 
 /*
 ** Macros that can be used for configuring the power and transfer parameters
@@ -195,9 +195,9 @@ extern "C" {
 #define HS_MMCSD_INTR_CMDBITERR         (MMCHS_IE_CEB_ENABLE)
 #define HS_MMCSD_INTR_CMDCRCERR         (MMCHS_IE_CCRC_ENABLE)
 #define HS_MMCSD_INTR_CMDTIMEOUT        (MMCHS_IE_CTO_ENABLE)
-#define HS_MMCSD_INTR_CARDINS           (MMCHS_IE_CINS_ENABLE)                    
-#define HS_MMCSD_INTR_BUFRDRDY          (MMCHS_IE_BRR_ENABLE)                    
-#define HS_MMCSD_INTR_BUFWRRDY          (MMCHS_IE_BWR_ENABLE)                    
+#define HS_MMCSD_INTR_CARDINS           (MMCHS_IE_CINS_ENABLE)
+#define HS_MMCSD_INTR_BUFRDRDY          (MMCHS_IE_BRR_ENABLE)
+#define HS_MMCSD_INTR_BUFWRRDY          (MMCHS_IE_BWR_ENABLE)
 #define HS_MMCSD_INTR_TRNFCOMP          (MMCHS_IE_TC_ENABLE)
 #define HS_MMCSD_INTR_CMDCOMP           (MMCHS_IE_CC_ENABLE)
 
@@ -213,9 +213,9 @@ extern "C" {
 #define HS_MMCSD_STAT_CMDBITERR         (MMCHS_STAT_CEB)
 #define HS_MMCSD_STAT_CMDCRCERR         (MMCHS_STAT_CCRC)
 #define HS_MMCSD_STAT_CMDTIMEOUT        (MMCHS_STAT_CTO)
-#define HS_MMCSD_STAT_CARDINS           (MMCHS_STAT_CINS)                    
-#define HS_MMCSD_STAT_BUFRDRDY          (MMCHS_STAT_BRR)                    
-#define HS_MMCSD_STAT_BUFWRRDY          (MMCHS_STAT_BWR)                    
+#define HS_MMCSD_STAT_CARDINS           (MMCHS_STAT_CINS)
+#define HS_MMCSD_STAT_BUFRDRDY          (MMCHS_STAT_BRR)
+#define HS_MMCSD_STAT_BUFWRRDY          (MMCHS_STAT_BWR)
 #define HS_MMCSD_STAT_TRNFCOMP          (MMCHS_STAT_TC)
 #define HS_MMCSD_STAT_CMDCOMP           (MMCHS_STAT_CC)
 
@@ -230,9 +230,9 @@ extern "C" {
 #define HS_MMCSD_SIGEN_CMDBITERR        (MMCHS_ISE_CEB_SIGEN)
 #define HS_MMCSD_SIGEN_CMDCRCERR        (MMCHS_ISE_CCRC_SIGEN)
 #define HS_MMCSD_SIGEN_CMDTIMEOUT       (MMCHS_ISE_CTO_SIGEN)
-#define HS_MMCSD_SIGEN_CARDINS          (MMCHS_ISE_CINS_SIGEN)                    
-#define HS_MMCSD_SIGEN_BUFRDRDY         (MMCHS_ISE_BRR_SIGEN)                    
-#define HS_MMCSD_SIGEN_BUFWRRDY         (MMCHS_ISE_BWR_SIGEN)                    
+#define HS_MMCSD_SIGEN_CARDINS          (MMCHS_ISE_CINS_SIGEN)
+#define HS_MMCSD_SIGEN_BUFRDRDY         (MMCHS_ISE_BRR_SIGEN)
+#define HS_MMCSD_SIGEN_BUFWRRDY         (MMCHS_ISE_BWR_SIGEN)
 #define HS_MMCSD_SIGEN_TRNFCOMP         (MMCHS_ISE_TC_SIGEN)
 #define HS_MMCSD_SIGEN_CMDCOMP          (MMCHS_ISE_CC_SIGEN)
 
diff --git a/lib/tiam1808/tiam1808/hsi2c.h b/lib/tiam1808/tiam1808/hsi2c.h
index 3f9431e91..3b4bf2208 100644
--- a/lib/tiam1808/tiam1808/hsi2c.h
+++ b/lib/tiam1808/tiam1808/hsi2c.h
@@ -57,9 +57,9 @@ extern "C" {
 #define     I2C_CFG_MST_TX              I2C_CON_TRX | I2C_CON_MST
 #define     I2C_CFG_MST_RX              I2C_CON_MST
 #define     I2C_CFG_STOP                I2C_CON_STP
-#define     I2C_CFG_N0RMAL_MODE         (0 << I2C_CON_STB_SHIFT) 
+#define     I2C_CFG_N0RMAL_MODE         (0 << I2C_CON_STB_SHIFT)
 #define     I2C_CFG_SRT_BYTE_MODE       I2C_CON_STB
-#define     I2C_CFG_7BIT_SLAVE_ADDR     (0 << I2C_CON_XSA_SHIFT) 
+#define     I2C_CFG_7BIT_SLAVE_ADDR     (0 << I2C_CON_XSA_SHIFT)
 #define     I2C_CFG_10BIT_SLAVE_ADDR    I2C_CON_XSA
 #define     I2C_CFG_10BIT_OWN_ADDR_0    I2C_CON_XOA0
 #define     I2C_CFG_10BIT_OWN_ADDR_1    I2C_CON_XOA1
@@ -89,11 +89,11 @@ extern "C" {
 #define     I2C_INT_TRANSMIT_UNDER_FLOW  I2C_IRQSTATUS_XUDF
 #define     I2C_INT_RECV_OVER_RUN        I2C_IRQSTATUS_ROVR
 #define     I2C_INT_RECV_DRAIN           I2C_IRQSTATUS_RDR
-#define     I2C_INT_TRANSMIT_DRAIN       I2C_IRQSTATUS_XDR   
+#define     I2C_INT_TRANSMIT_DRAIN       I2C_IRQSTATUS_XDR
 
 /****************************************************************************/
 /*
-** Values that can be passed to I2CFIFOThersholdConfig/I2CFIFOClear API as 
+** Values that can be passed to I2CFIFOThersholdConfig/I2CFIFOClear API as
 ** flag to select recieve or transmit mode.
 */
 #define     I2C_TX_MODE                  1
@@ -126,10 +126,10 @@ extern "C" {
 ** any one of the idle mode of operation.
 */
 
-#define     I2C_FORCE_IDLE_MODE          (0 << I2C_SYSC_IDLEMODE_SHIFT)   
-#define     I2C_NO_IDLE_MODE             (1 << I2C_SYSC_IDLEMODE_SHIFT)   
-#define     I2C_SMART_IDLE_MODE          (2 << I2C_SYSC_IDLEMODE_SHIFT)   
-#define     I2C_SMART_IDLE_WAKEUP_MODE   (3 << I2C_SYSC_IDLEMODE_SHIFT)   
+#define     I2C_FORCE_IDLE_MODE          (0 << I2C_SYSC_IDLEMODE_SHIFT)
+#define     I2C_NO_IDLE_MODE             (1 << I2C_SYSC_IDLEMODE_SHIFT)
+#define     I2C_SMART_IDLE_MODE          (2 << I2C_SYSC_IDLEMODE_SHIFT)
+#define     I2C_SMART_IDLE_WAKEUP_MODE   (3 << I2C_SYSC_IDLEMODE_SHIFT)
 
 /****************************************************************************/
 /*
@@ -137,10 +137,10 @@ extern "C" {
 ** the type of activity
 */
 
-#define     I2C_CUT_OFF_BOTH_CLK         (0 << I2C_SYSC_CLKACTIVITY_SHIFT)   
-#define     I2C_CUT_OFF_SYS_CLK          (1 << I2C_SYSC_CLKACTIVITY_SHIFT)   
-#define     I2C_CUT_OFF_OCP_CLK          (2 << I2C_SYSC_CLKACTIVITY_SHIFT)   
-#define     I2C_KEEP_ALIVE_BOTH_CLK      (3 << I2C_SYSC_CLKACTIVITY_SHIFT)   
+#define     I2C_CUT_OFF_BOTH_CLK         (0 << I2C_SYSC_CLKACTIVITY_SHIFT)
+#define     I2C_CUT_OFF_SYS_CLK          (1 << I2C_SYSC_CLKACTIVITY_SHIFT)
+#define     I2C_CUT_OFF_OCP_CLK          (2 << I2C_SYSC_CLKACTIVITY_SHIFT)
+#define     I2C_KEEP_ALIVE_BOTH_CLK      (3 << I2C_SYSC_CLKACTIVITY_SHIFT)
 
 /****************************************************************************/
 /*
@@ -170,7 +170,7 @@ extern "C" {
 #define     I2C_WAKE_UP_IRQ               1
 #define     I2C_WAKE_UP_DMA_RECV          2
 #define     I2C_WAKE_UP_DMA_TRANSMIT      3
-  
+
 /****************************************************************************/
 /*
 ** Values that can be passed to I2CMasterIntStatus/I2CSlaveIntStatus
diff --git a/lib/tiam1808/tiam1808/hw/hw_cm_cefuse.h b/lib/tiam1808/tiam1808/hw/hw_cm_cefuse.h
index e17fcc392..5442e2a55 100644
--- a/lib/tiam1808/tiam1808/hw/hw_cm_cefuse.h
+++ b/lib/tiam1808/tiam1808/hw/hw_cm_cefuse.h
@@ -69,7 +69,7 @@
 #define CM_CEFUSE_CLKSTCTRL   (0x0)
 #define CM_CEFUSE_CEFUSE_CLKCTRL   (0x20)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_cm_device.h b/lib/tiam1808/tiam1808/hw/hw_cm_device.h
index 7dd936a54..1a5419336 100644
--- a/lib/tiam1808/tiam1808/hw/hw_cm_device.h
+++ b/lib/tiam1808/tiam1808/hw/hw_cm_device.h
@@ -68,7 +68,7 @@
 
 #define CM_DEVICE_CM_CLKOUT_CTRL   (0x0)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_cm_dpll.h b/lib/tiam1808/tiam1808/hw/hw_cm_dpll.h
index 48dd73e18..0d3a129dd 100644
--- a/lib/tiam1808/tiam1808/hw/hw_cm_dpll.h
+++ b/lib/tiam1808/tiam1808/hw/hw_cm_dpll.h
@@ -81,7 +81,7 @@
 #define CM_DPLL_CLKSEL_WDT1_CLK   (0x38)
 #define CM_DPLL_CLKSEL_GPIO0_DBCLK   (0x3c)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_cm_gfx.h b/lib/tiam1808/tiam1808/hw/hw_cm_gfx.h
index 0f9ea6689..8004aa1f8 100644
--- a/lib/tiam1808/tiam1808/hw/hw_cm_gfx.h
+++ b/lib/tiam1808/tiam1808/hw/hw_cm_gfx.h
@@ -71,7 +71,7 @@
 #define CM_GFX_BITBLT_CLKCTRL   (0x8)
 #define CM_GFX_L4LS_GFX_CLKSTCTRL   (0xc)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_cm_mpu.h b/lib/tiam1808/tiam1808/hw/hw_cm_mpu.h
index 5b0f1cfac..8588823a3 100644
--- a/lib/tiam1808/tiam1808/hw/hw_cm_mpu.h
+++ b/lib/tiam1808/tiam1808/hw/hw_cm_mpu.h
@@ -69,7 +69,7 @@
 #define CM_MPU_CLKSTCTRL   (0x0)
 #define CM_MPU_MPU_CLKCTRL   (0x4)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_cm_per.h b/lib/tiam1808/tiam1808/hw/hw_cm_per.h
index 9a3979781..3e9e1025d 100644
--- a/lib/tiam1808/tiam1808/hw/hw_cm_per.h
+++ b/lib/tiam1808/tiam1808/hw/hw_cm_per.h
@@ -136,7 +136,7 @@
 #define CM_PER_CLKDIV32K_CLKCTRL   (0x14c)
 #define CM_PER_CLK_24MHZ_CLKSTCTRL   (0x150)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_cm_rtc.h b/lib/tiam1808/tiam1808/hw/hw_cm_rtc.h
index d543b6283..0aa313934 100644
--- a/lib/tiam1808/tiam1808/hw/hw_cm_rtc.h
+++ b/lib/tiam1808/tiam1808/hw/hw_cm_rtc.h
@@ -69,7 +69,7 @@
 #define CM_RTC_RTC_CLKCTRL   (0x0)
 #define CM_RTC_CLKSTCTRL   (0x4)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_cm_wkup.h b/lib/tiam1808/tiam1808/hw/hw_cm_wkup.h
index 7fe4f0192..acd27042b 100644
--- a/lib/tiam1808/tiam1808/hw/hw_cm_wkup.h
+++ b/lib/tiam1808/tiam1808/hw/hw_cm_wkup.h
@@ -122,7 +122,7 @@
 #define CM_WKUP_WDT1_CLKCTRL   (0xd4)
 #define CM_WKUP_CM_DIV_M6_DPLL_CORE   (0xd8)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_ddr2_mddr.h b/lib/tiam1808/tiam1808/hw/hw_ddr2_mddr.h
index 495f97072..5cc57dcfe 100644
--- a/lib/tiam1808/tiam1808/hw/hw_ddr2_mddr.h
+++ b/lib/tiam1808/tiam1808/hw/hw_ddr2_mddr.h
@@ -89,8 +89,8 @@ extern "C" {
 #define DDR2_MDDR_SDCR_DDR2TERM1_SHIFT  (0x0000001Bu)
 /*----DDR2TERM1 Tokens----*/
 /* Tokens shown below should be used in conjunction with tokens for DDR2TERM0 to
- * generate the required temination resistor settings.                          
- * For example: 
+ * generate the required temination resistor settings.
+ * For example:
  * To disable termination the required value is 00 (binary), which would
  * require DDR2TERM0 to be 0 and DDR2TERM1 to be 0. This could be generated as
  * shown below:
@@ -107,10 +107,10 @@ extern "C" {
 #define DDR2_MDDR_SDCR_DDRDRIVE1_SHIFT  (0x00000018u)
 /*----DDRDRIVE1 Tokens----*/
 /* Tokens shown below should be used in conjunction with tokens for DDRDRIVE1 to
- * generate the required temination resistor settings.                          
- * For example: 
+ * generate the required temination resistor settings.
+ * For example:
  * For the case of weak driver streangth for DDR2 or 1/2 driver strength for mDDR
- * setting the required value is 01 (binary), which would require DDRDRIVE0 to 
+ * setting the required value is 01 (binary), which would require DDRDRIVE0 to
  * be 1 and DDRDRIVE1 to be 0. This could be generated as shown below:
  * ((DDR2_MDDR_SDCR_DDRDRIVE0_SET | DDR2_MDDR_SDCR_DDRDRIVE0_SHIFT) |
  *  (DDR2_MDDR_SDCR_DDRDRIVE1_CLEAR | DDR2_MDDR_SDCR_DDRDRIVE1_SHIFT))
@@ -125,8 +125,8 @@ extern "C" {
 #define DDR2_MDDR_SDCR_DDR2TERM0_SHIFT  (0x00000015u)
 /*----DDR2TERM0 Tokens----*/
 /* Tokens shown below should be used in conjunction with tokens for DDR2TERM1 to
- * generate the required temination resistor settings.                          
- * For example: 
+ * generate the required temination resistor settings.
+ * For example:
  * For disable termination the required value is 00 (binary), which would
  * require DDR2TERM0 to be 0 and DDR2TERM1 to be 0. This could be generated as
  * shown below:
@@ -144,10 +144,10 @@ extern "C" {
 #define DDR2_MDDR_SDCR_DDRDRIVE0_SHIFT  (0x00000012u)
 /*----DDRDRIVE0 Tokens----*/
 /* Tokens shown below should be used in conjunction with tokens for DDRDRIVE0 to
- * generate the required temination resistor settings.                          
- * For example: 
+ * generate the required temination resistor settings.
+ * For example:
  * For the case of weak driver streangth for DDR2 or 1/2 driver strength for mDDR
- * setting the required value is 01 (binary), which would require DDRDRIVE0 to 
+ * setting the required value is 01 (binary), which would require DDRDRIVE0 to
  * be 1 and DDRDRIVE1 to be 0. This could be generated as shown below:
  * ((DDR2_MDDR_SDCR_DDRDRIVE0_SET | DDR2_MDDR_SDCR_DDRDRIVE0_SHIFT) |
  *  (DDR2_MDDR_SDCR_DDRDRIVE1_CLEAR | DDR2_MDDR_SDCR_DDRDRIVE1_SHIFT))
diff --git a/lib/tiam1808/tiam1808/hw/hw_dmtimer.h b/lib/tiam1808/tiam1808/hw/hw_dmtimer.h
index ef00472f7..15b15a5d7 100644
--- a/lib/tiam1808/tiam1808/hw/hw_dmtimer.h
+++ b/lib/tiam1808/tiam1808/hw/hw_dmtimer.h
@@ -87,7 +87,7 @@ extern "C" {
 #define DMTIMER_TCAR(n)   (0x50 + (((n) - 1) * 8))
 #define DMTIMER_TSICR   (0x54)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_ehrpwm.h b/lib/tiam1808/tiam1808/hw/hw_ehrpwm.h
index e6965258b..bf60c00ee 100644
--- a/lib/tiam1808/tiam1808/hw/hw_ehrpwm.h
+++ b/lib/tiam1808/tiam1808/hw/hw_ehrpwm.h
@@ -82,7 +82,7 @@ extern "C" {
 
 /*
 ** The macro defined below corresponds to HRCTL register of EHRPWM module.
-** This definition is used to keep compatibility with the driver(EHRPWM DAL). 
+** This definition is used to keep compatibility with the driver(EHRPWM DAL).
 */
 #if defined(am335x) || defined(am335x_15x15) || defined(c6a811x) || \
     defined(am386x) || defined(c6741x)
diff --git a/lib/tiam1808/tiam1808/hw/hw_emif4d.h b/lib/tiam1808/tiam1808/hw/hw_emif4d.h
index 6fff8e42a..bc7662edd 100644
--- a/lib/tiam1808/tiam1808/hw/hw_emif4d.h
+++ b/lib/tiam1808/tiam1808/hw/hw_emif4d.h
@@ -113,7 +113,7 @@ extern "C" {
 #define EMIF_DDR_PHY_CTRL_1_SHDW  (0xE8)
 #define EMIF_DDR_PHY_CTRL_2   (0xEC)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_emifb.h b/lib/tiam1808/tiam1808/hw/hw_emifb.h
index 91b93ff1f..cf0f350a9 100644
--- a/lib/tiam1808/tiam1808/hw/hw_emifb.h
+++ b/lib/tiam1808/tiam1808/hw/hw_emifb.h
@@ -47,7 +47,7 @@
 extern "C" {
 #endif
 
-#define EMIFB_REVID		(0x0)	
+#define EMIFB_REVID		(0x0)
 #define EMIFB_SDCFG		(0x4)
 #define EMIFB_SDRFC		(0x8)
 #define EMIFB_SDTIM1		(0xC)
diff --git a/lib/tiam1808/tiam1808/hw/hw_gpmc.h b/lib/tiam1808/tiam1808/hw/hw_gpmc.h
index 88c02ea5b..0cb1c28c5 100644
--- a/lib/tiam1808/tiam1808/hw/hw_gpmc.h
+++ b/lib/tiam1808/tiam1808/hw/hw_gpmc.h
@@ -119,7 +119,7 @@ extern "C" {
 #define GPMC_BCH_RESULT5(n)   (0x304 + (n * (0x10)))
 #define GPMC_BCH_RESULT6(n)   (0x308 + (n * (0x10)))
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_hs_mmcsd.h b/lib/tiam1808/tiam1808/hw/hw_hs_mmcsd.h
index 707a0d877..41822c0c8 100644
--- a/lib/tiam1808/tiam1808/hw/hw_hs_mmcsd.h
+++ b/lib/tiam1808/tiam1808/hw/hw_hs_mmcsd.h
@@ -99,7 +99,7 @@ extern "C" {
 #define MMCHS_ADMASAL   (0x258)
 #define MMCHS_REV   (0x2FC)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_hsi2c.h b/lib/tiam1808/tiam1808/hw/hw_hsi2c.h
index 737d3ea5b..ddbbee7b7 100644
--- a/lib/tiam1808/tiam1808/hw/hw_hsi2c.h
+++ b/lib/tiam1808/tiam1808/hw/hw_hsi2c.h
@@ -101,7 +101,7 @@ extern "C" {
 #define I2C_ACTOA   (0xD0)
 #define I2C_SBLOCK   (0xD4)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_mcspi.h b/lib/tiam1808/tiam1808/hw/hw_mcspi.h
index 4b58670ea..634595497 100644
--- a/lib/tiam1808/tiam1808/hw/hw_mcspi.h
+++ b/lib/tiam1808/tiam1808/hw/hw_mcspi.h
@@ -88,7 +88,7 @@ extern "C" {
 #define MCSPI_RX(n)   (0x13C + (n * 0x14))
 #define MCSPI_XFERLEVEL   (0x17C)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_prm_cefuse.h b/lib/tiam1808/tiam1808/hw/hw_prm_cefuse.h
index 9f22cbc73..4343277be 100644
--- a/lib/tiam1808/tiam1808/hw/hw_prm_cefuse.h
+++ b/lib/tiam1808/tiam1808/hw/hw_prm_cefuse.h
@@ -69,7 +69,7 @@
 #define PRM_CEFUSE_PM_CEFUSE_PWRSTCTRL   (0x0)
 #define PRM_CEFUSE_PM_CEFUSE_PWRSTST   (0x4)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_prm_device.h b/lib/tiam1808/tiam1808/hw/hw_prm_device.h
index 2d8843635..55dfdada7 100644
--- a/lib/tiam1808/tiam1808/hw/hw_prm_device.h
+++ b/lib/tiam1808/tiam1808/hw/hw_prm_device.h
@@ -75,7 +75,7 @@
 #define PRM_DEVICE_PRM_LDO_SRAM_MPU_SETUP   (0x18)
 #define PRM_DEVICE_PRM_LDO_SRAM_MPU_CTRL   (0x1c)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_prm_gfx.h b/lib/tiam1808/tiam1808/hw/hw_prm_gfx.h
index d90994170..fe243d3a5 100644
--- a/lib/tiam1808/tiam1808/hw/hw_prm_gfx.h
+++ b/lib/tiam1808/tiam1808/hw/hw_prm_gfx.h
@@ -71,7 +71,7 @@
 #define PRM_GFX_PM_GFX_PWRSTST   (0x10)
 #define PRM_GFX_RM_GFX_RSTST   (0x14)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_prm_mpu.h b/lib/tiam1808/tiam1808/hw/hw_prm_mpu.h
index 71be213f2..2fdb53ae0 100644
--- a/lib/tiam1808/tiam1808/hw/hw_prm_mpu.h
+++ b/lib/tiam1808/tiam1808/hw/hw_prm_mpu.h
@@ -70,7 +70,7 @@
 #define PRM_MPU_PM_MPU_PWRSTST   (0x4)
 #define PRM_MPU_RM_MPU_RSTST   (0x8)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_prm_per.h b/lib/tiam1808/tiam1808/hw/hw_prm_per.h
index d2ba0bb9a..981192d68 100644
--- a/lib/tiam1808/tiam1808/hw/hw_prm_per.h
+++ b/lib/tiam1808/tiam1808/hw/hw_prm_per.h
@@ -71,7 +71,7 @@
 #define PRM_PER_PM_PER_PWRSTST   (0x8)
 #define PRM_PER_PM_PER_PWRSTCTRL   (0xc)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_prm_rtc.h b/lib/tiam1808/tiam1808/hw/hw_prm_rtc.h
index 3e97b2adf..7002c8103 100644
--- a/lib/tiam1808/tiam1808/hw/hw_prm_rtc.h
+++ b/lib/tiam1808/tiam1808/hw/hw_prm_rtc.h
@@ -69,7 +69,7 @@
 #define PRM_RTC_PM_RTC_PWRSTCTRL   (0x0)
 #define PRM_RTC_PM_RTC_PWRSTST   (0x4)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_prm_wkup.h b/lib/tiam1808/tiam1808/hw/hw_prm_wkup.h
index ea60227eb..93008bef8 100644
--- a/lib/tiam1808/tiam1808/hw/hw_prm_wkup.h
+++ b/lib/tiam1808/tiam1808/hw/hw_prm_wkup.h
@@ -71,7 +71,7 @@
 #define PRM_WKUP_PM_WKUP_PWRSTST   (0x8)
 #define PRM_WKUP_RM_WKUP_RSTST   (0xc)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_pwmss.h b/lib/tiam1808/tiam1808/hw/hw_pwmss.h
index 2a3c5e1a4..b275a681a 100644
--- a/lib/tiam1808/tiam1808/hw/hw_pwmss.h
+++ b/lib/tiam1808/tiam1808/hw/hw_pwmss.h
@@ -52,7 +52,7 @@
 
 #define PWMSS_EHRPWM_CLK_EN_ACK_SHIFT    0x08
 
-#define PWMSS_EHRPWM_CLK_STOP_ACK_SHIFT  0x09  
+#define PWMSS_EHRPWM_CLK_STOP_ACK_SHIFT  0x09
 
 #define PWMSS_ECAP_CLK_EN_ACK            0x01
 
@@ -63,4 +63,4 @@
 #define PWMSS_EHRPWM_CLK_STOP_ACK        0x200
 
 
-#endif 
+#endif
diff --git a/lib/tiam1808/tiam1808/hw/hw_tsc_adc_ss.h b/lib/tiam1808/tiam1808/hw/hw_tsc_adc_ss.h
index 3fecff431..9207b00ed 100644
--- a/lib/tiam1808/tiam1808/hw/hw_tsc_adc_ss.h
+++ b/lib/tiam1808/tiam1808/hw/hw_tsc_adc_ss.h
@@ -96,7 +96,7 @@ extern "C" {
 #define TSC_ADC_SS_DMAREQ(n)   (0xec + (n * 0xc))
 #define TSC_ADC_SS_FIFODATA(n)   (0x100 + (n * 0x100))
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/hw/hw_usb.h b/lib/tiam1808/tiam1808/hw/hw_usb.h
index 12982b6e9..be8a69fb7 100644
--- a/lib/tiam1808/tiam1808/hw/hw_usb.h
+++ b/lib/tiam1808/tiam1808/hw/hw_usb.h
@@ -63,7 +63,7 @@
 #include "hw_psc_C6748.h"
 #include "hw_usbphyGS60.h"
 #include "hw_usbOtg_C6748.h"
-#elif defined(am335x) || defined(am335x_13x13) || defined(am335x_15x15) 
+#elif defined(am335x) || defined(am335x_13x13) || defined(am335x_15x15)
 #include "soc_AM335x.h"
 #include "hw_usbphyGS70.h"
 #include "hw_usbOtg_AM335x.h"
diff --git a/lib/tiam1808/tiam1808/hw/hw_usbOtg_AM1808.h b/lib/tiam1808/tiam1808/hw/hw_usbOtg_AM1808.h
index 7d1ec4107..3aa2e85c1 100644
--- a/lib/tiam1808/tiam1808/hw/hw_usbOtg_AM1808.h
+++ b/lib/tiam1808/tiam1808/hw/hw_usbOtg_AM1808.h
@@ -60,7 +60,7 @@ extern "C"
 #define USB_0_CTRL	            	0x04
 #define USB_0_STAT	            	0x08
 #define USB_0_EMULATION				0x08
-#define USB_0_MODE					0x10    
+#define USB_0_MODE					0x10
 #define USB_0_AUTOREQ 	        	0x14
 #define USB_0_SRP_FIX_TIME 	    	0x18
 #define USB_0_TEARDOWN 	        	0x1c
diff --git a/lib/tiam1808/tiam1808/hw/hw_usbphyGS60.h b/lib/tiam1808/tiam1808/hw/hw_usbphyGS60.h
index 22b25549b..b699ccd37 100644
--- a/lib/tiam1808/tiam1808/hw/hw_usbphyGS60.h
+++ b/lib/tiam1808/tiam1808/hw/hw_usbphyGS60.h
@@ -58,7 +58,7 @@ extern "C"
 /******************************************************************************
 **                      PHY REGISTER ADDRESS
 *******************************************************************************/
-#define CFGCHIP2_USBPHYCTRL 	SOC_USB_0_PHY_REGS	
+#define CFGCHIP2_USBPHYCTRL 	SOC_USB_0_PHY_REGS
 
 
 /******************************************************************************
diff --git a/lib/tiam1808/tiam1808/hw/hw_watchdog.h b/lib/tiam1808/tiam1808/hw/hw_watchdog.h
index df3d2f1d4..6bc5f3c53 100644
--- a/lib/tiam1808/tiam1808/hw/hw_watchdog.h
+++ b/lib/tiam1808/tiam1808/hw/hw_watchdog.h
@@ -88,7 +88,7 @@ extern "C" {
 #define WDT_WIRQENSET   (0x5C)
 #define WDT_WIRQENCLR   (0x60)
 
-/**************************************************************************\ 
+/**************************************************************************\
  * Field Definition Macros
 \**************************************************************************/
 
diff --git a/lib/tiam1808/tiam1808/i2c.h b/lib/tiam1808/tiam1808/i2c.h
index 6af00c088..68461ab33 100644
--- a/lib/tiam1808/tiam1808/i2c.h
+++ b/lib/tiam1808/tiam1808/i2c.h
@@ -51,7 +51,7 @@ extern "C" {
 
 /******************Macros to confiure I2C********************************************/
 
-#define I2C_CFG_MST_TX                  (I2C_ICMDR_MST |I2C_ICMDR_TRX) 
+#define I2C_CFG_MST_TX                  (I2C_ICMDR_MST |I2C_ICMDR_TRX)
 
 #define I2C_CFG_MST_RX                  (I2C_ICMDR_MST |(I2C_ICMDR_TRX & 0x00000000))
 
@@ -121,10 +121,10 @@ extern "C" {
 
 #define I2C_INTCODE_AAS                I2C_ICIVR_INTCODE_AAS
 
-#define I2C_INTCODE_AL                 I2C_ICIVR_INTCODE_AL 
+#define I2C_INTCODE_AL                 I2C_ICIVR_INTCODE_AL
 /**************************************************************************************/
 #define I2C_DMA_TX_ENABLE              (0x01 << I2C_ICDMAC_TXDMAEN_SHIFT)
-#define I2C_DMA_RX_ENABLE              I2C_ICDMAC_RXDMAEN      
+#define I2C_DMA_RX_ENABLE              I2C_ICDMAC_RXDMAEN
 
 /*********Prototype of driver API*****************************************************/
 
diff --git a/lib/tiam1808/tiam1808/mcasp.h b/lib/tiam1808/tiam1808/mcasp.h
index 3f49a9b29..e767c4334 100644
--- a/lib/tiam1808/tiam1808/mcasp.h
+++ b/lib/tiam1808/tiam1808/mcasp.h
@@ -53,7 +53,7 @@ extern "C" {
 ** Macros to combine to pass as formatVal to the API McASPTxFmtSet.
 ** The value formatVal is directly written to the register. So
 ** proper combination of the below macros shall be selected
-** Thus the default value is 
+** Thus the default value is
 ** (MCASP_TX_SYNC_DELAY_0BIT | MCASP_TX_BITSTREAM_LSB_FIRST |
 **  MCASP_TX_PAD_WITH_0 | MCASP_TX_SLOTSIZE_8BITS |MCASP_TX_BUF_DMAPORT
 **  MCASP_TX_ROT_RIGHT_NONE)
@@ -111,7 +111,7 @@ extern "C" {
 ** Macros to combine to pass as formatVal to the API McASPRxFmtSet.
 ** The value formatVal is directly written to the register. So
 ** proper combination of the below macros shall be selected
-** Thus the default value is 
+** Thus the default value is
 ** (MCASP_RX_SYNC_DELAY_0BIT | MCASP_RX_BITSTREAM_LSB_FIRST |
 **  MCASP_RX_PAD_WITH_0 | MCASP_RX_SLOTSIZE_8BITS |MCASP_RX_BUF_DMAPORT
 **  MCASP_RX_ROT_RIGHT_NONE)
@@ -210,7 +210,7 @@ i** Macros which can be passed as rxMode to McASPRxFmtI2SSet API.
 
 /*****************************************************************************/
 /*
-** Macros which can be passed as clkSrc to McASPTxClkCfg API and 
+** Macros which can be passed as clkSrc to McASPTxClkCfg API and
 ** McASPTxClkStart API.
 */
 #define MCASP_TX_CLK_INTERNAL                  (0x00008020u)
@@ -282,7 +282,7 @@ i** Macros which can be passed as rxMode to McASPRxFmtI2SSet API.
 
 /*****************************************************************************/
 /*
-** Macros which can be used in pinMask to the APIs 
+** Macros which can be used in pinMask to the APIs
 ** McASPPinDirOutput and SetMcASPPinDirInputSet, McASPPinMcASPSet
 ** and McASPPinGPIOSet
 */
@@ -375,7 +375,7 @@ i** Macros which can be passed as rxMode to McASPRxFmtI2SSet API.
 
 /*****************************************************************************/
 /*
-** Macros which can be passed as usrDataBits to the APIs 
+** Macros which can be passed as usrDataBits to the APIs
 ** McASPDITChanUsrDataWrite and McASPDITChanUsrDataRead.
 */
 #define MCASP_DIT_USRDATA_BITS_0_31            (0x00000000)
@@ -417,12 +417,12 @@ i** Macros which can be passed as rxMode to McASPRxFmtI2SSet API.
 
 /*****************************************************************************/
 /*
-** Macros to be used for the variable 'sectFlag' for 'McASPContextSave' 
+** Macros to be used for the variable 'sectFlag' for 'McASPContextSave'
 ** and 'McASPContextRestore'
 */
 #define McASP_CONTEXT_TX                       (0x01)
 #define McASP_CONTEXT_RX                       (0x02)
-#define McASP_CONTEXT_BOTH                     (0x03)  
+#define McASP_CONTEXT_BOTH                     (0x03)
 
 /*****************************************************************************/
 /*
@@ -479,15 +479,15 @@ extern void McASPRxClkCfg(unsigned int baseAddr, unsigned int clkSrc,
                           unsigned int mixClkDiv, unsigned int auxClkDiv);
 extern void McASPTxClkPolaritySet(unsigned int baseAddr, unsigned int polarity);
 extern void McASPRxClkPolaritySet(unsigned int baseAddr, unsigned int polarity);
-extern void McASPTxHFClkPolaritySet(unsigned int baseAddr, 
+extern void McASPTxHFClkPolaritySet(unsigned int baseAddr,
                                     unsigned int polarity);
-extern void McASPRxHFClkPolaritySet(unsigned int baseAddr, 
+extern void McASPRxHFClkPolaritySet(unsigned int baseAddr,
                                     unsigned int polarity);
 extern void McASPTxRxClkSyncEnable(unsigned int baseAddr);
 extern void McASPTxRxClkSyncDisable(unsigned int baseAddr);
 extern void McASPSerializerTxSet(unsigned int baseAddr, unsigned int serNum);
 extern void McASPSerializerRxSet(unsigned int baseAddr, unsigned int serNum);
-extern void McASPSerializerInactivate(unsigned int baseAddr, 
+extern void McASPSerializerInactivate(unsigned int baseAddr,
                                       unsigned int serNum);
 extern void McASPPinDirOutputSet(unsigned int baseAddr, unsigned int pinMask);
 extern void McASPPinDirInputSet(unsigned int baseAddr, unsigned int pinMask);
@@ -510,7 +510,7 @@ extern void McASPAMuteEnable(unsigned int baseAddr, unsigned int errFlags,
 extern void McASPAMuteDisable(unsigned int baseAddr);
 extern void McASPAMUTEINActivate(unsigned int baseAddr, unsigned int polarity);
 extern void McASPTxClkCheckConfig(unsigned int baseAddr, unsigned int clkDiv,
-                                  unsigned char boundMin, 
+                                  unsigned char boundMin,
                                   unsigned char boundMax);
 extern void McASPRxClkCheckConfig(unsigned int baseAddr, unsigned int clkDiv,
                                   unsigned char boundMin,
@@ -521,16 +521,16 @@ extern void McASPDITEnable(unsigned int baseAddr, unsigned int vBit);
 extern void McASPDITDisable(unsigned int baseAddr);
 extern void McASPDITChanStatWrite(unsigned int baseAddr,
                                   unsigned int chStatBits,
-                                  unsigned int channel, 
+                                  unsigned int channel,
                                   unsigned int data);
-extern void McASPDITChanUsrDataWrite(unsigned int baseAddr, 
+extern void McASPDITChanUsrDataWrite(unsigned int baseAddr,
                                      unsigned int chUsrDataBits,
-                                     unsigned int channel, 
+                                     unsigned int channel,
                                      unsigned int data);
 extern unsigned int McASPDITChanStatRead(unsigned int baseAddr,
                                          unsigned int chStatBits,
                                          unsigned int channel);
-extern unsigned int McASPDITChanUsrDataRead(unsigned int baseAddr, 
+extern unsigned int McASPDITChanUsrDataRead(unsigned int baseAddr,
                                             unsigned int chUsrDataBits,
                                             unsigned int channel);
 extern unsigned int McASPRxBufRead(unsigned int baseAddr, unsigned int serNum);
diff --git a/lib/tiam1808/tiam1808/mcspi.h b/lib/tiam1808/tiam1808/mcspi.h
index f4db7094e..c9203882e 100644
--- a/lib/tiam1808/tiam1808/mcspi.h
+++ b/lib/tiam1808/tiam1808/mcspi.h
@@ -50,7 +50,7 @@ extern "C" {
 #endif
 
 /****************************************************************************
-**                       MACRO DEFINITIONS 
+**                       MACRO DEFINITIONS
 ****************************************************************************/
 
 /*
@@ -66,13 +66,13 @@ extern "C" {
 */
 #define MCSPI_MAX_CH                   (4)
 /*
-** Values used for determining the granularity for McSPI clock. 
+** Values used for determining the granularity for McSPI clock.
 */
 #define MCSPI_CLK_GRAN_2_PWR_N         (0)
 #define MCSPI_CLK_GRAN_1               (1)
 
 /*
-** Values of polarity and phase of SPICLK that are used to configure the clock 
+** Values of polarity and phase of SPICLK that are used to configure the clock
 ** value in various modes of operation.
 */
 #define MCSPI_CLK_MODE_0              ((MCSPI_CH0CONF_POL_ACTIVEHIGH << \
@@ -101,12 +101,12 @@ extern "C" {
 #define MCSPI_CS_TCS_0PNT5_CLK             (MCSPI_CH0CONF_TCS0_0P5 << \
                                             MCSPI_CH0CONF_TCS0_SHIFT)
 #define MCSPI_CS_TCS_1PNT5_CLK             (MCSPI_CH0CONF_TCS0_1P5 << \
-                                            MCSPI_CH0CONF_TCS0_SHIFT) 
+                                            MCSPI_CH0CONF_TCS0_SHIFT)
 #define MCSPI_CS_TCS_2PNT5_CLK             (MCSPI_CH0CONF_TCS0_2P5 << \
                                             MCSPI_CH0CONF_TCS0_SHIFT)
 #define MCSPI_CS_TCS_3PNT5_CLK             (MCSPI_CH0CONF_TCS0_3P5 << \
                                             MCSPI_CH0CONF_TCS0_SHIFT)
-    
+
 /*
 ** Value used to set the polarity for start bit for McSPI communication.
 */
@@ -114,11 +114,11 @@ extern "C" {
 #define MCSPI_START_BIT_POL_HIGH           (MCSPI_CH0CONF_SBPOL)
 
 /*
-** Values used to configure communication on data line pins. 
+** Values used to configure communication on data line pins.
 */
 #define MCSPI_DATA_LINE_COMM_MODE_0        ((MCSPI_CH0CONF_IS_LINE0) | \
                                             (MCSPI_CH0CONF_DPE1_ENABLED) | \
-                                            (MCSPI_CH0CONF_DPE0_ENABLED)) 
+                                            (MCSPI_CH0CONF_DPE0_ENABLED))
 #define MCSPI_DATA_LINE_COMM_MODE_1        ((MCSPI_CH0CONF_IS_LINE0)| \
                                             (MCSPI_CH0CONF_DPE1_ENABLED)| \
                                             (MCSPI_CH0CONF_DPE0_DISABLED << \
@@ -126,7 +126,7 @@ extern "C" {
 #define MCSPI_DATA_LINE_COMM_MODE_2        ((MCSPI_CH0CONF_IS_LINE0) | \
                                             (MCSPI_CH0CONF_DPE1_DISABLED << \
                                              MCSPI_CH0CONF_DPE1_SHIFT) | \
-                                            (MCSPI_CH0CONF_DPE0_ENABLED)) 
+                                            (MCSPI_CH0CONF_DPE0_ENABLED))
 #define MCSPI_DATA_LINE_COMM_MODE_3        ((MCSPI_CH0CONF_IS_LINE0) | \
                                             (MCSPI_CH0CONF_DPE1_DISABLED << \
                                              MCSPI_CH0CONF_DPE1_SHIFT) | \
@@ -174,9 +174,9 @@ extern "C" {
 
 /*
 ** Values used to determine transmit/receive modes of McSPI peripheral in
-**  master or slave modes. 
+**  master or slave modes.
 */
-#define MCSPI_TX_RX_MODE                    (MCSPI_CH0CONF_TRM_TXRX) 
+#define MCSPI_TX_RX_MODE                    (MCSPI_CH0CONF_TRM_TXRX)
 #define MCSPI_RX_ONLY_MODE                  (MCSPI_CH0CONF_TRM_RXONLY << \
                                              MCSPI_CH0CONF_TRM_SHIFT)
 #define MCSPI_TX_ONLY_MODE                  (MCSPI_CH0CONF_TRM_TXONLY << \
@@ -185,7 +185,7 @@ extern "C" {
 /*
 ** Values that can be passed to enable/disable/clear status of  the various
 ** interrupts of McSPI peripheral.
-** These macros can also be used to check the status obtained from 
+** These macros can also be used to check the status obtained from
 ** 'McSPIIntStatusGet' API.
 ** 0 <= chan <= 3 \n
 */
@@ -200,7 +200,7 @@ extern "C" {
 */
 #define MCSPI_CH_STAT_RXS_FULL             (MCSPI_CH0STAT_RXS)
 #define MCSPI_CH_STAT_TXS_EMPTY            (MCSPI_CH0STAT_TXS)
-#define MCSPI_CH_STAT_EOT                  (MCSPI_CH0STAT_EOT)    
+#define MCSPI_CH_STAT_EOT                  (MCSPI_CH0STAT_EOT)
 #define MCSPI_CH_TXFFE                     (MCSPI_CH0STAT_TXFFE)
 #define MCSPI_CH_TXFFF                     (MCSPI_CH0STAT_TXFFF)
 #define MCSPI_CH_RXFFE                     (MCSPI_CH0STAT_RXFFE)
@@ -219,7 +219,7 @@ extern "C" {
                                          MCSPI_CH0CONF_SPIENSLV_SHIFT)
 
 /*
-** Values used to configure the SPIDAT[1:0] pins as input or output. 
+** Values used to configure the SPIDAT[1:0] pins as input or output.
 */
 #define MCSPI_DAT0_OUT_DAT1_IN          (MCSPI_SYST_SPIDATDIR0_OUT | \
                                          MCSPI_SYST_SPIDATDIR1)
@@ -233,7 +233,7 @@ extern "C" {
 
 /*
 ** Values used to set the word length for McSPI communication.
-** 'n' can take values only between 4 <= n <= 32. 
+** 'n' can take values only between 4 <= n <= 32.
 */
 #define MCSPI_WORD_LENGTH(n)           ((n - 1) << MCSPI_CH0CONF_WL_SHIFT)
 /*
@@ -243,24 +243,24 @@ extern "C" {
 #define MCSPI_CS_POL_LOW             (MCSPI_CH0CONF_EPOL)
 
 /*
-** Values used to enable/disable the read/write DMA events of McSPI peripheral. 
+** Values used to enable/disable the read/write DMA events of McSPI peripheral.
 */
 #define MCSPI_DMA_RX_EVENT           (MCSPI_CH0CONF_DMAR)
 #define MCSPI_DMA_TX_EVENT           (MCSPI_CH0CONF_DMAW)
 
 /*
-** Value used to enable the turbo mode of operation for McSPI peripheral. 
+** Value used to enable the turbo mode of operation for McSPI peripheral.
 */
 #define MCSPI_SET_STATUS_BIT         (MCSPI_SYST_SSB)
 
 /*
-** Value used to set the value of SPICLK in master mode of McSPI peripheral. 
+** Value used to set the value of SPICLK in master mode of McSPI peripheral.
 */
 #define MCSPI_CLK_HIGH               (MCSPI_SYST_SPICLK)
 #define MCSPI_CLK_LOW                (0x00000000)
 
 /*
-** Values used to set the instance of SPIEN used. 
+** Values used to set the instance of SPIEN used.
 */
 #define MCSPI_SPIEN_0                (MCSPI_SYST_SPIEN_0)
 #define MCSPI_SPIEN_1                (MCSPI_SYST_SPIEN_1)
@@ -268,25 +268,25 @@ extern "C" {
 #define MCSPI_SPIEN_3                (MCSPI_SYST_SPIEN_3)
 
 /*
-** Value used to enable/disable multiple word ocp access. 
+** Value used to enable/disable multiple word ocp access.
 */
 #define MCSPI_MOA_ENABLE            (MCSPI_MODULCTRL_MOA)
 #define MCSPI_MOA_DISABLE           (MCSPI_MODULCTRL_MOA_DISABLED)
 
 /*
-** Value used to enable/disable FDAA operation of McSPI peripheral. 
+** Value used to enable/disable FDAA operation of McSPI peripheral.
 */
 #define MCSPI_FDAA_DISABLE           (MCSPI_MODULCTRL_FDAA_NOSHADOWREG)
 #define MCSPI_FDAA_ENABLE            (MCSPI_MODULCTRL_FDAA)
 
 /*
-** Value used to enable/disable auto-idle mode of operation of McSPI peripheral. 
+** Value used to enable/disable auto-idle mode of operation of McSPI peripheral.
 */
 #define MCSPI_AUTO_IDLE_ENABLE       (MCSPI_SYSCONFIG_AUTOIDLE_ENABLE)
 #define MCSPI_AUTO_IDLE_DISABLE      (MCSPI_SYSCONFIG_AUTOIDLE_DISABLE)
 
 /*
-** Value used to set mode of operation  in smart idle mode of McSPI peripheral. 
+** Value used to set mode of operation  in smart idle mode of McSPI peripheral.
 */
 #define MCSPI_SIDLE_MODE_FORCE       (MCSPI_SYSCONFIG_SIDLEMODE_FORCE)
 #define MCSPI_SIDLE_MODE_NOIDLE      (MCSPI_SYSCONFIG_SIDLEMODE_NOIDLE << \
@@ -295,7 +295,7 @@ extern "C" {
                        			      MCSPI_SYSCONFIG_SIDLEMODE_SHIFT)
 
 /*
-** Value used to set clock activity of McSPI peripheral. 
+** Value used to set clock activity of McSPI peripheral.
 */
 #define MCSPI_CLK_ACTIVITY_NONE      (MCSPI_SYSCONFIG_CLOCKACTIVITY_NONE)
 #define MCSPI_CLK_ACTIVITY_OCP       (MCSPI_SYSCONFIG_CLOCKACTIVITY_OCP << \
@@ -306,27 +306,27 @@ extern "C" {
                       			      MCSPI_SYSCONFIG_CLOCKACTIVITY_SHIFT)
 
 /*
-** Values used to enable/disable the Tx/Rx FIFOs of McSPI peripheral. 
+** Values used to enable/disable the Tx/Rx FIFOs of McSPI peripheral.
 */
 #define MCSPI_RX_FIFO_ENABLE         (MCSPI_CH0CONF_FFER)
 #define MCSPI_RX_FIFO_DISABLE        (MCSPI_CH0CONF_FFER_FFDISABLED)
-#define MCSPI_TX_FIFO_ENABLE         (MCSPI_CH0CONF_FFEW)    
-#define MCSPI_TX_FIFO_DISABLE        (MCSPI_CH0CONF_FFEW_FFDISABLED)    
+#define MCSPI_TX_FIFO_ENABLE         (MCSPI_CH0CONF_FFEW)
+#define MCSPI_TX_FIFO_DISABLE        (MCSPI_CH0CONF_FFEW_FFDISABLED)
 
 /*
-** Values used to drive the data pins of McSPI peripheral high/low. 
+** Values used to drive the data pins of McSPI peripheral high/low.
 */
 #define MCSPI_DATA_PIN_HIGH          (0x00000001)
-#define MCSPI_DATA_PIN_LOW           (0x00000000)        
+#define MCSPI_DATA_PIN_LOW           (0x00000000)
 
 /*
-** Values used to drive the SPIEN pins of McSPI peripheral high/low. 
+** Values used to drive the SPIEN pins of McSPI peripheral high/low.
 */
 #define MCSPI_SPIEN_HIGH             (0x00000001)
 #define MCSPI_SPIEN_LOW              (0x00000000)
 
 
-extern void McSPIClkConfig(unsigned int baseAdd, unsigned int spiInClk, 
+extern void McSPIClkConfig(unsigned int baseAdd, unsigned int spiInClk,
                            unsigned int spiOutClk,
                            unsigned int chNum, unsigned int clkMode);
 extern void McSPIWordLengthSet(unsigned int baseAdd, unsigned int wordLength,
@@ -338,16 +338,16 @@ extern void McSPICSTimeControlSet(unsigned int baseAdd, unsigned int csTimeContr
 extern void McSPICSAssert(unsigned int baseAdd, unsigned int chNum);
 extern void McSPICSDeAssert(unsigned int baseAdd, unsigned int chNum);
 extern void McSPIStartBitEnable(unsigned int baseAdd, unsigned int chNum);
-extern void McSPIStartBitPolarityConfig(unsigned int baseAdd, 
+extern void McSPIStartBitPolarityConfig(unsigned int baseAdd,
                  unsigned int startBitPol, unsigned int chNum);
 extern void McSPICSPolarityConfig(unsigned int baseAdd, unsigned int spiEnPol,
                            unsigned int chNum);
 extern void McSPIStartBitDisable(unsigned int baseAdd,unsigned int chNum);
 extern void McSPIMasterModeEnable(unsigned int baseAdd);
 extern void McSPISlaveModeEnable(unsigned int baseAdd);
-extern unsigned int McSPIMasterModeConfig(unsigned int baseAdd, 
-                                          unsigned int channelMode, 
-                                          unsigned int trMode, 
+extern unsigned int McSPIMasterModeConfig(unsigned int baseAdd,
+                                          unsigned int channelMode,
+                                          unsigned int trMode,
                           unsigned int pinMode,
                                           unsigned int chNum);
 extern unsigned int McSPISlaveModeConfig(unsigned int baseAdd, unsigned int trMode,
@@ -355,15 +355,15 @@ extern unsigned int McSPISlaveModeConfig(unsigned int baseAdd, unsigned int trMo
 extern void McSPIChannelEnable(unsigned int baseAdd, unsigned int chNum);
 extern void McSPIChannelDisable(unsigned int baseAdd, unsigned int chNum);
 extern void McSPIReset(unsigned int baseAdd);
-extern void McSPIDataPinDirectionConfig(unsigned int baseAdd, 
+extern void McSPIDataPinDirectionConfig(unsigned int baseAdd,
                  unsigned int datDirection);
 extern void McSPITurboModeEnable(unsigned int baseAdd, unsigned int chNum);
 extern void McSPITurboModeDisable(unsigned int baseAdd, unsigned int chNum);
-extern void McSPITxFIFOConfig(unsigned int baseAdd, unsigned int txFifo, 
+extern void McSPITxFIFOConfig(unsigned int baseAdd, unsigned int txFifo,
                        unsigned int chNum);
-extern void McSPIRxFIFOConfig(unsigned int baseAdd, unsigned int rxFifo, 
+extern void McSPIRxFIFOConfig(unsigned int baseAdd, unsigned int rxFifo,
                        unsigned int chNum);
-extern void McSPIFIFOTrigLvlSet(unsigned int baseAdd, unsigned char afl, 
+extern void McSPIFIFOTrigLvlSet(unsigned int baseAdd, unsigned char afl,
                          unsigned char ael, unsigned int trMode);
 extern void McSPIWordCountSet(unsigned int baseAdd, unsigned short wCnt);
 extern void McSPIDMAEnable(unsigned int baseAdd, unsigned int dmaFlags,
@@ -385,7 +385,7 @@ extern unsigned int McSPIClkForceWrite(unsigned int baseAdd, unsigned int spiClk
 extern unsigned int McSPIDataPinRead(unsigned int baseAdd, unsigned int dataPin, unsigned int *spiDat);
 extern unsigned int McSPIDataPinWrite(unsigned int baseAdd, unsigned int dataDir,
                                     unsigned int spiDat);
-extern unsigned int McSPICSRead(unsigned int baseAdd, unsigned int *spiEn, 
+extern unsigned int McSPICSRead(unsigned int baseAdd, unsigned int *spiEn,
                          unsigned int spiEnNum);
 extern unsigned int McSPICSForceWrite(unsigned int baseAdd, unsigned int spiEnLvl,
                    unsigned int spiEnNum);
diff --git a/lib/tiam1808/tiam1808/pruss.h b/lib/tiam1808/tiam1808/pruss.h
index 6ead66b94..f328d1faf 100644
--- a/lib/tiam1808/tiam1808/pruss.h
+++ b/lib/tiam1808/tiam1808/pruss.h
@@ -15,12 +15,12 @@
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
-*    Redistributions of source code must retain the above copyright 
+*    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the 
-*    documentation and/or other materials provided with the   
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
@@ -73,7 +73,7 @@ extern "C" {
 #define	PRUSS_ECAP_BASE               0x4a330000
 #define	PRUSS_MIIRT_BASE              0x4a332000
 #define	PRUSS_MDIO_BASE               0x4a332400
-#else 
+#else
 //***********************************************************************
 //  PRUSS Register Offsets for AM18X SOC
 //***********************************************************************/
@@ -99,10 +99,10 @@ extern "C" {
 #define PRU_EVTOUT_5            5
 #define PRU_EVTOUT_6            6
 #define PRU_EVTOUT_7            7
-/* 
+/*
  * PRUSS Interrupt Controller (PRUSS INTC) Registers Offsets
  */
- 
+
 #define PRU_INTC_REVID_REG  0x000
 #define PRU_INTC_CR_REG     0x004
 #define PRU_INTC_HCR_REG    0x00C
@@ -172,7 +172,7 @@ extern "C" {
 #define	PRUSS0_MII_RT           9
 #define	PRUSS0_MDIO            10
 //***********************************************************************
-//  Macros representing Interrupt-Channel-Host sizes 
+//  Macros representing Interrupt-Channel-Host sizes
 //***********************************************************************/
 #define MAX_HOSTS_SUPPORTED	 10
 #define NUM_PRU_HOSTS        10
@@ -180,11 +180,11 @@ extern "C" {
 #define NUM_PRU_SYS_EVTS     64
 
 //***********************************************************************
-//  Macros to support dynamic chip detecting feature 
+//  Macros to support dynamic chip detecting feature
 //***********************************************************************/
 #define AM18XX_INTC_PHYS_BASE		0x01C34000
 #define AM18XX_DATARAM0_PHYS_BASE	0x01C30000
-#define AM18XX_PRUSS_INTC_REV		0x4E825900	
+#define AM18XX_PRUSS_INTC_REV		0x4E825900
 #define AM33XX_INTC_PHYS_BASE		0x4a320000
 #define AM33XX_DATARAM0_PHYS_BASE	0x4a300000
 #define AM33XX_PRUSS_INTC_REV		0x4E82A900
@@ -197,31 +197,31 @@ extern "C" {
      short sysevt;
      short channel;
  }tsysevt_to_channel_map;
- 
+
  typedef struct __channel_to_host_map
  {
      short channel;
      short host;
  }tchannel_to_host_map;
- 
- typedef struct __pruss_intc_initdata 
+
+ typedef struct __pruss_intc_initdata
  {
      //Enabled SYSEVTs - Range:0..63
      //{-1} indicates end of list
      char sysevts_enabled[NUM_PRU_SYS_EVTS];
- 
+
      //SysEvt to Channel map. SYSEVTs - Range:0..63 Channels -Range: 0..9
      //{-1, -1} indicates end of list
      tsysevt_to_channel_map sysevt_to_channel_map[NUM_PRU_SYS_EVTS];
-     
-     //Channel to Host map.Channels -Range: 0..9  HOSTs - Range:0..9 
+
+     //Channel to Host map.Channels -Range: 0..9  HOSTs - Range:0..9
      //{-1, -1} indicates end of list
      tchannel_to_host_map channel_to_host_map[NUM_PRU_CHANNELS];
- 
+
      //10-bit mask - Enable Host0-Host9 {Host0/1:PRU0/1, Host2..9 : PRUEVT_OUT0..7)
      unsigned int host_enable_bitmask;
  }tpruss_intc_initdata;
- 
+
  //typedef void *(*PRUSSDRV_IRQ_HANDLER) (void *);
  typedef void (*PRUSSDRV_IRQ_HANDLER)(void);
 
@@ -240,16 +240,16 @@ int PRUSSDRVPruExecProgram(int prunum, char *filename);
 int PRUSSDRVPruSendEvent(unsigned int eventnum);
 int PRUSSDRVPruClearEvent(unsigned int eventnum);
 int PRUSSDRVPruWaitEvent(unsigned int pruEvtoutNum);
-int PRUSSDRVPruSendWaitCearEvent(unsigned int sendEventNum, 
+int PRUSSDRVPruSendWaitCearEvent(unsigned int sendEventNum,
 								 unsigned int pruEvtoutNum,
 								 unsigned int ackEventNum);
-int PRUSSDRVRegisterIrqHandler(unsigned int pruEvtoutNum, 
+int PRUSSDRVRegisterIrqHandler(unsigned int pruEvtoutNum,
 						       unsigned char channel,
 						       PRUSSDRV_IRQ_HANDLER irqHandler);
-int PRUSSDRVSetPRUBuffer(unsigned int pruNum, 
+int PRUSSDRVSetPRUBuffer(unsigned int pruNum,
 						 void *buffer,
 						 unsigned int numBytes);
- 
+
 int PRUSSDRVMapL3Mem(void **address);
 int PRUSSDRVMapExtMem(void **address);
 int PRUSSDRVMapPruMem(unsigned int pru_ram_id, void **address);
diff --git a/lib/tiam1808/tiam1808/psc.h b/lib/tiam1808/tiam1808/psc.h
index e33497d0e..d73e146d5 100644
--- a/lib/tiam1808/tiam1808/psc.h
+++ b/lib/tiam1808/tiam1808/psc.h
@@ -1,8 +1,8 @@
 /**
  *  \file  psc.h
  *
- *  \brief This file contains the function prototypes for the device abstraction 
- *         layer for PSC. It also contains some related macro definitions and some 
+ *  \brief This file contains the function prototypes for the device abstraction
+ *         layer for PSC. It also contains some related macro definitions and some
  *         files to be included.
  */
 
diff --git a/lib/tiam1808/tiam1808/rtc.h b/lib/tiam1808/tiam1808/rtc.h
index 4eb95a8ac..5e293fe7f 100644
--- a/lib/tiam1808/tiam1808/rtc.h
+++ b/lib/tiam1808/tiam1808/rtc.h
@@ -2,7 +2,7 @@
 /**
  * \file   rtc.h
  *
- * \brief  Header file for RTC driver module. This file contains the 
+ * \brief  Header file for RTC driver module. This file contains the
  *         prototypes of the APIs of RTC module and some related macros.
  */
 
@@ -51,7 +51,7 @@ extern "C" {
 #endif
 
 /*****************************************************************************/
-/* Either of these macros are returned by the RTCEnableStatus() API.*/   
+/* Either of these macros are returned by the RTCEnableStatus() API.*/
 
 /* Used to disable RTC instance.*/
 #define RTC_DISABLED              RTC_CTRL_RTCDISABLE
@@ -68,7 +68,7 @@ extern "C" {
 #define RTC_24HOUR_MODE           (0 << RTC_CTRL_HOURMODE_SHIFT)
 /*****************************************************************************/
 /*
-** One among the following  macros are passed as a parameter to 
+** One among the following  macros are passed as a parameter to
 ** RTCIntTimerEnable() API.
 */
 
@@ -107,13 +107,13 @@ extern "C" {
 ** by the RTCEventUpdateGet() API.
 */
 /*
-** Used to indicate that DAY register was incremented in the latest 
+** Used to indicate that DAY register was incremented in the latest
 ** time update.
 */
 #define RTC_DAY_EVENT                RTC_STATUS_DAYEVT
 
 /*
-** Used to indicate that HOUR register was incremented in the latest 
+** Used to indicate that HOUR register was incremented in the latest
 ** time update.
 */
 #define RTC_HOUR_EVENT               RTC_STATUS_HREVT
@@ -136,7 +136,7 @@ extern "C" {
 #define RTC_BUSY                     RTC_STATUS_BUSY
 
 /*
-** Used to indicate that RTC is free and is currently not updating its 
+** Used to indicate that RTC is free and is currently not updating its
 ** registers.
 */
 #define RTC_FREE                     RTC_STATUS_BUSY_SHIFT
@@ -152,7 +152,7 @@ extern "C" {
 /*****************************************************************************/
 /*
 ** Either of following macros are passed as a parameter to
-** RTCAlarmHourMeridiemSet() and RTCMeridiemSet() APIs. Similarly either of 
+** RTCAlarmHourMeridiemSet() and RTCMeridiemSet() APIs. Similarly either of
 ** these are returned by RTCAlarmHourMeridiemGet() and RTCMeridiemGet() APIs.
 */
 
@@ -163,7 +163,7 @@ extern "C" {
 #define RTC_ANTE_MERIDIEM            (0 << RTC_HOUR_MERIDIEM_SHIFT)
 /*****************************************************************************/
 /*
-** One among the following  macros are passed as a parameter to 
+** One among the following  macros are passed as a parameter to
 ** RTCDayOfTheWeekSet() API. Similarly one of these macros are returned by the
 ** RTCDayOfTheWeekGet() API.
 */
@@ -246,7 +246,7 @@ extern "C" {
 /*****************************************************************************/
 
 /******************************************************************************
-**            DRIVER API FUNCTIONS PROTOTYPES                              
+**            DRIVER API FUNCTIONS PROTOTYPES
 ******************************************************************************/
 /******************************************************************************
 **         APIs common to the RTC IPs of both AM1808 and AM335x.
diff --git a/lib/tiam1808/tiam1808/spi.h b/lib/tiam1808/tiam1808/spi.h
index 294402112..8cc75e394 100644
--- a/lib/tiam1808/tiam1808/spi.h
+++ b/lib/tiam1808/tiam1808/spi.h
@@ -79,8 +79,8 @@ extern "C" {
 
  /* Assert CS pin(line)*/
 #define SPI_CSHOLD                    SPI_SPIDAT1_CSHOLD
- 
-/* Enable Counter */ 
+
+/* Enable Counter */
 #define SPI_DELCOUNT_ENABLE           SPI_SPIDAT1_WDEL
 
 /* Disable Counter */
@@ -98,7 +98,7 @@ extern "C" {
  /* Active high clock */
 #define SPI_CLK_POL_LOW               0
 
- /* In Phase clock */ 
+ /* In Phase clock */
 #define SPI_CLK_INPHASE               0
 
  /* Out of Phase clock */
@@ -121,10 +121,10 @@ extern "C" {
 ** interrupts to interrupt line INT1
 */
 
-  /* Data length error interrupt enable level */    
+  /* Data length error interrupt enable level */
 #define SPI_DATALEN_ERR_INTLVL        SPI_SPILVL_DLENERRLVL
 
- /* Time out interrupt level */ 
+ /* Time out interrupt level */
 #define SPI_TIMEOUT_INTLVL            SPI_SPILVL_TIMEOUTLVL
 
  /* Parrity interrupt level */
@@ -204,8 +204,8 @@ void SPIOutOfReset(unsigned int baseAdd);
 
 void SPIModeConfigure(unsigned int baseAdd, unsigned int flag);
 
-void SPIPinControl(unsigned int baseAdd, unsigned int idx,
-                   unsigned int flag, unsigned int *val);
+void SPIPinControlGet(unsigned int baseAdd, unsigned int idx, unsigned int *val);
+void SPIPinControlSet(unsigned int baseAdd, unsigned int idx, unsigned int val);
 
 void SPIDelayConfigure(unsigned int baseAdd, unsigned int c2edelay,
                        unsigned int t2edelay, unsigned int t2cdelay,
diff --git a/lib/tiam1808/tiam1808/timer.h b/lib/tiam1808/tiam1808/timer.h
index 94fc65f78..bdae1102c 100644
--- a/lib/tiam1808/tiam1808/timer.h
+++ b/lib/tiam1808/tiam1808/timer.h
@@ -169,13 +169,13 @@ extern "C" {
 /*
 ** Prototypes for the APIs
 */
-extern unsigned int TimerCompareGet(unsigned int baseAddr, 
+extern unsigned int TimerCompareGet(unsigned int baseAddr,
                                      unsigned int regIndex);
-extern unsigned int TimerOUTStatusGet(unsigned int baseAddr, 
+extern unsigned int TimerOUTStatusGet(unsigned int baseAddr,
                                        unsigned int timer);
-extern unsigned int TimerIntStatusGet(unsigned int baseAddr, 
+extern unsigned int TimerIntStatusGet(unsigned int baseAddr,
                                     unsigned int statFlag);
-extern unsigned int TimerIntStatusClear(unsigned int baseAddr, 
+extern unsigned int TimerIntStatusClear(unsigned int baseAddr,
                                     unsigned int statFlag);
 extern unsigned int TimerCaptureGet(unsigned int baseAddr,unsigned int timer);
 extern unsigned int TimerCounterGet(unsigned int baseAddr, unsigned int timer);
@@ -184,15 +184,15 @@ extern unsigned int TimerReloadGet(unsigned int baseAddr, unsigned int timer);
 extern unsigned int TimerPreScalarCount34Get(unsigned int baseAddr);
 extern unsigned int TimerDivDwnRatio34Get(unsigned int baseAddr);
 
-extern void TimerCounterSet(unsigned int baseAddr, unsigned int timer, 
+extern void TimerCounterSet(unsigned int baseAddr, unsigned int timer,
                             unsigned int counter);
-extern void TimerPeriodSet(unsigned int baseAddr, unsigned int timer, 
+extern void TimerPeriodSet(unsigned int baseAddr, unsigned int timer,
                            unsigned int period);
-extern void TimerReloadSet(unsigned int baseAddr, unsigned int timer, 
+extern void TimerReloadSet(unsigned int baseAddr, unsigned int timer,
                            unsigned int reload);
-extern void TimerEnable(unsigned int baseAddr, unsigned int timer, 
+extern void TimerEnable(unsigned int baseAddr, unsigned int timer,
                                                 unsigned int enaMode);
-extern void TimerPreScalarCount34Set(unsigned int baseAddr, 
+extern void TimerPreScalarCount34Set(unsigned int baseAddr,
                                      unsigned int psc34);
 extern void TimerDivDwnRatio34Set(unsigned int baseAddr, unsigned int tddr34);
 extern void TimerInvertOUTDisable(unsigned int baseAddr, unsigned int timer);
diff --git a/lib/tiam1808/tiam1808/uart.h b/lib/tiam1808/tiam1808/uart.h
index 7864fed9c..080cc2f9a 100644
--- a/lib/tiam1808/tiam1808/uart.h
+++ b/lib/tiam1808/tiam1808/uart.h
@@ -65,9 +65,9 @@ extern "C" {
 /***********************************************************************/
 /*
 ** The macros below are used to set the reciever trigger levels.
-** One of the macros  below is passed as 'rxLevel' to'UARTFIFOLevelSet', 
+** One of the macros  below is passed as 'rxLevel' to'UARTFIFOLevelSet',
 ** as 'flags' to 'UARTDMAEnable' and to 'UARTDMADisable'.
-*/ 
+*/
 
 /* This is used to select the receiver trigger level as 1 byte.*/
 #define UART_RX_TRIG_LEVEL_1       (UART_FCR_RXFIFTL_CHAR1                  \
@@ -116,8 +116,8 @@ extern "C" {
 /***************************************************************************/
 
 /************************************************************************/
-/* 
-** These macros are used to set the Parity settings. 
+/*
+** These macros are used to set the Parity settings.
 ** They are used in the functions 'UARTConfigSetExpClk', 'UARTConfigGetExpClk',
 ** 'UARTParityModeSet', 'UARTParityModeGet'.
 */
@@ -166,7 +166,7 @@ extern "C" {
 /* This is used to select single/multiple stop bits.*/
 #define UART_STOP_BIT                  UART_LCR_STB
 
-/* This can be used as a mask for word length selection bits.*/ 
+/* This can be used as a mask for word length selection bits.*/
 #define UART_WORDL                     UART_LCR_WLS
 
 /* This is used to select character length as 5 bits per frame.*/
@@ -238,7 +238,7 @@ extern "C" {
 /* This is used to enable/disable Transmitter Empty Interrupt.*/
 #define UART_INT_TX_EMPTY              UART_IER_ETBEI
 
-/* This is used to enable/disable Receiver Data Available and Character Timeout 
+/* This is used to enable/disable Receiver Data Available and Character Timeout
    Interrupt*/
 #define UART_INT_RXDATA_CTI            UART_IER_ERBI
 
@@ -248,33 +248,33 @@ extern "C" {
 /*
 ** These macros are used to identify what events have generated interrupts.
 ** These are used in the function: 'UARTIntStatus'.
-** One of the macro below is returned by 'UARTIntStatus'. Refer to 
+** One of the macro below is returned by 'UARTIntStatus'. Refer to
 ** definition of 'UARTIntStatus' function for more information.
 */
 
 /* This is used to identify whether FIFO mode is enabled or not.*/
 #define UART_FIFOEN_STAT              UART_IIR_FIFOEN
 
-/* This can be used as a mask for the Interrupt Identification(INTID) bits in 
+/* This can be used as a mask for the Interrupt Identification(INTID) bits in
  * the Interrupt Identification Register(IIR).*/
 #define UART_INTID                    UART_IIR_INTID
 
 /* This is used to identify whether Transmitter Empty event has generated an
-**  interrupt. 
+**  interrupt.
 */
-#define UART_INTID_TX_EMPTY           UART_IIR_INTID_THRE                    
+#define UART_INTID_TX_EMPTY           UART_IIR_INTID_THRE
 
-/* This is used to identify whether Receiver Data Available event has generated 
+/* This is used to identify whether Receiver Data Available event has generated
  * an interrupt.*/
-#define UART_INTID_RX_DATA            UART_IIR_INTID_RDA                     
+#define UART_INTID_RX_DATA            UART_IIR_INTID_RDA
 
 /* This is used to identify whether Receiver Line Status event has generated
  * an interrupt.*/
-#define UART_INTID_RX_LINE_STAT       UART_IIR_INTID_RLS                     
+#define UART_INTID_RX_LINE_STAT       UART_IIR_INTID_RLS
 
 /* This is used to identify whether Character Timeout event has generated an
  * interrupt.*/
-#define UART_INTID_CTI                UART_IIR_INTID_CTI		     
+#define UART_INTID_CTI                UART_IIR_INTID_CTI
 
 /* This is used to identify whether the servicing of any interrupt is pending
  * or not. */
@@ -349,7 +349,7 @@ extern "C" {
 */
 
 /* This is used to identify the Over-sampling rate being set.*/
-#define UART_OVER_SAMP_RATE             UART_MDR_OSM_SEL                            
+#define UART_OVER_SAMP_RATE             UART_MDR_OSM_SEL
 
 /* This is used to select Over-sampling rate as 16. */
 #define UART_OVER_SAMP_RATE_16          UART_MDR_OSM_SEL_SHIFT
@@ -365,21 +365,21 @@ extern "C" {
 //**********************************************************************/
 
 void UARTConfigSetExpClk (unsigned int baseAdd, unsigned int uartClk,
-                          unsigned int baudrate, unsigned int config, 
-                          unsigned int overSampRate); 
+                          unsigned int baudrate, unsigned int config,
+                          unsigned int overSampRate);
 void UARTConfigGetExpClk (unsigned int baseAdd, unsigned int uartClk,
                           unsigned int *pBaud, unsigned int *pConfig);
 void UARTFIFOLevelSet (unsigned int baseAdd, unsigned int rxLevel);
 void UARTParityModeSet(unsigned int baseAdd, unsigned int parityMode);
-unsigned int UARTParityModeGet(unsigned int baseAdd);                                     
+unsigned int UARTParityModeGet(unsigned int baseAdd);
 void UARTEnable (unsigned int baseAdd);
 void UARTDisable (unsigned int baseAdd);
 void UARTFIFOEnable(unsigned int baseAdd);
 void UARTFIFODisable(unsigned int baseAdd);
-unsigned int UARTCharsAvail(unsigned int baseAdd);                                           
+unsigned int UARTCharsAvail(unsigned int baseAdd);
 
-unsigned int UARTSpaceAvail(unsigned int baseAdd);                                           
-unsigned int UARTCharPutNonBlocking(unsigned int baseAdd, 
+unsigned int UARTSpaceAvail(unsigned int baseAdd);
+unsigned int UARTCharPutNonBlocking(unsigned int baseAdd,
                                     unsigned char byteWrite);
 
 int UARTCharGetNonBlocking(unsigned int baseAdd);
diff --git a/lib/tiam1808/tiam1808/usblib/usb-ids.h b/lib/tiam1808/tiam1808/usblib/usb-ids.h
index 022d1cb74..df4d1da45 100755
--- a/lib/tiam1808/tiam1808/usblib/usb-ids.h
+++ b/lib/tiam1808/tiam1808/usblib/usb-ids.h
@@ -4,20 +4,20 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
+//
 // This is part of revision 6288 of the Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbcdc.h b/lib/tiam1808/tiam1808/usblib/usbcdc.h
index 0e7cc74c7..1d94bd8ee 100755
--- a/lib/tiam1808/tiam1808/usblib/usbcdc.h
+++ b/lib/tiam1808/tiam1808/usblib/usbcdc.h
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbdbulk.h b/lib/tiam1808/tiam1808/usblib/usbdbulk.h
index 1e84a56e3..59d028836 100755
--- a/lib/tiam1808/tiam1808/usblib/usbdbulk.h
+++ b/lib/tiam1808/tiam1808/usblib/usbdbulk.h
@@ -4,20 +4,20 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
+//
 // This is part of revision 6288 of the Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbdcdc.h b/lib/tiam1808/tiam1808/usblib/usbdcdc.h
index a6fb8bae6..e9b3d1966 100755
--- a/lib/tiam1808/tiam1808/usblib/usbdcdc.h
+++ b/lib/tiam1808/tiam1808/usblib/usbdcdc.h
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbdcomp.h b/lib/tiam1808/tiam1808/usblib/usbdcomp.h
index afc38564d..ad536a88c 100755
--- a/lib/tiam1808/tiam1808/usblib/usbdcomp.h
+++ b/lib/tiam1808/tiam1808/usblib/usbdcomp.h
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbdevice.h b/lib/tiam1808/tiam1808/usblib/usbdevice.h
index bd31dbd89..046700222 100755
--- a/lib/tiam1808/tiam1808/usblib/usbdevice.h
+++ b/lib/tiam1808/tiam1808/usblib/usbdevice.h
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbdevicepriv.h b/lib/tiam1808/tiam1808/usblib/usbdevicepriv.h
index cdfd79661..291b618ba 100755
--- a/lib/tiam1808/tiam1808/usblib/usbdevicepriv.h
+++ b/lib/tiam1808/tiam1808/usblib/usbdevicepriv.h
@@ -7,21 +7,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbdhid.h b/lib/tiam1808/tiam1808/usblib/usbdhid.h
index 7843724ba..7f3119de3 100755
--- a/lib/tiam1808/tiam1808/usblib/usbdhid.h
+++ b/lib/tiam1808/tiam1808/usblib/usbdhid.h
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbdhidmouse.h b/lib/tiam1808/tiam1808/usblib/usbdhidmouse.h
index cada2eb39..df234981f 100755
--- a/lib/tiam1808/tiam1808/usblib/usbdhidmouse.h
+++ b/lib/tiam1808/tiam1808/usblib/usbdhidmouse.h
@@ -5,21 +5,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbdmsc.h b/lib/tiam1808/tiam1808/usblib/usbdmsc.h
index 3126eb5c6..5cd90a3a4 100755
--- a/lib/tiam1808/tiam1808/usblib/usbdmsc.h
+++ b/lib/tiam1808/tiam1808/usblib/usbdmsc.h
@@ -4,20 +4,20 @@
 //
 // Copyright (c) 2009-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
+//
 // This is part of revision 6288 of the Stellaris USB Library.
 //
 //*****************************************************************************
@@ -162,7 +162,7 @@ tMSCDMedia;
 
 //*****************************************************************************
 //
-// These defines the USB instance number. This can be replaced with dynamic instance number 
+// These defines the USB instance number. This can be replaced with dynamic instance number
 // later.
 //
 //*****************************************************************************
@@ -207,7 +207,7 @@ typedef struct
 
     tUSBDMSCMediaStatus eMediaStatus;
 
-   	unsigned int pulBuffer[DEVICE_BLOCK_SIZE]; 
+   	unsigned int pulBuffer[DEVICE_BLOCK_SIZE];
     unsigned int ulBytesToTransfer;
     unsigned int ulCurrentLBA;
 
diff --git a/lib/tiam1808/tiam1808/usblib/usbhhid.h b/lib/tiam1808/tiam1808/usblib/usbhhid.h
index 2beb77a8c..357e535d7 100755
--- a/lib/tiam1808/tiam1808/usblib/usbhhid.h
+++ b/lib/tiam1808/tiam1808/usblib/usbhhid.h
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library, resused from revision 6288 of the 
+//
+// This is part of AM1808 StarterWare USB Library, resused from revision 6288 of the
 // stellaris USB Library
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbhhidkeyboard.h b/lib/tiam1808/tiam1808/usblib/usbhhidkeyboard.h
index a66646ec6..13072e62b 100755
--- a/lib/tiam1808/tiam1808/usblib/usbhhidkeyboard.h
+++ b/lib/tiam1808/tiam1808/usblib/usbhhidkeyboard.h
@@ -5,20 +5,20 @@
 //
 // Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
+//
 // This is part of revision 8049 of the Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbhhidmouse.h b/lib/tiam1808/tiam1808/usblib/usbhhidmouse.h
index 7718b7e98..44e7be4cc 100755
--- a/lib/tiam1808/tiam1808/usblib/usbhhidmouse.h
+++ b/lib/tiam1808/tiam1808/usblib/usbhhidmouse.h
@@ -5,21 +5,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library, modified  resused from revision 6288 of the 
+//
+// This is part of AM1808 StarterWare USB Library, modified  resused from revision 6288 of the
 // stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbhid.h b/lib/tiam1808/tiam1808/usblib/usbhid.h
index 6d16bad76..a7be32118 100755
--- a/lib/tiam1808/tiam1808/usblib/usbhid.h
+++ b/lib/tiam1808/tiam1808/usblib/usbhid.h
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbhmsc.h b/lib/tiam1808/tiam1808/usblib/usbhmsc.h
index de0939363..1a4ce0d49 100755
--- a/lib/tiam1808/tiam1808/usblib/usbhmsc.h
+++ b/lib/tiam1808/tiam1808/usblib/usbhmsc.h
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library, resused from revision 6288 of the 
+//
+// This is part of AM1808 StarterWare USB Library, resused from revision 6288 of the
 // stellaris USB Library
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbhost.h b/lib/tiam1808/tiam1808/usblib/usbhost.h
index dc0bf71f0..e146f5975 100755
--- a/lib/tiam1808/tiam1808/usblib/usbhost.h
+++ b/lib/tiam1808/tiam1808/usblib/usbhost.h
@@ -4,20 +4,20 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
+//
 // This is part of revision 6288 of the Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbhscsi.h b/lib/tiam1808/tiam1808/usblib/usbhscsi.h
index 3d96db3da..d06aba9bc 100755
--- a/lib/tiam1808/tiam1808/usblib/usbhscsi.h
+++ b/lib/tiam1808/tiam1808/usblib/usbhscsi.h
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library, resused from revision 6288 of the 
+//
+// This is part of AM1808 StarterWare USB Library, resused from revision 6288 of the
 // stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usblib.h b/lib/tiam1808/tiam1808/usblib/usblib.h
index 2750d1b34..ed562ff11 100755
--- a/lib/tiam1808/tiam1808/usblib/usblib.h
+++ b/lib/tiam1808/tiam1808/usblib/usblib.h
@@ -3,21 +3,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usblibpriv.h b/lib/tiam1808/tiam1808/usblib/usblibpriv.h
index 5dd030204..20edd8bc9 100755
--- a/lib/tiam1808/tiam1808/usblib/usblibpriv.h
+++ b/lib/tiam1808/tiam1808/usblib/usblibpriv.h
@@ -6,21 +6,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/usblib/usbmsc.h b/lib/tiam1808/tiam1808/usblib/usbmsc.h
index 7264354de..91f40ab54 100755
--- a/lib/tiam1808/tiam1808/usblib/usbmsc.h
+++ b/lib/tiam1808/tiam1808/usblib/usbmsc.h
@@ -4,20 +4,20 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
+//
 // This is part of revision 6288 of the Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/tiam1808/vpif.h b/lib/tiam1808/tiam1808/vpif.h
index 9382e0ac0..f9dd68db5 100644
--- a/lib/tiam1808/tiam1808/vpif.h
+++ b/lib/tiam1808/tiam1808/vpif.h
@@ -4,7 +4,7 @@
  * \brief This file contains the driver API prototypes and macro definitions
  *        for the VPIF module.
  */
- 
+
 /*
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 */
@@ -56,7 +56,7 @@ extern "C" {
 /***************************************************************************/
 /*
 ** Constants that represent VPIF channel
-** Channel 0 & 1 are capture channels; channel 2 & 3 are display channels 
+** Channel 0 & 1 are capture channels; channel 2 & 3 are display channels
 ** Used in most APIs
 */
 
@@ -67,7 +67,7 @@ extern "C" {
 
 /***************************************************************************/
 /*
-** Values that represent top/bottom field 
+** Values that represent top/bottom field
 ** Used in all the FBConfig (frame buffer config) APIs
 */
 
@@ -95,7 +95,7 @@ extern "C" {
 /***************************************************************************/
 /*
 ** Values that can be passed to VPIFCaptureModeConfig/VPIFDisplayModeConfig
-** API to select mode of capture/display 
+** API to select mode of capture/display
 ** More supported modes will be added
 */
 
@@ -105,7 +105,7 @@ extern "C" {
 
 /***************************************************************************/
 /*
-** Values that represent different VPIF interrupts 
+** Values that represent different VPIF interrupts
 ** Used in all the interrupt APIs
 */
 
@@ -121,21 +121,21 @@ extern "C" {
 ** Used in the ErrorStatus APIs
 */
 
- /* Underflow error for channel 3 */ 
+ /* Underflow error for channel 3 */
 #define VPIF_UNDERFLOW3                         (1 << VPIF_ERRSTAT_UNDERFLOW3_SHIFT)
- /* Underflow error for channel 2 */ 
+ /* Underflow error for channel 2 */
 #define VPIF_UNDERFLOW2                         (1 << VPIF_ERRSTAT_UNDERFLOW2_SHIFT)
- /* Overflow error for channel 1 */ 
+ /* Overflow error for channel 1 */
 #define VPIF_OVERFLOW1                          (1 << VPIF_ERRSTAT_OVERFLOW1_SHIFT)
- /* Overflow error for channel 0 */ 
+ /* Overflow error for channel 0 */
 #define VPIF_OVERFLOW0                          (1 << VPIF_ERRSTAT_OVERFLOW0_SHIFT)
- /* Synchronization error for channel 1 (mismatch EAV2SAV/SAV2EAV) */ 
+ /* Synchronization error for channel 1 (mismatch EAV2SAV/SAV2EAV) */
 #define VPIF_SYNCDISTERR1                       (1 << VPIF_ERRSTAT_SYNCDISTERR1_SHIFT)
- /* Synchronization error for channel 0 (mismatch EAV2SAV/SAV2EAV) */ 
+ /* Synchronization error for channel 0 (mismatch EAV2SAV/SAV2EAV) */
 #define VPIF_SYNCDISTERR0                       (1 << VPIF_ERRSTAT_SYNCDISTERR0_SHIFT)
- /* Error in EAV2SAV/SAV2EAV code for channel 1 */ 
+ /* Error in EAV2SAV/SAV2EAV code for channel 1 */
 #define VPIF_BITERR1                            (1 << VPIF_ERRSTAT_BITERR1_SHIFT)
- /* Error in EAV2SAV/SAV2EAV code for channel 1 */ 
+ /* Error in EAV2SAV/SAV2EAV code for channel 1 */
 #define VPIF_BITERR0                            (1 << VPIF_ERRSTAT_BITERR0_SHIFT)
 
 /***************************************************************************/
@@ -189,7 +189,7 @@ extern "C" {
 
 /***************************************************************************/
 /*
-** Values that represent storage mode of the data. 
+** Values that represent storage mode of the data.
 ** Used in the FieldframeModeSelect APIs of channel 2/0. However, setting on
 ** channel 2 will apply to channel 3, and setting on channel 0 will apply to
 ** channel 1.
@@ -227,7 +227,7 @@ extern "C" {
 /***************************************************************************/
 /*
 ** Values that represent the particular field being processed (in interlaced mode)
-** Value read in the FidModeRead APIs of all channels 
+** Value read in the FidModeRead APIs of all channels
 */
 #define VPIF_FIELD_IDENTIFICATION_TOP           (0 << VPIF_C0CTRL_FID_SHIFT)
 #define VPIF_FIELD_IDENTIFICATION_BOTTOM        (1 << VPIF_C0CTRL_FID_SHIFT)
@@ -235,7 +235,7 @@ extern "C" {
 /***************************************************************************/
 /*
 ** Values that represent the data format
-** Value used in the YcmuxModeSelect APIs of all channels 
+** Value used in the YcmuxModeSelect APIs of all channels
 */
  /* Y & C data are non-muxed, parallel over a 16-bit bus */
 #define VPIF_YC_NONMUXED                        (0 << VPIF_C0CTRL_YCMUX_SHIFT)
@@ -244,7 +244,7 @@ extern "C" {
 
 /***************************************************************************/
 /*
-** Values that represent the capture mode. 
+** Values that represent the capture mode.
 ** (Raw w/ external sync, or BT w/ embedded sync)
 ** Value used in the VPIFCaptureCapmodeModeSelect API
 */
@@ -267,7 +267,7 @@ typedef struct vbufParam
     unsigned int eav2sav;
     unsigned int vsize;
     unsigned int l1;
-    unsigned int l3;    
+    unsigned int l3;
     unsigned int l5;
     unsigned int l7;
     unsigned int l9;
@@ -291,7 +291,7 @@ extern unsigned int VPIFInterruptStatus(unsigned int baseAddr, unsigned int intr
 
 /* C0CTRL & C1CTRL */
 extern void VPIFCaptureClkedgeModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode);
-extern void VPIFCaptureRawDatawidthConfig(unsigned int baseAddr, unsigned int width); 
+extern void VPIFCaptureRawDatawidthConfig(unsigned int baseAddr, unsigned int width);
 extern void VPIFCaptureRawIntlineConfig(unsigned int baseAddr, unsigned int interval);
 extern void VPIFCaptureRawFidinvSet(unsigned int baseAddr, unsigned int mode);
 extern void VPIFCaptureRawVvinvSet(unsigned int baseAddr, unsigned int mode);
@@ -317,14 +317,14 @@ extern unsigned int VPIFCaptureFBExchange(unsigned int baseAddr, unsigned int ch
 
 /* C2CTRL & C3CTRL */
 extern void VPIFDisplayClkedgeModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode);
-extern void VPIFDisplayClipancEnable(unsigned int baseAddr, unsigned int channel); 
-extern void VPIFDisplayClipancDisable(unsigned int baseAddr, unsigned int channel); 
-extern void VPIFDisplayClipvidEnable(unsigned int baseAddr, unsigned int channel); 
-extern void VPIFDisplayClipvidDisable(unsigned int baseAddr, unsigned int channel); 
+extern void VPIFDisplayClipancEnable(unsigned int baseAddr, unsigned int channel);
+extern void VPIFDisplayClipancDisable(unsigned int baseAddr, unsigned int channel);
+extern void VPIFDisplayClipvidEnable(unsigned int baseAddr, unsigned int channel);
+extern void VPIFDisplayClipvidDisable(unsigned int baseAddr, unsigned int channel);
 extern void VPIFDisplayFieldframeModeSelect(unsigned int baseAddr, unsigned int mode);
 extern void VPIFDisplayIntrprogModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode);
-extern void VPIFDisplayPixelEnable(unsigned int baseAddr, unsigned int channel); 
-extern void VPIFDisplayPixelDisable(unsigned int baseAddr, unsigned int channel); 
+extern void VPIFDisplayPixelEnable(unsigned int baseAddr, unsigned int channel);
+extern void VPIFDisplayPixelDisable(unsigned int baseAddr, unsigned int channel);
 extern void VPIFDisplayVancEnable(unsigned int baseAddr, unsigned int channel);
 extern void VPIFDisplayVancDisable(unsigned int baseAddr, unsigned int channel);
 extern void VPIFDisplayHancEnable(unsigned int baseAddr, unsigned int channel);
@@ -332,7 +332,7 @@ extern void VPIFDisplayHancDisable(unsigned int baseAddr, unsigned int channel);
 extern void VPIFDisplayIntframeConfig(unsigned int baseAddr, unsigned int channel, unsigned int mode);
 extern unsigned int VPIFDisplayFidModeRead(unsigned int baseAddr, unsigned int channel);
 extern void VPIFDisplayYcmuxModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode);
-extern void VPIFDisplayClkenEnable(unsigned int baseAddr, unsigned int channel); 
+extern void VPIFDisplayClkenEnable(unsigned int baseAddr, unsigned int channel);
 extern void VPIFDisplayClkenDisable(unsigned int baseAddr, unsigned int channel);
 extern void VPIFDisplayChanenEnable(unsigned int baseAddr, unsigned int channel);
 extern void VPIFDisplayChanenDisable(unsigned int baseAddr, unsigned int channel);
diff --git a/lib/tiam1808/tiam1808/watchdog.h b/lib/tiam1808/tiam1808/watchdog.h
index 124c256cc..4958b1c39 100644
--- a/lib/tiam1808/tiam1808/watchdog.h
+++ b/lib/tiam1808/tiam1808/watchdog.h
@@ -50,11 +50,11 @@ extern "C" {
 #endif
 /*****************************************************************************/
 /*
-** Values that can be passed to WatchdogTimerEmulationModeConfigure API as 
-** emuMode. 
+** Values that can be passed to WatchdogTimerEmulationModeConfigure API as
+** emuMode.
 */
 /* WDT counter free-running in emulation mode */
-#define WDT_EMULATION_FREE              (WDT_WDSC_EMUFREE)    
+#define WDT_EMULATION_FREE              (WDT_WDSC_EMUFREE)
 
 /* WDT counter frozen in emulation mode */
 #define WDT_EMULATION_FROZEN            (WDT_WDSC_EMUFREE_TIMER_FROZEN)
@@ -91,7 +91,7 @@ extern "C" {
 /*
 ** Values that can be passed to WatchdogTimerIntRawStatusSet,
 ** WatchdogTimerIntStatusClear APIs as intFlags.
-** These values can also be used to read the status obatined from 
+** These values can also be used to read the status obatined from
 ** WatchdogTimerIntRawStatusGet, WatchdogTimerIntStatusGet APIs.
 ** These values can also be combined together and passed.
 ** For e.g. (WDT_INT_DELAY | WDT_INT_OVERFLOW)
@@ -105,7 +105,7 @@ extern "C" {
 /*****************************************************************************/
 /*
 ** Values that can be passed to WatchdogTimerIntEnable as intFlags.
-** These values can also be used to read the status obtained from 
+** These values can also be used to read the status obtained from
 ** WatchdogTimerIntEnableStatusGet API.
 ** These values can also be combined together and passed.
 ** For e.g. (WDT_INT_ENABLE_DELAY | WDT_INT_ENABLE_OVRFLW)
@@ -130,7 +130,7 @@ extern "C" {
 
 /*****************************************************************************/
 /*
-** Values that can be used to read the status obtained from 
+** Values that can be used to read the status obtained from
 ** WatchdogTimerWritePostedStatusGet API.
 ** These values can also be combined while reading.
 ** For e.g. (WDT_WRITE_PENDING_WCLR | WDT_WRITE_PENDING_WCRR)
@@ -157,13 +157,13 @@ extern "C" {
 
 /***************************************************************************/
 /*
-** Watchdog timer API prototypes 
+** Watchdog timer API prototypes
 */
 extern void WatchdogTimerEnable(unsigned int baseAdd);
 extern void WatchdogTimerDisable(unsigned int baseAdd);
 extern unsigned int WatchdogTimerRevisionIDGet(unsigned int baseAdd);
 extern void WatchdogTimerReset(unsigned int baseAdd);
-extern void WatchdogTimerEmulationModeConfigure(unsigned int baseAdd, 
+extern void WatchdogTimerEmulationModeConfigure(unsigned int baseAdd,
                                          unsigned int emuMode);
 extern void WatchdogTimerPreScalerClkEnable(unsigned int baseAdd, unsigned int ptv);
 extern void WatchdogTimerPreScalerClkDisable(unsigned int baseAdd);
diff --git a/lib/tiam1808/usblib/device/usbdbulk.c b/lib/tiam1808/usblib/device/usbdbulk.c
index 0aac7cd6a..01a1b0d40 100755
--- a/lib/tiam1808/usblib/device/usbdbulk.c
+++ b/lib/tiam1808/usblib/device/usbdbulk.c
@@ -4,20 +4,20 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
+//
 // This is part of revision 6288 of the Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/usblib/device/usbdcdc.c b/lib/tiam1808/usblib/device/usbdcdc.c
index 16c5f2126..51f14ad37 100755
--- a/lib/tiam1808/usblib/device/usbdcdc.c
+++ b/lib/tiam1808/usblib/device/usbdcdc.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
@@ -93,7 +93,7 @@
 #define MAX_REQUEST_DATA_SIZE sizeof(tLineCoding)
 
 //*****************************************************************************
-//This macro is used to diable the bit band operartion. Need to undefine this macro to use the 
+//This macro is used to diable the bit band operartion. Need to undefine this macro to use the
 // bit band operation.
 //***************************************************************************
 #define DISABLE_BIT_BAND
@@ -1081,7 +1081,7 @@ ProcessDataFromHost(const tUSBDCDCDevice *psDevice, unsigned int ulStatus)
                                     (void *)0);
         }
 
-	
+
     }
     else
     {
@@ -1572,7 +1572,7 @@ HandleRequests(void *pvInstance, tUSBRequest *pUSBRequest)
     tCDCSerInstance *psInst;
 	tLineCoding sLineCoding;
 	tBoolean bRetcode;
-	
+
 
     ASSERT(pvInstance != 0);
 
@@ -1698,7 +1698,7 @@ HandleRequests(void *pvInstance, tUSBRequest *pUSBRequest)
         //
         case USB_CDC_GET_LINE_CODING:
         {
-            //						
+            //
             // ACK what we have already received
             //
             USBDevEndpointDataAck(psInst->ulUSBBase, USB_EP_0, false);
@@ -2276,8 +2276,8 @@ USBDCDCInit(unsigned int ulIndex, const tUSBDCDCDevice *psCDCDevice)
         // the CDC device on the bus.
         //
         USBDCDInit(ulIndex, psInst->psDevInfo);
-		
-	   
+
+
     }
 
     return(pvRet);
@@ -2490,7 +2490,7 @@ USBDCDCPacketWrite(void *pvInstance, unsigned char *pcData,
 {
     tCDCSerInstance *psInst;
     int iRetcode;
-	
+
     ASSERT(pvInstance);
 
     //
diff --git a/lib/tiam1808/usblib/device/usbdcdesc.c b/lib/tiam1808/usblib/device/usbdcdesc.c
index e53ea67f6..acf435241 100755
--- a/lib/tiam1808/usblib/device/usbdcdesc.c
+++ b/lib/tiam1808/usblib/device/usbdcdesc.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/usblib/device/usbdcomp.c b/lib/tiam1808/usblib/device/usbdcomp.c
index f93bd2c55..4ea9992ef 100755
--- a/lib/tiam1808/usblib/device/usbdcomp.c
+++ b/lib/tiam1808/usblib/device/usbdcomp.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //****************************************************************************
diff --git a/lib/tiam1808/usblib/device/usbdconfig.c b/lib/tiam1808/usblib/device/usbdconfig.c
index e534b96f3..a76171ef9 100755
--- a/lib/tiam1808/usblib/device/usbdconfig.c
+++ b/lib/tiam1808/usblib/device/usbdconfig.c
@@ -4,13 +4,13 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -18,7 +18,7 @@
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
 //
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
@@ -98,7 +98,7 @@ GetEndpointFIFOSize(unsigned int ulMaxPktSize, const tFIFOEntry *psFIFOParams,
     // requested size.  Step through each of the supported sizes until we
     // find one that will do.
     //
-    for(ulLoop = USB_FIFO_SZ_8; ulLoop <= USB_FIFO_SZ_8192; ulLoop++) 
+    for(ulLoop = USB_FIFO_SZ_8; ulLoop <= USB_FIFO_SZ_8192; ulLoop++)
     {
         //
         // How many bytes does this FIFO value represent?
diff --git a/lib/tiam1808/usblib/device/usbdenum.c b/lib/tiam1808/usblib/device/usbdenum.c
index b344eefcf..f58685816 100755
--- a/lib/tiam1808/usblib/device/usbdenum.c
+++ b/lib/tiam1808/usblib/device/usbdenum.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
@@ -444,7 +444,7 @@ USBDCDInit(unsigned int ulIndex, tDeviceInfo *psDevice)
         //
         // Enable Clocking to the USB controller.
         //
-	
+
 		USBModuleClkEnable(ulIndex, USB0_BASE);
 
 		USBReset(USB_0_OTGBASE);
@@ -454,13 +454,13 @@ USBDCDInit(unsigned int ulIndex, tDeviceInfo *psDevice)
         UsbPhyOn();
     }
 
-	
+
 
 	//
     // Initialize the USB tick module.
     //
 
-	InternalUSBTickInit();    
+	InternalUSBTickInit();
 
     //
     // Only do hardware update if the stack is in Device mode, do not touch the
@@ -489,7 +489,7 @@ USBDCDInit(unsigned int ulIndex, tDeviceInfo *psDevice)
                                        USB_INTCTRL_SUSPEND |
                                        USB_INTCTRL_SOF);
         USBIntEnableEndpoint(USB0_BASE, USB_INTEP_ALL);
-		
+
     }
 
     //
@@ -621,7 +621,7 @@ USBDCDTerm(unsigned int ulIndex)
     // Disable the USB peripheral
     //
 	USBModuleClkDisable(ulIndex, USB0_BASE);
-	 
+
 }
 
 //*****************************************************************************
@@ -993,8 +993,8 @@ USBDReadAndDispatchRequest(unsigned int ulIndex)
 
 
 
-	
-		
+
+
 
 	if((pRequest->bmRequestType & USB_RTYPE_TYPE_M) != USB_RTYPE_STANDARD)
     {
@@ -2925,7 +2925,7 @@ USBDEP0StateTxConfig(unsigned int ulIndex)
 //
 //*****************************************************************************
 void
-USBDeviceIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus, 
+USBDeviceIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus,
 													unsigned int *endPStatus)
 {
     static unsigned int ulSOFDivide = 0;
@@ -2933,7 +2933,7 @@ USBDeviceIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus,
     void *pvInstance;
 	unsigned int epStatus;
 	unsigned int epnStatus = 0;
-    
+
 	//
     // Get the controller interrupt status from the wrapper registers
     // Only the lower 16bits contain EP intr data
@@ -2947,8 +2947,8 @@ USBDeviceIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus,
 	{
 		epStatus = *endPStatus;
 	}
-	
-	ulStatus |= USBIntStatusControl(USB0_BASE);	
+
+	ulStatus |= USBIntStatusControl(USB0_BASE);
 
 	//
     // If device initialization has not been performed then just disconnect
diff --git a/lib/tiam1808/usblib/device/usbdhandler.c b/lib/tiam1808/usblib/device/usbdhandler.c
index ac5ef1e23..a482fe1e0 100755
--- a/lib/tiam1808/usblib/device/usbdhandler.c
+++ b/lib/tiam1808/usblib/device/usbdhandler.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
@@ -85,8 +85,8 @@ USB0DeviceIntHandler(void)
 	//
 	HWREG(USB_0_OTGBASE + USB_0_IRQ_STATUS_0) = epStatus;
 
-#ifdef DMA_MODE	
-	HWREG(USBSS_BASE + USBSS_IRQ_STATUS) = 
+#ifdef DMA_MODE
+	HWREG(USBSS_BASE + USBSS_IRQ_STATUS) =
 		HWREG(USBSS_BASE + USBSS_IRQ_STATUS);
 #endif
 	//
@@ -102,7 +102,7 @@ USB0DeviceIntHandler(void)
 	HWREG(USBSS_BASE + USBSS_IRQ_EOI) = 0;
 #endif
 
-#else	
+#else
 	//
 	// Get the controller interrupt status.
 	//
@@ -123,7 +123,7 @@ USB0DeviceIntHandler(void)
 
 	// End of Interrupts
 	HWREG(USB_0_OTGBASE + USB_0_END_OF_INTR) = 0;
-#endif	
+#endif
 
 }
 
diff --git a/lib/tiam1808/usblib/device/usbdhid.c b/lib/tiam1808/usblib/device/usbdhid.c
index a31967cf3..39d26dfd8 100755
--- a/lib/tiam1808/usblib/device/usbdhid.c
+++ b/lib/tiam1808/usblib/device/usbdhid.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
@@ -42,7 +42,7 @@
 
 
 //*****************************************************************************
-//This macro is used to diable the bit band operartion. Need to undefine this macro to use the 
+//This macro is used to diable the bit band operartion. Need to undefine this macro to use the
 // bit band operation.
 //***************************************************************************
 #define DISABLE_BIT_BAND
diff --git a/lib/tiam1808/usblib/device/usbdhidmouse.c b/lib/tiam1808/usblib/device/usbdhidmouse.c
index 51580fffd..1c4269088 100755
--- a/lib/tiam1808/usblib/device/usbdhidmouse.c
+++ b/lib/tiam1808/usblib/device/usbdhidmouse.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library and reused from revision 6288 
+//
+// This is part of AM1808 StarterWare USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/usblib/device/usbdmsc.c b/lib/tiam1808/usblib/device/usbdmsc.c
index 7856b5b79..19fde3493 100755
--- a/lib/tiam1808/usblib/device/usbdmsc.c
+++ b/lib/tiam1808/usblib/device/usbdmsc.c
@@ -4,20 +4,20 @@
 //
 // Copyright (c) 2009-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
+//
 // This is part of revision 6288 of the Stellaris USB Library.
 //
 //*****************************************************************************
@@ -515,7 +515,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
     tMSCInstance *psInst;
     tMSCCBW *pSCSICBW;
     unsigned int pendReg = 0;
-	
+
 #ifdef DMA_MODE
 	unsigned int rxBuffer;
 	unsigned int txBuffer;
@@ -542,15 +542,15 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 #ifdef DMA_MODE
 	// Get the Starvation interrupt status
 	CppiDmaGetINTD0Status(USB_INSTANCE);
-	
+
 	// Get the DMA Interrupt status
 	pendReg = CppiDmaGetPendStatus(USB_INSTANCE);
 #endif
-	
+
     //
     // Handler for the bulk IN data endpoint.
     //
-    if(ulStatus & (1 << USB_EP_TO_INDEX(psInst->ucINEndpoint)) 
+    if(ulStatus & (1 << USB_EP_TO_INDEX(psInst->ucINEndpoint))
 		|| (pendReg & CPDMA_TX_PENDING))
     {
 
@@ -561,7 +561,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 			 dmaStatus = dmaTxCompletion(USB_INSTANCE, psInst->ucINEndpoint);
 		}
 #endif
-		
+
 		switch(psInst->ucSCSIState)
         {
 			//
@@ -569,8 +569,8 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
             // command.
             //
             case STATE_SCSI_SEND_BLOCKS:
-            {	
-				
+            {
+
 #ifndef DMA_MODE
 				//
                 // Decrement the number of bytes left to send.
@@ -581,7 +581,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 				//Add the bytes transfered
 				//
 				g_bytesRead = g_bytesRead + MAX_TRANSFER_SIZE;
-				
+
 #else			//
 				// Check if DMA is completed, Check the remaining bytes
 				//
@@ -593,20 +593,20 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 						g_bytesRead = g_bytesRead + DMA_TX_MAX_CHUNK_SIZE;
 					}
 					else
-					{							
+					{
 						g_bytesRead = g_bytesRead +psInst->ulBytesToTransfer;
 						psInst->ulBytesToTransfer = 0;
 					}
 
 				}
 #endif
-			    
+
                 //
                 // If we are done then move on to the status phase.
                 //
                 if(psInst->ulBytesToTransfer == 0)
                 {
-												
+
 					//
                     // Set the status so that it can be sent when this
                     // response has has be successfully sent.
@@ -614,12 +614,12 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
                     g_sSCSICSW.bCSWStatus = 0;
                     g_sSCSICSW.dCSWDataResidue = 0;
 					g_bytesRead = 0;
-                                      
+
                     //
                     // Send back the status once this transfer is complete.
                     //
                     psInst->ucSCSIState = STATE_SCSI_SEND_STATUS;
-					
+
 #ifdef DMA_MODE
 					//
 					//Disable the RX and TX DMA before sending the CSW
@@ -628,7 +628,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 					disableCoreTxDMA(USB_INSTANCE, psInst->ucINEndpoint);
 					disableCoreRxDMA(USB_INSTANCE, psInst->ucOUTEndpoint);
 #endif
-					
+
 					USBDSCSISendStatus(psDevice);
 
                     if(psDevice->pfnEventCallback)
@@ -643,7 +643,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
                     break;
                 }
 
-		
+
 #ifndef DMA_MODE
 
 				if(g_bytesRead == DEVICE_BLOCK_SIZE)
@@ -658,11 +658,11 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 				//
 				// Read the new data and send it out.
 				//
-#ifdef DMA_MODE	
+#ifdef DMA_MODE
 				if(dmaStatus == DMA_TX_COMPLETED)
 				{
 					//
-					//If current DMA is operation is completed, check how may byets remaining 
+					//If current DMA is operation is completed, check how may byets remaining
 					//to send
 					//
 					g_bytesRead = 0;
@@ -671,7 +671,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 
 					if(nBlocks > (DMA_TX_MAX_CHUNK_SIZE / MAX_TRANSFER_SIZE))
 						nBlocks = (DMA_TX_MAX_CHUNK_SIZE / MAX_TRANSFER_SIZE);
-					
+
 					//Allocate buffer for the remaining data
 					txBuffer = (unsigned int)cppiDmaAllocnBuffer(nBlocks);
 
@@ -680,7 +680,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 					//
 					psDevice->sMediaFunctions.BlockRead(psInst->pvMedia,
 						(unsigned char *)txBuffer, psInst->ulCurrentLBA, nBlocks);
-														
+
 					doDmaTxTransfer(USB_INSTANCE, (unsigned char *)txBuffer,
 						 (nBlocks * DEVICE_BLOCK_SIZE), psInst->ucINEndpoint);
 				}
@@ -692,11 +692,11 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 					(unsigned char *)psInst->pulBuffer,
 					psInst->ulCurrentLBA, 1);
 
-				USBEndpointDataPut(USB0_BASE,  psInst->ucINEndpoint, 
+				USBEndpointDataPut(USB0_BASE,  psInst->ucINEndpoint,
 					(unsigned char *)psInst->pulBuffer, MAX_TRANSFER_SIZE);
 				USBEndpointDataSend(USB0_BASE,  psInst->ucINEndpoint, USB_TRANS_IN);
 #endif
-				
+
 				break;
             }
 
@@ -704,7 +704,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
             // Handle sending status.
             //
             case STATE_SCSI_SEND_STATUS:
-            {				
+            {
 #ifdef DMA_MODE
 				//
 				//Disable the RX and TX DMA before sending the CSW
@@ -713,7 +713,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 				disableCoreTxDMA(USB_INSTANCE, psInst->ucINEndpoint);
 				disableCoreRxDMA(USB_INSTANCE, psInst->ucOUTEndpoint);
 #endif
-				
+
 				//
                 // Indicate success and no extra data coming.
                 //
@@ -728,11 +728,11 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
             case STATE_SCSI_SENT_STATUS:
             {
 
-#ifdef DMA_MODE				
+#ifdef DMA_MODE
 				disableCoreTxDMA(USB_INSTANCE, psInst->ucINEndpoint);
 				disableCoreRxDMA(USB_INSTANCE, psInst->ucOUTEndpoint);
 #endif
-				
+
 				psInst->ucSCSIState = STATE_SCSI_IDLE;
 
                 break;
@@ -756,7 +756,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
     if(ulStatus & (0x10000 << USB_EP_TO_INDEX(psInst->ucOUTEndpoint))
 		|| (pendReg & CPDMA_RX_PENDING))
     {
-       
+
         switch(psInst->ucSCSIState)
         {
             //
@@ -769,7 +769,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 				//
 				//Get the data from the FIFO and send Ack
 				//
-				USBEndpointDataGet(psInst->ulUSBBase, psInst->ucOUTEndpoint, 
+				USBEndpointDataGet(psInst->ulUSBBase, psInst->ucOUTEndpoint,
 					(unsigned char *)psInst->pulBuffer, &ulMaxsize);
 
 				USBDevEndpointDataAck(psInst->ulUSBBase, psInst->ucOUTEndpoint, false);
@@ -777,12 +777,12 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 				//
 				//Write the data to the block media
 				//
-				psDevice->sMediaFunctions.BlockWrite(psInst->pvMedia, 
-					(unsigned char *)psInst->pulBuffer, 
+				psDevice->sMediaFunctions.BlockWrite(psInst->pvMedia,
+					(unsigned char *)psInst->pulBuffer,
 						psInst->ulCurrentLBA, 1);
-				
+
 #endif
-				
+
 #ifdef DMA_MODE
 				//
 				//During receive operation, we need to wait in loop till we recive all data
@@ -791,15 +791,15 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 				{
 
 					//Decrement the bytes recived
-					psInst->ulBytesToTransfer -= DMA_RX_MAX_CHUNK_SIZE;	
+					psInst->ulBytesToTransfer -= DMA_RX_MAX_CHUNK_SIZE;
 					g_bytesWritten = g_bytesWritten + DMA_RX_MAX_CHUNK_SIZE;
-				
+
 #else
-					psInst->ulBytesToTransfer -= MAX_TRANSFER_SIZE;	
+					psInst->ulBytesToTransfer -= MAX_TRANSFER_SIZE;
 					g_bytesWritten = g_bytesWritten + MAX_TRANSFER_SIZE;
 #endif
 
-#ifdef DMA_MODE					
+#ifdef DMA_MODE
 					//
 					//Get the data from the RX completeion queue
 					//
@@ -809,26 +809,26 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 					//
 					//Write the data to the block media
 					//
-					psDevice->sMediaFunctions.BlockWrite(psInst->pvMedia, 
+					psDevice->sMediaFunctions.BlockWrite(psInst->pvMedia,
 						(unsigned char *)rxBuffer, psInst->ulCurrentLBA, 1);
 					//
 					//Load another BD to the receive queue
 					//
-					doDmaRxTransfer(USB_INSTANCE, MAX_TRANSFER_SIZE, 
+					doDmaRxTransfer(USB_INSTANCE, MAX_TRANSFER_SIZE,
 						(unsigned char *)rxBuffer, psInst->ucOUTEndpoint);
-						
+
 #endif
-					if(g_bytesWritten == DEVICE_BLOCK_SIZE)					
+					if(g_bytesWritten == DEVICE_BLOCK_SIZE)
 
 					{
 		               	g_bytesWritten = 0;
 						psInst->ulCurrentLBA++;
 
 					}
-					
+
 #ifdef DMA_MODE
 				}
-					
+
 					cppiDmaHandleError(USB_INSTANCE);
 #endif
 
@@ -845,7 +845,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
                  	g_sSCSICSW.dCSWDataResidue = 0;
 					g_bytesWritten = 0;
 					psInst->ucSCSIState = STATE_SCSI_SEND_STATUS;
-					
+
 #ifdef DMA_MODE
 					//
 					//Disable the RX and TX DMA before sending the CSW
@@ -860,7 +860,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 
 					USBDSCSISendStatus(psDevice);
 
-                 }              
+                 }
 
                 break;
             }
@@ -871,23 +871,23 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
             //
             case STATE_SCSI_IDLE:
             {
-               
+
 #ifdef DMA_MODE
-                
+
 				//
 				//Enable the RX DMA as it is disabled during last CSW
 				//
 				enableCoreRxDMA(USB_INSTANCE, psInst->ucOUTEndpoint);
 				while(!(CppiDmaGetPendStatus(USB_INSTANCE) & CPDMA_RX_PENDING));
-				rxBuffer = dmaRxCompletion(USB_INSTANCE, psInst->ucOUTEndpoint);							
-				pSCSICBW = (tMSCCBW *)rxBuffer;					
-				
+				rxBuffer = dmaRxCompletion(USB_INSTANCE, psInst->ucOUTEndpoint);
+				pSCSICBW = (tMSCCBW *)rxBuffer;
+
 				//
 				//Recceive the command
 				//
-				doDmaRxTransfer(USB_INSTANCE, MAX_TRANSFER_SIZE, 
-					(unsigned char *)rxBuffer, psInst->ucOUTEndpoint);	
-					
+				doDmaRxTransfer(USB_INSTANCE, MAX_TRANSFER_SIZE,
+					(unsigned char *)rxBuffer, psInst->ucOUTEndpoint);
+
 #else
                 //
                 // Attempt to handle the new command.
@@ -909,7 +909,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
 				USBDevEndpointDataAck(psInst->ulUSBBase, psInst->ucOUTEndpoint,
 										false);
 #endif
-				
+
 				//
                 // If this is a valid CBW then handle it.
                 //
@@ -920,7 +920,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
                     g_sSCSICSW.dCSWDataResidue = 0;
                     g_sSCSICSW.bCSWStatus = 0;
 					USBDSCSICommand(psDevice, pSCSICBW);
-					 
+
                 }
                 else
                 {
@@ -931,7 +931,7 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
                     // controller.
                     //
                     psInst->ucSCSIState = STATE_SCSI_IDLE;
-					
+
                 }
 
                 break;
@@ -942,9 +942,9 @@ HandleEndpoints(void *pvInstance, unsigned int ulStatus)
             }
         }
 
-		
+
     }
-	
+
 
 }
 
@@ -1131,13 +1131,13 @@ USBDMSCInit(unsigned int ulIndex, const tUSBDMSCDevice *psDevice)
     ASSERT(psDevice->psPrivateData);
 
     USBDMSCCompositeInit(ulIndex, psDevice);
-	
+
     //
     // All is well so now pass the descriptors to the lower layer and put
     // the bulk device on the bus.
     //
     USBDCDInit(ulIndex, psDevice->psPrivateData->psDevInfo);
-	
+
 	//
 	// Return the pointer to the instance indicating that everything went well.
 	//
@@ -1198,7 +1198,7 @@ USBDMSCCompositeInit(unsigned int ulIndex, const tUSBDMSCDevice *psDevice)
     //
     psInst->ucInterface = 0;
     psInst->ucOUTEndpoint = DATA_OUT_ENDPOINT;
-    psInst->ucOUTDMA = DATA_OUT_DMA_CHANNEL; 
+    psInst->ucOUTDMA = DATA_OUT_DMA_CHANNEL;
     psInst->ucINEndpoint = DATA_IN_ENDPOINT;
     psInst->ucINDMA = DATA_IN_DMA_CHANNEL;
 
@@ -1257,7 +1257,7 @@ USBDMSCCompositeInit(unsigned int ulIndex, const tUSBDMSCDevice *psDevice)
     // Enable Clocking to the USB controller.
     //
 	USBModuleClkEnable(ulIndex, USB0_BASE);
-	
+
 
     //
     // Turn on USB Phy clock.
@@ -1428,16 +1428,16 @@ USBDSCSIInquiry(const tUSBDMSCDevice *psDevice)
         g_pucCommand[iIdx + 32] = psDevice->pucVersion[iIdx];
     }
 
-  
+
 
 #ifdef DMA_MODE
-	
+
 	//
 	//Allocate buffer for the command
 	//
 	cmdBuffer = (unsigned char*)cppiDmaAllocBuffer();
 	memcpy(cmdBuffer, g_pucCommand, 36);
-	
+
 	//
 	//send command response
 	//
@@ -1448,7 +1448,7 @@ USBDSCSIInquiry(const tUSBDMSCDevice *psDevice)
 	//
 	// Send the SCSI Inquiry Response.
 	//
-	USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint, g_pucCommand, 36); 
+	USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint, g_pucCommand, 36);
 
 	//
 	// Send the data to the host.
@@ -1456,7 +1456,7 @@ USBDSCSIInquiry(const tUSBDMSCDevice *psDevice)
 	USBEndpointDataSend(USB0_BASE, psInst->ucINEndpoint, USB_TRANS_IN);
 #endif
 
-	
+
 
     //
     // Set the status so that it can be sent when this response has
@@ -1510,7 +1510,7 @@ USBDSCSIReadCapacities(const tUSBDMSCDevice *psDevice)
         //
         // Current media capacity
         //
-        g_pucCommand[8] = 0x02;  
+        g_pucCommand[8] = 0x02;
 
         //
         // Fill in the block size, which is fixed at DEVICE_BLOCK_SIZE.
@@ -1529,15 +1529,15 @@ USBDSCSIReadCapacities(const tUSBDMSCDevice *psDevice)
 		//
 		cmdBuffer = (unsigned char*)cppiDmaAllocBuffer();
 		memcpy(cmdBuffer, g_pucCommand, 12);
-		
+
 		//
 		//Send the command response
 		//
 		doDmaTxTransfer(USB_INSTANCE, cmdBuffer, 12, psInst->ucINEndpoint);
 		enableCoreTxDMA(USB_INSTANCE, psInst->ucINEndpoint);
-#else		
-		USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint, g_pucCommand, 12);  
-		USBEndpointDataSend(USB0_BASE, psInst->ucINEndpoint, USB_TRANS_IN); 
+#else
+		USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint, g_pucCommand, 12);
+		USBEndpointDataSend(USB0_BASE, psInst->ucINEndpoint, USB_TRANS_IN);
 #endif
 
 		//
@@ -1615,7 +1615,7 @@ USBDSCSIReadCapacity(const tUSBDMSCDevice *psDevice)
         g_pucCommand[1] = 0xff & (ulBlocks >> 16);
         g_pucCommand[2] = 0xff & (ulBlocks >> 8);
         g_pucCommand[3] = 0xff & (ulBlocks);
-	
+
         g_pucCommand[4] = 0;
 
         //
@@ -1635,14 +1635,14 @@ USBDSCSIReadCapacity(const tUSBDMSCDevice *psDevice)
 		//
 		cmdBuffer = (unsigned char*)cppiDmaAllocBuffer();
 		memcpy(cmdBuffer, g_pucCommand, 8);
-		
+
 		//
 		//Send the command response
 		//
 		doDmaTxTransfer(USB_INSTANCE, cmdBuffer, 8, psInst->ucINEndpoint);
 		enableCoreTxDMA(USB_INSTANCE, psInst->ucINEndpoint);
 #else
-		USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint, g_pucCommand, 8); 
+		USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint, g_pucCommand, 8);
 		USBEndpointDataSend(USB0_BASE, psInst->ucINEndpoint, USB_TRANS_IN);
 #endif
 
@@ -1780,7 +1780,7 @@ USBDSCSIRequestSense(const tUSBDMSCDevice *psDevice)
 static void
 USBDSCSIRead10(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
 {
-    tMSCInstance *psInst;	
+    tMSCInstance *psInst;
 	unsigned int usNumBlocks;
 
 #ifdef DMA_MODE
@@ -1792,13 +1792,13 @@ USBDSCSIRead10(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
     // Default the number of blocks.
     //
     usNumBlocks = 0;
-	
+
     //
     // Get our instance data pointer.
     //
     psInst = psDevice->psPrivateData;
 
-	
+
 	if(psInst->pvMedia != 0)
     {
         //
@@ -1809,24 +1809,24 @@ USBDSCSIRead10(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
                                (pSCSICBW->CBWCB[3] << 16) |
                                (pSCSICBW->CBWCB[4] << 8) |
                                (pSCSICBW->CBWCB[5] << 0);
-		
+
 		//
         // More bytes to read.
         //
         usNumBlocks = (pSCSICBW->CBWCB[7] << 8) | pSCSICBW->CBWCB[8];
-		
-		
+
+
 #ifdef DMA_MODE
 		if(usNumBlocks > (DMA_TX_MAX_CHUNK_SIZE / MAX_TRANSFER_SIZE))
 			nBlocks = (DMA_TX_MAX_CHUNK_SIZE / MAX_TRANSFER_SIZE);
 		else
 			nBlocks = usNumBlocks;
-		
+
 		//
 		//Allocate buffer for TX data
 		//
 		txBuffer=(unsigned int)cppiDmaAllocnBuffer(nBlocks);
-		
+
 		//
         // Read the next logical block from the storage device.
         //
@@ -1836,53 +1836,53 @@ USBDSCSIRead10(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
         {
             psInst->pvMedia = 0;
             psDevice->sMediaFunctions.Close(0);
-	    }		
+	    }
 #else
 
 		//
         // Read the next logical block from the storage device.
         //
 		if(psDevice->sMediaFunctions.BlockRead(psInst->pvMedia,
-			((unsigned char *)psInst->pulBuffer),              
-			psInst->ulCurrentLBA, 1) == 0)        
-			{            
-				psInst->pvMedia = 0;            
-				psDevice->sMediaFunctions.Close(0);	    
-			}		
+			((unsigned char *)psInst->pulBuffer),
+			psInst->ulCurrentLBA, 1) == 0)
+			{
+				psInst->pvMedia = 0;
+				psDevice->sMediaFunctions.Close(0);
+			}
 
 
 #endif
     }
-	 
-	
+
+
 
 	//
     // If there is media present then start transferring the data.
     //
     if(psInst->pvMedia != 0)
     {
-       		
+
         //
         // Schedule the remaining bytes to send.
         //
         psInst->ulBytesToTransfer = (DEVICE_BLOCK_SIZE * usNumBlocks);
 
-#ifdef DMA_MODE			
+#ifdef DMA_MODE
 
 		//
 		//Load the DMA queue with the data buffer
 		//
-		doDmaTxTransfer(USB_INSTANCE, (unsigned char *)txBuffer, 
+		doDmaTxTransfer(USB_INSTANCE, (unsigned char *)txBuffer,
 			(nBlocks *DEVICE_BLOCK_SIZE), psInst->ucINEndpoint);
 		//
 		//Enable the DMA for TX operation
 		//
-		enableCoreTxDMA(USB_INSTANCE, psInst->ucINEndpoint);	 
+		enableCoreTxDMA(USB_INSTANCE, psInst->ucINEndpoint);
 #else
-		USBEndpointDataPut(USB0_BASE,  psInst->ucINEndpoint, 
-			(unsigned char *)psInst->pulBuffer, 
+		USBEndpointDataPut(USB0_BASE,  psInst->ucINEndpoint,
+			(unsigned char *)psInst->pulBuffer,
 				MAX_TRANSFER_SIZE);
-		USBEndpointDataSend(USB0_BASE,	psInst->ucINEndpoint, 
+		USBEndpointDataSend(USB0_BASE,	psInst->ucINEndpoint,
 			USB_TRANS_IN);
 #endif
 		//
@@ -1932,7 +1932,7 @@ USBDSCSIWrite10(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
 {
 	unsigned short usNumBlocks;
 	tMSCInstance *psInst;
-	
+
 	//
     // Get our instance data pointer.
     //
@@ -1963,11 +1963,11 @@ USBDSCSIWrite10(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
         // DEVICE_BLOCK_SIZE bytes.
         //
         psInst->ucSCSIState = STATE_SCSI_RECEIVE_BLOCKS;
-		
+
 #ifdef DMA_MODE
 		enableCoreRxDMA(USB_INSTANCE, psInst->ucOUTEndpoint);
 #endif
-		
+
 		//
         // Notify the application of the write event.
         //
@@ -1975,8 +1975,8 @@ USBDSCSIWrite10(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
         {
             psDevice->pfnEventCallback(0, USBD_MSC_EVENT_WRITING, 0, 0);
         }
-        
-		
+
+
     }
     else
     {
@@ -2105,11 +2105,11 @@ USBDSCSISendStatus(const tUSBDMSCDevice *psDevice)
 
     //
     // Respond with the requested status.
-    //	
-	
+    //
+
 	USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint,
                      (unsigned char *)&g_sSCSICSW, 13);
-  	USBEndpointDataSend(USB0_BASE, psInst->ucINEndpoint, USB_TRANS_IN);		
+  	USBEndpointDataSend(USB0_BASE, psInst->ucINEndpoint, USB_TRANS_IN);
 
     //
     // Move the state to status sent so that the next interrupt will move the
@@ -2144,7 +2144,7 @@ USBDSCSICommand(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
     // Save the transfer length because it may be overwritten by some calls.
     //
     ulTransferLength = pSCSICBW->dCBWDataTransferLength;
-	
+
     switch(pSCSICBW->CBWCB[0])
     {
         //
@@ -2260,9 +2260,9 @@ USBDSCSICommand(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
 			psInst->ucSCSIState = STATE_SCSI_IDLE;
             g_sSCSICSW.bCSWStatus = 0;
             g_sSCSICSW.dCSWDataResidue = pSCSICBW->dCBWDataTransferLength;
-            break;			
+            break;
 		}
-		
+
         default:
         {
 			psInst->ucSCSIState = STATE_SCSI_IDLE;
@@ -2279,7 +2279,7 @@ USBDSCSICommand(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
             //
             if(pSCSICBW->dCBWDataTransferLength != 0)
             {
-				
+
                 if(pSCSICBW->bmCBWFlags & CBWFLAGS_DIR_IN)
                 {
                     //
@@ -2318,8 +2318,8 @@ USBDSCSICommand(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
     // If there is no data then send out the current status.
     //
     if(ulTransferLength == 0)
-    {    
-	
+    {
+
 		#ifdef DMA_MODE
 			disableCoreTxDMA(USB_INSTANCE, psInst->ucINEndpoint);
 			disableCoreRxDMA(USB_INSTANCE, psInst->ucOUTEndpoint);
diff --git a/lib/tiam1808/usblib/host/usbhhid.c b/lib/tiam1808/usblib/host/usbhhid.c
index b5fa61f20..0c1afafc0 100755
--- a/lib/tiam1808/usblib/host/usbhhid.c
+++ b/lib/tiam1808/usblib/host/usbhhid.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library, resused from revision 6288 of the 
+//
+// This is part of AM1808 StarterWare USB Library, resused from revision 6288 of the
 // stellaris USB Library
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/usblib/host/usbhhidkeyboard.c b/lib/tiam1808/usblib/host/usbhhidkeyboard.c
index 0f7eab924..9c9e671c3 100755
--- a/lib/tiam1808/usblib/host/usbhhidkeyboard.c
+++ b/lib/tiam1808/usblib/host/usbhhidkeyboard.c
@@ -5,20 +5,20 @@
 //
 // Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
+//
 // This is part of revision 8049 of the Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/usblib/host/usbhhidmouse.c b/lib/tiam1808/usblib/host/usbhhidmouse.c
index 1eb41992e..ea1a1ef3e 100755
--- a/lib/tiam1808/usblib/host/usbhhidmouse.c
+++ b/lib/tiam1808/usblib/host/usbhhidmouse.c
@@ -5,21 +5,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library, modified resused from revision 6288 of the 
+//
+// This is part of AM1808 StarterWare USB Library, modified resused from revision 6288 of the
 // stellaris USB Library
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/usblib/host/usbhmsc.c b/lib/tiam1808/usblib/host/usbhmsc.c
index 5669fc529..4cc6d4405 100755
--- a/lib/tiam1808/usblib/host/usbhmsc.c
+++ b/lib/tiam1808/usblib/host/usbhmsc.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library, resused from revision 6288 of the 
+//
+// This is part of AM1808 StarterWare USB Library, resused from revision 6288 of the
 // stellaris USB Library
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/usblib/host/usbhostenum.c b/lib/tiam1808/usblib/host/usbhostenum.c
index 7bb6b2872..e61784fd2 100755
--- a/lib/tiam1808/usblib/host/usbhostenum.c
+++ b/lib/tiam1808/usblib/host/usbhostenum.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library, modified resused from revision 6288 of the 
+//
+// This is part of AM1808 StarterWare USB Library, modified resused from revision 6288 of the
 // stellaris USB Library.
 //
 //*****************************************************************************
@@ -718,7 +718,7 @@ USBHCDPipeAllocSize(unsigned int ulIndex, unsigned int ulEndpointType,
                     tHCDPipeCallback pfnCallback)
 {
     int iIdx;
-    
+
     ASSERT(ulIndex == 0);
 
     //
@@ -736,7 +736,7 @@ USBHCDPipeAllocSize(unsigned int ulIndex, unsigned int ulEndpointType,
             //
             if(g_sUSBHCD.USBOUTPipes[iIdx].ulDevAddr == 0)
             {
- 
+
                 //
                 // Save the endpoint type and device address and callback
                 // function.
@@ -782,8 +782,8 @@ USBHCDPipeAllocSize(unsigned int ulIndex, unsigned int ulEndpointType,
             // A zero address indicates free.
             //
             if(g_sUSBHCD.USBINPipes[iIdx].ulDevAddr == 0)
-            {     
-                                  
+            {
+
                 //
                 // Save the endpoint type and device address and callback
                 // function.
@@ -1049,7 +1049,7 @@ USBHCDPipeWrite(unsigned int ulPipe, unsigned char *pucData,
     unsigned int ulRemainingBytes;
     unsigned int ulByteToSend;
     unsigned int ulPipeIdx;
-	
+
 #ifdef DMA_MODE
 	unsigned int txBuffer;
 	unsigned int nBlocks;
@@ -1095,7 +1095,7 @@ USBHCDPipeWrite(unsigned int ulPipe, unsigned char *pucData,
         // Start a write request.
         //
         g_sUSBHCD.USBOUTPipes[ulPipeIdx].eState = PIPE_WRITING;
-		
+
 #ifdef DMA_MODE
 
 		//
@@ -1116,7 +1116,7 @@ USBHCDPipeWrite(unsigned int ulPipe, unsigned char *pucData,
 		//Allocate enough buffer
 		//
 		txBuffer=(unsigned int)cppiDmaAllocnBuffer(nBlocks);
-		
+
 		//
 		// Set pending transmit DMA flag
 		//
@@ -1125,18 +1125,18 @@ USBHCDPipeWrite(unsigned int ulPipe, unsigned char *pucData,
 		//
 		//Copy the data to the TX buffer
 		//
-		memcpy((unsigned char *)txBuffer, pucData, ulLength); 
+		memcpy((unsigned char *)txBuffer, pucData, ulLength);
 		//
 		//Load the DMA queue with the data buffer
 		//
-		doDmaTxTransfer(USB_INSTANCE, (unsigned char *)txBuffer, 
+		doDmaTxTransfer(USB_INSTANCE, (unsigned char *)txBuffer,
 			ulLength, ulEndpoint);
 
 		ulByteToSend = ulSize;
 		//
 		//Enable the DMA for TX operation
 		//
-		enableCoreTxDMA(USB_INSTANCE, ulEndpoint);	 
+		enableCoreTxDMA(USB_INSTANCE, ulEndpoint);
 
 #else
 
@@ -1150,7 +1150,7 @@ USBHCDPipeWrite(unsigned int ulPipe, unsigned char *pucData,
         //
         USBEndpointDataSend(USB0_BASE, ulEndpoint, USB_TRANS_OUT);
 #endif
-       
+
         //
         // Wait for a status change.
         //
@@ -1237,7 +1237,7 @@ USBHCDPipeSchedule(unsigned int ulPipe, unsigned char *pucData,
                    unsigned int ulSize)
 {
     unsigned int ulEndpoint;
-   
+
     //
     // Determine which endpoint interface that this pipe is using.
     //
@@ -1258,7 +1258,7 @@ USBHCDPipeSchedule(unsigned int ulPipe, unsigned char *pucData,
         //
         // Schedule the data to be sent.
         //
-        USBEndpointDataSend(USB0_BASE, ulEndpoint, USB_TRANS_OUT); 
+        USBEndpointDataSend(USB0_BASE, ulEndpoint, USB_TRANS_OUT);
 
 	}
     else
@@ -1267,7 +1267,7 @@ USBHCDPipeSchedule(unsigned int ulPipe, unsigned char *pucData,
         // Start a read request.
         //
         g_sUSBHCD.USBINPipes[EP_PIPE_IDX_M & ulPipe].eState = PIPE_READING;
-       
+
         //
         // Trigger a request for data from the device.
         //
@@ -1355,7 +1355,7 @@ USBHCDPipeRead(unsigned int ulPipe, unsigned char *pucData,
     unsigned int ulEndpoint;
     unsigned int ulRemainingBytes;
     unsigned int ulPipeIdx;
-#ifdef DMA_MODE	
+#ifdef DMA_MODE
 	unsigned int ulLength;
 #else
     unsigned int ulBytesRead = 0;
@@ -1365,7 +1365,7 @@ USBHCDPipeRead(unsigned int ulPipe, unsigned char *pucData,
     //
     ulPipeIdx = ulPipe & EP_PIPE_IDX_M;
 
-    
+
     //
     // Determine which endpoint interface that this pipe is using.
     //
@@ -1393,7 +1393,7 @@ USBHCDPipeRead(unsigned int ulPipe, unsigned char *pucData,
 		ulLength = USB_PACKET_LENGTH;
 	}
 
-#endif      
+#endif
 
 	while(ulRemainingBytes != 0)
     {
@@ -1402,13 +1402,13 @@ USBHCDPipeRead(unsigned int ulPipe, unsigned char *pucData,
 		// Give enough buffer to DMA
 		//
 		rxBuffer = (unsigned char *)cppiDmaAllocBuffer();
-		doDmaRxTransfer(USB_INSTANCE, ulLength, rxBuffer, 
-									ulEndpoint);		
+		doDmaRxTransfer(USB_INSTANCE, ulLength, rxBuffer,
+									ulEndpoint);
 		//
 		//Enable the DMA
 		//
 		enableCoreRxDMA(USB_INSTANCE, ulEndpoint);
-#endif      
+#endif
         //
         // Start a read request.
         //
@@ -1438,7 +1438,7 @@ USBHCDPipeRead(unsigned int ulPipe, unsigned char *pucData,
         {
 
 
-#ifdef DMA_MODE			
+#ifdef DMA_MODE
 			disableCoreRxDMA(USB_INSTANCE, ulEndpoint);
 
 			//
@@ -1446,7 +1446,7 @@ USBHCDPipeRead(unsigned int ulPipe, unsigned char *pucData,
 			//
 			//memset (pucData, 0, ulLength);
 			memcpy(pucData, rxBuffer, ulLength);
-			
+
 			//
 			//Free the DMA Buffer
 			//
@@ -1486,7 +1486,7 @@ USBHCDPipeRead(unsigned int ulPipe, unsigned char *pucData,
             //
             // Acknowledge that the data was read from the endpoint.
             //
-            USBHostEndpointDataAck(USB0_BASE, ulEndpoint); 
+            USBHostEndpointDataAck(USB0_BASE, ulEndpoint);
 
             //
             // Subtract the number of bytes read from the bytes remaining.
@@ -1527,7 +1527,7 @@ USBHCDPipeRead(unsigned int ulPipe, unsigned char *pucData,
             //
             // This is the actual endpoint number.
             //
-         	USBHCDClearFeature(1, ulPipe, USB_FEATURE_EP_HALT);       
+         	USBHCDClearFeature(1, ulPipe, USB_FEATURE_EP_HALT);
 
             //
             // If there was a stall, then no more data is coming so break out.
@@ -1739,7 +1739,7 @@ USBHCDInitInternal(unsigned int ulIndex, void *pvPool,
                               (USB_EP_MODE_CTRL | USB_EP_SPEED_HIGH |
                                USB_EP_HOST_OUT));
 
-		
+
 		USBEnableOtgIntr(USB_0_OTGBASE);
 
         //
@@ -2033,7 +2033,7 @@ USBHCDInit(unsigned int ulIndex, void *pvPool, unsigned int ulPoolSize)
     {
 		//
 		// Enable Clocking to the USB controller.
-		//        
+		//
 		USBModuleClkEnable(ulIndex, USB0_BASE);
 
 		USBReset(USB_0_OTGBASE);
@@ -2066,8 +2066,8 @@ USBHCDInit(unsigned int ulIndex, void *pvPool, unsigned int ulPoolSize)
             //
             g_sUSBHCD.iEventDriver = iDriver;
         }
-    }    
-    
+    }
+
 }
 
 //*****************************************************************************
@@ -2191,7 +2191,7 @@ USBHCDReset(unsigned int ulIndex)
 
     //
     // Wait 20ms
-    //    
+    //
     delay(20);
 
     //
@@ -2203,7 +2203,7 @@ USBHCDReset(unsigned int ulIndex)
     // Need to wait at least 10ms to let the device recover from
     // the reset.  This is the delay specified in the USB 2.0 spec.
     // We will hold the reset for 20ms.
-    //  
+    //
     delay(20);
 }
 
@@ -2256,7 +2256,7 @@ USBHCDResume(unsigned int ulIndex)
 
     //
     // Wait 100ms
-    // 
+    //
   	delay(100);
 
     //
@@ -2813,7 +2813,7 @@ USBHostIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus, unsigned
 	unsigned int epStatus;
 	unsigned int epnStatus = 0;
 #ifdef DMA_MODE
-	unsigned int pendReg = 0;	
+	unsigned int pendReg = 0;
 #endif
 	//
     // Get the controller interrupt status from the wrapper registers
@@ -2829,7 +2829,7 @@ USBHostIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus, unsigned
 		epStatus = *endPStatus;
 	}
 	ulStatus |= USBIntStatusControl(USB0_BASE);
-	
+
 
     if(ulStatus & USB_INTCTRL_SOF)
     {
@@ -2952,11 +2952,11 @@ USBHostIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus, unsigned
         USBHCDEnumHandler();
     }
 
-	
+
 	/*
 	converting the epstatus(Wrapper register data) to ulStatus( MUSB register data)
 	*/
-	
+
 	if(endPStatus ==  NULL)
 	{
 		epnStatus = 0xFF & epStatus;
@@ -2978,7 +2978,7 @@ USBHostIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus, unsigned
     for(ulIdx = 0; ulIdx < MAX_NUM_PIPES; ulIdx++)
     {
 
-		
+
 		if((epnStatus == 0) && (g_ulDMAPending == 0))
 		{
 			break;
@@ -2988,10 +2988,10 @@ USBHostIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus, unsigned
 		//
 		// Check for any pending RX transaction
 		//
-		if((pendReg & CPDMA_RX_PENDING) && (g_ulDMAPending & 
+		if((pendReg & CPDMA_RX_PENDING) && (g_ulDMAPending &
 								(DMA_PEND_RECEIVE_FLAG << ulIdx)))
 		{
-			//	
+			//
 			//Reset the pending flag
 			//
 			g_ulDMAPending &= ~(DMA_PEND_RECEIVE_FLAG << ulIdx);
@@ -2999,7 +2999,7 @@ USBHostIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus, unsigned
 			//
 			//Read the completion queue
 			//
-			rxBuffer = (unsigned char *)dmaRxCompletion(USB_INSTANCE,  
+			rxBuffer = (unsigned char *)dmaRxCompletion(USB_INSTANCE,
 										INDEX_TO_USB_EP(ulIdx + 1));
 			//
 			//Send an ACk
@@ -3012,7 +3012,7 @@ USBHostIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus, unsigned
 			g_sUSBHCD.USBINPipes[ulIdx].eState = PIPE_DATA_READY;
 
 			//
-			//Set the RX event 
+			//Set the RX event
 			//
 			ulEvent = USB_EVENT_RX_AVAILABLE;
 
@@ -3029,7 +3029,7 @@ USBHostIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus, unsigned
 		//
 		//Check for any pending TX transaction
 		//
-		if((pendReg & CPDMA_TX_PENDING) && (g_ulDMAPending & 
+		if((pendReg & CPDMA_TX_PENDING) && (g_ulDMAPending &
 								(DMA_PEND_TRANSMIT_FLAG << ulIdx)))
 		{
 
@@ -3037,7 +3037,7 @@ USBHostIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus, unsigned
             // Handle the case where the pipe is writing
             //
             if(g_sUSBHCD.USBOUTPipes[ulIdx].eState == PIPE_WRITING)
-            {	
+            {
             	//
 				//Reset the the pending flag
 				//
@@ -3046,7 +3046,7 @@ USBHostIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus, unsigned
 				//
 				//Read the completion queue
 				//
-				dmaTxCompletion(USB_INSTANCE,  
+				dmaTxCompletion(USB_INSTANCE,
 										INDEX_TO_USB_EP(ulIdx + 1));
 				//
 				// Data was transmitted successfully.
@@ -3057,17 +3057,17 @@ USBHostIntHandlerInternal(unsigned int ulIndex, unsigned int ulStatus, unsigned
                 // Notify the pipe that its last transaction was completed.
                 //
                 ulEvent = USB_EVENT_TX_COMPLETE;
-				
+
             }
 		}
-		
-#endif       
+
+#endif
 
         //
         // Check the next pipe, the first time through this will clear out
         // any interrupts dealing with endpoint zero since it was handled above.
         //
-        
+
 		epnStatus >>= 1;
 
         //
@@ -3216,19 +3216,19 @@ void
 USB0HostIntHandler(void)
 {
     unsigned int ulStatus = 0;
-	
+
 #if defined(am335x) || defined(c6a811x) || defined(am386x) || \
     defined(c6741x)
 
-    unsigned int epStatus = 0;	
+    unsigned int epStatus = 0;
 
 	ulStatus = HWREG(USB_0_OTGBASE + USB_0_IRQ_STATUS_1);
 	epStatus = HWREG(USB_0_OTGBASE + USB_0_IRQ_STATUS_0);
 	HWREG(USB_0_OTGBASE + USB_0_IRQ_STATUS_1) = ulStatus;
 	HWREG(USB_0_OTGBASE + USB_0_IRQ_STATUS_0) = epStatus;
 
-#ifdef DMA_MODE	
-	HWREG(USBSS_BASE + USBSS_IRQ_STATUS) = 
+#ifdef DMA_MODE
+	HWREG(USBSS_BASE + USBSS_IRQ_STATUS) =
 		HWREG(USBSS_BASE + USBSS_IRQ_STATUS);
 #endif
 
@@ -3238,15 +3238,15 @@ USB0HostIntHandler(void)
 #ifdef DMA_MODE
 		HWREG(USBSS_BASE + USBSS_IRQ_EOI) = 0;
 #endif
-	
-#else	
+
+#else
 
     //
     // Get the control interrupt status.
     //
-    
+
 	ulStatus = HWREG(USB_0_OTGBASE + USB_0_INTR_SRC);
-  
+
 	// Clear the Interrupts
 	HWREG(USB_0_OTGBASE + USB_0_INTR_SRC_CLEAR) = ulStatus;
 #ifdef _TMS320C6X
@@ -3261,8 +3261,8 @@ USB0HostIntHandler(void)
     USBHostIntHandlerInternal(0, ulStatus, NULL);
 
 	// End of Interrupts
-	HWREG(USB_0_OTGBASE + USB_0_END_OF_INTR) = 0;	
-#endif	
+	HWREG(USB_0_OTGBASE + USB_0_END_OF_INTR) = 0;
+#endif
 
 }
 
@@ -3461,7 +3461,7 @@ USBHCDDeviceDisconnected(unsigned int ulIndex)
             g_sUSBHCD.EventInfo.ulInstance = 0;
         }
     }
-    
+
 }
 
 //*****************************************************************************
@@ -3593,7 +3593,7 @@ USBHCDMain(void)
 #else
             IntSystemDisable(INT_USB0);
 #endif
-           
+
             //
             // If there was a device in any state of connection then indicate
             // that it has been disconnected.
@@ -3614,7 +3614,7 @@ USBHCDMain(void)
 
             //
             // Wait for 100ms before trying to re-power the device.
-            //        	
+            //
         	delay(100);
 
             //
diff --git a/lib/tiam1808/usblib/host/usbhscsi.c b/lib/tiam1808/usblib/host/usbhscsi.c
index 96d461661..89a435f63 100755
--- a/lib/tiam1808/usblib/host/usbhscsi.c
+++ b/lib/tiam1808/usblib/host/usbhscsi.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 StarterWare USB Library, resused from revision 6288 of the 
+//
+// This is part of AM1808 StarterWare USB Library, resused from revision 6288 of the
 // stellaris USB Library.
 //
 //*****************************************************************************
@@ -209,14 +209,14 @@ USBHSCSIInquiry(unsigned int ulInPipe, unsigned int ulOutPipe,
     //
     SCSICmd.bCBWCBLength = 6;
 
-#if defined (__IAR_SYSTEMS_ICC__)     
+#if defined (__IAR_SYSTEMS_ICC__)
     //
     // Send Inquiry command with no request for vital product data.
     //
     SCSICmd.CBWCB[0] = SCSI_INQUIRY_CMD;
     SCSICmd.CBWCB[1] = 0;
     SCSICmd.CBWCB[2] = 0;
-    SCSICmd.CBWCB[3] = 0;  
+    SCSICmd.CBWCB[3] = 0;
     //
     // Allocation length.
     //
@@ -256,7 +256,7 @@ USBHSCSIInquiry(unsigned int ulInPipe, unsigned int ulOutPipe,
 	*((unsigned int *)&SCSICmd.CBWCB[4]) = SCSI_INQUIRY_DATA_SZ;
 	*((unsigned int *)&SCSICmd.CBWCB[8]) = 0;
 	*((unsigned int *)&SCSICmd.CBWCB[12]) = 0;
-#endif  
+#endif
 
 
 
@@ -315,17 +315,17 @@ USBHSCSIReadCapacity(unsigned int ulInPipe, unsigned int ulOutPipe,
     //
     // Set the length of the command itself.
     //
-    SCSICmd.bCBWCBLength = 12;   
-    
+    SCSICmd.bCBWCBLength = 12;
+
 	//
 	// Only use the first byte and set it to the Read Capacity command.  The
 	// rest are set to 0.	//
-	 
-#if defined (__IAR_SYSTEMS_ICC__)  
+
+#if defined (__IAR_SYSTEMS_ICC__)
     SCSICmd.CBWCB[0] = SCSI_READ_CAPACITY;
     SCSICmd.CBWCB[1] = 0;
     SCSICmd.CBWCB[2] = 0;
-    SCSICmd.CBWCB[3] = 0;  
+    SCSICmd.CBWCB[3] = 0;
     SCSICmd.CBWCB[4] = 0;
 	SCSICmd.CBWCB[5] = 0;
 	SCSICmd.CBWCB[6] = 0;
@@ -396,16 +396,16 @@ USBHSCSIReadCapacities(unsigned int ulInPipe, unsigned int ulOutPipe,
     // Set the length of the command itself.
     //
     SCSICmd.bCBWCBLength = 12;
-           
+
     //
     // Only use the first byte and set it to the Read Capacity command.  The
     // rest are set to 0.
     //
-#if defined (__IAR_SYSTEMS_ICC__)  
+#if defined (__IAR_SYSTEMS_ICC__)
     SCSICmd.CBWCB[0] = SCSI_READ_CAPACITIES;
     SCSICmd.CBWCB[1] = 0;
     SCSICmd.CBWCB[2] = 0;
-    SCSICmd.CBWCB[3] = 0;  
+    SCSICmd.CBWCB[3] = 0;
     SCSICmd.CBWCB[4] = 0;
 	SCSICmd.CBWCB[5] = 0;
 	SCSICmd.CBWCB[6] = 0;
@@ -517,12 +517,12 @@ USBHSCSIModeSense6(unsigned int ulInPipe, unsigned int ulOutPipe,
 
     //
     // Set the options for the Mode Sense Command (6).
-    //    
-#if defined (__IAR_SYSTEMS_ICC__)   
+    //
+#if defined (__IAR_SYSTEMS_ICC__)
     SCSICmd.CBWCB[0] = (SCSI_MODE_SENSE_6 | ulFlags);
 	SCSICmd.CBWCB[1] = 0;
     SCSICmd.CBWCB[2] = 0;
-    SCSICmd.CBWCB[3] = 0;  
+    SCSICmd.CBWCB[3] = 0;
     SCSICmd.CBWCB[4] = (unsigned char)*pulSize;
 	SCSICmd.CBWCB[5] = 0;
 	SCSICmd.CBWCB[6] = 0;
@@ -597,11 +597,11 @@ USBHSCSITestUnitReady(unsigned int ulInPipe, unsigned int ulOutPipe)
     //
     // Set the parameter options.
     //
-#if defined (__IAR_SYSTEMS_ICC__) 
+#if defined (__IAR_SYSTEMS_ICC__)
     SCSICmd.CBWCB[0] = SCSI_TEST_UNIT_READY;
     SCSICmd.CBWCB[1] = 0;
     SCSICmd.CBWCB[2] = 0;
-    SCSICmd.CBWCB[3] = 0;  
+    SCSICmd.CBWCB[3] = 0;
     SCSICmd.CBWCB[4] = 0;
 	SCSICmd.CBWCB[5] = 0;
 	SCSICmd.CBWCB[6] = 0;
@@ -676,11 +676,11 @@ USBHSCSIRequestSense(unsigned int ulInPipe, unsigned int ulOutPipe,
     //
     // Set the parameter options.
     //
-#if defined (__IAR_SYSTEMS_ICC__) 
-	SCSICmd.CBWCB[0] = SCSI_REQUEST_SENSE;    
+#if defined (__IAR_SYSTEMS_ICC__)
+	SCSICmd.CBWCB[0] = SCSI_REQUEST_SENSE;
     SCSICmd.CBWCB[1] = 0;
     SCSICmd.CBWCB[2] = 0;
-    SCSICmd.CBWCB[3] = 0;  
+    SCSICmd.CBWCB[3] = 0;
     SCSICmd.CBWCB[4] = 18;
 	SCSICmd.CBWCB[5] = 0;
 	SCSICmd.CBWCB[6] = 0;
@@ -800,10 +800,10 @@ USBHSCSIRead10(unsigned int ulInPipe, unsigned int ulOutPipe,
 #elif defined (_TMS320C6X)
 	_mem4(&SCSICmd.CBWCB[8]) = (ulNumBlocks & 0xFF);
 	_mem4(&SCSICmd.CBWCB[12]) = 0;
-#else	
+#else
 	*((unsigned int *)&SCSICmd.CBWCB[8]) = (ulNumBlocks & 0xFF);
 	*((unsigned int *)&SCSICmd.CBWCB[12]) = 0;
-#endif    
+#endif
 
     //
     // Send the command and get the results.
@@ -886,7 +886,7 @@ USBHSCSIWrite10(unsigned int ulInPipe, unsigned int ulOutPipe,
     //
     SCSICmd.CBWCB[7] = (ulNumBlocks & 0xFF00) >> 8;
 
-#if defined (__IAR_SYSTEMS_ICC__)    
+#if defined (__IAR_SYSTEMS_ICC__)
 	SCSICmd.CBWCB[8] = (ulNumBlocks & 0xFF);
 	SCSICmd.CBWCB[9] = 0;
 	SCSICmd.CBWCB[10]= 0;
@@ -898,10 +898,10 @@ USBHSCSIWrite10(unsigned int ulInPipe, unsigned int ulOutPipe,
 #elif defined (_TMS320C6X)
 	_mem4(&SCSICmd.CBWCB[8]) = ulNumBlocks & 0xFF;
 	_mem4(&SCSICmd.CBWCB[12]) = 0;
-#else	
+#else
 	*((unsigned int *)&SCSICmd.CBWCB[8]) = (ulNumBlocks & 0xFF);
 	*((unsigned int *)&SCSICmd.CBWCB[12]) = 0;
-#endif   
+#endif
     //
     // Send the command and get the results.
     //
diff --git a/lib/tiam1808/usblib/usbbuffer.c b/lib/tiam1808/usblib/usbbuffer.c
index 55d68db44..260c491bf 100755
--- a/lib/tiam1808/usblib/usbbuffer.c
+++ b/lib/tiam1808/usblib/usbbuffer.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 Sitaraware USB Library and reused from revision 6288 
+//
+// This is part of AM1808 Sitaraware USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/usblib/usbdesc.c b/lib/tiam1808/usblib/usbdesc.c
index 323a97752..44ee41894 100755
--- a/lib/tiam1808/usblib/usbdesc.c
+++ b/lib/tiam1808/usblib/usbdesc.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 Sitaraware USB Library and reused from revision 6288 
+//
+// This is part of AM1808 Sitaraware USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/usblib/usbkeyboardmap.c b/lib/tiam1808/usblib/usbkeyboardmap.c
index 69ce04cb7..2789f9f80 100755
--- a/lib/tiam1808/usblib/usbkeyboardmap.c
+++ b/lib/tiam1808/usblib/usbkeyboardmap.c
@@ -5,20 +5,20 @@
 //
 // Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
+//
 // This is part of revision 8049 of the Stellaris USB Library.
 //
 //*****************************************************************************
diff --git a/lib/tiam1808/usblib/usbringbuf.c b/lib/tiam1808/usblib/usbringbuf.c
index a65dbb0e6..7961348ef 100755
--- a/lib/tiam1808/usblib/usbringbuf.c
+++ b/lib/tiam1808/usblib/usbringbuf.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 Sitaraware USB Library and reused from revision 6288 
+//
+// This is part of AM1808 Sitaraware USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************
@@ -218,7 +218,7 @@ void
 USBRingBufFlush(tUSBRingBufObject *ptUSBRingBuf)
 {
    	unsigned int bIntsOff;
-	 
+
 
     //
     // Check the arguments.
@@ -240,7 +240,7 @@ void
 USBRingBufFlush(tUSBRingBufObject *ptUSBRingBuf)
 {
    	unsigned char bIntsOff;
-	 
+
 
     //
     // Check the arguments.
diff --git a/lib/tiam1808/usblib/usbtick.c b/lib/tiam1808/usblib/usbtick.c
index 0897af96b..1bae28577 100755
--- a/lib/tiam1808/usblib/usbtick.c
+++ b/lib/tiam1808/usblib/usbtick.c
@@ -4,21 +4,21 @@
 //
 // Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
-// 
+//
 // Texas Instruments (TI) is supplying this software for use solely and
 // exclusively on TI's microcontroller products. The software is owned by
 // TI and/or its suppliers, and is protected under applicable copyright
 // laws. You may not combine this software with "viral" open-source
 // software in order to form a larger program.
-// 
+//
 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
 // DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of AM1808 Sitaraware USB Library and reused from revision 6288 
+//
+// This is part of AM1808 Sitaraware USB Library and reused from revision 6288
 // of the  Stellaris USB Library.
 //
 //*****************************************************************************