esp32: Merge with master up to version 1.14.0.b1.

Author: Daniel Campora

drivers/sx127x/sx1272/sx1272.c

@@ -853,7 +853,7 @@ void SX1272Reset( void )
         // Wait 6 ms
         DelayMs( 6 );
     } else {
-        DelayMs( 1 );
+        DelayMs( 2 );
     }
 }
 
@@ -998,7 +998,7 @@ void SX1272OnTimeoutIrq( void )
     }
 }
 
-void SX1272RadioFlagsIrq (void) {
+IRAM_ATTR void SX1272RadioFlagsIrq (void) {
     if (SX1272.irqFlags & RADIO_IRQ_FLAG_RX_TIMEOUT) {
         SX1272.irqFlags &= ~RADIO_IRQ_FLAG_RX_TIMEOUT;
         if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) )

drivers/sx127x/sx1276/sx1276.c

@@ -214,6 +214,10 @@ void SX1276Init( RadioEvents_t *events )
 
     SX1276Reset( );
 
+    SX1276SetOpMode( RF_OPMODE_SLEEP );
+
+    SX1276SetModem( MODEM_FSK );
+
     RxChainCalibration( );
 
     SX1276SetOpMode( RF_OPMODE_SLEEP );
@@ -971,7 +975,7 @@ void SX1276Reset( void )
         // Wait 6 ms
         DelayMs( 6 );
     } else {
-        DelayMs( 1 );
+        DelayMs( 2 );
     }
 }
 
@@ -1001,6 +1005,11 @@ IRAM_ATTR void SX1276SetModem( RadioModems_t modem )
     {
     default:
     case MODEM_FSK:
+        SX1276SetSleep( );
+        SX1276Write( REG_OPMODE, ( SX1276Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
+
+        SX1276Write( REG_DIOMAPPING1, 0x00 );
+        SX1276Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
         break;
     case MODEM_LORA:
         SX1276SetSleep( );
@@ -1120,7 +1129,7 @@ void SX1276OnTimeoutIrq( void )
     }
 }
 
-void SX1276RadioFlagsIrq (void) {
+IRAM_ATTR void SX1276RadioFlagsIrq (void) {
     if (SX1276.irqFlags & RADIO_IRQ_FLAG_RX_TIMEOUT) {
         SX1276.irqFlags &= ~RADIO_IRQ_FLAG_RX_TIMEOUT;
         if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) )
@@ -1183,7 +1192,6 @@ IRAM_ATTR void SX1276OnDio0Irq( void )
     switch( SX1276.Settings.State )
     {
         case RF_RX_RUNNING:
-            //TimerStop( &RxTimeoutTimer );
             // RxDone interrupt
             switch( SX1276.Settings.Modem )
             {

esp32/3gpp/lib3GPP.c

@@ -838,7 +838,7 @@ int ppposInit()
 			tcpip_adapter_init();
 			tcpip_adapter_initialized = 1;
 		}
-		xTaskCreate(&pppos_client_task, "pppos_client_task", PPPOS_CLIENT_STACK_SIZE, NULL, 10, NULL);
+		xTaskCreatePinnedToCore(&pppos_client_task, "pppos_client_task", PPPOS_CLIENT_STACK_SIZE, NULL, 10, NULL, 1);
 		while (task_s == 0) {
 			vTaskDelay(10 / portTICK_RATE_MS);
 			xSemaphoreTake(pppos_mutex, PPPOSMUTEX_TIMEOUT);

esp32/Makefile

@@ -24,6 +24,7 @@ BTYPE ?= release
 LORA_BAND ?= USE_BAND_868
 
 BUILD = build/$(BOARD)/$(BTYPE)
+
 ifeq ($(BOARD), $(filter $(BOARD), LOPY FIPY))
     ifeq ($(LORA_BAND), USE_BAND_868)
         LORA_FREQ = 868
@@ -68,10 +69,9 @@ LDFLAGS += -Wl,-static -Wl,--undefined=uxTopUsedPriority -Wl,--gc-sections
 
 LIBS = -L$(ESP_IDF_COMP_PATH)/esp32/lib -L$(ESP_IDF_COMP_PATH)/esp32/ld -L$(ESP_IDF_COMP_PATH)/bt/lib \
        -L$(ESP_IDF_COMP_PATH)/esp32 -L$(ESP_IDF_COMP_PATH)/newlib/lib -Lbootloader \
-       -Llib -lnvs_flash -ltcpip_adapter -L$(BUILD) -lhal -lcore -lwps -lcoexist \
+       -Llib -lnvs_flash -ltcpip_adapter -L$(BUILD) -lhal -lcore -lwps -lcoexist -lstdc++ \
        -lnet80211 -lphy -lpp -lrtc -llog -lsmartconfig -lwpa -lwpa2 -lbtdm_app -lcxx -u __cxa_guard_dummy \
        -lsigfox -lspi_flash -lnvs_flash -lgcc -lnghttp -ldriver -lesp32 -lexpat -lpthread -lesp_adc_cal \
-       $(ESP_IDF_COMP_PATH)/esp32/libstdc++-psram-workaround.a \
        $(ESP_IDF_COMP_PATH)/newlib/lib/libm-psram-workaround.a \
        $(ESP_IDF_COMP_PATH)/newlib/lib/libc-psram-workaround.a \
        -lfreertos -ljson -ljsmn -llwip -lnewlib -lvfs -lopenssl -lmbedtls -lwpa_supplicant \

esp32/application.mk

@@ -15,6 +15,7 @@ APP_INC += -Imods
 APP_INC += -Itelnet
 APP_INC += -Iftp
 APP_INC += -Ilora
+APP_INC += -Ican
 APP_INC += -Ibootloader
 APP_INC += -Ifatfs/src/drivers
 APP_INC += -I$(BUILD)
@@ -113,6 +114,7 @@ APP_MODS_SRC_C = $(addprefix mods/,\
 	machspi.c \
 	machine_i2c.c \
 	machpwm.c \
+	machcan.c \
 	modmachine.c \
 	moduos.c \
 	modusocket.c \
@@ -121,6 +123,7 @@ APP_MODS_SRC_C = $(addprefix mods/,\
 	moduselect.c \
 	modutime.c \
 	modpycom.c \
+	moduqueue.c \
 	moduhashlib.c \
 	moducrypto.c \
 	machtimer.c \
@@ -250,6 +253,10 @@ APP_FTP_SRC_C = $(addprefix ftp/,\
 	updater.c \
 	)
 
+APP_CAN_SRC_C = $(addprefix can/,\
+	CAN.c \
+	)
+
 BOOT_SRC_C = $(addprefix bootloader/,\
 	bootloader.c \
 	bootmgr.c \
@@ -280,7 +287,7 @@ endif
 OBJ += $(addprefix $(BUILD)/, $(APP_MAIN_SRC_C:.c=.o) $(APP_HAL_SRC_C:.c=.o) $(APP_LIB_SRC_C:.c=.o))
 OBJ += $(addprefix $(BUILD)/, $(APP_MODS_SRC_C:.c=.o) $(APP_STM_SRC_C:.c=.o))
 OBJ += $(addprefix $(BUILD)/, $(APP_FATFS_SRC_C:.c=.o) $(APP_UTIL_SRC_C:.c=.o) $(APP_TELNET_SRC_C:.c=.o))
-OBJ += $(addprefix $(BUILD)/, $(APP_FTP_SRC_C:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(APP_FTP_SRC_C:.c=.o) $(APP_CAN_SRC_C:.c=.o))
 OBJ += $(BUILD)/pins.o
 
 BOOT_OBJ = $(addprefix $(BUILD)/, $(BOOT_SRC_C:.c=.o))

esp32/boards/LOPY4/mpconfigboard.h

@@ -16,9 +16,7 @@
 
 #define DEFAULT_AP_SSID                                         "lopy4-wlan"
 
-#define MICROPY_HW_FLASH_SIZE                                   (4 * 1024 * 1024)
-
-#define MICROPY_LPWAN_DIO_PIN                                   true
+#define MICROPY_LPWAN_DIO_PIN
 
 extern uint32_t micropy_hw_flash_size;
 

esp32/bootloader/bootloader.c

@@ -50,6 +50,7 @@
 #include "bootloader_flash.h"
 #include "bootmgr.h"
 #include "bootloader_random.h"
+#include "bootloader_clock.h"
 
 #include "flash_qio_mode.h"
 #include "mperror.h"
@@ -87,7 +88,6 @@ static void set_cache_and_start_app(uint32_t drom_addr,
 static void update_flash_config(const esp_image_header_t* pfhdr);
 static void vddsdio_configure();
 static void flash_gpio_configure();
-static void clock_configure(void);
 static void uart_console_configure(void);
 static void wdt_reset_check(void);
 
@@ -104,6 +104,11 @@ static void wdt_reset_check(void);
 //     mac[5] = mac_low;
 // }
 
+/*
+ * We arrive here after the ROM bootloader finished loading this second stage bootloader from flash.
+ * The hardware is mostly uninitialized, flash cache is down and the app CPU is in reset.
+ * We do have a stack, so we can do the initialization in C.
+ */
 void call_start_cpu0()
 {
     cpu_configure_region_protection();
@@ -489,7 +494,7 @@ static void bootloader_main()
 {
     vddsdio_configure();
     flash_gpio_configure();
-    clock_configure();
+    bootloader_clock_configure();
     uart_console_configure();
     wdt_reset_check();
     ESP_LOGI(TAG, "ESP-IDF %s 2nd stage bootloader");
@@ -754,12 +759,11 @@ static void vddsdio_configure()
 {
 #if CONFIG_BOOTLOADER_VDDSDIO_BOOST
     rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
-    if (cfg.tieh == 0) {    // 1.8V is used
+    if (cfg.enable == 1 && cfg.tieh == 0) {    // VDDSDIO regulator is enabled @ 1.8V
         cfg.drefh = 3;
         cfg.drefm = 3;
         cfg.drefl = 3;
         cfg.force = 1;
-        cfg.enable = 1;
         rtc_vddsdio_set_config(cfg);
         ets_delay_us(10); // wait for regulator to become stable
     }
@@ -806,24 +810,20 @@ static void IRAM_ATTR flash_gpio_configure()
 
     if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
         // For ESP32D2WD the SPI pins are already configured
-        ESP_LOGI(TAG, "Detected ESP32D2WD");
-        //flash clock signal should come from IO MUX.
+        // flash clock signal should come from IO MUX.
         PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
         SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
     } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
         // For ESP32PICOD2 the SPI pins are already configured
-        ESP_LOGI(TAG, "Detected ESP32PICOD2");
-        //flash clock signal should come from IO MUX.
+        // flash clock signal should come from IO MUX.
         PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
         SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
     } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
         // For ESP32PICOD4 the SPI pins are already configured
-        ESP_LOGI(TAG, "Detected ESP32PICOD4");
-        //flash clock signal should come from IO MUX.
+        // flash clock signal should come from IO MUX.
         PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
         SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
     } else {
-        ESP_LOGI(TAG, "Detected ESP32");
         const uint32_t spiconfig = ets_efuse_get_spiconfig();
         if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
             gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
@@ -849,36 +849,6 @@ static void IRAM_ATTR flash_gpio_configure()
     }
 }
 
-static void clock_configure(void)
-{
-    // ROM bootloader may have put a lot of text into UART0 FIFO.
-    // Wait for it to be printed.
-    // This is not needed on power on reset, when ROM bootloader is running at
-    // 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
-    // and will be done with the bootloader much earlier than UART FIFO is empty.
-    uart_tx_wait_idle(0);
-
-    /* Set CPU to 80MHz. Keep other clocks unmodified. */
-    rtc_cpu_freq_t cpu_freq = RTC_CPU_FREQ_80M;
-
-    /* On ESP32 rev 0, switching to 80MHz if clock was previously set to
-     * 240 MHz may cause the chip to lock up (see section 3.5 of the errata
-     * document). For rev. 0, switch to 240 instead if it was chosen in
-     * menuconfig.
-     */
-    uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
-    if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 &&
-            CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ == 240) {
-        cpu_freq = RTC_CPU_FREQ_240M;
-    }
-
-    rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
-    clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
-    clk_cfg.cpu_freq = cpu_freq;
-    clk_cfg.slow_freq = rtc_clk_slow_freq_get();
-    clk_cfg.fast_freq = rtc_clk_fast_freq_get();
-    rtc_clk_init(clk_cfg);
-}
 
 static void uart_console_configure(void)
 {