Output VCD file compliant with the standard

Author: oscargus

pymtl3/passes/tracing/VcdGenerationPass.py

@@ -204,7 +204,7 @@ def recurse_models( m, spaces ):
       # The first cycle VCD contains the default value
       bin_str = net[0]._dsl.Type().to_bits().bin()
 
-      print( f"b{bin_str} {net_symbol_mapping[i]}", file=vcd_file )
+      print( f"b{bin_str[2:]} {net_symbol_mapping[i]}", file=vcd_file )
 
       # Set this to be the last cycle value str
       last_values[i] = bin_str
@@ -221,7 +221,7 @@ def recurse_models( m, spaces ):
                       if i != vcd_clock_net_idx ]
 
     # Flip clock for the first cycle
-    print( '\n#0\nb0b1 {}\n'.format( clock_symbol ), file=vcd_file, flush=True )
+    print( '\n#0\n1{}\n'.format( clock_symbol ), file=vcd_file, flush=True )
 
     # Returns a dump_vcd function that is ready to be appended to _sched.
     # TODO: type check?
@@ -249,15 +249,15 @@ def dump_vcd_inner( s ):
         # We store strings instead of values ...
         if last_values[i] != net_bits_bin_str:
           last_values[i] = net_bits_bin_str
-          print( f'b{net_bits_bin_str} {symbol}', file=vcd_file )
+          print( f'b{net_bits_bin_str[2:]} {symbol}', file=vcd_file )
 
       # Flop clock at the end of cycle
       next_neg_edge = 100 * vcd_sim_ncycles + 50
-      print( f'\n#{next_neg_edge}\nb0b0 {clock_symbol}', file=vcd_file )
+      print( f'\n#{next_neg_edge}\n0{clock_symbol}', file=vcd_file )
 
       # Flip clock of the next cycle
       next_pos_edge = next_neg_edge + 50
-      print( f'#{next_pos_edge}\nb0b1 {clock_symbol}\n', file=vcd_file, flush=True )
+      print( f'#{next_pos_edge}\n1{clock_symbol}\n', file=vcd_file, flush=True )
       vcd_sim_ncycles += 1
 
     def gen_dump_vcd( s ):