Merge pull request #1017 from flit/refactor/dp_reset

DP reset refactoring

Author: flit

docs/command_reference.md

@@ -196,9 +196,9 @@ Write DP register.
 <tr><td>
 <a href="#reset"><tt>reset</tt></a>
 </td><td>
-[halt|-halt|-h]
+[halt|-halt|-h] [TYPE]
 </td><td>
-Reset the target.
+Reset the target, optionally specifying the reset type.
 </td></tr>
 
 <tr><td>
@@ -297,6 +297,15 @@ ADDR [LEN]
 Read 32-bit words.
 </td></tr>
 
+<tr><td>
+<a href="#read64"><tt>read64</tt></a>,
+<a href="#read64"><tt>rd</tt></a>
+</td><td>
+ADDR [LEN]
+</td><td>
+Read 64-bit words.
+</td></tr>
+
 <tr><td>
 <a href="#read8"><tt>read8</tt></a>,
 <a href="#read8"><tt>rb</tt></a>
@@ -332,6 +341,15 @@ ADDR DATA+
 Write 32-bit words to memory.
 </td></tr>
 
+<tr><td>
+<a href="#write64"><tt>write64</tt></a>,
+<a href="#write64"><tt>wd</tt></a>
+</td><td>
+ADDR DATA...
+</td><td>
+Write 64-bit double-words to memory.
+</td></tr>
+
 <tr><td>
 <a href="#write8"><tt>write8</tt></a>,
 <a href="#write8"><tt>wb</tt></a>
@@ -749,8 +767,8 @@ Write DP register.
 
 ##### `reset`
 
-**Usage**: [halt|-halt|-h] \
-Reset the target.
+**Usage**: [halt|-halt|-h] [TYPE] \
+Reset the target, optionally specifying the reset type. The reset type must be one of 'default', 'hw', 'sw', 'hardware', 'software', 'sw_sysresetreq', 'sw_vectreset', 'sw_emulated', 'sysresetreq', 'vectreset', or 'emulated'.
 
 
 ##### `unlock`
@@ -818,14 +836,21 @@ Load a binary file to an address in memory (RAM or flash). This command is depre
 
 **Aliases**: `rh` \
 **Usage**: ADDR [LEN] \
-Read 16-bit halfwords. Optional length parameter is the number of bytes to read. It must be divisible by 2. If the length is not provided, one halfword is read. The address may be unaligned.
+Read 16-bit halfwords. Optional length parameter is the number of bytes (not half-words) to read. It must be divisible by 2. If the length is not provided, one halfword is read. The address may be unaligned.
 
 
 ##### `read32`
 
 **Aliases**: `rw` \
 **Usage**: ADDR [LEN] \
-Read 32-bit words. Optional length parameter is the number of bytes to read. It must be divisible by 4. If the length is not provided, one word is read. The address may be unaligned.
+Read 32-bit words. Optional length parameter is the number of bytes (not words) to read. It must be divisible by 4. If the length is not provided, one word is read. The address may be unaligned.
+
+
+##### `read64`
+
+**Aliases**: `rd` \
+**Usage**: ADDR [LEN] \
+Read 64-bit words. Optional length parameter is the number of bytes (not double-words!) to read. It must be divisible by 8. If the length is not provided, one word is read. The address may be unaligned.
 
 
 ##### `read8`
@@ -855,6 +880,13 @@ Write 16-bit halfwords to memory. The data arguments are 16-bit halfwords in big
 Write 32-bit words to memory. The data arguments are 32-bit words in big-endian format and are written as little-endian. The address may be unaligned. Can write to both RAM and flash. Flash writes are subject to minimum write size and alignment, and the flash page must have been previously erased.
 
 
+##### `write64`
+
+**Aliases**: `wd` \
+**Usage**: ADDR DATA... \
+Write 64-bit double-words to memory. The data arguments are 64-bit words in big-endian format and are written as little-endian. The address may be unaligned. Can write to both RAM and flash. Flash writes are subject to minimum write size and alignment, and the flash page must have been previously erased.
+
+
 ##### `write8`
 
 **Aliases**: `wb` \

pyocd/commands/commander.py

@@ -81,6 +81,10 @@ def run(self):
                             status, self.session.board.unique_id))
                     except exceptions.TransferFaultError:
                         pass
+                else:
+                    # Say what we're connected to, but without status.
+                    print("Connected to %s [no init mode]: %s" % (self.context.target.part_number,
+                        self.session.board.unique_id))
 
                 # Run the REPL interface.
                 console = PyocdRepl(self.context)

pyocd/commands/commands.py

@@ -29,7 +29,10 @@
 from ..flash.file_programmer import FileProgrammer
 from ..gdbserver.gdbserver import GDBServer
 from ..utility import conversion
-from ..utility.cmdline import UniquePrefixMatcher
+from ..utility.cmdline import (
+    UniquePrefixMatcher,
+    convert_reset_type,
+    )
 from ..utility.hex import (
     format_hex_width,
     dump_hex_data_to_str,
@@ -328,20 +331,29 @@ class ResetCommand(CommandBase):
             'names': ['reset'],
             'group': 'standard',
             'category': 'device',
-            'nargs': [0, 1],
-            'usage': "[halt|-halt|-h]",
-            'help': "Reset the target.",
+            'nargs': [0, 1, 2],
+            'usage': "[halt|-halt|-h] [TYPE]",
+            'help': "Reset the target, optionally specifying the reset type.",
+            'extra_help': "The reset type must be one of 'default', 'hw', 'sw', 'hardware', 'software', "
+                          "'sw_sysresetreq', 'sw_vectreset', 'sw_emulated', 'sysresetreq', 'vectreset', "
+                          "or 'emulated'.",
+
             }
 
     def parse(self, args):
         self.do_halt = False
-        if len(args) == 1:
+        self.reset_type = None
+        if len(args) >= 1:
             self.do_halt = (args[0] in ('-h', '--halt', 'halt'))
+            if self.do_halt:
+                args.pop(0)
+        if len(args) == 1:
+            self.reset_type = convert_reset_type(args[0])
 
     def execute(self):
         if self.do_halt:
             self.context.write("Resetting target with halt")
-            self.context.selected_core.reset_and_halt()
+            self.context.selected_core.reset_and_halt(self.reset_type)
 
             status = self.context.selected_core.get_state()
             if status != Target.State.HALTED:
@@ -350,7 +362,7 @@ def execute(self):
                 self.context.write("Successfully halted device on reset")
         else:
             self.context.write("Resetting target")
-            self.context.selected_core.reset()
+            self.context.selected_core.reset(self.reset_type)
 
 class DisassembleCommand(CommandBase):
     INFO = {
@@ -428,7 +440,7 @@ class Read16Command(ReadCommandBase):
             'nargs': [1, 2],
             'usage': "ADDR [LEN]",
             'width': 16,
-            'help': "Read 16-bit halfwords",
+            'help': "Read 16-bit halfwords.",
             'extra_help': "Optional length parameter is the number of bytes (not half-words) to read. It "
                            "must be divisible by 2. If the length is not provided, one halfword is read. "
                            "The address may be unaligned."
@@ -442,21 +454,21 @@ class Read32Command(ReadCommandBase):
             'nargs': [1, 2],
             'usage': "ADDR [LEN]",
             'width': 32,
-            'help': "Read 32-bit words",
+            'help': "Read 32-bit words.",
             'extra_help': "Optional length parameter is the number of bytes (not words) to read. It must be "
                            "divisible by 4. If the length is not provided, one word is read. "
                            "The address may be unaligned.",
             }
 
 class Read64Command(ReadCommandBase):
     INFO = {
-            'names': ['read64', 'r64', 'rd'],
+            'names': ['read64', 'rd'],
             'group': 'standard',
             'category': 'memory',
             'nargs': [1, 2],
             'usage': "ADDR [LEN]",
             'width': 64,
-            'help': "Read 64-bit words",
+            'help': "Read 64-bit words.",
             'extra_help': "Optional length parameter is the number of bytes (not double-words!) to read. "
                            "It must be divisible by 8. If the length is not provided, one word is read. "
                            "The address may be unaligned."
@@ -549,13 +561,13 @@ class Write32Command(WriteCommandBase):
 
 class Write64Command(WriteCommandBase):
     INFO = {
-            'names': ['write64', 'w64', 'wd'],
+            'names': ['write64', 'wd'],
             'group': 'standard',
             'category': 'memory',
             'nargs': '*',
             'usage': "ADDR DATA...",
             'width': 64,
-            'help': "Write 64-bit double-words to memory",
+            'help': "Write 64-bit double-words to memory.",
             'extra_help': "The data arguments are 64-bit words in big-endian format and are written as "
                           "little-endian. The address may be unaligned. Can write to both RAM and flash. "
                           "Flash writes are subject to minimum write size and alignment, and the flash "

pyocd/commands/execution_context.py

@@ -202,7 +202,7 @@ def attach_session(self, session):
         @retval False An error occurred when opening the session or initing the context state.
         """
         assert self._session is None
-        assert session.is_open
+        assert session.is_open or self._no_init
         self._session = session
 
         # Select the first core's MEM-AP by default.

pyocd/commands/values.py

@@ -243,7 +243,13 @@ def modify(self, args):
             raise exceptions.CommandError("missing reset state")
         state = int(args[0], base=0)
         self.context.writef("nRESET = {}", state)
-        self.context.probe.assert_reset((state == 0))
+        
+        # Use the probe to assert reset if the DP doesn't exist for some reason, otherwise
+        # use the DP so reset notifications are sent.
+        if self.context.target.dp is None:
+            self.context.probe.assert_reset((state == 0))
+        else:
+            self.context.target.dp.assert_reset((state == 0))
 
 class SessionOptionValue(ValueBase):
     INFO = {

pyocd/core/soc_target.py

@@ -211,7 +211,11 @@ def remove_watchpoint(self, addr, size, type):
     def reset(self, reset_type=None):
         # Perform a hardware reset if there is not a core.
         if self.selected_core is None:
-            self.session.probe.reset()
+            # Use the probe to reset if the DP doesn't exist yet.
+            if self.dp is None:
+                self.session.probe.reset()
+            else:
+                self.dp.reset()
             return
         self.selected_core.reset(reset_type)
 

pyocd/coresight/ap.py

@@ -20,6 +20,7 @@
 from enum import Enum
 
 from ..core import (exceptions, memory_interface)
+from ..core.target import Target
 from ..utility.concurrency import locked
 
 LOG = logging.getLogger(__name__)
@@ -413,10 +414,6 @@ def read_reg(self, addr, now=True):
     def write_reg(self, addr, data):
         self.dp.write_ap(self.address.address + addr, data)
 
-    def reset_did_occur(self):
-        """! @brief Invoked by the DebugPort to inform APs that a reset was performed."""
-        pass
-    
     def lock(self):
         """! @brief Lock the AP from access by other threads."""
         self.dp.probe.lock()
@@ -523,6 +520,9 @@ def __init__(self, dp, ap_address, idr=None, name="", flags=0, cmpid=None):
             self.read_memory = self._read_memory
             self.write_memory_block32 = self._write_memory_block32
             self.read_memory_block32 = self._read_memory_block32
+        
+        # Subscribe to reset events.
+        self.dp.session.subscribe(self._reset_did_occur, (Target.Event.PRE_RESET, Target.Event.POST_RESET))
 
     @property
     def supported_transfer_sizes(self):
@@ -707,7 +707,7 @@ def find_components(self):
                     self.rom_table.init()
         except exceptions.TransferError as error:
             LOG.error("Transfer error while reading %s ROM table: %s", self.short_description, error,
-                exc_info=self.dp.target.session.log_tracebacks)
+                exc_info=self.dp.session.log_tracebacks)
 
     @property
     def implemented_hprot_mask(self):
@@ -837,13 +837,17 @@ def write_reg(self, addr, data):
         except exceptions.ProbeError:
             # Invalidate cached CSW on exception.
             if ap_regaddr == self._reg_offset + MEM_AP_CSW:
-                self._cached_csw = -1
+                self._invalidate_cache()
             raise
 
-    def reset_did_occur(self):
-        """! @copydoc AccessPort.reset_did_occur()"""
-        # TODO use notifications to invalidate CSW cache.
+    def _invalidate_cache(self):
+        """! @brief Invalidate cached registers associated with this AP."""
         self._cached_csw = -1
+    
+    def _reset_did_occur(self, notification):
+        """! @brief Handles reset notifications to invalidate CSW cache."""
+        # We clear the cache on all resets just to be safe.
+        self._invalidate_cache()
 
     @locked
     def _write_memory(self, addr, data, transfer_size=32):
@@ -1045,7 +1049,7 @@ def _read_memory_block32(self, addr, size):
 
     def _handle_error(self, error, num):
         self.dp._handle_error(error, num)
-        self._cached_csw = -1
+        self._invalidate_cache()
 
 class AHB_AP(MEM_AP):
     """! @brief AHB-AP access port subclass.

pyocd/coresight/coresight_target.py

@@ -105,10 +105,10 @@ def pre_connect(self):
         mode = self.session.options.get('connect_mode')
         if mode == 'pre-reset':
             LOG.info("Performing connect pre-reset")
-            self.session.probe.reset()
+            self.dp.reset()
         elif mode == 'under-reset':
             LOG.info("Asserting reset prior to connect")
-            self.session.probe.assert_reset(True)
+            self.dp.assert_reset(True)
 
     def perform_halt_on_connect(self):
         """! @brief Halt cores.
@@ -139,7 +139,7 @@ def post_connect(self):
         mode = self.session.options.get('connect_mode')
         if mode == 'under-reset':
             LOG.info("Deasserting reset post connect")
-            self.session.probe.assert_reset(False)
+            self.dp.assert_reset(False)
 
             LOG.debug("Clearing reset catch")
             # Apply to all cores.

pyocd/coresight/cortex_m.py

@@ -706,7 +706,7 @@ def _perform_reset(self, reset_type):
         """! @brief Perform a reset of the specified type."""
         assert isinstance(reset_type, Target.ResetType)
         if reset_type is Target.ResetType.HW:
-            self.session.probe.reset()
+            self.session.target.dp.reset()
         elif reset_type is Target.ResetType.SW_EMULATED:
             self._perform_emulated_reset()
         else:
@@ -739,12 +739,14 @@ def reset(self, reset_type=None):
         
         After a call to this function, the core is running.
         """
-        self.session.notify(Target.Event.PRE_RESET, self)
-
         reset_type = self._get_actual_reset_type(reset_type)
 
         LOG.debug("reset, core %d, type=%s", self.core_number, reset_type.name)
 
+        # The HW reset type is passed to the DP, which itself sends reset notifications.
+        if reset_type is not Target.ResetType.HW:
+            self.session.notify(Target.Event.PRE_RESET, self)
+
         self._run_token += 1
 
         # Give the delegate a chance to overide reset. If the delegate returns True, then it
@@ -766,7 +768,8 @@ def reset(self, reset_type=None):
                     self.flush()
                     sleep(0.01)
 
-        self.session.notify(Target.Event.POST_RESET, self)
+        if reset_type is not Target.ResetType.HW:
+            self.session.notify(Target.Event.POST_RESET, self)
 
     def set_reset_catch(self, reset_type=None):
         """! @brief Prepare to halt core on reset."""