|
1 | 1 | # pyOCD debugger |
2 | | -# Copyright (c) 2015-2020 Arm Limited |
| 2 | +# Copyright (c) 2015-2021 Arm Limited |
3 | 3 | # SPDX-License-Identifier: Apache-2.0 |
4 | 4 | # |
5 | 5 | # Licensed under the Apache License, Version 2.0 (the "License"); |
|
52 | 52 | # Known devtype values |
53 | 53 | # 0x11 = TPIU |
54 | 54 | # 0x21 = ETB |
| 55 | +# 0x31 = MTB |
55 | 56 | # 0x12 = Trace funnel (CSFT) |
| 57 | +# 0x32 = TMC |
56 | 58 | # 0x13 = CPU trace source (ETM, MTB?) |
57 | | -# 0x16 = PMU |
58 | 59 | # 0x43 = ITM |
59 | 60 | # 0x14 = ECT/CTI/CTM |
60 | | -# 0x31 = MTB |
61 | | -# 0x32 = TMC |
62 | 61 | # 0x34 = Granular Power Requestor |
| 62 | +# 0x15 = CPU debug |
| 63 | +# 0x16 = PMU |
63 | 64 |
|
64 | 65 | ## Pairs a component name with a factory method. |
65 | 66 | CmpInfo = namedtuple('CmpInfo', 'name factory') |
66 | 67 |
|
67 | 68 | ## Map from (designer, class, part, devtype, archid) to component name and class. |
68 | 69 | COMPONENT_MAP = { |
| 70 | + # Archid-only entries |
| 71 | + # Designer|Component Class |Part |Type |Archid |
| 72 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x0a00) : CmpInfo('RASv1', None ), |
| 73 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x1a01) : CmpInfo('ITMv2', ITM.factory ), |
| 74 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x1a02) : CmpInfo('DWTv2', DWTv2.factory ), |
| 75 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x1a03) : CmpInfo('FPBv2', FPB.factory ), |
| 76 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x2a04) : CmpInfo('v8-M Debug', CortexM_v8M.factory ), |
| 77 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x6a05) : CmpInfo('v8-R Debug', None ), |
| 78 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x0a06) : CmpInfo('v8-M PMUv1', None ), |
| 79 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x4a13) : CmpInfo('ETMv4', None ), |
| 80 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x1a14) : CmpInfo('CTIv2', None ), |
| 81 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x6a15) : CmpInfo('v8.0-A Debug', None ), |
| 82 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x7a15) : CmpInfo('v8.1-A Debug', None ), |
| 83 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x8a15) : CmpInfo('v8.2-A Debug', None ), |
| 84 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x2a16) : CmpInfo('PMUv2', None ), |
| 85 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x0a17) : CmpInfo('MEM-APv2', AccessPort.create ), |
| 86 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x0a34) : CmpInfo('GPR', GPR.factory ), |
| 87 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x0a55) : CmpInfo('PMCv0/1', None ), |
| 88 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x2a56) : CmpInfo('SMMUv3', None ), |
| 89 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x0a63) : CmpInfo('STMv1', None ), |
| 90 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x0a66) : CmpInfo('AMUv1', None ), |
| 91 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x0a75) : CmpInfo('ELA', None ), |
| 92 | + (ARM_ID, CORESIGHT_CLASS, None, None, 0x0af7) : CmpInfo('ROM', None ), |
| 93 | + # Full ID entries |
69 | 94 | # Designer|Component Class |Part |Type |Archid |
70 | | - (ARM_ID, CORESIGHT_CLASS, 0x193, 0x00, 0x0a57) : CmpInfo('CS-600 TSGEN', None ), |
| 95 | + (ARM_ID, CORESIGHT_CLASS, 0x193, 0x00, 0x0a57) : CmpInfo('CS-600 TSGEN', None ), |
71 | 96 | (ARM_ID, CORESIGHT_CLASS, 0x906, 0x14, 0) : CmpInfo('CTI', None ), |
72 | 97 | (ARM_ID, CORESIGHT_CLASS, 0x907, 0x21, 0) : CmpInfo('ETB', None ), |
73 | 98 | (ARM_ID, CORESIGHT_CLASS, 0x908, 0x12, 0) : CmpInfo('CSTF', None ), |
74 | 99 | (ARM_ID, CORESIGHT_CLASS, 0x912, 0x11, 0) : CmpInfo('TPIU', TPIU.factory ), |
75 | 100 | (ARM_ID, CORESIGHT_CLASS, 0x923, 0x11, 0) : CmpInfo('TPIU-M3', TPIU.factory ), |
76 | 101 | (ARM_ID, CORESIGHT_CLASS, 0x924, 0x13, 0) : CmpInfo('ETM-M3', None ), |
77 | 102 | (ARM_ID, CORESIGHT_CLASS, 0x925, 0x13, 0) : CmpInfo('ETM-M4', None ), |
| 103 | + (ARM_ID, CORESIGHT_CLASS, 0x926, 0x13, 0) : CmpInfo('ETM-SC300', None ), |
| 104 | + (ARM_ID, CORESIGHT_CLASS, 0x927, 0x11, 0) : CmpInfo('TPIU-SC300',None ), |
78 | 105 | (ARM_ID, CORESIGHT_CLASS, 0x932, 0x31, 0x0a31) : CmpInfo('MTB-M0+', None ), |
79 | 106 | (ARM_ID, CORESIGHT_CLASS, 0x950, 0x13, 0) : CmpInfo('PTM-A9', None ), |
80 | | - (ARM_ID, CORESIGHT_CLASS, 0x961, 0x32, 0) : CmpInfo('TMC ETF', None ), # Trace Memory Controller |
| 107 | + (ARM_ID, CORESIGHT_CLASS, 0x961, 0x32, 0) : CmpInfo('ETF', None ), # Trace Memory Controller ETF |
| 108 | + (ARM_ID, CORESIGHT_CLASS, 0x962, 0x63, 0x0a63) : CmpInfo('STM', None ), # System Trace Macrocell |
| 109 | + (ARM_ID, CORESIGHT_CLASS, 0x963, 0x63, 0x0a63) : CmpInfo('STM-500', None ), # System Trace Macrocell |
81 | 110 | (ARM_ID, CORESIGHT_CLASS, 0x975, 0x13, 0x4a13) : CmpInfo('ETM-M7', None ), |
82 | 111 | (ARM_ID, CORESIGHT_CLASS, 0x9a0, 0x16, 0) : CmpInfo('PMU-A9', None ), |
83 | 112 | (ARM_ID, CORESIGHT_CLASS, 0x9a1, 0x11, 0) : CmpInfo('TPIU-M4', TPIU.factory ), |
84 | 113 | (ARM_ID, CORESIGHT_CLASS, 0x9a3, 0x13, 0x0) : CmpInfo('MTB-M0', None ), |
85 | 114 | (ARM_ID, CORESIGHT_CLASS, 0x9a4, 0x34, 0x0a34) : CmpInfo('GPR', GPR.factory ), # Granular Power Requestor |
86 | | - (ARM_ID, CORESIGHT_CLASS, 0x9a6, 0x14, 0x1a14) : CmpInfo('CTI', None ), |
| 115 | + (ARM_ID, CORESIGHT_CLASS, 0x9a5, 0x16, 0) : CmpInfo('PMU-A5', None ), |
| 116 | + (ARM_ID, CORESIGHT_CLASS, 0x9a6, 0x14, 0x1a14) : CmpInfo('CTI-M0+', None ), |
| 117 | + (ARM_ID, CORESIGHT_CLASS, 0x9a7, 0x16, 0) : CmpInfo('PMU-A7', None ), |
| 118 | + (ARM_ID, CORESIGHT_CLASS, 0x9a9, 0x11, 0) : CmpInfo('TPIU-M7', TPIU.factory ), |
| 119 | + (ARM_ID, CORESIGHT_CLASS, 0x9ba, 0x55, 0x0a55) : CmpInfo('PMC-100', None ), # Programmable MBIST Controller |
| 120 | + (ARM_ID, CORESIGHT_CLASS, 0x9db, 0x13, 0x4a13) : CmpInfo('ETM-A32', None ), # ETMv4 |
| 121 | + (ARM_ID, CORESIGHT_CLASS, 0x9db, 0x14, 0x1a14) : CmpInfo('CTI-A32', None ), # CTIv2 |
| 122 | + (ARM_ID, CORESIGHT_CLASS, 0x9db, 0x16, 0x2a16) : CmpInfo('PMU-A32', None ), # PMUv3 |
87 | 123 | (ARM_ID, CORESIGHT_CLASS, 0x9e2, 0x00, 0x0a17) : CmpInfo('CS-600 APB-AP', AccessPort.create ), |
88 | 124 | (ARM_ID, CORESIGHT_CLASS, 0x9e3, 0x00, 0x0a17) : CmpInfo('CS-600 AHB-AP', AccessPort.create ), |
89 | 125 | (ARM_ID, CORESIGHT_CLASS, 0x9e4, 0x00, 0x0a17) : CmpInfo('CS-600 AXI-AP', AccessPort.create ), |
90 | 126 | (ARM_ID, CORESIGHT_CLASS, 0x9e5, 0x00, 0x0a47) : CmpInfo('CS-600 APv1 Adapter', AccessPort.create ), |
91 | 127 | (ARM_ID, CORESIGHT_CLASS, 0x9e6, 0x00, 0x0a27) : CmpInfo('CS-600 JTAG-AP', AccessPort.create ), |
92 | 128 | (ARM_ID, CORESIGHT_CLASS, 0x9e7, 0x11, 0) : CmpInfo('CS-600 TPIU', TPIU.factory ), |
93 | | - (ARM_ID, CORESIGHT_CLASS, 0x9e8, 0x21, 0) : CmpInfo('CS-600 TMC ETR', None ), |
94 | | - (ARM_ID, CORESIGHT_CLASS, 0x9e9, 0x21, 0) : CmpInfo('CS-600 TMC ETB', None ), |
95 | | - (ARM_ID, CORESIGHT_CLASS, 0x9ea, 0x32, 0) : CmpInfo('CS-600 TMC ETF', None ), |
| 129 | + (ARM_ID, CORESIGHT_CLASS, 0x9e8, 0x21, 0) : CmpInfo('CS-600 ETR', None ), |
| 130 | + (ARM_ID, CORESIGHT_CLASS, 0x9e9, 0x21, 0) : CmpInfo('CS-600 ETB', None ), |
| 131 | + (ARM_ID, CORESIGHT_CLASS, 0x9ea, 0x32, 0) : CmpInfo('CS-600 ETF', None ), |
96 | 132 | (ARM_ID, CORESIGHT_CLASS, 0x9eb, 0x12, 0) : CmpInfo('CS-600 ATB Funnel', None ), |
97 | 133 | (ARM_ID, CORESIGHT_CLASS, 0x9ec, 0x22, 0) : CmpInfo('CS-600 ATB Replicator', None ), |
98 | 134 | (ARM_ID, CORESIGHT_CLASS, 0x9ed, 0x14, 0x1a14) : CmpInfo('CS-600 CTI', None ), |
99 | 135 | (ARM_ID, CORESIGHT_CLASS, 0x9ee, 0x00, 0) : CmpInfo('CS-600 CATU', None ), |
100 | 136 | (ARM_ID, CORESIGHT_CLASS, 0x9ef, 0x00, 0x0a57) : CmpInfo('CS-600 SDC-600', SDC600.factory ), |
| 137 | + (ARM_ID, CORESIGHT_CLASS, 0x9f0, 0x00, 0) : CmpInfo('GPIO Control', None ), |
101 | 138 | (ARM_ID, CORESIGHT_CLASS, 0xc05, 0x15, 0) : CmpInfo('CPU-A5', None ), |
102 | 139 | (ARM_ID, CORESIGHT_CLASS, 0xc07, 0x15, 0) : CmpInfo('CPU-A7', None ), |
103 | 140 | (ARM_ID, CORESIGHT_CLASS, 0xc08, 0x15, 0) : CmpInfo('CPU-A8', None ), |
104 | 141 | (ARM_ID, CORESIGHT_CLASS, 0xc09, 0x15, 0) : CmpInfo('CPU-A9', None ), |
105 | 142 | (ARM_ID, CORESIGHT_CLASS, 0xc0d, 0x15, 0) : CmpInfo('CPU-A12', None ), |
106 | 143 | (ARM_ID, CORESIGHT_CLASS, 0xc0e, 0x15, 0) : CmpInfo('CPU-A17', None ), |
107 | 144 | (ARM_ID, CORESIGHT_CLASS, 0xc0f, 0x15, 0) : CmpInfo('CPU-A15', None ), |
108 | | - (ARM_ID, CORESIGHT_CLASS, 0x9a9, 0x11, 0) : CmpInfo('TPIU-M7', TPIU.factory ), |
| 145 | + (ARM_ID, CORESIGHT_CLASS, 0xd01, 0x15, 0x6a15) : CmpInfo('CPU-A32', None ), |
| 146 | + (ARM_ID, CORESIGHT_CLASS, 0xd02, 0x15, 0x6a15) : CmpInfo('CPU-A34', None ), |
| 147 | + (ARM_ID, CORESIGHT_CLASS, 0xd03, 0x15, 0x6a15) : CmpInfo('CPU-A53', None ), |
| 148 | + (ARM_ID, CORESIGHT_CLASS, 0xd04, 0x15, 0x6a15) : CmpInfo('CPU-A35', None ), |
| 149 | + (ARM_ID, CORESIGHT_CLASS, 0xd05, 0x15, 0x6a15) : CmpInfo('CPU-A55', None ), |
| 150 | + (ARM_ID, CORESIGHT_CLASS, 0xd06, 0x15, 0x6a15) : CmpInfo('CPU-A65', None ), |
| 151 | + (ARM_ID, CORESIGHT_CLASS, 0xd07, 0x15, 0x6a15) : CmpInfo('CPU-A57', None ), |
| 152 | + (ARM_ID, CORESIGHT_CLASS, 0xd08, 0x15, 0x6a15) : CmpInfo('CPU-A72', None ), |
| 153 | + (ARM_ID, CORESIGHT_CLASS, 0xd09, 0x15, 0x6a15) : CmpInfo('CPU-A73', None ), |
| 154 | + (ARM_ID, CORESIGHT_CLASS, 0xd0a, 0x15, 0x6a15) : CmpInfo('CPU-A75', None ), |
| 155 | + (ARM_ID, CORESIGHT_CLASS, 0xd0b, 0x15, 0x6a15) : CmpInfo('CPU-A76', None ), |
109 | 156 | (ARM_ID, CORESIGHT_CLASS, 0xd20, 0x11, 0) : CmpInfo('TPIU-M23', TPIU.factory ), |
110 | 157 | (ARM_ID, CORESIGHT_CLASS, 0xd20, 0x13, 0) : CmpInfo('ETM-M23', None ), |
111 | 158 | (ARM_ID, CORESIGHT_CLASS, 0xd20, 0x31, 0x0a31) : CmpInfo('MTB-M23', None ), # M23 |
112 | | - (ARM_ID, CORESIGHT_CLASS, 0xd20, 0x00, 0x1a02) : CmpInfo('DWT', DWTv2.factory ), # M23 |
113 | | - (ARM_ID, CORESIGHT_CLASS, 0xd20, 0x00, 0x1a03) : CmpInfo('BPU', FPB.factory ), # M23 |
114 | | - (ARM_ID, CORESIGHT_CLASS, 0xd20, 0x14, 0x1a14) : CmpInfo('CTI', None ), # M23 |
| 159 | + (ARM_ID, CORESIGHT_CLASS, 0xd20, 0x00, 0x1a02) : CmpInfo('DWT-M23', DWTv2.factory ), # M23 |
| 160 | + (ARM_ID, CORESIGHT_CLASS, 0xd20, 0x00, 0x1a03) : CmpInfo('BPU-M23', FPB.factory ), # M23 |
| 161 | + (ARM_ID, CORESIGHT_CLASS, 0xd20, 0x14, 0x1a14) : CmpInfo('CTI-M23', None ), # M23 |
115 | 162 | (ARM_ID, CORESIGHT_CLASS, 0xd20, 0x00, 0x2a04) : CmpInfo('SCS-M23', CortexM_v8M.factory ), # M23 |
116 | 163 | (ARM_ID, CORESIGHT_CLASS, 0xd21, 0x31, 0x0a31) : CmpInfo('MTB-M33', None ), # M33 |
117 | | - (ARM_ID, CORESIGHT_CLASS, 0xd21, 0x43, 0x1a01) : CmpInfo('ITM', ITM.factory ), # M33 |
118 | | - (ARM_ID, CORESIGHT_CLASS, 0xd21, 0x00, 0x1a02) : CmpInfo('DWT', DWTv2.factory ), # M33 |
119 | | - (ARM_ID, CORESIGHT_CLASS, 0xd21, 0x00, 0x1a03) : CmpInfo('BPU', FPB.factory ), # M33 |
120 | | - (ARM_ID, CORESIGHT_CLASS, 0xd21, 0x14, 0x1a14) : CmpInfo('CTI', None ), # M33 |
| 164 | + (ARM_ID, CORESIGHT_CLASS, 0xd21, 0x43, 0x1a01) : CmpInfo('ITM-M33', ITM.factory ), # M33 |
| 165 | + (ARM_ID, CORESIGHT_CLASS, 0xd21, 0x00, 0x1a02) : CmpInfo('DWT-M33', DWTv2.factory ), # M33 |
| 166 | + (ARM_ID, CORESIGHT_CLASS, 0xd21, 0x00, 0x1a03) : CmpInfo('BPU-M33', FPB.factory ), # M33 |
| 167 | + (ARM_ID, CORESIGHT_CLASS, 0xd21, 0x14, 0x1a14) : CmpInfo('CTI-M33', None ), # M33 |
121 | 168 | (ARM_ID, CORESIGHT_CLASS, 0xd21, 0x00, 0x2a04) : CmpInfo('SCS-M33', CortexM_v8M.factory ), # M33 |
122 | 169 | (ARM_ID, CORESIGHT_CLASS, 0xd21, 0x13, 0x4a13) : CmpInfo('ETM-M33', None ), # M33 |
123 | 170 | (ARM_ID, CORESIGHT_CLASS, 0xd21, 0x11, 0) : CmpInfo('TPIU-M33', TPIU.factory ), # M33 |
|
0 commit comments