Merge pull request #1022 from ttt-t3r/lpc55s69-add-unlock

Added code to unlock AP for lpc55s69

Author: flit

docs/options.md

@@ -14,6 +14,14 @@ processed. The consequence of this is that these options cannot be set in a YAML
 
 <tr><th>Option Name</th><th>Type</th><th>Default</th><th>Description</th></tr>
 
+<tr><td>adi.v5.max_invalid_ap_count</td>
+<td>int</td>
+<td>3</td>
+<td>
+If this number of invalid APs is found in a row, then AP scanning will stop. The 'scan_all_aps' option
+takes precedence over this option if set.
+</td></tr>
+
 <tr><td>allow_no_cores</td>
 <td>bool</td>
 <td>False</td>

pyocd/core/options.py

@@ -22,6 +22,9 @@
 ## @brief Definitions of the builtin options.
 BUILTIN_OPTIONS = [
     # Common options
+    OptionInfo('adi.v5.max_invalid_ap_count', int, 3,
+        "If this number of invalid APs is found in a row, then AP scanning will stop. The 'scan_all_aps' option "
+        "takes precedence over this option if set."),
     OptionInfo('allow_no_cores', bool, False,
         "Prevents raising an error if no core were found after CoreSight discovery."),
     OptionInfo('auto_unlock', bool, True,

pyocd/coresight/ap.py

@@ -528,6 +528,39 @@ def __init__(self, dp, ap_address, idr=None, name="", flags=0, cmpid=None):
     def supported_transfer_sizes(self):
         """! @brief Tuple of transfer sizes supported by this AP."""
         return self._transfer_sizes
+    
+    @property
+    def is_enabled(self):
+        """! @brief Whether any memory transfers are allowed by this AP.
+        
+        Memory transfers may be disabled by an input signal to the AP. This is often done when debug security
+        is enabled on the device, to disallow debugger access to internal memory.
+        """
+        return self.is_enabled_for(Target.SecurityState.NONSECURE)
+    
+    def is_enabled_for(self, security_state):
+        """! @brief Checks whether memory transfers are allowed by this AP for the given security state.
+        
+        Memory transfers may be disabled by an input signal to the AP. This is often done when debug security
+        is enabled on the device, to disallow debugger access to internal memory.
+        
+        @param self The AP instance.
+        @param security_state One of the @ref pyocd.core.target.Target.SecurityState "SecurityState" enums.
+        @return Boolean indicating whether memory transfers can be performed in the requested security state. You
+            may change the security state used for transfers with the hnonsec property and hnonsec_lock() method.
+        """
+        assert isinstance(security_state, Target.SecurityState)
+        
+        # Call to superclass to read CSW. We want to bypass our CSW cache since the enable signal can change
+        # asynchronously.
+        csw = AccessPort.read_reg(self, self._reg_offset + MEM_AP_CSW)
+        if security_state is Target.SecurityState.NONSECURE:
+            # Nonsecure transfers are always allowed when security transfers are enabled.
+            return (csw & (CSW_DEVICEEN | CSW_SDEVICEEN)) != 0
+        elif security_state is Target.SecurityState.SECURE:
+            return (csw & CSW_SDEVICEEN) != 0
+        else:
+            assert False, "unsupported security state"
 
     @locked
     def init(self):
@@ -694,6 +727,10 @@ def _init_rom_table_base():
     def find_components(self):
         try:
             if self.has_rom_table:
+                if not self.is_enabled:
+                    LOG.warning("Skipping CoreSight discovery for %s because it is disabled", self.short_description)
+                    return
+                
                 # Import locally to work around circular import.
                 from .rom_table import (CoreSightComponentID, ROMTable)
 

pyocd/coresight/discovery.py

@@ -51,9 +51,13 @@ def discover(self):
         raise NotImplementedError()
 
     def _create_component(self, cmpid):
-        LOG.debug("Creating %s component", cmpid.name)
-        cmp = cmpid.factory(cmpid.ap, cmpid, cmpid.address)
-        cmp.init()
+        try:
+            LOG.debug("Creating %s component", cmpid.name)
+            cmp = cmpid.factory(cmpid.ap, cmpid, cmpid.address)
+            cmp.init()
+        except exceptions.Error as err:
+            LOG.error("Error attempting to create component %s: %s", cmpid.name, err,
+                    exc_info=self.session.log_tracebacks)
 
     def _create_cores(self):
         self._apply_to_all_components(self._create_component,
@@ -127,7 +131,7 @@ def _find_aps(self):
                     invalid_count = 0
                 elif not self.session.options.get('scan_all_aps'):
                     invalid_count += 1
-                    if invalid_count == 2:
+                    if invalid_count == self.session.options.get('adi.v5.max_invalid_ap_count'):
                         break
             except exceptions.Error as e:
                 LOG.error("Exception while probing AP#%d: %s", apsel, e,

pyocd/target/family/__init__.py

@@ -18,6 +18,7 @@
 from collections import namedtuple
 
 from . import target_kinetis
+from . import target_lpc5500
 from . import target_nRF52
 
 ## @brief Container for family matching information.
@@ -32,6 +33,7 @@
 # 'DsubFamily' (if present) attributes, or the 'Dname' part number. The comparisons are performed in
 # order from specific to general, starting with the part number.
 FAMILIES = [
+    FamilyInfo("NXP",                   re.compile(r'LPC55S?[0-9]{2}.*'),   target_lpc5500.LPC5500Family  ),
     FamilyInfo("NXP",                   re.compile(r'MK[LEVWS]?.*'),    target_kinetis.Kinetis  ),
     FamilyInfo("Nordic Semiconductor",  re.compile(r'nRF52[0-9]+.*'),   target_nRF52.NRF52      ),
     ]