DAP: send notifications on reset, use for register cache invalidation.

flit · flit · commit be325cf79ab3 · 2020-11-29T15:42:22.000-06:00
- The DP reset() and assert_reset() methods send pre- and post-reset
  notifications.
- AccessPort and DebugPort classes subscribe to reset events in order
  to invalidate their register caches, replacing the
  AccessPort.reset_did_occur() method.
- JLinkProbe uses reset notifications to invalidate its DP_SELECT cache.
diff --git a/pyocd/coresight/ap.py b/pyocd/coresight/ap.py
@@ -20,6 +20,7 @@
 from enum import Enum
 
 from ..core import (exceptions, memory_interface)
+from ..core.target import Target
 from ..utility.concurrency import locked
 
 LOG = logging.getLogger(__name__)
@@ -413,10 +414,6 @@ def read_reg(self, addr, now=True):
     def write_reg(self, addr, data):
         self.dp.write_ap(self.address.address + addr, data)
     
-    def reset_did_occur(self):
-        """! @brief Invoked by the DebugPort to inform APs that a reset was performed."""
-        pass
-    
     def lock(self):
         """! @brief Lock the AP from access by other threads."""
         self.dp.probe.lock()
@@ -523,6 +520,9 @@ def __init__(self, dp, ap_address, idr=None, name="", flags=0, cmpid=None):
             self.read_memory = self._read_memory
             self.write_memory_block32 = self._write_memory_block32
             self.read_memory_block32 = self._read_memory_block32
+        
+        # Subscribe to reset events.
+        self.dp.probe.session.subscribe(self._reset_did_occur, (Target.Event.PRE_RESET, Target.Event.POST_RESET))
 
     @property
     def supported_transfer_sizes(self):
@@ -837,13 +837,17 @@ def write_reg(self, addr, data):
         except exceptions.ProbeError:
             # Invalidate cached CSW on exception.
             if ap_regaddr == self._reg_offset + MEM_AP_CSW:
-                self._cached_csw = -1
+                self._invalidate_cache()
             raise
     
-    def reset_did_occur(self):
-        """! @copydoc AccessPort.reset_did_occur()"""
-        # TODO use notifications to invalidate CSW cache.
+    def _invalidate_cache(self):
+        """! @brief Invalidate cached registers associated with this AP."""
         self._cached_csw = -1
+    
+    def _reset_did_occur(self, notification):
+        """! @brief Handles reset notifications to invalidate CSW cache."""
+        # We clear the cache on all resets just to be safe.
+        self._invalidate_cache()
 
     @locked
     def _write_memory(self, addr, data, transfer_size=32):
@@ -1045,7 +1049,7 @@ def _read_memory_block32(self, addr, size):
 
     def _handle_error(self, error, num):
         self.dp._handle_error(error, num)
-        self._cached_csw = -1
+        self._invalidate_cache()
 
 class AHB_AP(MEM_AP):
     """! @brief AHB-AP access port subclass.
diff --git a/pyocd/coresight/cortex_m.py b/pyocd/coresight/cortex_m.py
@@ -739,12 +739,14 @@ def reset(self, reset_type=None):
         
         After a call to this function, the core is running.
         """
-        self.session.notify(Target.Event.PRE_RESET, self)
-
         reset_type = self._get_actual_reset_type(reset_type)
 
         LOG.debug("reset, core %d, type=%s", self.core_number, reset_type.name)
 
+        # The HW reset type is passed to the DP, which itself sends reset notifications.
+        if reset_type is not Target.ResetType.HW:
+            self.session.notify(Target.Event.PRE_RESET, self)
+
         self._run_token += 1
 
         # Give the delegate a chance to overide reset. If the delegate returns True, then it
@@ -766,7 +768,8 @@ def reset(self, reset_type=None):
                     self.flush()
                     sleep(0.01)
 
-        self.session.notify(Target.Event.POST_RESET, self)
+        if reset_type is not Target.ResetType.HW:
+            self.session.notify(Target.Event.POST_RESET, self)
 
     def set_reset_catch(self, reset_type=None):
         """! @brief Prepare to halt core on reset."""
diff --git a/pyocd/coresight/dap.py b/pyocd/coresight/dap.py
@@ -20,6 +20,7 @@
 from enum import Enum
 
 from ..core import (exceptions, memory_interface)
+from ..core.target import Target
 from ..probe.debug_probe import DebugProbe
 from ..probe.swj import SWJSequenceSender
 from .ap import (MEM_AP_CSW, APSEL, APBANKSEL, APSEL_APBANKSEL, APREG_MASK, AccessPort)
@@ -204,6 +205,7 @@ class DebugPort(object):
     def __init__(self, probe, target):
         self._probe = probe
         self.target = target
+        self._session = target.session
         self.valid_aps = None
         self.dpidr = None
         self.aps = {}
@@ -221,11 +223,18 @@ def __init__(self, probe, target):
         self._errmode = None
         self._base_addr = None
         self._apacc_mem_interface = None
+        
+        # Subscribe to reset events.
+        self._probe.session.subscribe(self._reset_did_occur, (Target.Event.PRE_RESET, Target.Event.POST_RESET))
 
     @property
     def probe(self):
         return self._probe
     
+    @property
+    def session(self):
+        return self._session
+    
     @property
     def adi_version(self):
         return ADIVersion.ADIv6 if self._is_dpv3 else ADIVersion.ADIv5
@@ -404,23 +413,64 @@ def power_down_debug(self):
         
         return True
 
-    def reset(self):
+    def _invalidate_cache(self):
+        """! @brief Invalidate cached DP registers."""
         self._cached_dp_select = None
-        for ap in self.aps.values():
-            ap.reset_did_occur()
+    
+    def _reset_did_occur(self, notification):
+        """! @brief Handles reset notifications to invalidate register cache.
+        
+        The cache is cleared on all resets just to be safe. On most devices, warm resets do not reset
+        debug logic, but it does happen on some devices.
+        """
+        self._invalidate_cache()
+    
+    def reset(self):
+        """! @brief Hardware reset.
+        
+        Pre- and post-reset notifications are sent.
+        
+        This method can be called before the DebugPort is connected.
+        """
+        self.session.notify(Target.Event.PRE_RESET, self)
         self.probe.reset()
+        self.session.notify(Target.Event.POST_RESET, self)
 
     def assert_reset(self, asserted):
-        self._cached_dp_select = None
-        if asserted:
-            for ap in self.aps.values():
-                ap.reset_did_occur()
+        """! @brief Assert or deassert the hardware reset signal.
+        
+        A pre-reset notification is sent before asserting reset, whereas a post-reset notification is sent
+        after deasserting reset.
+        
+        This method can be called before the DebugPort is connected.
+        
+        @param self This object.
+        @param asserted True if nRESET is to be driven low; False will drive nRESET high.
+        """
+        is_asserted = self.is_reset_asserted()
+        if asserted and not is_asserted:
+            self.session.notify(Target.Event.PRE_RESET, self)
+
         self.probe.assert_reset(asserted)
 
+        if not asserted and is_asserted:
+            self.session.notify(Target.Event.POST_RESET, self)
+
     def is_reset_asserted(self):
+        """! @brief Returns the current state of the nRESET signal.
+        
+        This method can be called before the DebugPort is initalized.
+
+        @retval True Reset is asserted; nRESET is low.
+        @retval False Reset is not asserted; nRESET is high.
+        """
         return self.probe.is_reset_asserted()
 
     def set_clock(self, frequency):
+        """! @brief Change the wire protocol's clock frequency.
+        @param self This object.
+        @param frequency New wire protocol frequency in Hertz.
+        """
         self.probe.set_clock(frequency)
 
     def _write_dp_select(self, mask, value):
@@ -677,7 +727,7 @@ def _handle_error(self, error, num):
             self.write_reg(DP_ABORT, ABORT_DAPABORT)
 
     def clear_sticky_err(self):
-        self._cached_dp_select = None
+        self._invalidate_cache()
         mode = self.probe.wire_protocol
         if mode == DebugProbe.Protocol.SWD:
             self.write_reg(DP_ABORT, ABORT_ORUNERRCLR | ABORT_WDERRCLR | ABORT_STKERRCLR | ABORT_STKCMPCLR)
diff --git a/pyocd/probe/jlink_probe.py b/pyocd/probe/jlink_probe.py
@@ -24,6 +24,7 @@
 from ..core import (exceptions, memory_interface)
 from ..core.plugin import Plugin
 from ..core.options import OptionInfo
+from ..core.target import Target
 
 LOG = logging.getLogger(__name__)
 
@@ -177,13 +178,19 @@ def open(self):
                 self._default_protocol = DebugProbe.Protocol.SWD
             else:
                 self._default_protocol = DebugProbe.Protocol.JTAG
+        
+            # Subscribe to reset events.
+            self.session.subscribe(self._reset_did_occur, (Target.Event.PRE_RESET, Target.Event.POST_RESET))
         except JLinkException as exc:
             six.raise_from(self._convert_exception(exc), exc)
     
     def close(self):
         try:
             self._link.close()
             self._is_open = False
+        
+            # Unsubscribe from reset events.
+            self.session.unsubscribe(self._reset_did_occur, (Target.Event.PRE_RESET, Target.Event.POST_RESET))
         except JLinkException as exc:
             six.raise_from(self._convert_exception(exc), exc)
 
@@ -359,6 +366,9 @@ def _invalidate_cached_registers(self):
         # Invalidate cached DP SELECT register.
         self._dp_select = -1
 
+    def _reset_did_occur(self, notification):
+        self._invalidate_cached_registers()
+
     @staticmethod
     def _convert_exception(exc):
         if isinstance(exc, JLinkException):
diff --git a/pyocd/target/family/target_psoc6.py b/pyocd/target/family/target_psoc6.py
@@ -33,7 +33,8 @@ class CortexM_PSoC6(CortexM):
     VTBASE_CM4 = None
 
     def reset(self, reset_type=None):
-        self.session.notify(Target.Event.PRE_RESET, self)
+        if reset_type is not Target.ResetType.HW:
+            self.session.notify(Target.Event.PRE_RESET, self)
         self._run_token += 1
         if reset_type is Target.ResetType.HW:
             self._ap.dp.reset()
@@ -69,7 +70,8 @@ def reset(self, reset_type=None):
 
                     sleep(0.01)
 
-        self.session.notify(Target.Event.POST_RESET, self)
+        if reset_type is not Target.ResetType.HW:
+            self.session.notify(Target.Event.POST_RESET, self)
 
     def wait_halted(self):
         with Timeout(5.0) as t_o:
@@ -186,7 +188,8 @@ def skip_reset_and_halt(self, value):
         self._skip_reset_and_halt = value
 
     def reset(self, reset_type=None):
-        self.session.notify(Target.Event.PRE_RESET, self)
+        if reset_type is not Target.ResetType.HW:
+            self.session.notify(Target.Event.PRE_RESET, self)
 
         self._run_token += 1
 
@@ -219,7 +222,8 @@ def reset(self, reset_type=None):
                 except exceptions.TransferError:
                     pass
 
-        self.session.notify(Target.Event.POST_RESET, self)
+        if reset_type is not Target.ResetType.HW:
+            self.session.notify(Target.Event.POST_RESET, self)
 
     def wait_halted(self):
         with Timeout(5.0) as t_o:
