Devices with 'hidden' cores breaks connect sequence in pyOCD

[xoriath]

I was connecting to a PIC32CK2051SG01144 today, and it fails with the following exception;

0004096 D Running task create_cores [sequencer]
0004096 D Creating SCS component [discovery]
0004097 D selected core #0 [soc_target]
0004100 I CPU core #0: Cortex-M33 r0p4, v8.0-M architecture [cortex_m]
0004100 I   Extensions: [DSP, FPU, FPU_V5, MPU, SEC] [cortex_m]
0004100 I   FPU present: FPv5-SP-D16-M [cortex_m]
0004100 D Creating SCS component [discovery]
0004101 D uninit session <pyocd.core.session.Session object at 0x000001D6D676B4F0> [session]
0004102 C Error: <APv1Address@0x1d6da825540 #1 dp=0> [__main__]
Traceback (most recent call last):
  File "C:\developers\temp\pyOCD\pyocd\__main__.py", line 161, in run
    status = cmd.invoke()
  File "C:\developers\temp\pyOCD\pyocd\subcommands\commander_cmd.py", line 75, in invoke
    PyOCDCommander(self._args, cmds).run()
  File "C:\developers\temp\pyOCD\pyocd\commands\commander.py", line 83, in run
    if do_connect and not self.connect():
  File "C:\developers\temp\pyOCD\pyocd\commands\commander.py", line 224, in connect
    if not self._post_connect():
  File "C:\developers\temp\pyOCD\pyocd\commands\commander.py", line 251, in _post_connect
    self.session.open(init_board=not self.args.no_init)
  File "C:\developers\temp\pyOCD\pyocd\core\session.py", line 557, in open
    self._board.init()
  File "C:\developers\temp\pyOCD\pyocd\board\board.py", line 156, in init
    self.target.init()
  File "C:\developers\temp\pyOCD\pyocd\coresight\coresight_target.py", line 123, in init
    super().init()
  File "C:\developers\temp\pyOCD\pyocd\core\soc_target.py", line 174, in init
    seq.invoke()
  File "C:\developers\temp\pyOCD\pyocd\utility\sequencer.py", line 213, in invoke
    resultSequence.invoke()
  File "C:\developers\temp\pyOCD\pyocd\utility\sequencer.py", line 208, in invoke
    resultSequence = call()
  File "C:\developers\temp\pyOCD\pyocd\coresight\discovery.py", line 63, in _create_cores
    self._apply_to_all_components(self._create_component,
  File "C:\developers\temp\pyOCD\pyocd\coresight\discovery.py", line 74, in _apply_to_all_components
    ap.rom_table.for_each(action, filter)
  File "C:\developers\temp\pyOCD\pyocd\coresight\rom_table.py", line 338, in for_each
    action(component)
  File "C:\developers\temp\pyOCD\pyocd\coresight\discovery.py", line 56, in _create_component
    cmp = cmpid.factory(cmpid.ap, cmpid, cmpid.address)
  File "C:\developers\temp\pyOCD\pyocd\coresight\cortex_m.py", line 242, in factory
    root.add_core(core)
  File "C:\developers\temp\pyOCD\pyocd\target\pack\pack_target.py", line 513, in _pack_target_add_core
    pname = _self._pack_device.processors_ap_map[cast(CortexM, core).ap.address].name
KeyError: <APv1Address@0x1d6da825540 #1 dp=0> 

The reason for this is that the Hardware Security Module (HSM) has an extra M0+ core on the AP..

However, we cannot (I work for Microchip), at the moment provide more user facing information about this core, hence it is not listed in the .pdsc file, and thus the lookup fails.

Debugging through this I think it makes sense to just let 'undescribed' cores pass through without the pname lookup that is done.

[xoriath]

Looks like this is very similar to #1678, and #1637 just a different cause on the chip side

[xoriath]

With the fix in the pr, I can control both cores;

Connected to PIC32CK2051SG01144 [Halted]: 020057703RYN000336
pyocd> core
Core 0 (Cortex-M33) is selected
pyocd> status
Core 0 (Cortex-M33):  Halted [Secure]
Core 1 (None):  Running
pyocd> core 1
Selected core 1 (None) (AHB-AP#1)
pyocd> halt
0159996 D halting core 1 [cortex_m]
Successfully halted device
pyocd> status
Core 0 (Cortex-M33):  Halted [Secure]
Core 1 (None):  Halted

[xoriath]

@RobertRostohar any thoughts?

[xoriath]

Anyone? this is blocking enabling pyOCD for multiple of device families from Microchip :)

[TeoMahnic]

Hi @xoriath, thank you for raising this issue and for preparing a PR.
Could you please check whether #1865 resolves the problem? It builds on #1801 and adds the required updates to cbuild-run support. It also standardizes the use of the core type as the name for “Unknown” cores.