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Author: pyocd-bot

docs/builtin-targets.html

@@ -675,6 +675,11 @@ <h5 class="sidebar-header">On this page</h5>
     <td>LPC5526</td>
     </tr>
 
+    <tr><td><code>lpc55s16</code></td>
+    <td>NXP</td>
+    <td>LPC55S16</td>
+    </tr>
+
     <tr><td><code>lpc55s28</code></td>
     <td>NXP</td>
     <td>LPC55S28</td>
@@ -975,6 +980,26 @@ <h5 class="sidebar-header">On this page</h5>
     <td>W7500</td>
     </tr>
 
+    <tr><td><code>ytm32b1ld0</code></td>
+    <td>Yuntu Microelectronics</td>
+    <td>YTM32B1LD0</td>
+    </tr>
+
+    <tr><td><code>ytm32b1le0</code></td>
+    <td>Yuntu Microelectronics</td>
+    <td>YTM32B1LE0</td>
+    </tr>
+
+    <tr><td><code>ytm32b1md1</code></td>
+    <td>Yuntu Microelectronics</td>
+    <td>YTM32B1MD1</td>
+    </tr>
+
+    <tr><td><code>ytm32b1me0</code></td>
+    <td>YTMicro</td>
+    <td>YTM32B1ME0</td>
+    </tr>
+
 
 </table>
 

docs/command_reference.html

@@ -307,6 +307,11 @@ <h5 class="sidebar-header">On this page</h5>
 <li class="toc-entry toc-h5"><a href="#wreg">wreg</a></li>
 </ul>
 </li>
+<li class="toc-entry toc-h3"><a href="#rtt">Rtt</a>
+<ul>
+<li class="toc-entry toc-h5"><a href="#rtt-1">rtt</a></li>
+</ul>
+</li>
 <li class="toc-entry toc-h3"><a href="#semihosting">Semihosting</a>
 <ul>
 <li class="toc-entry toc-h5"><a href="#arm">arm</a></li>
@@ -334,6 +339,11 @@ <h5 class="sidebar-header">On this page</h5>
 <li class="toc-entry toc-h5"><a href="#threads-1">threads</a></li>
 </ul>
 </li>
+<li class="toc-entry toc-h3"><a href="#utility">Utility</a>
+<ul>
+<li class="toc-entry toc-h5"><a href="#sleep">sleep</a></li>
+</ul>
+</li>
 <li class="toc-entry toc-h3"><a href="#values">Values</a>
 <ul>
 <li class="toc-entry toc-h5"><a href="#set">set</a></li>
@@ -344,8 +354,10 @@ <h5 class="sidebar-header">On this page</h5>
 </li>
 <li class="toc-entry toc-h2"><a href="#value-details">Value details</a>
 <ul>
+<li class="toc-entry toc-h5"><a href="#accessible-pins">accessible-pins</a></li>
 <li class="toc-entry toc-h5"><a href="#aps">aps</a></li>
 <li class="toc-entry toc-h5"><a href="#cores">cores</a></li>
+<li class="toc-entry toc-h5"><a href="#debug-sequences">debug-sequences</a></li>
 <li class="toc-entry toc-h5"><a href="#fault">fault</a></li>
 <li class="toc-entry toc-h5"><a href="#frequency">frequency</a></li>
 <li class="toc-entry toc-h5"><a href="#graph">graph</a></li>
@@ -358,8 +370,10 @@ <h5 class="sidebar-header">On this page</h5>
 <li class="toc-entry toc-h5"><a href="#nreset">nreset</a></li>
 <li class="toc-entry toc-h5"><a href="#option">option</a></li>
 <li class="toc-entry toc-h5"><a href="#peripherals">peripherals</a></li>
+<li class="toc-entry toc-h5"><a href="#pins">pins</a></li>
 <li class="toc-entry toc-h5"><a href="#probe-uid">probe-uid</a></li>
 <li class="toc-entry toc-h5"><a href="#register-groups">register-groups</a></li>
+<li class="toc-entry toc-h5"><a href="#reset-type">reset-type</a></li>
 <li class="toc-entry toc-h5"><a href="#step-into-interrupts">step-into-interrupts</a></li>
 <li class="toc-entry toc-h5"><a href="#target-1">target</a></li>
 <li class="toc-entry toc-h5"><a href="#vector-catch">vector-catch</a></li>
@@ -382,7 +396,10 @@ <h5 class="sidebar-header">On this page</h5>
 command names. In addition, commonly used commands often have a short alias. The alias takes
 precedence even when it is a prefix of multiple other commands.</p>
 
-<!-- Maintainer note: the following is auto-generated. Edit the command INFO source material. -->
+<!--
+Maintainer note: the following is auto-generated. Edit the command class INFO dict source material,
+then run ./scripts/generate_command_help.py.
+-->
 
 <h2 id="all-commands">All commands</h2>
 
@@ -494,9 +511,9 @@ <h2 id="all-commands">All commands</h2>
 <tr><td>
 <a href="#core"><tt>core</tt></a>
 </td><td>
-[NUM]
+[NUMBER | NAME]
 </td><td>
-Select CPU core by number or print selected core.
+Select CPU core by number or name, or print selected core.
 </td></tr>
 
 <tr><td>
@@ -561,7 +578,7 @@ <h2 id="all-commands">All commands</h2>
 </td><td>
 [halt|-halt|-h] [TYPE]
 </td><td>
-Reset the target, optionally specifying the reset type.
+Reset the target, optionally with halt and/or specifying the reset type.
 </td></tr>
 
 <tr><td>
@@ -769,6 +786,16 @@ <h2 id="all-commands">All commands</h2>
 Set the value of a core or peripheral register.
 </td></tr>
 
+<tr><td colspan="3"><b>Rtt</b></td></tr>
+
+<tr><td>
+<a href="#rtt"><tt>rtt</tt></a>
+</td><td>
+rtt {setup,start,stop,channels,server}
+</td><td>
+Control SEGGER RTT compatible interface.
+</td></tr>
+
 <tr><td colspan="3"><b>Semihosting</b></td></tr>
 
 <tr><td>
@@ -835,6 +862,16 @@ <h2 id="all-commands">All commands</h2>
 Control thread awareness.
 </td></tr>
 
+<tr><td colspan="3"><b>Utility</b></td></tr>
+
+<tr><td>
+<a href="#sleep"><tt>sleep</tt></a>
+</td><td>
+MILLISECONDS
+</td><td>
+Sleep for a number of milliseconds before continuing.
+</td></tr>
+
 <tr><td colspan="3"><b>Values</b></td></tr>
 
 <tr><td>
@@ -866,6 +903,14 @@ <h2 id="all-values">All values</h2>
 
 <tr><th>Value</th><th>Access</th><th>Description</th></tr>
 
+<tr><td>
+<a href="#accessible-pins"><tt>accessible-pins</tt></a>
+</td><td>
+read-write
+</td><td>
+Display which debug probe pins can be read and written with the 'pins' value.
+</td></tr>
+
 <tr><td>
 <a href="#aps"><tt>aps</tt></a>
 </td><td>
@@ -882,6 +927,14 @@ <h2 id="all-values">All values</h2>
 Information about CPU cores in the target.
 </td></tr>
 
+<tr><td>
+<a href="#debug-sequences"><tt>debug-sequences</tt></a>
+</td><td>
+read-only
+</td><td>
+Show the available debug sequences from the target's DFP.
+</td></tr>
+
 <tr><td>
 <a href="#fault"><tt>fault</tt></a>
 </td><td>
@@ -979,6 +1032,14 @@ <h2 id="all-values">All values</h2>
 List of target peripheral instances.
 </td></tr>
 
+<tr><td>
+<a href="#pins"><tt>pins</tt></a>
+</td><td>
+read-write
+</td><td>
+Current debug probe protocol I/O pin states.
+</td></tr>
+
 <tr><td>
 <a href="#probe-uid"><tt>probe-uid</tt></a>,
 <a href="#probe-uid"><tt>uid</tt></a>
@@ -996,6 +1057,14 @@ <h2 id="all-values">All values</h2>
 Display available register groups for the selected core.
 </td></tr>
 
+<tr><td>
+<a href="#reset-type"><tt>reset-type</tt></a>
+</td><td>
+read-write
+</td><td>
+Show reset configuration and all available reset types for each core. Set current reset type.
+</td></tr>
+
 <tr><td>
 <a href="#step-into-interrupts"><tt>step-into-interrupts</tt></a>,
 <a href="#step-into-interrupts"><tt>si</tt></a>
@@ -1100,8 +1169,8 @@ <h5 id="continue"><code class="highlighter-rouge">continue</code></h5>
 
 <h5 id="core-1"><code class="highlighter-rouge">core</code></h5>
 
-<p><strong>Usage</strong>: core [NUM] <br />
-Select CPU core by number or print selected core.</p>
+<p><strong>Usage</strong>: core [NUMBER | NAME] <br />
+Select CPU core by number or name, or print selected core.</p>
 
 <h5 id="halt"><code class="highlighter-rouge">halt</code></h5>
 
@@ -1146,7 +1215,7 @@ <h3 id="device">Device</h3>
 <h5 id="reset"><code class="highlighter-rouge">reset</code></h5>
 
 <p><strong>Usage</strong>: reset [halt|-halt|-h] [TYPE] <br />
-Reset the target, optionally specifying the reset type. The reset type must be one of ‘default’, ‘hw’, ‘sw’, ‘hardware’, ‘software’, ‘sw_sysresetreq’, ‘sw_vectreset’, ‘sw_emulated’, ‘sysresetreq’, ‘vectreset’, or ‘emulated’.</p>
+Reset the target, optionally with halt and/or specifying the reset type. The reset type must be one of ‘default’, ‘hw’, ‘sw’, ‘hardware’, ‘software’, ‘system’, ‘core’, ‘emulated’, ‘sw_system’, ‘sw_core’, ‘sw_sysresetreq’, ‘sw_vectreset’, ‘sw_emulated’, ‘sysresetreq’, or ‘vectreset’.</p>
 
 <h5 id="unlock"><code class="highlighter-rouge">unlock</code></h5>
 
@@ -1288,6 +1357,13 @@ <h5 id="wreg"><code class="highlighter-rouge">wreg</code></h5>
 <strong>Usage</strong>: wreg [-r] [-p] [-f] REG VALUE <br />
 Set the value of a core or peripheral register. The REG parameter must be a core register name or a peripheral.register. When a peripheral register is written, if the -r option is passed then it is read back and the updated value printed. The -p option forces evaluating the register name as a peripheral register name. If the -f option is passed, then individual fields of peripheral registers will be printed in addition to the full value.</p>
 
+<h3 id="rtt">Rtt</h3>
+
+<h5 id="rtt-1"><code class="highlighter-rouge">rtt</code></h5>
+
+<p><strong>Usage</strong>: rtt rtt {setup,start,stop,channels,server} <br />
+Control SEGGER RTT compatible interface.</p>
+
 <h3 id="semihosting">Semihosting</h3>
 
 <h5 id="arm"><code class="highlighter-rouge">arm</code></h5>
@@ -1335,6 +1411,13 @@ <h5 id="threads-1"><code class="highlighter-rouge">threads</code></h5>
 <p><strong>Usage</strong>: threads {flush,enable,disable,status} <br />
 Control thread awareness.</p>
 
+<h3 id="utility">Utility</h3>
+
+<h5 id="sleep"><code class="highlighter-rouge">sleep</code></h5>
+
+<p><strong>Usage</strong>: sleep MILLISECONDS <br />
+Sleep for a number of milliseconds before continuing.</p>
+
 <h3 id="values">Values</h3>
 
 <h5 id="set"><code class="highlighter-rouge">set</code></h5>
@@ -1349,6 +1432,12 @@ <h5 id="show"><code class="highlighter-rouge">show</code></h5>
 
 <h2 id="value-details">Value details</h2>
 
+<h5 id="accessible-pins"><code class="highlighter-rouge">accessible-pins</code></h5>
+
+<p><strong>Access</strong>: read-write <br />
+<strong>Usage</strong>: show accessible-pins, set accessible-pins VALUE <br />
+Display which debug probe pins can be read and written with the ‘pins’ value.</p>
+
 <h5 id="aps"><code class="highlighter-rouge">aps</code></h5>
 
 <p><strong>Access</strong>: read-only <br />
@@ -1361,6 +1450,12 @@ <h5 id="cores"><code class="highlighter-rouge">cores</code></h5>
 <strong>Usage</strong>: show cores <br />
 Information about CPU cores in the target.</p>
 
+<h5 id="debug-sequences"><code class="highlighter-rouge">debug-sequences</code></h5>
+
+<p><strong>Access</strong>: read-only <br />
+<strong>Usage</strong>: show debug-sequences <br />
+Show the available debug sequences from the target’s DFP. Only available for CMSIS-Pack based targets.</p>
+
 <h5 id="fault"><code class="highlighter-rouge">fault</code></h5>
 
 <p><strong>Access</strong>: read-only <br />
@@ -1438,6 +1533,12 @@ <h5 id="peripherals"><code class="highlighter-rouge">peripherals</code></h5>
 <strong>Usage</strong>: show peripherals <br />
 List of target peripheral instances.</p>
 
+<h5 id="pins"><code class="highlighter-rouge">pins</code></h5>
+
+<p><strong>Access</strong>: read-write <br />
+<strong>Usage</strong>: show pins, set pins VALUE <br />
+Current debug probe protocol I/O pin states. The pins value is a mask containing the state of all accessible protocol pins. See the <code class="highlighter-rouge">accessible-pins</code> value for protocol pins that can be read and written by the connected debug probe.</p>
+
 <h5 id="probe-uid"><code class="highlighter-rouge">probe-uid</code></h5>
 
 <p><strong>Aliases</strong>: <code class="highlighter-rouge">uid</code> <br />
@@ -1451,6 +1552,12 @@ <h5 id="register-groups"><code class="highlighter-rouge">register-groups</code><
 <strong>Usage</strong>: show register-groups <br />
 Display available register groups for the selected core.</p>
 
+<h5 id="reset-type"><code class="highlighter-rouge">reset-type</code></h5>
+
+<p><strong>Access</strong>: read-write <br />
+<strong>Usage</strong>: show reset-type, set reset-type VALUE <br />
+Show reset configuration and all available reset types for each core. Set current reset type.</p>
+
 <h5 id="step-into-interrupts"><code class="highlighter-rouge">step-into-interrupts</code></h5>
 
 <p><strong>Aliases</strong>: <code class="highlighter-rouge">si</code> <br />

docs/configuring_logging.html

@@ -365,6 +365,14 @@ <h3 id="trace-loggers">Trace loggers</h3>
       <td><code class="highlighter-rouge">pyocd.debug.semihost.trace</code></td>
       <td>Semihost file operations</td>
     </tr>
+    <tr>
+      <td><code class="highlighter-rouge">pyocd.debug.sequences.scope.trace</code></td>
+      <td>Open-CMSIS-Pack debug sequence variable read/write</td>
+    </tr>
+    <tr>
+      <td><code class="highlighter-rouge">pyocd.debug.sequences.sequences.trace</code></td>
+      <td>Open-CMSIS-Pack debug sequence statements</td>
+    </tr>
     <tr>
       <td><code class="highlighter-rouge">pyocd.flash.flash.trace</code></td>
       <td>Flash algorithm operations</td>

docs/multicore_debug.html

@@ -217,30 +217,28 @@ <h5 class="sidebar-header">On this page</h5>
                   </div>
 
                   <p>pyOCD supports debugging multicore devices. It does this by serving one gdb server per core, to which
-you connect independant gdb instances. This is the most reliable method of debugging multicore
-embedded devices using gdb.</p>
+independent gdb instances are connected. This is the most reliable method of debugging asymmetric multicore
+devices using gdb.</p>
 
-<p><code class="highlighter-rouge">pyocd gdbserver</code> automatically creates one <code class="highlighter-rouge">GDBServer</code> instance per core. The first core is given the
-user-specified port number. Additional cores have port numbers incremented from there.</p>
+<p><code class="highlighter-rouge">pyocd gdbserver</code> automatically creates one gdb server instance per core by default. The primary core is given the user-specified port number. Additional cores have port numbers incremented from there. If a gdb server for only one or a subset of cores is desired, the <code class="highlighter-rouge">--core</code> command line argument can be used with a list of core numbers.</p>
 
-<p>To prevent reset requests from multiple connected gdb instances causing havoc, secondary cores have
-their default reset type set to core-only reset (VECTRESET), which will fall back to an emulated
-reset for non-v7-M architectures. This feature can be disabled by setting the
-<code class="highlighter-rouge">enable_multicore_debug</code> session option to false.</p>
+<p>By default, the primary core is core number 0. For Arm CoreSight based devices, this will be the core with the lowest associated access port address. Use the <code class="highlighter-rouge">primary_core</code> session option to change the primary core.</p>
+
+<p>When performing multicore debug where multiple gdb instances are connected simultaneously, it is important to set the <code class="highlighter-rouge">enable_multicore_debug</code> session option to true. This changes secondary cores to have their default reset type set to core-only reset (<code class="highlighter-rouge">sw_core</code>). This prevents competing reset requests from the multiple gdb instances causing havoc. On v7-M architecture cores, VECTRESET is used. However, VECTRESET is not supported on other core architecture, so non-v7-M architectures will fall back to an emulated core reset.</p>
 
 <p>To debug a multicore device, run <code class="highlighter-rouge">pyocd gdbserver</code> as usual. This will connect to the device, detect
 the cores, and create the gdb server instances on separate ports. Next, start up two gdb instances
 and connect to the two gdb server ports. For instance, on a dual core device if you pass 3333 for
-the port, connect to port 3333 for the first core and port 3334 for the second core.</p>
+the port (or leave it set to default), connect to port 3333 for the first core and port 3334 for the second core.</p>
 
 <p>On many devices, secondary cores are by default held in reset until released by the primary core.
 Because gdb does not have a concept of a core held in reset, pyOCD will report a core held in reset
 by telling gdb that there is a single thread with the name “Reset”. This is visible if you run the
-show threads gdb command, and will appear in the Eclipe Debug view’s list of threads. All register
+show threads gdb command, and will appear in the VSCode or Eclipse Debug view’s list of threads. All register
 values will be reported as 0 until the core is released from reset.</p>
 
-<p>Usually you want to have the primary core load code for the secondary core, so configure the second
-core’s gdb to not load any code to the target. This is highly device-specific, though, and may
+<p>Usually you want to have the primary core load code and/or configure the reset vector for secondary cores prior to releasing those cores from reset. For this situation, configure the second
+core’s gdb to not load any code to the target. This usage is highly device-specific, though, and may
 depend on whether the secondary core’s code is running out of flash or RAM.</p>