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Commit 66084cc

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cleanups
1 parent 7efb8db commit 66084cc

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2 files changed

+1
-11
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2 files changed

+1
-11
lines changed

mypyc/codegen/emitmodule.py

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -226,10 +226,6 @@ def compile_scc_to_ir(
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if errors.num_errors > 0:
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return modules
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# XXX: HOW WILL WE DEAL WITH REFCOUNTING ON THE SPILLAGE
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# DO WE DO IT... LAST? MAYBE MAYBE MAYBE YES
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# ONLY DO UNINIT.... YEAH OK
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# Insert uninit checks.
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for module in modules.values():
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for fn in module.functions:

mypyc/transform/spill.py

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -24,17 +24,11 @@ def insert_spills(ir: FuncIR, env: ClassIR) -> None:
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live = analyze_live_regs(ir.blocks, cfg)
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entry_live = live.before[ir.blocks[0], 0]
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# from mypyc.ir.pprint import format_func
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# print('\n'.join(format_func(ir)))
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entry_live = {op for op in entry_live if not (isinstance(op, Register) and op.is_arg)}
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# XXX: Actually for now, no Registers at all -- we keep the manual spills
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# TODO: Actually for now, no Registers at all -- we keep the manual spills
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entry_live = {op for op in entry_live if not isinstance(op, Register)}
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ir.blocks = spill_regs(ir.blocks, env, entry_live, live)
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# print("\n".join(format_func(ir)))
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# print("\n\n\n=========")
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def spill_regs(

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