[AMDGPU][DOC][NFC] Updated GFX10 assembler syntax description

The description has been updated to reflect AMDGPU MC changes:
- enabled literals for src0 of v_fmaak_f*, v_fmamk_f*, v_madak_f32, v_madmk_f32;
- enabled global_atomic_fcmpswap and global_atomic_fcmpswap_x2;
- enabled dlc with flat_atomic* and global_atomic_*.

Bug fixing and improvements:
- enabled s_wait_idle;
- enabled s_waitcnt_depctr;
- added description of s_waitcnt_depctr syntactic sugar;
- disabled SYSMSG_OP_HOST_TRAP_ACK (it is not supported on GFX10);
- corrected description of lgkmcnt (accept values from 0 to 63).

Author: dpreobra

llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst

@@ -41,27 +41,27 @@ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
 
 Defined register *names* include:
 
-    =================== ==========================================
-    Name                Description
-    =================== ==========================================
-    HW_REG_MODE         Shader writeable mode bits.
-    HW_REG_STATUS       Shader read-only status.
-    HW_REG_TRAPSTS      Trap status.
-    HW_REG_HW_ID1       Id of wave, simd, compute unit, etc.
-    HW_REG_HW_ID2       Id of queue, pipeline, etc.
-    HW_REG_GPR_ALLOC    Per-wave SGPR and VGPR allocation.
-    HW_REG_LDS_ALLOC    Per-wave LDS allocation.
-    HW_REG_IB_STS       Counters of outstanding instructions.
-    HW_REG_SH_MEM_BASES Memory aperture.
-    HW_REG_TBA_LO       tba_lo register.
-    HW_REG_TBA_HI       tba_hi register.
-    HW_REG_TMA_LO       tma_lo register.
-    HW_REG_TMA_HI       tma_hi register.
-    HW_REG_FLAT_SCR_LO  flat_scratch_lo register.
-    HW_REG_FLAT_SCR_HI  flat_scratch_hi register.
-    HW_REG_XNACK_MASK   xnack_mask register.
-    HW_REG_POPS_PACKER  pops_packer register.
-    =================== ==========================================
+    ==================== ==========================================
+    Name                 Description
+    ==================== ==========================================
+    HW_REG_MODE          Shader writeable mode bits.
+    HW_REG_STATUS        Shader read-only status.
+    HW_REG_TRAPSTS       Trap status.
+    HW_REG_HW_ID1        Id of wave, simd, compute unit, etc.
+    HW_REG_HW_ID2        Id of queue, pipeline, etc.
+    HW_REG_GPR_ALLOC     Per-wave SGPR and VGPR allocation.
+    HW_REG_LDS_ALLOC     Per-wave LDS allocation.
+    HW_REG_IB_STS        Counters of outstanding instructions.
+    HW_REG_SH_MEM_BASES  Memory aperture.
+    HW_REG_TBA_LO        tba_lo register.
+    HW_REG_TBA_HI        tba_hi register.
+    HW_REG_TMA_LO        tma_lo register.
+    HW_REG_TMA_HI        tma_hi register.
+    HW_REG_FLAT_SCR_LO   flat_scratch_lo register.
+    HW_REG_FLAT_SCR_HI   flat_scratch_hi register.
+    HW_REG_XNACK_MASK    xnack_mask register.
+    HW_REG_POPS_PACKER   pops_packer register.
+    ==================== ==========================================
 
 Examples:
 

llvm/docs/AMDGPU/gfx10_hwreg.rst

@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx10_imm16:
+.. _amdgpu_synid_gfx10_imm16_73139a:
 
 imm16
 =====

llvm/docs/AMDGPU/gfx10_imm16_2.rst

@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx10_imm16_1:
+.. _amdgpu_synid_gfx10_imm16_a04fb3:
 
 imm16
 =====

llvm/docs/AMDGPU/gfx10_imm16.rst renamed to llvm/docs/AMDGPU/gfx10_imm16_73139a.rst

@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx10_m_1:
+.. _amdgpu_synid_gfx10_m_254bcb:
 
 m
 =

llvm/docs/AMDGPU/gfx10_imm16_1.rst renamed to llvm/docs/AMDGPU/gfx10_imm16_a04fb3.rst

@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx10_m:
+.. _amdgpu_synid_gfx10_m_f5d306:
 
 m
 =

llvm/docs/AMDGPU/gfx10_m_1.rst renamed to llvm/docs/AMDGPU/gfx10_m_254bcb.rst

@@ -47,29 +47,28 @@ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
 
 Each message type supports specific operations:
 
-    =================== ========== ============================== ============ ==========
-    Message name        Message Id Supported Operations           Operation Id Stream Id
-    =================== ========== ============================== ============ ==========
-    MSG_INTERRUPT       1          \-                             \-           \-
-    MSG_GS              2          GS_OP_CUT                      1            Optional
-    \                              GS_OP_EMIT                     2            Optional
-    \                              GS_OP_EMIT_CUT                 3            Optional
-    MSG_GS_DONE         3          GS_OP_NOP                      0            \-
-    \                              GS_OP_CUT                      1            Optional
-    \                              GS_OP_EMIT                     2            Optional
-    \                              GS_OP_EMIT_CUT                 3            Optional
-    MSG_SAVEWAVE        4          \-                             \-           \-
-    MSG_STALL_WAVE_GEN  5          \-                             \-           \-
-    MSG_HALT_WAVES      6          \-                             \-           \-
-    MSG_ORDERED_PS_DONE 7          \-                             \-           \-
-    MSG_GS_ALLOC_REQ    9          \-                             \-           \-
-    MSG_GET_DOORBELL    10         \-                             \-           \-
-    MSG_GET_DDID        11         \-                             \-           \-
-    MSG_SYSMSG          15         SYSMSG_OP_ECC_ERR_INTERRUPT    1            \-
-    \                              SYSMSG_OP_REG_RD               2            \-
-    \                              SYSMSG_OP_HOST_TRAP_ACK        3            \-
-    \                              SYSMSG_OP_TTRACE_PC            4            \-
-    =================== ========== ============================== ============ ==========
+    ====================== ========== ============================== ============ ==========
+    Message name           Message Id Supported Operations           Operation Id Stream Id
+    ====================== ========== ============================== ============ ==========
+    MSG_INTERRUPT          1          \-                             \-           \-
+    MSG_GS                 2          GS_OP_CUT                      1            Optional
+    \                                 GS_OP_EMIT                     2            Optional
+    \                                 GS_OP_EMIT_CUT                 3            Optional
+    MSG_GS_DONE            3          GS_OP_NOP                      0            \-
+    \                                 GS_OP_CUT                      1            Optional
+    \                                 GS_OP_EMIT                     2            Optional
+    \                                 GS_OP_EMIT_CUT                 3            Optional
+    MSG_SAVEWAVE           4          \-                             \-           \-
+    MSG_STALL_WAVE_GEN     5          \-                             \-           \-
+    MSG_HALT_WAVES         6          \-                             \-           \-
+    MSG_ORDERED_PS_DONE    7          \-                             \-           \-
+    MSG_GS_ALLOC_REQ       9          \-                             \-           \-
+    MSG_GET_DOORBELL       10         \-                             \-           \-
+    MSG_GET_DDID           11         \-                             \-           \-
+    MSG_SYSMSG             15         SYSMSG_OP_ECC_ERR_INTERRUPT    1            \-
+    \                                 SYSMSG_OP_REG_RD               2            \-
+    \                                 SYSMSG_OP_TTRACE_PC            4            \-
+    ====================== ========== ============================== ============ ==========
 
 *Sendmsg* arguments are validated depending on how *type* value is specified:
 

llvm/docs/AMDGPU/gfx10_m.rst renamed to llvm/docs/AMDGPU/gfx10_m_f5d306.rst

@@ -5,14 +5,14 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx10_saddr:
+.. _amdgpu_synid_gfx10_saddr_beaa25:
 
 saddr
 =====
 
 An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
 
-See :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>` for description of available addressing modes.
+See :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` for description of available addressing modes.
 
 *Size:* 2 dwords.
 

llvm/docs/AMDGPU/gfx10_msg.rst

@@ -5,14 +5,14 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx10_saddr_1:
+.. _amdgpu_synid_gfx10_saddr_da2a8a:
 
 saddr
 =====
 
 An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
 
-Either this operand or :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>` must be set to :ref:`off<amdgpu_synid_off>`.
+Either this operand or :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>` must be set to :ref:`off<amdgpu_synid_off>`.
 
 *Size:* 1 dword.