Qualcomm AI Engine Direct - support XR2Gen3 SoC (#9181)

### Summary
- add SXR2330P

### Test plan
```bash
python backends/qualcomm/tests/test_qnn_delegate.py -k TestQNNQuantizedOperator -s $SERIAL_NO -m SM8650 -b build-android
```

Author: haowhsu-quic

backends/qualcomm/serialization/qc_compiler_spec.fbs

@@ -32,16 +32,17 @@ table HtpInfo {
 /// to get SoC Model in supported snapdragon devices
 enum QcomChipset: int {
   UNKNOWN_SM = 0,
+  SA8295 = 39,
   SM8450 = 36,
   SM8475 = 42,
   SM8550 = 43,
-  SSG2115P = 46,
   SM8650 = 57,
-  SA8295 = 39,
   SM8750 = 69,
+  SSG2115P = 46,
+  SSG2125P = 58,
   SXR1230P = 45,
   SXR2230P = 53,
-  SSG2125P = 58,
+  SXR2330P = 75,
 }
 
 /// Indicate the information of the specified SoC.

backends/qualcomm/serialization/qc_schema.py

@@ -37,16 +37,17 @@ class HtpInfo:
 @unique
 class QcomChipset(IntEnum):
     UNKNOWN_SM = 0
+    SA8295 = 39  # v68
     SM8450 = 36  # v69
     SM8475 = 42  # v69
     SM8550 = 43  # v73
-    SSG2115P = 46  # v73
     SM8650 = 57  # v75
-    SA8295 = 39  # v68
     SM8750 = 69  # v79
-    SXR1230P = 45
-    SXR2230P = 53
-    SSG2125P = 58
+    SSG2115P = 46  # v73
+    SSG2125P = 58  # v73
+    SXR1230P = 45  # v73
+    SXR2230P = 53  # v69
+    SXR2330P = 75  # v79
 
 
 @dataclass
@@ -56,16 +57,17 @@ class SocInfo:
 
 
 _soc_info_table = {
+    QcomChipset.SA8295: SocInfo(QcomChipset.SA8295, HtpInfo(HtpArch.V68, 8)),
     QcomChipset.SM8450: SocInfo(QcomChipset.SM8450, HtpInfo(HtpArch.V69, 8)),
     QcomChipset.SM8475: SocInfo(QcomChipset.SM8475, HtpInfo(HtpArch.V69, 8)),
     QcomChipset.SM8550: SocInfo(QcomChipset.SM8550, HtpInfo(HtpArch.V73, 8)),
     QcomChipset.SM8650: SocInfo(QcomChipset.SM8650, HtpInfo(HtpArch.V75, 8)),
     QcomChipset.SM8750: SocInfo(QcomChipset.SM8750, HtpInfo(HtpArch.V79, 8)),
     QcomChipset.SSG2115P: SocInfo(QcomChipset.SSG2115P, HtpInfo(HtpArch.V73, 2)),
-    QcomChipset.SA8295: SocInfo(QcomChipset.SA8295, HtpInfo(HtpArch.V68, 8)),
+    QcomChipset.SSG2125P: SocInfo(QcomChipset.SSG2125P, HtpInfo(HtpArch.V73, 2)),
     QcomChipset.SXR1230P: SocInfo(QcomChipset.SXR1230P, HtpInfo(HtpArch.V73, 2)),
     QcomChipset.SXR2230P: SocInfo(QcomChipset.SXR2230P, HtpInfo(HtpArch.V69, 8)),
-    QcomChipset.SSG2125P: SocInfo(QcomChipset.SSG2125P, HtpInfo(HtpArch.V73, 2)),
+    QcomChipset.SXR2330P: SocInfo(QcomChipset.SXR2330P, HtpInfo(HtpArch.V79, 8)),
 }
 
 

backends/qualcomm/utils/utils.py

@@ -1280,25 +1280,33 @@ def generate_qnn_executorch_compiler_spec(
 
 def get_soc_to_arch_map():
     return {
-        "SSG2115P": HtpArch.V73,
-        "SM8750": HtpArch.V79,
-        "SM8650": HtpArch.V75,
-        "SM8550": HtpArch.V73,
-        "SM8475": HtpArch.V69,
-        "SM8450": HtpArch.V69,
         "SA8295": HtpArch.V68,
+        "SM8450": HtpArch.V69,
+        "SM8475": HtpArch.V69,
+        "SM8550": HtpArch.V73,
+        "SM8650": HtpArch.V75,
+        "SM8750": HtpArch.V79,
+        "SSG2115P": HtpArch.V73,
+        "SSG2125P": HtpArch.V73,
+        "SXR1230P": HtpArch.V73,
+        "SXR2230P": HtpArch.V69,
+        "SXR2330P": HtpArch.V79,
     }
 
 
 def get_soc_to_chipset_map():
     return {
-        "SSG2115P": QcomChipset.SSG2115P,
-        "SM8750": QcomChipset.SM8750,
-        "SM8650": QcomChipset.SM8650,
-        "SM8550": QcomChipset.SM8550,
-        "SM8475": QcomChipset.SM8475,
-        "SM8450": QcomChipset.SM8450,
         "SA8295": QcomChipset.SA8295,
+        "SM8450": QcomChipset.SM8450,
+        "SM8475": QcomChipset.SM8475,
+        "SM8550": QcomChipset.SM8550,
+        "SM8650": QcomChipset.SM8650,
+        "SM8750": QcomChipset.SM8750,
+        "SSG2115P": QcomChipset.SSG2115P,
+        "SSG2125P": QcomChipset.SSG2125P,
+        "SXR1230P": QcomChipset.SXR1230P,
+        "SXR2230P": QcomChipset.SXR2230P,
+        "SXR2330P": QcomChipset.SXR2330P,
     }