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Qualcomm AI Engine Direct - op enablement sign asin xor floor_divide binary (#13675)
Summary • Enable sign,asin,xor,floor_divide,binary • test cases Test plan python backends/qualcomm/tests/test_qnn_delegate.py -k TestQNNQuantizedOperators.test_qnn_backend_ -s $DEVICE_SERIAL -m SM8650 -b build-android/ python backends/qualcomm/tests/test_qnn_delegate.py -k TestQNNFloatingPointOperators.test_qnn_backend_ -s $DEVICE_SERIAL -m SM8650 -b build-android/
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-11
lines changed

14 files changed

+530
-11
lines changed

‎backends/qualcomm/_passes/layout_transform.py‎

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@@ -64,8 +64,10 @@ class LayoutTransform(ExportPass):
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exir_ops.edge.aten.add.Tensor,
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exir_ops.edge.aten.amax.default,
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exir_ops.edge.aten.amin.default,
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exir_ops.edge.aten.asin.default,
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exir_ops.edge.aten.atan.default,
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exir_ops.edge.aten.bitwise_or.Tensor,
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exir_ops.edge.aten.bitwise_xor.Tensor,
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exir_ops.edge.aten.bmm.default,
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exir_ops.edge.aten.bitwise_and.Tensor,
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exir_ops.edge.aten.cat.default,
@@ -78,6 +80,7 @@ class LayoutTransform(ExportPass):
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exir_ops.edge.aten.eq.Tensor,
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exir_ops.edge.aten.exp.default,
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exir_ops.edge.aten.floor.default,
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exir_ops.edge.aten.floor_divide.default,
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exir_ops.edge.aten.full.default,
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exir_ops.edge.aten.full_like.default,
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exir_ops.edge.aten.ge.Tensor,
@@ -107,6 +110,7 @@ class LayoutTransform(ExportPass):
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exir_ops.edge.aten.relu.default,
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exir_ops.edge.aten.round.default,
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exir_ops.edge.aten.sigmoid.default,
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exir_ops.edge.aten.sign.default,
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exir_ops.edge.aten.split_with_sizes.default,
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exir_ops.edge.aten.split_with_sizes_copy.default,
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exir_ops.edge.aten.sqrt.default,

‎backends/qualcomm/_passes/lift_constant_scalar_operands.py‎

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@@ -54,6 +54,7 @@ class TensorOpInfo:
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aten.where.ScalarOther: TensorOpInfo(aten.where.self, False, True),
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aten.where.Scalar: TensorOpInfo(aten.where.self, False, True),
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aten.masked_fill.Scalar: TensorOpInfo(aten.masked_fill.Tensor, False, False),
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aten.bitwise_xor.Scalar: TensorOpInfo(aten.bitwise_xor.Tensor, False, False),
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}
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@@ -64,6 +65,7 @@ class TensorOpInfo:
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aten.arange.default,
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aten.scalar_tensor.default,
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aten.elu.default,
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aten.hardtanh.default,
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}
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‎backends/qualcomm/builders/README.md‎

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@@ -360,7 +360,12 @@ The operator now should be functional for Qualcomm backends. For operator to wor
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## Operator Support Status
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Please help update following table if you are contributing new operators:
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| Operators | HTP - 82/116 Enabled |
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+ ✓ = Supported
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+ ✗ = Not Supported
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+ 🚫 = Deprecated, supported with other QNN Ops
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| Operators | HTP - 90/116 Enabled |
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|-----------|---------|
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| Argmax | ✓ |
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| Argmin | ✓ |
@@ -381,16 +386,16 @@ Please help update following table if you are contributing new operators:
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| ElementWiseAbs | ✓ |
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| ElementWiseAdd | ✓ |
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| ElementWiseAnd | ✓ |
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| ElementWiseAsin | ✗ |
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| ElementWiseAsin | ✓ |
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| ElementWiseAtan | ✓ |
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| ElementWiseBinary | ✗ |
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| ElementWiseBinary | ✓ |
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| ElementWiseCeil | ✓ |
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| ElementWiseCos | ✓ |
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| ElementWiseDivide | ✓ |
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| ElementWiseEqual | ✓ |
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| ElementWiseExp | ✓ |
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| ElementWiseFloor | ✓ |
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| ElementWiseFloorDiv | ✗ |
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| ElementWiseFloorDiv | ✓ |
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| ElementWiseGreater | ✓ |
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| ElementWiseGreaterEqual | ✓ |
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| ElementWiseLess | ✓ |
@@ -408,13 +413,13 @@ Please help update following table if you are contributing new operators:
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| ElementWiseRound | ✓ |
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| ElementWiseRsqrt | ✓ |
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| ElementWiseSelect | ✓ |
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| ElementWiseSign | ✗ |
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| ElementWiseSign | ✓ |
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| ElementWiseSin | ✓ |
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| ElementWiseSquaredDifference | ✗ |
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| ElementWiseSquareRoot | ✓ |
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| ElementWiseSubtract | ✓ |
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| ElementWiseUnary | ✗ |
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| ElementWiseXor | ✗ |
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| ElementWiseXor | ✓ |
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| Elu | ✓ |
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| ExpandDims | ✓ |
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| ExtractGlimpse | ✗ |
@@ -452,11 +457,11 @@ Please help update following table if you are contributing new operators:
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| ReduceMin | ✓ |
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| ReduceSum | ✓ |
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| Relu | ✓ |
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| Relu1 | ✗ |
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| Relu6 | ✗ |
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| Relu1 | 🚫 |
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| Relu6 | 🚫 |
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| ReluMinMax | ✓ |
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| Reshape | ✓ |
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| Resize | ✗ |
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| Resize | ✓ |
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| ResizeBilinear | ✓ |
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| ResizeNearestNeighbor | ✓ |
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| RoiAlign | ✗ |

‎backends/qualcomm/builders/__init__.py‎

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op_arange,
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op_argmax,
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op_argmin,
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op_asin,
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op_atan,
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op_avg_pool2d,
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op_batch_norm,
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op_binary,
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op_bmm,
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op_cat,
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op_ceil,
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op_scalar_tensor,
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op_select_copy,
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op_sigmoid,
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op_sign,
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op_sin,
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op_skip_ops,
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op_slice_copy,
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op_upsample_bilinear2d,
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op_upsample_nearest2d,
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op_where,
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op_xor,
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)
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__all__ = [
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op_arange,
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op_argmax,
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op_argmin,
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op_asin,
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op_atan,
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op_avg_pool2d,
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op_batch_norm,
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op_binary,
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op_bmm,
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op_cat,
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op_ceil,
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op_scalar_tensor,
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op_select_copy,
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op_sigmoid,
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op_sign,
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op_sin,
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op_skip_ops,
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op_slice_copy,
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op_upsample_bilinear2d,
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op_upsample_nearest2d,
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op_where,
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op_xor,
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]

‎backends/qualcomm/builders/op_asin.py‎

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# Copyright (c) Qualcomm Innovation Center, Inc.
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# All rights reserved
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#
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# This source code is licensed under the BSD-style license found in the
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# LICENSE file in the root directory of this source tree.from typing import cast, Dict
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from typing import Dict
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import executorch.backends.qualcomm.python.PyQnnWrapperAdaptor as PyQnnWrapper
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import torch
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from .node_visitor import NodeVisitor
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from .node_visitor_manager import register_node_visitor
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from .qnn_constants import OpElementWiseAsin, QNN_OP_PACKAGE_NAME_QTI_AISW
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@register_node_visitor
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class asin(NodeVisitor):
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target = ["aten.asin.default"]
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def __init__(self, *args) -> None:
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super().__init__(*args)
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def define_node(
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self,
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node: torch.fx.Node,
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nodes_to_wrappers: Dict[torch.fx.Node, PyQnnWrapper.TensorWrapper],
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) -> PyQnnWrapper.PyQnnOpWrapper:
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input_node = self.get_node(node.args[0])
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input_tensor = self.get_tensor(input_node, node)
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input_tensor_wrapper = self.define_tensor(
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input_node,
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node,
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input_tensor,
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PyQnnWrapper.Qnn_TensorType_t.QNN_TENSOR_TYPE_NATIVE,
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nodes_to_wrappers,
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)
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output_tensor = self.get_tensor(node, node)
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output_tensor_wrapper = self.define_tensor(
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node,
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node,
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output_tensor,
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PyQnnWrapper.Qnn_TensorType_t.QNN_TENSOR_TYPE_NATIVE,
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nodes_to_wrappers,
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)
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asin_op = PyQnnWrapper.PyQnnOpWrapper(
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node.name,
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QNN_OP_PACKAGE_NAME_QTI_AISW,
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OpElementWiseAsin.op_name,
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)
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asin_op.AddInputTensors([input_tensor_wrapper])
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asin_op.AddOutputTensors([output_tensor_wrapper])
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return asin_op

‎backends/qualcomm/builders/op_binary.py‎

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# Copyright (c) Qualcomm Innovation Center, Inc.
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# All rights reserved
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#
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# This source code is licensed under the BSD-style license found in the
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# LICENSE file in the root directory of this source tree.
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import warnings
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from typing import Dict
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import executorch.backends.qualcomm.python.PyQnnWrapperAdaptor as PyQnnWrapper
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import numpy as np
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import torch
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from executorch.backends.qualcomm.utils.constants import QCOM_DATA
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from executorch.exir.dialects._ops import ops as exir_ops
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from .node_visitor import NodeVisitor
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from .node_visitor_manager import register_node_visitor
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from .qnn_constants import OpElementWiseBinary, QNN_OP_PACKAGE_NAME_QTI_AISW
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# Refer to QnnOpDef.h for the value.
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QNN_BINARY_OPERATOR = {
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exir_ops.edge.aten.floor_divide.default: 4,
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}
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@register_node_visitor
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class Binary(NodeVisitor):
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target = ["aten.floor_divide.default"]
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def __init__(self, *args) -> None:
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super().__init__(*args)
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def define_node(
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self,
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node: torch.fx.Node,
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nodes_to_wrappers: Dict[torch.fx.Node, PyQnnWrapper.TensorWrapper],
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) -> PyQnnWrapper.PyQnnOpWrapper:
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out_tensor = self.get_tensor(node, node)
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output_tensor_wrapper = self.define_tensor(
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node,
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node,
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out_tensor,
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PyQnnWrapper.Qnn_TensorType_t.QNN_TENSOR_TYPE_NATIVE,
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nodes_to_wrappers,
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)
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binary_output_tensors = [output_tensor_wrapper]
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binary_input_tensors = []
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for index in range(2):
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input_node = self.get_node(node.args[index])
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input_tensor = self.get_tensor(input_node, node)
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tensor_type = PyQnnWrapper.Qnn_TensorType_t.QNN_TENSOR_TYPE_NATIVE
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input_tensor_wrapper = self.define_tensor(
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input_node,
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node,
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input_tensor,
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tensor_type,
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nodes_to_wrappers,
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)
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binary_input_tensors.append(input_tensor_wrapper)
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binary_op = PyQnnWrapper.PyQnnOpWrapper(
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node.name,
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QNN_OP_PACKAGE_NAME_QTI_AISW,
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OpElementWiseBinary.op_name,
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)
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binary_op.AddInputTensors(binary_input_tensors)
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binary_op.AddOutputTensors(binary_output_tensors)
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if node.target not in QNN_BINARY_OPERATOR:
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warnings.warn(
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"[QNN Delegate Op Builder]: This binary operator is not yet supported.",
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stacklevel=1,
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)
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return None
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binary_op.AddScalarParam(
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OpElementWiseBinary.param_operation,
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PyQnnWrapper.Qnn_DataType_t.QNN_DATATYPE_UINT_32,
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{QCOM_DATA: np.uint32(QNN_BINARY_OPERATOR[node.target])},
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)
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return binary_op

‎backends/qualcomm/builders/op_ne.py‎

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@register_node_visitor
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class NotEqual(NodeVisitor):
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target = ["aten.ne.Tensor", "aten.ne.Scalar"]
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target = ["aten.ne.Tensor"]
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def __init__(self, *args) -> None:
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super().__init__(*args)

‎backends/qualcomm/builders/op_sign.py‎

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# Copyright (c) Qualcomm Innovation Center, Inc.
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# All rights reserved
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#
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# This source code is licensed under the BSD-style license found in the
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# LICENSE file in the root directory of this source tree.
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from typing import Dict
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import executorch.backends.qualcomm.python.PyQnnWrapperAdaptor as PyQnnWrapper
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import torch
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from .node_visitor import NodeVisitor
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from .node_visitor_manager import register_node_visitor
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from .qnn_constants import OpElementWiseSign, QNN_OP_PACKAGE_NAME_QTI_AISW
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@register_node_visitor
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class Sign(NodeVisitor):
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target = ["aten.sign.default"]
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def __init__(self, *args) -> None:
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super().__init__(*args)
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def define_node(
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self,
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node: torch.fx.Node,
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nodes_to_wrappers: Dict[torch.fx.Node, PyQnnWrapper.TensorWrapper],
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) -> PyQnnWrapper.PyQnnOpWrapper:
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input_node = self.get_node(node.args[0])
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input_tensor = self.get_tensor(input_node, node)
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input_tensor_wrapper = self.define_tensor(
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input_node,
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node,
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input_tensor,
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PyQnnWrapper.Qnn_TensorType_t.QNN_TENSOR_TYPE_NATIVE,
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nodes_to_wrappers,
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)
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output_tensor = self.get_tensor(node, node)
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output_tensor_wrapper = self.define_tensor(
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node,
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node,
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output_tensor,
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PyQnnWrapper.Qnn_TensorType_t.QNN_TENSOR_TYPE_NATIVE,
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nodes_to_wrappers,
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)
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sign_op = PyQnnWrapper.PyQnnOpWrapper(
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node.name,
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QNN_OP_PACKAGE_NAME_QTI_AISW,
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OpElementWiseSign.op_name,
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)
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sign_op.AddInputTensors([input_tensor_wrapper])
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sign_op.AddOutputTensors([output_tensor_wrapper])
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return sign_op

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