diff --git a/examples/arm/ethos-u-setup/core_platform/0001-Add-got-section-to-the-DDR.patch b/examples/arm/ethos-u-setup/core_platform/0001-Add-got-section-to-the-DDR.patch
deleted file mode 100644
index f2088f3c933..00000000000
--- a/examples/arm/ethos-u-setup/core_platform/0001-Add-got-section-to-the-DDR.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From e637571ca767671d8114542d85bca7965e0a4251 Mon Sep 17 00:00:00 2001
-From: Per Held <per.held@arm.com>
-Date: Fri, 25 Apr 2025 13:25:29 +0200
-Subject: [PATCH 1/2] Add got section to the DDR
-
----
- targets/corstone-300/platform.ld | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld
-index d586b97..b746aa0 100644
---- a/targets/corstone-300/platform.ld
-+++ b/targets/corstone-300/platform.ld
-@@ -281,7 +281,7 @@ SECTIONS
- #endif
-     * (expected_output_data_sec)
-     * (sec_command_stream, sec_weight_data, sec_input_data)
--
-+    * (.got*)
-     * (ethosu_core_in_queue)
-     * (ethosu_core_out_queue)
-     . = ALIGN(4);
--- 
-2.43.0
-
diff --git a/examples/arm/ethos-u-setup/core_platform/0002-Move-input_data_sec-to-NOLOAD-area.patch b/examples/arm/ethos-u-setup/core_platform/0002-Move-input_data_sec-to-NOLOAD-area.patch
deleted file mode 100644
index e9f1c332b42..00000000000
--- a/examples/arm/ethos-u-setup/core_platform/0002-Move-input_data_sec-to-NOLOAD-area.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-From 42a16a7e9c73e79e55ee25534e3bbc39f169af62 Mon Sep 17 00:00:00 2001
-From: Per Held <per.held@arm.com>
-Date: Mon, 28 Apr 2025 10:56:09 +0200
-Subject: [PATCH 2/2] Move input_data_sec to NOLOAD area
-
----
- targets/corstone-300/platform.ld | 10 ++++++++--
- targets/corstone-320/platform.ld |  8 ++++++--
- 2 files changed, 14 insertions(+), 4 deletions(-)
-
-diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld
-index b746aa0..5043be2 100644
---- a/targets/corstone-300/platform.ld
-+++ b/targets/corstone-300/platform.ld
-@@ -273,19 +273,25 @@ SECTIONS
-     *(.bss.tensor_arena)
- #endif
- 
--    . = ALIGN(4);
--    *(input_data_sec)
-     . = ALIGN(16);
- #if (ETHOSU_MODEL == 1)
-     *(network_model_sec)
- #endif
-     * (expected_output_data_sec)
-+    . = ALIGN(16);
-     * (sec_command_stream, sec_weight_data, sec_input_data)
-     * (.got*)
-     * (ethosu_core_in_queue)
-     * (ethosu_core_out_queue)
-     . = ALIGN(4);
-   } > DDR :rom_dram
-+  .ddr_noload (NOLOAD) :
-+  {
-+    . = ALIGN(16);
-+    *(input_data_sec)
-+    . = ALIGN(16);
-+  } > DDR :null
-+
- 
-   __eddr_data = ALIGN(4);
-   .sram.data :
-diff --git a/targets/corstone-320/platform.ld b/targets/corstone-320/platform.ld
-index 1f4f521..8c5e402 100644
---- a/targets/corstone-320/platform.ld
-+++ b/targets/corstone-320/platform.ld
-@@ -268,8 +268,6 @@ SECTIONS
-     *(network_model_sec)
- #endif
- 
--    . = ALIGN(4);
--    *(input_data_sec)
-     *(expected_output_data_sec)
-     *(output_data_sec)
- 
-@@ -279,6 +277,12 @@ SECTIONS
-     __etext = .;
-   } > DDR :rom_dram
- 
-+  .ddr_noload (NOLOAD) :
-+  {
-+    . = ALIGN(16);
-+    *(input_data_sec)
-+  } > DDR :null
-+
-   .bss :
-   {
-     . = ALIGN(4);
--- 
-2.43.0
-
diff --git a/examples/arm/ethos-u-setup/core_platform/0003-Move-the-portable-kernels-to-the-BRAM.patch b/examples/arm/ethos-u-setup/core_platform/0003-Move-the-portable-kernels-to-the-BRAM.patch
deleted file mode 100644
index ccb27b83711..00000000000
--- a/examples/arm/ethos-u-setup/core_platform/0003-Move-the-portable-kernels-to-the-BRAM.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 81f5bd9092bc25c343d8d85b692698c6d961d0bd Mon Sep 17 00:00:00 2001
-From: George Gekov <george.gekov@arm.com>
-Date: Mon, 28 Jul 2025 15:23:50 +0100
-Subject: [PATCH] Move the portable kernels to the BRAM
-
-On the Corstone-300, we have 512KB of ITCM and by default,
-the .text section lives in the ITCM. However, as we build more
-portable kernels, we sometimes overflow and the .text section
-no longer fits in the ITCM. This patch moves the portable kernels
-to the BRAM as we have 1MB of BRAM
----
- targets/corstone-300/platform.ld | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
-diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld
-index 5043be2..399e9f7 100644
---- a/targets/corstone-300/platform.ld
-+++ b/targets/corstone-300/platform.ld
-@@ -135,7 +135,11 @@ SECTIONS
-   {
-     _vectors = .;
-     KEEP(*(.vectors))
--    *(.text*)
-+    *(EXCLUDE_FILE(
-+                  *op_*.cpp.obj
-+                   )
-+
-+    .text*)
- 
-     KEEP(*(.init))
-     KEEP(*(.fini))
-@@ -299,6 +303,7 @@ SECTIONS
-     __sram_data_start__ = .;
-     *(.sram.data)
-     . = ALIGN(4);
-+    *op_*.cpp.obj (*.text*)
-     __sram_data_end__ = .;
-   } > BRAM AT >DDR :rom_dram
- 
--- 
-2.39.5 (Apple Git-154)
-
diff --git a/examples/arm/executor_runner/CMakeLists.txt b/examples/arm/executor_runner/CMakeLists.txt
index 5e1d7b08147..69a5c945bfa 100644
--- a/examples/arm/executor_runner/CMakeLists.txt
+++ b/examples/arm/executor_runner/CMakeLists.txt
@@ -143,8 +143,28 @@ target_sources(
                               arm_memory_allocator.cpp
 )
 
-# Include the target's bare-metal linker script
-ethosu_eval_link_options(arm_executor_runner)
+# Use our own linkerscripts
+# Check for "U55" in SYSTEM_CONFIG
+string(FIND "${SYSTEM_CONFIG}" "U55" U55_FOUND)
+
+# Check for "U85" in SYSTEM_CONFIG
+string(FIND "${SYSTEM_CONFIG}" "U85" U85_FOUND)
+
+# Check if neither "U55" nor "U85" was found
+if(U55_FOUND EQUAL -1 AND U85_FOUND EQUAL -1)
+    message(FATAL_ERROR "SYSTEM_CONFIG does not contain 'U55' or 'U85'. Configuration aborting.")
+endif()
+
+# Proceed with specific actions if either is found
+if(NOT U55_FOUND EQUAL -1)
+    message(STATUS "SYSTEM_CONFIG contains 'U55'.")
+    target_link_options(arm_executor_runner PRIVATE "-T" "${CMAKE_SOURCE_DIR}/Corstone-300.ld")
+endif()
+
+if(NOT U85_FOUND EQUAL -1)
+    message(STATUS "SYSTEM_CONFIG contains 'U85'.")
+    target_link_options(arm_executor_runner PRIVATE "-T" "${CMAKE_SOURCE_DIR}/Corstone-320.ld")
+endif()
 
 set(arm_executor_runner_link)
 list(
diff --git a/examples/arm/executor_runner/Corstone-300.ld b/examples/arm/executor_runner/Corstone-300.ld
new file mode 100644
index 00000000000..6880e9f0cb6
--- /dev/null
+++ b/examples/arm/executor_runner/Corstone-300.ld
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates.
+ *
+ * This source code is licensed under the BSD-style license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+ /*
+ * This is a simplified linkerscript for the Corstone-300 memory system.
+ * This example has been modified to place certain sections in specific memory.
+ * Please refer to the Corstone SSE-300 Technical Reference Manual for
+ * further information.
+ *
+ * https://developer.arm.com/Processors/Corstone-300
+ */
+
+__STACK_SIZE = 0x00008000;
+__HEAP_SIZE = 0x00008000;
+MEMORY
+{
+  ITCM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
+  BRAM (rw) : ORIGIN = 0x11000000, LENGTH = 0x00100000
+  DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 0x00080000
+  SRAM (rw) : ORIGIN = 0x31000000, LENGTH = 0x00200000
+  QSPI (rw) : ORIGIN = 0x38000000, LENGTH = 0x00800000
+  DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x60000000
+}
+PHDRS
+{
+    rom_exec PT_LOAD;
+    rom_dram PT_LOAD;
+    null PT_NULL;
+}
+ENTRY(Reset_Handler)
+SECTIONS
+{
+  .text :
+  {
+    _vectors = .;
+    KEEP(*(.vectors))
+    *(EXCLUDE_FILE(
+                  *op_*.cpp.obj
+                   )
+    .text*)
+    KEEP(*(.init))
+    KEEP(*(.fini))
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+    KEEP(*(.eh_frame*))
+  } > ITCM :rom_exec
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > ITCM :rom_exec
+  .ARM.exidx :
+  {
+  __exidx_start = .;
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  __exidx_end = .;
+  } > ITCM :rom_exec
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+    LONG (__etext)
+    LONG (__data_start__)
+    LONG ((__data_end__ - __data_start__) / 4)
+    LONG (__eddr_data)
+    LONG (__sram_data_start__)
+    LONG ((__sram_data_end__ - __sram_data_start__) / 4)
+    LONG (__eddr_data + (__sram_data_end__ - __sram_data_start__))
+    LONG (__rodata_start__)
+    LONG ((__rodata_end__ - __rodata_start__) / 4)
+    __copy_table_end__ = .;
+  } > ITCM :rom_exec
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+    LONG (__bss_start__)
+    LONG ((__bss_end__ - __bss_start__) / 4)
+    __zero_table_end__ = .;
+  __etext = ALIGN (4);
+  } > ITCM :rom_exec
+  .data : AT(__etext)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;
+  } > DTCM :rom_exec
+  .sram.bss :
+  {
+    . = ALIGN(16);
+    . = ALIGN(32);
+    *(.bss.tensor_arena)
+    . = ALIGN(16);
+    *(.bss.ethosu_scratch);
+    *.(output_data_sec)
+  } > SRAM :null
+  .ddr :
+  {
+    . = ALIGN(16);
+    *(network_model_sec)
+    * (expected_output_data_sec)
+    . = ALIGN(16);
+    * (sec_command_stream, sec_weight_data, sec_input_data)
+    * (.got*)
+    * (ethosu_core_in_queue)
+    * (ethosu_core_out_queue)
+    . = ALIGN(4);
+  } > DDR :rom_dram
+  .ddr_noload (NOLOAD) :
+  {
+    . = ALIGN(16);
+    *(input_data_sec)
+    . = ALIGN(16);
+  } > DDR :null
+  __eddr_data = ALIGN(4);
+  .sram.data :
+  {
+    __sram_data_start__ = .;
+    *(.sram.data)
+    . = ALIGN(4);
+    *op_*.cpp.obj (*.text*)
+    __sram_data_end__ = .;
+  } > BRAM AT >DDR :rom_dram
+  .rodata :
+  {
+    __rodata_start__ = .;
+    *(.rodata)
+    *(.rodata.*)
+    . = ALIGN(4);
+    __rodata_end__ = .;
+  } > DTCM AT >DDR :rom_dram
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > DTCM :null
+  .heap (COPY) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > DTCM :null
+  .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > DTCM :null
+  PROVIDE(__stack = __StackTop);
+  __RAM_segment_used_end__ = .;
+  ASSERT(__StackLimit >= __HeapLimit, "region DTCM overflowed with stack")
+}
diff --git a/examples/arm/executor_runner/Corstone-320.ld b/examples/arm/executor_runner/Corstone-320.ld
new file mode 100644
index 00000000000..7865d752f5b
--- /dev/null
+++ b/examples/arm/executor_runner/Corstone-320.ld
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates.
+ *
+ * This source code is licensed under the BSD-style license found in the
+ * LICENSE file in the root directory of this source tree.
+ */
+
+ /*
+ * This is a simplified linkerscript for the Corstone-300 memory system.
+ * This example has been modified to place certain sections in specific memory.
+ * Please refer to the Corstone SSE-300 Technical Reference Manual for
+ * further information.
+ *
+ * https://developer.arm.com/Processors/Corstone-320
+ */
+
+__STACK_SIZE = 0x8000;
+__HEAP_SIZE = 0x10000;
+MEMORY
+{
+  ITCM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x00008000
+  BROM (rx) : ORIGIN = 0x11000000, LENGTH = 0x00020000
+  BRAM (rwx) : ORIGIN = 0x12000000, LENGTH = 0x00200000
+  DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000
+  SRAM (rw) : ORIGIN = 0x31000000, LENGTH = 0x00400000
+  QSPI (rw) : ORIGIN = 0x38000000, LENGTH = 0x00800000
+  DDR (rw) : ORIGIN = 0x70000000, LENGTH = 0x10000000
+}
+PHDRS
+{
+    rom_boot PT_LOAD;
+    rom_exec PT_LOAD;
+    rom_dram PT_LOAD;
+    null PT_NULL;
+}
+ENTRY(Reset_Handler)
+SECTIONS
+{
+  .text.vectors :
+  {
+    KEEP(*(.vectors))
+  } > BROM :rom_boot
+  .data.vtable_rw (COPY):
+  {
+    . = ALIGN(0x800);
+    KEEP(*(.vtable_rw))
+  } > ITCM :null
+  .text :
+  {
+    *crt* (.text*)
+    *startup_ARMCM85.c.obj (.text*)
+    *system_ARMCM85.c.obj (.text*)
+    *target.cpp.obj (.text*)
+    KEEP(*(.init))
+    KEEP(*(.fini))
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+    *(.text*)
+    KEEP(*(.eh_frame*))
+  } > BRAM :rom_exec
+  .data :
+  {
+    . = ALIGN(4);
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+    *(.rodata*)
+    . = ALIGN(4);
+    __data_end__ = .;
+  } > BRAM :rom_exec
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > BRAM :rom_exec
+  .ARM.exidx :
+  {
+  __exidx_start = .;
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  __exidx_end = .;
+  } > BRAM :rom_exec
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+    LONG (LOADADDR(.sram))
+    LONG (ADDR(.sram))
+    LONG (SIZEOF(.sram) / 4)
+    __copy_table_end__ = .;
+  } > BRAM :rom_exec
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+    LONG (ADDR(.bss))
+    LONG (SIZEOF(.bss) / 4)
+    LONG (ADDR(.sram.bss))
+    LONG (SIZEOF(.sram.bss) / 4)
+    __zero_table_end__ = .;
+  } > BRAM :rom_exec
+  .sram : AT(__etext)
+  {
+    . = ALIGN(16);
+    *(.sram.data)
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    KEEP(*(.jcr*))
+  } > SRAM :rom_dram
+  .sram.bss :
+  {
+    . = ALIGN(16);
+    *(.bss.ethosu_scratch);
+  } > SRAM :null
+  .ddr :
+  {
+    . = ALIGN(32);
+    *(.bss.tensor_arena)
+    . = ALIGN(16);
+    *(network_model_sec)
+    *(expected_output_data_sec)
+    *(output_data_sec)
+    *(ethosu_core_in_queue ethosu_core_out_queue)
+    __etext = .;
+  } > DDR :rom_dram
+  .ddr_noload (NOLOAD) :
+  {
+    . = ALIGN(16);
+    *(input_data_sec)
+  } > DDR :null
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > BRAM :null
+  .heap (ORIGIN(BRAM) + LENGTH(BRAM) - __HEAP_SIZE) (COPY) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > BRAM :null
+  .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > DTCM :null
+  PROVIDE(__stack = __StackTop);
+  ASSERT(LENGTH(DTCM) >= __STACK_SIZE, "region DTCM overflowed with stack")
+}