Arm backend: Handle Ethos-U output layout mismatches #15588
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Vela can pad or pack an inference output, so the byte layout of a tensor may not match what ExecuTorch expects. The runtime now detects those cases and strips padding and/or expand packed 4‑bit activations back into signed int8 tensors. Change-Id: I730b91b83f3793e7fba0755e4a5ed01147555cb8 Signed-off-by: Sebastian Larsson <[email protected]>
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/15588
Note: Links to docs will display an error until the docs builds have been completed. ✅ You can merge normally! (6 Unrelated Failures)As of commit 965b6cf with merge base 993254c ( FLAKY - The following job failed but was likely due to flakiness present on trunk:
BROKEN TRUNK - The following jobs failed but was present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
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Vela can pad or pack an inference output, so the byte layout of a tensor may not match what ExecuTorch expects. The runtime now detects those cases and strips padding and/or expand packed 4‑bit activations back into signed int8 tensors. Signed-off-by: Sebastian Larsson <[email protected]>
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Vela can pad or pack an inference output, so the byte layout of a tensor may not match what ExecuTorch expects. The runtime now detects those cases and strips padding and/or expand packed 4‑bit activations back into signed int8 tensors.
cc @freddan80 @per @zingo @oscarandersson8218 @digantdesai