Skip to content

Conversation

@zingo
Copy link
Collaborator

@zingo zingo commented Nov 13, 2024

As some bigger model don't fit in the SRAM area in the Corstone 3x0 FVP setup lets default to useing the DDR area.

Signed-off-by: Zingo Andersen <[email protected]>
Change-Id: I34e9e6cf8ef506236c656ea270ba9db58d9a64da
@pytorch-bot
Copy link

pytorch-bot bot commented Nov 13, 2024

🔗 Helpful Links

🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/6812

Note: Links to docs will display an error until the docs builds have been completed.

❌ 1 New Failure

As of commit b0c5dc4 with merge base 97e0417 (image):

NEW FAILURE - The following job has failed:

This comment was automatically generated by Dr. CI and updates every 15 minutes.

@facebook-github-bot facebook-github-bot added the CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. label Nov 13, 2024
@zingo zingo added partner: arm For backend delegation, kernels, demo, etc. from the 3rd-party partner, Arm ciflow/trunk labels Nov 13, 2024
@freddan80 freddan80 merged commit 73893e1 into pytorch:main Nov 13, 2024
96 of 97 checks passed
@zingo zingo deleted the Arm-Backend-Place-pte-file/data-in-DDR-area branch November 14, 2024 14:56
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

ciflow/trunk CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. partner: arm For backend delegation, kernels, demo, etc. from the 3rd-party partner, Arm

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants