From b0c5dc4533200b9916ccf5bce3f80e49ab08357b Mon Sep 17 00:00:00 2001 From: Zingo Andersen Date: Tue, 5 Nov 2024 10:11:55 +0100 Subject: [PATCH] Arm Backend: Place pte file/data in DDR area Signed-off-by: Zingo Andersen Change-Id: I34e9e6cf8ef506236c656ea270ba9db58d9a64da --- examples/arm/executor_runner/CMakeLists.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/examples/arm/executor_runner/CMakeLists.txt b/examples/arm/executor_runner/CMakeLists.txt index be6e309a64b..064023a70de 100644 --- a/examples/arm/executor_runner/CMakeLists.txt +++ b/examples/arm/executor_runner/CMakeLists.txt @@ -63,6 +63,9 @@ endif() if(TARGET_BOARD STREQUAL "corstone-300") add_subdirectory(${ETHOS_SDK_PATH}/core_platform/targets/corstone-300 target) target_compile_definitions(ethosu_target_common INTERFACE + # ETHOSU_MODEL=0 place pte file/data in SRAM area + # ETHOSU_MODEL=1 place pte file/data in DDR area + ETHOSU_MODEL=1 # Configure NPU architecture timing adapters # Ethos_U55_High_End_Embedded # This is just example numbers and you should make this match your hardware @@ -98,6 +101,9 @@ if(TARGET_BOARD STREQUAL "corstone-300") elseif(TARGET_BOARD STREQUAL "corstone-320") add_subdirectory(${ETHOS_SDK_PATH}/core_platform/targets/corstone-320 target) target_compile_definitions(ethosu_target_common INTERFACE + # ETHOSU_MODEL=0 place pte file/data in SRAM area + # ETHOSU_MODEL=1 place pte file/data in DDR area + ETHOSU_MODEL=1 # Configure NPU architecture timing adapters # Ethos_U85_SYS_DRAM_Mid # This is just example numbers and you should make this match your hardware