Fix circuit-metadata propagation in SabreLayout (backport Qiskit#14186) (Qiskit#14190)

* Fix circuit-metadata propagation in `SabreLayout` (Qiskit#14186)

This has been a bug since Qiskitgh-10712, but wasn't caught by the integration
test in the test suite because the circuit has a perfect layout, so the
layout stage was short-circuiting out after VF2.

(cherry picked from commit 2504bde)

# Conflicts:
#	qiskit/transpiler/passes/layout/sabre_layout.py

* Fix merge conflicts

* Adjust plugins used in testing for 1.4.x

---------

Co-authored-by: Jake Lishman <[email protected]>
Co-authored-by: Matthew Treinish <[email protected]>

Author: 3 people

qiskit/transpiler/passes/layout/sabre_layout.py

@@ -305,6 +305,9 @@ def run(self, dag):
         # the layout and routing together as part of resolving the Sabre result.
         physical_qubits = QuantumRegister(self.coupling_map.size(), "q")
         mapped_dag = DAGCircuit()
+        mapped_dag.name = dag.name
+        mapped_dag.metadata = dag.metadata
+        mapped_dag.global_phase = dag.global_phase
         mapped_dag.add_qreg(physical_qubits)
         mapped_dag.add_clbits(dag.clbits)
         for creg in dag.cregs.values():
@@ -315,7 +318,7 @@ def run(self, dag):
             mapped_dag.add_captured_var(var)
         for var in dag.iter_declared_vars():
             mapped_dag.add_declared_var(var)
-        mapped_dag.global_phase = dag.global_phase
+
         self.property_set["original_qubit_indices"] = {
             bit: index for index, bit in enumerate(dag.qubits)
         }

releasenotes/notes/fix-sabre-metadata-88e2a63c02810e61.yaml

@@ -0,0 +1,5 @@
+---
+fixes:
+  - |
+    :class:`.SabreLayout` will now correctly propagate a circuit's :attr:`~.DAGCircuit.name` and
+    :attr:`~.DAGCircuit.metadata` fields when performing as a joint layout and routing pass.

test/python/transpiler/test_preset_passmanagers.py

@@ -1576,8 +1576,15 @@ def test_parse_seed_transpiler_raises_value_error(self):
         ):
             generate_preset_pass_manager(seed_transpiler=0.1)
 
-    @data(0, 1, 2, 3)
-    def test_preserves_circuit_metadata(self, optimization_level):
+    @combine(
+        optimization_level=[0, 1, 2, 3],
+        layout_method=["default", "dense", "sabre"],
+        routing_method=["sabre", "lookahead"],
+        translation_method=["translator", "synthesis"],
+    )
+    def test_preserves_circuit_metadata(
+        self, optimization_level, layout_method, routing_method, translation_method
+    ):
         """Test that basic metadata is preserved."""
         metadata = {"experiment_id": "1234", "execution_number": 4}
         name = "my circuit"
@@ -1592,7 +1599,12 @@ def test_preserves_circuit_metadata(self, optimization_level):
         target.add_instruction(CXGate(), {pair: None for pair in CouplingMap.from_line(num_qubits)})
 
         pm = generate_preset_pass_manager(
-            optimization_level=optimization_level, target=target, seed_transpiler=42
+            optimization_level=optimization_level,
+            target=target,
+            seed_transpiler=42,
+            layout_method=layout_method,
+            routing_method=routing_method,
+            translation_method=translation_method,
         )
         res = pm.run(circuit)
         self.assertEqual(res.metadata, metadata)