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update mac syscall return
1 parent 16aa783 commit 0eb66a9

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7 files changed

+16
-13
lines changed

7 files changed

+16
-13
lines changed

ChangeLog

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ BREAK CHANGE
1717
- Added support for binaries that return from their entrypoint (PE / ELF).
1818
- Configure Qiling with 'stop_on_stackpointer' or 'stop_on_exit_trap'.
1919
- Add basic Windows driver tests / example
20+
- UEFI refactor
2021

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2223
------------------------------------

qiling/arch/arm64.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ def __init__(self, ql):
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super(QlArchARM64, self).__init__(ql)
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1717
register_mappings = [
18-
reg_map, reg_map_part
18+
reg_map, reg_map_w
1919
]
2020

2121
for reg_maper in register_mappings:

qiling/arch/arm64_const.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@
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"tpidr_el0": UC_ARM64_REG_TPIDR_EL0,
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}
4646

47-
reg_map_part = {
47+
reg_map_w = {
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"w0" : UC_ARM64_REG_W0,
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"w1" : UC_ARM64_REG_W1,
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"w2" : UC_ARM64_REG_W2,

qiling/arch/x86.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ def __init__(self, ql):
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x64_register_mappings = [
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reg_map_8, reg_map_16, reg_map_32, reg_map_64,
73-
reg_map_cr, reg_map_st, reg_map_misc, reg_map_part
73+
reg_map_cr, reg_map_st, reg_map_misc, reg_map_r
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]
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for reg_maper in x64_register_mappings:

qiling/arch/x86_const.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@
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"rip": UC_X86_REG_RIP,
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}
108108

109-
reg_map_part = {
109+
reg_map_r = {
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"r8b": UC_X86_REG_R8B,
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"r9b": UC_X86_REG_R9B,
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"r10b": UC_X86_REG_R10B,

qiling/core.py

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,16 @@ def __init__(
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self._root = False
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self._filter = None
9999

100+
###############################
101+
# Properties configured later #
102+
###############################
103+
self.entry_point = None
104+
self.exit_point = None
105+
self.timeout = None
106+
self.count = None
107+
self._initial_sp = None
108+
109+
100110
"""
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Qiling Framework Core Engine
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"""
@@ -206,14 +216,6 @@ def __init__(
206216
# Add extra guard options when configured to do so
207217
self._init_stop_guard()
208218

209-
###############################
210-
# Properties configured later #
211-
###############################
212-
self.entry_point = None
213-
self.exit_point = None
214-
self.timeout = None
215-
self.count = None
216-
self._initial_sp = None
217219

218220
#####################
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# Qiling Components #

qiling/os/macos/syscall.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -541,7 +541,7 @@ def ql_syscall_write_nocancel(ql, write_fd, write_buf, write_count, *args, **kw)
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raise
542542
#if buf:
543543
# logging.info(buf.decode(errors='ignore'))
544-
ql.os.definesyscall_return(regreturn)
544+
return 0
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547547
# 0x18e

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