@@ -47,18 +47,6 @@ def __init__(self, ql: Qiling):
4747 self .elf_mem_start = 0x0
4848 self .load ()
4949
50- cc : QlCC = {
51- QL_ARCH .X86 : intel .cdecl ,
52- QL_ARCH .X8664 : intel .amd64 ,
53- QL_ARCH .ARM : arm .aarch32 ,
54- QL_ARCH .ARM64 : arm .aarch64 ,
55- QL_ARCH .MIPS : mips .mipso32 ,
56- QL_ARCH .RISCV : riscv .riscv ,
57- QL_ARCH .RISCV64 : riscv .riscv ,
58- }[ql .archtype ](ql )
59-
60- self .fcall = QlFunctionCall (ql , cc )
61-
6250 # use counters to get free Ids
6351 self .channel_id = 1
6452 # TODO: replace 0x400 with NR_OPEN from Qiling 1.25
@@ -118,10 +106,9 @@ def run(self):
118106 self .cpupage_tls_addr = int (self .ql .os .profile .get ("OS32" , "cpupage_tls_address" ), 16 )
119107 self .tls_data_addr = int (self .ql .os .profile .get ("OS32" , "tls_data_address" ), 16 )
120108 self .syspage_addr = int (self .ql .os .profile .get ("OS32" , "syspage_address" ), 16 )
121- syspage_path = os .path .join (self .ql .rootfs , "syspage.bin" )
109+ syspage_path = os .path .join (self .ql .rootfs , "syspage.bin" )
122110
123111 self .ql .mem .map (self .syspage_addr , 0x4000 , info = "[syspage_mem]" )
124-
125112
126113 with open (syspage_path , "rb" ) as sp :
127114 self .ql .mem .write (self .syspage_addr , sp .read ())
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