Fix stm32f4 DMA copy bug

Author: cla7aye15I4nd

qiling/hw/const/stm32f4xx_dma.py

@@ -146,10 +146,14 @@ class DMA_SxM1AR(IntEnum):
 	M1A = 0xffffffff << 0
 
 class DMA(IntEnum):
-    PERIPH_TO_MEMORY = 0
-    MEMORY_TO_PERIPH = DMA_SxCR.DIR_0
-    MEMORY_TO_MEMORY = DMA_SxCR.DIR_1
+	PERIPH_TO_MEMORY = 0
+	MEMORY_TO_PERIPH = DMA_SxCR.DIR_0
+	MEMORY_TO_MEMORY = DMA_SxCR.DIR_1
 
-    PDATAALIGN_BYTE     = 0
-    PDATAALIGN_HALFWORD = DMA_SxCR.MSIZE_0
-    PDATAALIGN_WORD     = DMA_SxCR.MSIZE_1
+	PDATAALIGN_BYTE     = 0
+	PDATAALIGN_HALFWORD = DMA_SxCR.PSIZE_0
+	PDATAALIGN_WORD     = DMA_SxCR.PSIZE_1
+
+	MDATAALIGN_BYTE     = 0
+	MDATAALIGN_HALFWORD = DMA_SxCR.MSIZE_0
+	MDATAALIGN_WORD     = DMA_SxCR.MSIZE_1

qiling/hw/dma/stm32f4xx_dma.py

@@ -23,7 +23,7 @@ def enable(self):
     def transfer_direction(self):
         return self.CR & DMA_SxCR.DIR
 
-    def transfer_size(self):
+    def transfer_peripheral_size(self):
         PSIZE = self.CR & DMA_SxCR.PSIZE
         if PSIZE == DMA.PDATAALIGN_BYTE:
             return 1
@@ -32,22 +32,35 @@ def transfer_size(self):
         if PSIZE == DMA.PDATAALIGN_WORD:
             return 4
 
+    def transfer_memory_size(self):
+        MSIZE = self.CR & DMA_SxCR.MSIZE
+        if MSIZE == DMA.MDATAALIGN_BYTE:
+            return 1
+        if MSIZE == DMA.MDATAALIGN_HALFWORD:
+            return 2
+        if MSIZE == DMA.MDATAALIGN_WORD:
+            return 4
+
     def step(self, mem):
         if self.NDTR == 0:
             return
 
-        dir_flag = self.transfer_direction() == DMA.MEMORY_TO_PERIPH 
+        dir_flag = self.transfer_direction() == DMA.MEMORY_TO_PERIPH
+
+        psize = self.transfer_peripheral_size()
+        msize = self.transfer_memory_size()
 
-        size = self.transfer_size()        
         src, dst = (self.M0AR, self.PAR) if dir_flag else (self.PAR, self.M0AR)
+        src_size, dst_size = (msize, psize) if dir_flag else (psize, msize)
+
+        data = bytes(mem.read(src, src_size)).ljust(dst_size)[:dst_size]
+        mem.write(dst, data)
 
-        mem.write(dst, bytes(mem.read(src, size)))
-        
         self.NDTR -= 1
         if self.CR & DMA_SxCR.MINC:
-            self.M0AR += size
+            self.M0AR += msize
         if self.CR & DMA_SxCR.PINC:
-            self.PAR  += size
+            self.PAR  += psize
 
         if self.NDTR == 0:
             self.CR &= ~DMA_SxCR.EN