Add ARM D* registers

Author: elicn

qiling/arch/arm_const.py

@@ -40,3 +40,39 @@
     "c13_c0_3": UC_ARM_REG_C13_C0_3,
     "fpexc": UC_ARM_REG_FPEXC
 }
+
+reg_vfp = {
+    "d0" : UC_ARM_REG_D0,
+    "d1" : UC_ARM_REG_D1,
+    "d2" : UC_ARM_REG_D2,
+    "d3" : UC_ARM_REG_D3,
+    "d4" : UC_ARM_REG_D4,
+    "d5" : UC_ARM_REG_D5,
+    "d6" : UC_ARM_REG_D6,
+    "d7" : UC_ARM_REG_D7,
+    "d8" : UC_ARM_REG_D8,
+    "d9" : UC_ARM_REG_D9,
+    "d10" : UC_ARM_REG_D10,
+    "d11" : UC_ARM_REG_D11,
+    "d12" : UC_ARM_REG_D12,
+    "d13" : UC_ARM_REG_D13,
+    "d14" : UC_ARM_REG_D14,
+    "d15" : UC_ARM_REG_D15,
+    "d16" : UC_ARM_REG_D16,
+    "d17" : UC_ARM_REG_D17,
+    "d18" : UC_ARM_REG_D18,
+    "d19" : UC_ARM_REG_D19,
+    "d20" : UC_ARM_REG_D20,
+    "d21" : UC_ARM_REG_D21,
+    "d22" : UC_ARM_REG_D22,
+    "d23" : UC_ARM_REG_D23,
+    "d24" : UC_ARM_REG_D24,
+    "d25" : UC_ARM_REG_D25,
+    "d26" : UC_ARM_REG_D26,
+    "d27" : UC_ARM_REG_D27,
+    "d28" : UC_ARM_REG_D28,
+    "d29" : UC_ARM_REG_D29,
+    "d30" : UC_ARM_REG_D30,
+    "d31" : UC_ARM_REG_D31,
+    "fpscr" : UC_ARM_REG_FPSCR
+}

qiling/debugger/gdb/xmlregs.py

@@ -7,6 +7,7 @@
 from pathlib import PurePath
 
 from qiling.arch.arm_const import reg_map as arm_regs
+from qiling.arch.arm_const import reg_vfp as arm_regs_vfp
 from qiling.arch.arm64_const import reg_map as arm64_regs
 from qiling.arch.mips_const import reg_map as mips_regs_gpr
 from qiling.arch.mips_const import reg_map_fpu as mips_regs_fpu
@@ -81,7 +82,7 @@ def load_regsmap(archtype: QL_ARCH) -> Sequence[RegEntry]:
         QL_ARCH.A8086    : dict(**x86_regs_16, **x86_regs_misc, **x86_regs_cr, **x86_regs_st),
         QL_ARCH.X86      : dict(**x86_regs_32, **x86_regs_misc, **x86_regs_cr, **x86_regs_st, **x86_regs_xmm),
         QL_ARCH.X8664    : dict(**x86_regs_64, **x86_regs_misc, **x86_regs_cr, **x86_regs_st, **x86_regs_xmm, **x86_regs_ymm),
-        QL_ARCH.ARM      : arm_regs,
+        QL_ARCH.ARM      : dict(**arm_regs, **arm_regs_vfp),
         QL_ARCH.CORTEX_M : arm_regs,
         QL_ARCH.ARM64    : arm64_regs,
         QL_ARCH.MIPS     : dict(**mips_regs_gpr, **mips_regs_fpu)