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Merge branch 'dev' into riscv
2 parents 025cfc3 + ffb4011 commit 32ff7d0

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lines changed

6 files changed

+54
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AUTHORS.TXT

Lines changed: 0 additions & 9 deletions
This file was deleted.

CREDITS.TXT

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14,16 +14,20 @@ NGUYEN Anh Quynh <[email protected]>
1414
Core Developers Crew
1515
====================
1616
Earl MARCUS (klks84) [email protected]
17-
DING tianze (D1iv3) <[email protected]>
18-
SUN bowen (w1tcher) <[email protected]>
19-
CHEN huitao (null) <[email protected]>
20-
YU tong (sp1ke) <[email protected]>
2117
WU chenxu (kabeor) <[email protected]>
2218
KONG ziqiao (lazymio) <[email protected]>
2319
YU zheng (dataisland) <[email protected]>
2420
Eli Cohen Nehemia (elicn) <[email protected]>
2521

2622

23+
Legacy Core Developers
24+
======================
25+
DING tianze (D1iv3) <[email protected]>
26+
SUN bowen (w1tcher) <[email protected]>
27+
CHEN huitao (null) <[email protected]>
28+
YU tong (sp1ke) <[email protected]>
29+
30+
2731
Travis, Website and Documentations
2832
==================================
2933
FOO Kevin (chfl4gs) <[email protected]>

ChangeLog

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3,14 +3,15 @@ This file details the changelog of Qiling Framework.
33
------------------------------------
44
[Version 1.4.1]: Nov Xth, 2021
55

6-
- Clean and tidy up core utils module (WIP)
7-
- Clean and tidy up path module
8-
- Other small adjustments so support the above changes
9-
- Rearranged the code to be more Pythonic and more readable
10-
- Removed unused members and methods
11-
- Added typing annotations
12-
- Added ql.platform_os and ql.platform_arch
13-
- update ql.os.posix.const_mapping with more os/arch match
6+
New features:
7+
- Introduced riscv, both 32 and 64 (#980)
8+
9+
Improvements:
10+
- Refactored core hooks (#966)
11+
- update ql.os.posix.const_mapping with more os/arch match (#973)
12+
- Minor refactor on ql.interpreter and ql.baremetal (#975)
13+
- More update in MCU modules (#971)
14+
- Fix getpeername and getsockname syscalls (#986)
1415

1516

1617
------------------------------------

qiling/core.py

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,7 @@ def __init__(
122122
self._ostype = arch_os_convert(self._archtype)
123123
else:
124124
self._ostype = ostype_convert(self._ostype.lower())
125-
125+
126126
if self._code == None:
127127
self._code = "qilingcode"
128128
if self._argv is None:
@@ -157,9 +157,6 @@ def __init__(
157157

158158
if not ql_is_valid_arch(self._archtype):
159159
raise QlErrorArch("Invalid Arch %s" % self._archtype)
160-
161-
162-
163160

164161
#######################################
165162
# Loader and General Purpose OS check #

qiling/os/posix/syscall/socket.py

Lines changed: 36 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -338,37 +338,49 @@ def ql_syscall_bind(ql: Qiling, bind_fd, bind_addr, bind_addrlen):
338338
return regreturn
339339

340340

341-
def ql_syscall_getsockname(ql: Qiling, sockfd, addr, addrlenptr):
342-
if 0 <= sockfd < NR_OPEN and ql.os.fd[sockfd] != 0:
343-
host, port = ql.os.fd[sockfd].getsockname()
344-
data = struct.pack("<h", int(ql.os.fd[sockfd].family))
345-
data += struct.pack(">H", port)
346-
data += ipaddress.ip_address(host).packed
347-
addrlen = ql.mem.read(addrlenptr, 4)
348-
addrlen = ql.unpack32(addrlen)
349-
data = data[:addrlen]
350-
ql.mem.write(addr, data)
351-
regreturn = 0
341+
def ql_syscall_getsockname(ql: Qiling, sockfd: int, addr: int, addrlenptr: int):
342+
if 0 <= sockfd < NR_OPEN:
343+
socket = ql.os.fd[sockfd]
344+
345+
if isinstance(socket, ql_socket):
346+
host, port = socket.getpeername()
347+
348+
data = struct.pack("<h", int(socket.family))
349+
data += struct.pack(">H", port)
350+
data += ipaddress.ip_address(host).packed
351+
352+
addrlen = ql.mem.read_ptr(addrlenptr)
353+
354+
ql.mem.write(addr, data[:addrlen])
355+
regreturn = 0
356+
else:
357+
regreturn = -EPERM
352358
else:
353-
regreturn = -1
359+
regreturn = -EPERM
354360

355361
ql.log.debug("getsockname(%d, 0x%x, 0x%x) = %d" % (sockfd, addr, addrlenptr, regreturn))
356362
return regreturn
357363

358364

359-
def ql_syscall_getpeername(ql: Qiling, sockfd, addr, addrlenptr):
360-
if 0 <= sockfd < NR_OPEN and ql.os.fd[sockfd] != 0:
361-
host, port = ql.os.fd[sockfd].getpeername()
362-
data = struct.pack("<h", int(ql.os.fd[sockfd].family))
363-
data += struct.pack(">H", port)
364-
data += ipaddress.ip_address(host).packed
365-
addrlen = ql.mem.read(addrlenptr, 4)
366-
addrlen = ql.unpack32(addrlen)
367-
data = data[:addrlen]
368-
ql.mem.write(addr, data)
369-
regreturn = 0
365+
def ql_syscall_getpeername(ql: Qiling, sockfd: int, addr: int, addrlenptr: int):
366+
if 0 <= sockfd < NR_OPEN:
367+
socket = ql.os.fd[sockfd]
368+
369+
if isinstance(socket, ql_socket):
370+
host, port = socket.getpeername()
371+
372+
data = struct.pack("<h", int(socket.family))
373+
data += struct.pack(">H", port)
374+
data += ipaddress.ip_address(host).packed
375+
376+
addrlen = ql.mem.read_ptr(addrlenptr)
377+
378+
ql.mem.write(addr, data[:addrlen])
379+
regreturn = 0
380+
else:
381+
regreturn = -EPERM
370382
else:
371-
regreturn = -1
383+
regreturn = -EPERM
372384

373385
ql.log.debug("getpeername(%d, 0x%x, 0x%x) = %d" % (sockfd, addr, addrlenptr, regreturn))
374386
return regreturn

qiling/os/posix/syscall/unistd.py

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -145,8 +145,6 @@ def ql_syscall_lseek(ql: Qiling, fd: int, offset: int, lseek_origin: int):
145145
regreturn = ql.os.fd[fd].lseek(offset, lseek_origin)
146146
except OSError:
147147
regreturn = -1
148-
else:
149-
regreturn = 0
150148
else:
151149
regreturn = -EBADF
152150

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