Make argreg a class member

Author: elicn

qiling/cc/__init__.py

@@ -2,7 +2,7 @@
 # 
 # Cross Platform and Multi Architecture Advanced Binary Emulation Framework
 
-from typing import Callable, Tuple
+from typing import Callable, Sequence, Tuple
 
 from qiling.arch.arch import QlArch
 
@@ -107,19 +107,17 @@ class QlCommonBaseCC(QlCC):
 	of the QlCC interface.
 	"""
 
-	_argregs = ()
+	_retreg: int
+	_argregs: Sequence
 	_shadow = 0
 	_retaddr_on_stack = True
 
-	def __init__(self, arch: QlArch, retreg: int):
+	def __init__(self, arch: QlArch):
 		super().__init__(arch)
 
 		# native address size in bytes
 		self._asize = self.arch.pointersize
 
-		# return value register
-		self._retreg = retreg
-
 	def __access_param(self, index: int, stack_access: Callable, reg_access: Callable) -> Tuple[Callable, int]:
 		"""[private] Generic accessor to function call parameters by their index.
 

qiling/cc/arm.py

@@ -8,7 +8,6 @@
 	UC_ARM64_REG_X4, UC_ARM64_REG_X5, UC_ARM64_REG_X6, UC_ARM64_REG_X7
 )
 
-from qiling.arch.arch import QlArch
 from qiling.cc import QlCommonBaseCC
 
 class QlArmBaseCC(QlCommonBaseCC):
@@ -29,13 +28,9 @@ def unwind(self, nslots: int) -> int:
 		return self.arch.stack_pop()
 
 class aarch64(QlArmBaseCC):
+	_retreg = UC_ARM64_REG_X0
 	_argregs = (UC_ARM64_REG_X0, UC_ARM64_REG_X1, UC_ARM64_REG_X2, UC_ARM64_REG_X3, UC_ARM64_REG_X4, UC_ARM64_REG_X5, UC_ARM64_REG_X6, UC_ARM64_REG_X7) + (None, ) * 8
 
-	def __init__(self, arch: QlArch) -> None:
-		super().__init__(arch, UC_ARM64_REG_X0)
-
 class aarch32(QlArmBaseCC):
+	_retreg = UC_ARM_REG_R0
 	_argregs = (UC_ARM_REG_R0, UC_ARM_REG_R1, UC_ARM_REG_R2, UC_ARM_REG_R3) + (None, ) * 12
-
-	def __init__(self, arch: QlArch) -> None:
-		super().__init__(arch, UC_ARM_REG_R0)

qiling/cc/intel.py

@@ -3,28 +3,18 @@
 # Cross Platform and Multi Architecture Advanced Binary Emulation Framework
 
 from unicorn.x86_const import (
-	UC_X86_REG_AX,	UC_X86_REG_EAX,	UC_X86_REG_RAX, UC_X86_REG_RCX,
-	UC_X86_REG_RDI,	UC_X86_REG_RDX,	UC_X86_REG_RSI,	UC_X86_REG_R8,
-	UC_X86_REG_R9,	UC_X86_REG_R10
+	UC_X86_REG_EAX,	UC_X86_REG_RAX, UC_X86_REG_RCX, UC_X86_REG_RDI,
+	UC_X86_REG_RDX,	UC_X86_REG_RSI,	UC_X86_REG_R8, UC_X86_REG_R9,
+	UC_X86_REG_R10
 )
 
-from qiling.arch.arch import QlArch
 from qiling.cc import QlCommonBaseCC
 
 class QlIntelBaseCC(QlCommonBaseCC):
 	"""Calling convention base class for Intel-based systems.
 	Supports arguments passing over registers and stack.
 	"""
 
-	def __init__(self, arch: QlArch):
-		retreg = {
-			16: UC_X86_REG_AX,
-			32: UC_X86_REG_EAX,
-			64: UC_X86_REG_RAX
-		}[arch.bits]
-
-		super().__init__(arch, retreg)
-
 	def setReturnAddress(self, addr: int) -> None:
 		self.arch.stack_push(addr)
 
@@ -36,6 +26,8 @@ class QlIntel64(QlIntelBaseCC):
 	"""Calling convention base class for Intel-based 64-bit systems.
 	"""
 
+	_retreg = UC_X86_REG_RAX
+
 	@staticmethod
 	def getNumSlots(argbits: int) -> int:
 		return max(argbits, 64) // 64
@@ -44,6 +36,8 @@ class QlIntel32(QlIntelBaseCC):
 	"""Calling convention base class for Intel-based 32-bit systems.
 	"""
 
+	_retreg = UC_X86_REG_EAX
+
 	@staticmethod
 	def getNumSlots(argbits: int) -> int:
 		return max(argbits, 32) // 32

qiling/cc/mips.py

@@ -4,17 +4,14 @@
 
 from unicorn.mips_const import UC_MIPS_REG_V0, UC_MIPS_REG_A0, UC_MIPS_REG_A1, UC_MIPS_REG_A2, UC_MIPS_REG_A3
 
-from qiling.arch.arch import QlArch
 from qiling.cc import QlCommonBaseCC
 
 class mipso32(QlCommonBaseCC):
+	_retreg = UC_MIPS_REG_V0
 	_argregs = (UC_MIPS_REG_A0, UC_MIPS_REG_A1, UC_MIPS_REG_A2, UC_MIPS_REG_A3) + (None, ) * 12
 	_shadow = 4
 	_retaddr_on_stack = False
 
-	def __init__(self, arch: QlArch):
-		super().__init__(arch, UC_MIPS_REG_V0)
-
 	@staticmethod
 	def getNumSlots(argbits: int):
 		return 1

qiling/cc/riscv.py

@@ -2,25 +2,21 @@
 # 
 # Cross Platform and Multi Architecture Advanced Binary Emulation Framework
 
-from qiling.arch.arch import QlArch
 from qiling.cc import QlCommonBaseCC
 
 from unicorn.riscv_const import (
-    UC_RISCV_REG_A0, UC_RISCV_REG_A1, UC_RISCV_REG_A2, 
-    UC_RISCV_REG_A3, UC_RISCV_REG_A4, UC_RISCV_REG_A5, 
+    UC_RISCV_REG_A0, UC_RISCV_REG_A1, UC_RISCV_REG_A2,
+    UC_RISCV_REG_A3, UC_RISCV_REG_A4, UC_RISCV_REG_A5
 )
 
-
 class riscv(QlCommonBaseCC):
     """Default calling convention for RISCV
-        First 6 arguments are passed in regs, the rest are passed on the stack.
+    First 6 arguments are passed in regs, the rest are passed on the stack.
     """
 
+    _retreg = UC_RISCV_REG_A0
     _argregs = (UC_RISCV_REG_A0, UC_RISCV_REG_A1, UC_RISCV_REG_A2, UC_RISCV_REG_A3, UC_RISCV_REG_A4, UC_RISCV_REG_A5) + (None, ) * 10
 
-    def __init__(self, arch: QlArch):
-        super().__init__(arch, UC_RISCV_REG_A0)
-
     @staticmethod
     def getNumSlots(argbits: int):
         return 1