Merge pull request #969 from cla7aye15I4nd/dev

Added some peripheral details

Author: cla7aye15I4nd

examples/mcu/stm32f4_hack_lock.py examples/mcu/stm32f407_hack_lock.pyexamples/mcu/stm32f4_hack_lock.py renamed to examples/mcu/stm32f407_hack_lock.py

@@ -9,8 +9,8 @@ def stm32f411_dma():
     ql = Qiling(["../rootfs/mcu/stm32f411/dma-clock.hex"],                    
         archtype="cortex_m", profile="stm32f411", verbose=QL_VERBOSE.DEBUG)
 
-    ql.hw.create('usart2')
-    ql.hw.create('dma1')
+    ql.hw.create('usart2').watch()
+    ql.hw.create('dma1').watch()
     ql.hw.create('rcc')
 
     ql.run(count=200000)

examples/mcu/stm32f4_dma.py examples/mcu/stm32f411_dma_logger.pyexamples/mcu/stm32f4_dma.py renamed to examples/mcu/stm32f411_dma_logger.py

@@ -9,9 +9,9 @@ def stm32f411_freertos():
     ql = Qiling(["../rootfs/mcu/stm32f411/os-demo.hex"],                    
         archtype="cortex_m", profile="stm32f411", verbose=QL_VERBOSE.DEBUG)
 
-    ql.hw.create('usart2')
-    ql.hw.create('rcc')
-    ql.hw.create('gpioa')
+    ql.hw.create('usart2').watch()
+    ql.hw.create('gpioa').watch()
+    ql.hw.create('rcc')    
 
     ql.hw.systick.set_ratio(100)
     ql.run(count=200000)

examples/mcu/stm32f4_freertos.py examples/mcu/stm32f411_freertos.pyexamples/mcu/stm32f4_freertos.py renamed to examples/mcu/stm32f411_freertos.py

@@ -9,9 +9,9 @@ def test_mcu_gpio_stm32f411():
     ql = Qiling(["../../examples/rootfs/mcu/stm32f411/hello_gpioA.hex"],                    
                 archtype="cortex_m", profile="stm32f411", verbose=QL_VERBOSE.DEBUG)
 
-    ql.hw.create('usart2')
-    ql.hw.create('rcc')
-    ql.hw.create('gpioa')
+    ql.hw.create('usart2').watch()
+    ql.hw.create('rcc').watch()
+    ql.hw.create('gpioa').watch()
 
 
     ql.hw.gpioa.hook_set(5, lambda: print('LED light up'))

examples/mcu/stm32f4_hello_gpio.py examples/mcu/stm32f411_gpio_hook.pyexamples/mcu/stm32f4_hello_gpio.py renamed to examples/mcu/stm32f411_gpio_hook.py

@@ -59,7 +59,7 @@ def __init__(self, ql, label, intn=None):
         self.recv_buf = bytearray()
         self.send_buf = bytearray()
 
-    @QlPeripheral.read_debug
+    @QlPeripheral.debug_info()
     def read(self, offset: int, size: int) -> int:
         buf = ctypes.create_string_buffer(size)
         ctypes.memmove(buf, ctypes.addressof(self.usart) + offset, size)
@@ -70,7 +70,7 @@ def read(self, offset: int, size: int) -> int:
 
         return retval
 
-    @QlPeripheral.write_debug
+    @QlPeripheral.debug_info()
     def write(self, offset: int, size: int, value: int):        
         if offset == self.struct.SR.offset:
             self.usart.SR &= value | USART_SR.CTS | USART_SR.LBD | USART_SR.TC | USART_SR.RXNE

examples/mcu/stm32f4_i2c.py examples/mcu/stm32f411_i2c_lcd.pyexamples/mcu/stm32f4_i2c.py renamed to examples/mcu/stm32f411_i2c_lcd.py

@@ -6,7 +6,7 @@
 from enum import IntEnum
 
 
-class DMA_CR(IntEnum):
+class DMA_SxCR(IntEnum):
     CHSEL    = 7 << 25
     CHSEL_0  = 1 << 25
     CHSEL_1  = 2 << 25
@@ -42,11 +42,114 @@ class DMA_CR(IntEnum):
     DMEIE    = 1 << 1
     EN       = 1 << 0
 
+class DMA_SxFCR(IntEnum):
+	FEIE  = 1 << 7
+	FS    = 0x7 << 3
+	DMDIS = 1 << 2
+	FTH   = 0x3 << 0
+
+class DMA_LISR(IntEnum):
+	TCIF3  = 1 << 27
+	HTIF3  = 1 << 26
+	TEIF3  = 1 << 25
+	DMEIF3 = 1 << 24
+	FEIF3  = 1 << 22
+	TCIF2  = 1 << 21
+	HTIF2  = 1 << 20
+	TEIF2  = 1 << 19
+	DMEIF2 = 1 << 18
+	FEIF2  = 1 << 16
+	TCIF1  = 1 << 11
+	HTIF1  = 1 << 10
+	TEIF1  = 1 << 9
+	DMEIF1 = 1 << 8
+	FEIF1  = 1 << 6
+	TCIF0  = 1 << 5
+	HTIF0  = 1 << 4
+	TEIF0  = 1 << 3
+	DMEIF0 = 1 << 2
+	FEIF0  = 1 << 0
+
+class DMA_HISR(IntEnum):
+	TCIF7  = 1 << 27
+	HTIF7  = 1 << 26
+	TEIF7  = 1 << 25
+	DMEIF7 = 1 << 24
+	FEIF7  = 1 << 22
+	TCIF6  = 1 << 21
+	HTIF6  = 1 << 20
+	TEIF6  = 1 << 19
+	DMEIF6 = 1 << 18
+	FEIF6  = 1 << 16
+	TCIF5  = 1 << 11
+	HTIF5  = 1 << 10
+	TEIF5  = 1 << 9
+	DMEIF5 = 1 << 8
+	FEIF5  = 1 << 6
+	TCIF4  = 1 << 5
+	HTIF4  = 1 << 4
+	TEIF4  = 1 << 3
+	DMEIF4 = 1 << 2
+	FEIF4  = 1 << 0
+
+class DMA_LIFCR(IntEnum):
+	CTCIF3  = 1 << 27
+	CHTIF3  = 1 << 26
+	CTEIF3  = 1 << 25
+	CDMEIF3 = 1 << 24
+	CFEIF3  = 1 << 22
+	CTCIF2  = 1 << 21
+	CHTIF2  = 1 << 20
+	CTEIF2  = 1 << 19
+	CDMEIF2 = 1 << 18
+	CFEIF2  = 1 << 16
+	CTCIF1  = 1 << 11
+	CHTIF1  = 1 << 10
+	CTEIF1  = 1 << 9
+	CDMEIF1 = 1 << 8
+	CFEIF1  = 1 << 6
+	CTCIF0  = 1 << 5
+	CHTIF0  = 1 << 4
+	CTEIF0  = 1 << 3
+	CDMEIF0 = 1 << 2
+	CFEIF0  = 1 << 0
+
+class DMA_HIFCR(IntEnum):
+	CTCIF7  = 1 << 27
+	CHTIF7  = 1 << 26
+	CTEIF7  = 1 << 25
+	CDMEIF7 = 1 << 24
+	CFEIF7  = 1 << 22
+	CTCIF6  = 1 << 21
+	CHTIF6  = 1 << 20
+	CTEIF6  = 1 << 19
+	CDMEIF6 = 1 << 18
+	CFEIF6  = 1 << 16
+	CTCIF5  = 1 << 11
+	CHTIF5  = 1 << 10
+	CTEIF5  = 1 << 9
+	CDMEIF5 = 1 << 8
+	CFEIF5  = 1 << 6
+	CTCIF4  = 1 << 5
+	CHTIF4  = 1 << 4
+	CTEIF4  = 1 << 3
+	CDMEIF4 = 1 << 2
+	CFEIF4  = 1 << 0
+
+class DMA_SxPAR(IntEnum):
+	PA = 0xffffffff << 0
+
+class DMA_SxM0AR(IntEnum):
+	M0A = 0xffffffff << 0
+
+class DMA_SxM1AR(IntEnum):
+	M1A = 0xffffffff << 0
+
 class DMA(IntEnum):
     PERIPH_TO_MEMORY = 0
-    MEMORY_TO_PERIPH = DMA_CR.DIR_0
-    MEMORY_TO_MEMORY = DMA_CR.DIR_1
+    MEMORY_TO_PERIPH = DMA_SxCR.DIR_0
+    MEMORY_TO_MEMORY = DMA_SxCR.DIR_1
 
     PDATAALIGN_BYTE     = 0
-    PDATAALIGN_HALFWORD = DMA_CR.MSIZE_0
-    PDATAALIGN_WORD     = DMA_CR.MSIZE_1
+    PDATAALIGN_HALFWORD = DMA_SxCR.MSIZE_0
+    PDATAALIGN_WORD     = DMA_SxCR.MSIZE_1