|
| 1 | +#!/usr/bin/env python3 |
| 2 | +# |
| 3 | +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework |
| 4 | +# |
| 5 | + |
| 6 | +from __future__ import annotations |
| 7 | + |
| 8 | +import weakref |
| 9 | + |
| 10 | +from typing import TYPE_CHECKING, Dict, Mapping, Tuple |
| 11 | + |
| 12 | +if TYPE_CHECKING: |
| 13 | + from unicorn import Uc |
| 14 | + |
| 15 | +_CPR_T = Tuple[int, int, int, int, int, int, bool] |
| 16 | + |
| 17 | + |
| 18 | +class QlCprManager: |
| 19 | + """Enables access to ARM coprocessor registers. |
| 20 | + """ |
| 21 | + |
| 22 | + # for more information about various aarch32 coprocessor register, pelase refer to: |
| 23 | + # https://developer.arm.com/documentation/ddi0601/latest/AArch32-Registers |
| 24 | + |
| 25 | + def __init__(self, uc: Uc, regs_map: Mapping[str, _CPR_T]) -> None: |
| 26 | + """Initialize the coprocessor registers manager. |
| 27 | + """ |
| 28 | + |
| 29 | + # this funny way of initialization is used to avoid calling self setattr and |
| 30 | + # getattr upon init. if it did, it would go into an endless recursion |
| 31 | + self.register_mapping: Dict[str, _CPR_T] |
| 32 | + super().__setattr__('register_mapping', regs_map) |
| 33 | + |
| 34 | + self.uc: Uc = weakref.proxy(uc) |
| 35 | + |
| 36 | + def __getattr__(self, name: str) -> int: |
| 37 | + if name in self.register_mapping: |
| 38 | + return self.read(*self.register_mapping[name]) |
| 39 | + |
| 40 | + else: |
| 41 | + return super().__getattribute__(name) |
| 42 | + |
| 43 | + def __setattr__(self, name: str, value: int) -> None: |
| 44 | + if name in self.register_mapping: |
| 45 | + self.write(*self.register_mapping[name], value) |
| 46 | + |
| 47 | + else: |
| 48 | + super().__setattr__(name, value) |
| 49 | + |
| 50 | + def read(self, coproc: int, opc1: int, crn: int, crm: int, opc2: int, el: int, is_64: bool) -> int: |
| 51 | + """Read a coprocessor register value. |
| 52 | +
|
| 53 | + Args: |
| 54 | + coproc : coprocessor to access, value varies between 0 and 15 |
| 55 | + opc1 : opcode 1, value varies between 0 and 7 |
| 56 | + crn : coprocessor register to access (CRn), value varies between 0 and 15 |
| 57 | + crm : additional coprocessor register to access (CRm), value varies between 0 and 15 |
| 58 | + opc2 : opcode 2, value varies between 0 and 7 |
| 59 | + el : the exception level the coprocessor register belongs to, value varies between 0 and 3 |
| 60 | + is_64 : indicates whether this is a 64-bit register |
| 61 | +
|
| 62 | + Returns: value of coprocessor register |
| 63 | + """ |
| 64 | + |
| 65 | + return self.uc.cpr_read(coproc, opc1, crn, crm, opc2, el, is_64) |
| 66 | + |
| 67 | + def write(self, coproc: int, opc1: int, crn: int, crm: int, opc2: int, el: int, is_64: bool, value: int) -> None: |
| 68 | + """Write a coprocessor register value. |
| 69 | +
|
| 70 | + Args: |
| 71 | + coproc : coprocessor to access, value varies between 0 and 15 |
| 72 | + opc1 : opcode 1, value varies between 0 and 7 |
| 73 | + crn : coprocessor register to access (CRn), value varies between 0 and 15 |
| 74 | + crm : additional coprocessor register to access (CRm), value varies between 0 and 15 |
| 75 | + opc2 : opcode 2, value varies between 0 and 7 |
| 76 | + el : the exception level the coprocessor register belongs to, value varies between 0 and 3 |
| 77 | + is_64 : indicates whether this is a 64-bit register |
| 78 | + value : value to write |
| 79 | + """ |
| 80 | + |
| 81 | + self.uc.cpr_write(coproc, opc1, crn, crm, opc2, el, is_64, value) |
| 82 | + |
| 83 | + def save(self) -> Dict[str, int]: |
| 84 | + """Save registers. |
| 85 | + """ |
| 86 | + |
| 87 | + return dict((name, self.read(*reg)) for name, reg in self.register_mapping.items()) |
| 88 | + |
| 89 | + def restore(self, context: Mapping[str, int]) -> None: |
| 90 | + """Restore registers. |
| 91 | + """ |
| 92 | + |
| 93 | + for name, val in context.items(): |
| 94 | + self.write(*self.register_mapping[name], val) |
| 95 | + |
| 96 | + |
| 97 | +__all__ = ['QlCprManager'] |
0 commit comments